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Tue, 9 Jul 2024 05:31:40 -0700 From: Itamar Gozlan To: , , , , , , , , Dariusz Sosnowski , Bing Zhao , Ori Kam , Matan Azrad CC: , Subject: [PATCH 7/8] net/mlx5/hws: fix NAT64 csum issue Date: Tue, 9 Jul 2024 15:31:02 +0300 Message-ID: <20240709123103.2101902-8-igozlan@nvidia.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240709123103.2101902-1-igozlan@nvidia.com> References: <20240707102532.2045942-10-igozlan@nvidia.com> <20240709123103.2101902-1-igozlan@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000055DF:EE_|PH7PR12MB6665:EE_ X-MS-Office365-Filtering-Correlation-Id: f512c133-fff2-402c-ae93-08dca0132bbf X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|82310400026|376014|921020; X-Microsoft-Antispam-Message-Info: GVIGTYO/4ZZu97sfHipqRp5/B06pjn9SdEFnhL82QGG0la+FEqEYUoburSP3ZpboHiDE+0puRkJudN0z52q31nFewuQCYfkUqaxTCZxkx/gnhXlZLeSc5T0o5Kst9I8T3jsWaEOXkOnHwaMOAwkNGfro8C2ZB63YSQ8Ep6jE2FMLKGWZOxWzXjNeaOrFR/4nrlIdbZrms2Ke4hDXWvb5ZqJiQjQWXbHShB2pub52GI5YIPY6ePxhh+zoLTZUubabKsR66BE7WtL5c7a69fa94HOd+ffKERxdph8+3TzmIJxQSHqoc4l0AoXkRc/D6QrsvtD+ilQ9Q0Vuo488JnBvquhGSYCUnyHE4jCEW4GKxEa82OncKV9P0WOvKq/FKm4a3q5jpourg0w3eAaQRMatxefI90mJ2pSIx2wlNi0emy+yuCfE2UMR0HM475TN48SyjtCa9jYrNafywfrT0IVjurb3gpBOMaYZLSnNWVUT/ZJaoj2TmqpRqUKfa13xdo8komIUInl0j+ZuKbJnB2zoFebJUp+aJ2mCm6O++GxR3YsUMRBi/zi6ArHYcvs8wXh3DgVWLC0/b/vVq/D+zhmhEEQnn4jUI36m+ac0YWsVKeZ4mWew9LpF/AgQlPnmcqjrUX4OusGVIBPQPSLkCjQZh2OYQur0mMqxbQ341WKnDEFeS/Id3AqcNTmbxJBonBavdVCvtmrvvg5j5J1Ay1nnc6fvVGVTMd8O2vEefLleOLdpbSFbQATwazju5s7gUvn7J1EFxOo8kr3wDm8UnGxYOpkXNbKVjTr+vPRWTqHblpoUV6pvVR5AAl3e00AC9DFDEu+hXx4JW9hJQ55ai3eLaaLhVrVSh/B8/f9W+83WDydAy5unFQEeCEA4qD5jliciIZFuNfy/kf+dyvxNOQyjEa3m6xnjH1YLMPVV4CCuWrrLPkoP0gy3FDivTRuSd3KzuiWtSZXXz4wKEE/oqruoWnAG7p0uyW6gSZgdNslbaVVhEG6H2zwf//dKrlPkddZYk0/4yFn9o34vLnXYXhqqqkyFeBL/7zZXgju90ZuLrOdhpaCv8JQHZKDMsdIRk8XVJOaecKJWwiIS3KH5czwyqREGtpooQU860ZjH8lTGDqKsmYMmf9+5r9b8bR1X5iolfdq2kxZTBXbMcadErMiKX8cl67yl4DFShtvAWXD/niJqbiZG5xjLguCSgrJ0kZOpoO6MZHbtvgb+fr/SNKxCD8QzojG/pEIkJyL8lOteqomWUR8yGELV8ruHqhwBTG3mY5OdKLAdS/zx1TZyWAfRsEVG/MiuzpqqUo9NYw17KnFgNCDzZCun8w4uJl+IXswxeB+QEToif2iuYZwCiq0MNXJ5KVmmk1gWIy0dLMNmXWMWCa5sIfK4/hnv7q2pN40yoUixp48EhuazwBxQqlKMYLEyRBOI2x1BVLtXSzYQZBd2dOLUjg3imZNf3B2hs5sZvfhss0MY4jLxtlxIwlc2Ww== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2024 12:32:16.9823 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f512c133-fff2-402c-ae93-08dca0132bbf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DF.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6665 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Erez Shitrit Due to HW limitation we got two csum's that were not correct, udp and ip, both of them were not calculated correctly by the HW. By adding the next W/A we allow the HW to collect it well: Separate the protocol field and zero all the addresses before fixed the UDP csum. We saw that the IP csum by the HW didn't take the ipv4 version as part of the csum because the way it was inserted into the packet, in order to solve that we added a prefix that takes into account the real csum for the ip version and from that point the HW calculating the csum correctly. Fixes: 06d969a8c5b8 ("net/mlx5/hws: support NAT64 flow action") Cc: erezsh@nvidia.com Cc: stable@dpdk.org Signed-off-by: Erez Shitrit Acked-by: Matan Azrad --- drivers/net/mlx5/hws/mlx5dr_action.c | 136 ++++++++++++++++++++++----- drivers/net/mlx5/hws/mlx5dr_action.h | 15 ++- 2 files changed, 123 insertions(+), 28 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c index 0d90280a7d..8d3d0033e5 100644 --- a/drivers/net/mlx5/hws/mlx5dr_action.c +++ b/drivers/net/mlx5/hws/mlx5dr_action.c @@ -249,6 +249,62 @@ static void mlx5dr_action_put_shared_stc(struct mlx5dr_action *action, mlx5dr_action_put_shared_stc_nic(ctx, stc_type, MLX5DR_TABLE_TYPE_FDB); } +static void +mlx5dr_action_create_nat64_zero_all_addr(uint8_t **action_ptr, bool is_v4_to_v6) +{ + if (is_v4_to_v6) { + MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET); + MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_SIPV4); + MLX5_SET(set_action_in, *action_ptr, data, 0); + *action_ptr += MLX5DR_ACTION_DOUBLE_SIZE; + + MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET); + MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_DIPV4); + MLX5_SET(set_action_in, *action_ptr, data, 0); + *action_ptr += MLX5DR_ACTION_DOUBLE_SIZE; + } else { + MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET); + MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_SIPV6_127_96); + MLX5_SET(set_action_in, *action_ptr, data, 0); + *action_ptr += MLX5DR_ACTION_DOUBLE_SIZE; + + MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET); + MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_SIPV6_95_64); + MLX5_SET(set_action_in, *action_ptr, data, 0); + *action_ptr += MLX5DR_ACTION_DOUBLE_SIZE; + + MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET); + MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_SIPV6_63_32); + MLX5_SET(set_action_in, *action_ptr, data, 0); + *action_ptr += MLX5DR_ACTION_DOUBLE_SIZE; + + MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET); + MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_SIPV6_31_0); + MLX5_SET(set_action_in, *action_ptr, data, 0); + *action_ptr += MLX5DR_ACTION_DOUBLE_SIZE; + + MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET); + MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_DIPV6_127_96); + MLX5_SET(set_action_in, *action_ptr, data, 0); + *action_ptr += MLX5DR_ACTION_DOUBLE_SIZE; + + MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET); + MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_DIPV6_95_64); + MLX5_SET(set_action_in, *action_ptr, data, 0); + *action_ptr += MLX5DR_ACTION_DOUBLE_SIZE; + + MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET); + MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_DIPV6_63_32); + MLX5_SET(set_action_in, *action_ptr, data, 0); + *action_ptr += MLX5DR_ACTION_DOUBLE_SIZE; + + MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET); + MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_DIPV6_31_0); + MLX5_SET(set_action_in, *action_ptr, data, 0); + *action_ptr += MLX5DR_ACTION_DOUBLE_SIZE; + } +} + static struct mlx5dr_action * mlx5dr_action_create_nat64_copy_state(struct mlx5dr_context *ctx, struct mlx5dr_action_nat64_attr *attr, @@ -329,17 +385,7 @@ mlx5dr_action_create_nat64_copy_state(struct mlx5dr_context *ctx, action_ptr += MLX5DR_ACTION_DOUBLE_SIZE; /* set sip and dip to 0, in order to have new csum */ - if (is_v4_to_v6) { - MLX5_SET(set_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET); - MLX5_SET(set_action_in, action_ptr, field, MLX5_MODI_OUT_SIPV4); - MLX5_SET(set_action_in, action_ptr, data, 0); - action_ptr += MLX5DR_ACTION_DOUBLE_SIZE; - - MLX5_SET(set_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET); - MLX5_SET(set_action_in, action_ptr, field, MLX5_MODI_OUT_DIPV4); - MLX5_SET(set_action_in, action_ptr, data, 0); - action_ptr += MLX5DR_ACTION_DOUBLE_SIZE; - } + mlx5dr_action_create_nat64_zero_all_addr(&action_ptr, is_v4_to_v6); pat[0].data = modify_action_data; pat[0].sz = (action_ptr - (uint8_t *)modify_action_data); @@ -383,9 +429,14 @@ mlx5dr_action_create_nat64_repalce_state(struct mlx5dr_context *ctx, memcpy(address_prefix, nat64_well_known_pref, MLX5DR_ACTION_NAT64_HEADER_MINUS_ONE * sizeof(uint32_t)); } else { + /* In order to fix HW csum issue, make the prefix ready */ + uint32_t ipv4_pref[] = {0x0, 0xffba0000, 0x0, 0x0, 0x0}; + header_size_in_dw = MLX5DR_ACTION_NAT64_IPV4_HEADER; ip_ver = MLX5DR_ACTION_NAT64_IPV4_VER; eth_type = RTE_ETHER_TYPE_IPV4; + memcpy(address_prefix, ipv4_pref, + MLX5DR_ACTION_NAT64_IPV4_HEADER * sizeof(uint32_t)); } memset(modify_action_data, 0, sizeof(modify_action_data)); @@ -441,6 +492,46 @@ mlx5dr_action_create_nat64_repalce_state(struct mlx5dr_context *ctx, return action; } +static struct mlx5dr_action * +mlx5dr_action_create_nat64_copy_proto_state(struct mlx5dr_context *ctx, + struct mlx5dr_action_nat64_attr *attr, + uint32_t flags) +{ + __be64 modify_action_data[MLX5DR_ACTION_NAT64_MAX_MODIFY_ACTIONS]; + struct mlx5dr_action_mh_pattern pat[2]; + struct mlx5dr_action *action; + uint8_t *action_ptr; + + memset(modify_action_data, 0, sizeof(modify_action_data)); + action_ptr = (uint8_t *)modify_action_data; + + MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_COPY); + MLX5_SET(copy_action_in, action_ptr, src_field, + attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]); + MLX5_SET(copy_action_in, action_ptr, dst_field, + MLX5_MODI_OUT_IP_PROTOCOL); + MLX5_SET(copy_action_in, action_ptr, src_offset, 16); + MLX5_SET(copy_action_in, action_ptr, dst_offset, 0); + MLX5_SET(copy_action_in, action_ptr, length, 8); + action_ptr += MLX5DR_ACTION_DOUBLE_SIZE; + + MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP); + action_ptr += MLX5DR_ACTION_DOUBLE_SIZE; + + pat[0].data = modify_action_data; + pat[0].sz = action_ptr - (uint8_t *)modify_action_data; + + action = mlx5dr_action_create_modify_header_reparse(ctx, 1, pat, 0, flags, + MLX5DR_ACTION_STC_REPARSE_ON); + if (!action) { + DR_LOG(ERR, "Failed to create action: action_sz: %zu, flags: 0x%x\n", + pat[0].sz, flags); + return NULL; + } + + return action; +} + static struct mlx5dr_action * mlx5dr_action_create_nat64_copy_back_state(struct mlx5dr_context *ctx, struct mlx5dr_action_nat64_attr *attr, @@ -490,16 +581,6 @@ mlx5dr_action_create_nat64_copy_back_state(struct mlx5dr_context *ctx, MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP); action_ptr += MLX5DR_ACTION_DOUBLE_SIZE; - MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_COPY); - MLX5_SET(copy_action_in, action_ptr, src_field, - attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]); - MLX5_SET(copy_action_in, action_ptr, dst_field, - MLX5_MODI_OUT_IP_PROTOCOL); - MLX5_SET(copy_action_in, action_ptr, src_offset, 16); - MLX5_SET(copy_action_in, action_ptr, dst_offset, 0); - MLX5_SET(copy_action_in, action_ptr, length, 8); - action_ptr += MLX5DR_ACTION_DOUBLE_SIZE; - MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP); action_ptr += MLX5DR_ACTION_DOUBLE_SIZE; @@ -2051,7 +2132,7 @@ mlx5dr_action_create_modify_header_hws(struct mlx5dr_action *action, return rte_errno; } -static struct mlx5dr_action * +struct mlx5dr_action * mlx5dr_action_create_modify_header_reparse(struct mlx5dr_context *ctx, uint8_t num_of_patterns, struct mlx5dr_action_mh_pattern *patterns, @@ -2927,17 +3008,24 @@ mlx5dr_action_create_nat64(struct mlx5dr_context *ctx, DR_LOG(ERR, "Nat64 failed creating replace state"); goto free_copy; } + action->nat64.stages[MLX5DR_ACTION_NAT64_STAGE_COPY_PROTOCOL] = + mlx5dr_action_create_nat64_copy_proto_state(ctx, attr, flags); + if (!action->nat64.stages[MLX5DR_ACTION_NAT64_STAGE_COPY_PROTOCOL]) { + DR_LOG(ERR, "Nat64 failed creating copy protocol state"); + goto free_replace; + } action->nat64.stages[MLX5DR_ACTION_NAT64_STAGE_COPYBACK] = mlx5dr_action_create_nat64_copy_back_state(ctx, attr, flags); if (!action->nat64.stages[MLX5DR_ACTION_NAT64_STAGE_COPYBACK]) { DR_LOG(ERR, "Nat64 failed creating copyback state"); - goto free_replace; + goto free_copy_proto; } return action; - +free_copy_proto: + mlx5dr_action_destroy(action->nat64.stages[MLX5DR_ACTION_NAT64_STAGE_COPY_PROTOCOL]); free_replace: mlx5dr_action_destroy(action->nat64.stages[MLX5DR_ACTION_NAT64_STAGE_REPLACE]); free_copy: diff --git a/drivers/net/mlx5/hws/mlx5dr_action.h b/drivers/net/mlx5/hws/mlx5dr_action.h index 57e059a572..faea6bb1f4 100644 --- a/drivers/net/mlx5/hws/mlx5dr_action.h +++ b/drivers/net/mlx5/hws/mlx5dr_action.h @@ -11,9 +11,6 @@ /* Max number of internal subactions of ipv6_ext */ #define MLX5DR_ACTION_IPV6_EXT_MAX_SA 4 -/* Number of MH in NAT64 */ -#define MLX5DR_ACTION_NAT64_STAGES 3 - enum mlx5dr_action_stc_idx { MLX5DR_ACTION_STC_IDX_CTRL = 0, MLX5DR_ACTION_STC_IDX_HIT = 1, @@ -88,7 +85,10 @@ enum { enum mlx5dr_action_nat64_stages { MLX5DR_ACTION_NAT64_STAGE_COPY = 0, MLX5DR_ACTION_NAT64_STAGE_REPLACE = 1, - MLX5DR_ACTION_NAT64_STAGE_COPYBACK = 2, + MLX5DR_ACTION_NAT64_STAGE_COPY_PROTOCOL = 2, + MLX5DR_ACTION_NAT64_STAGE_COPYBACK = 3, + /* Number of MH in NAT64 */ + MLX5DR_ACTION_NAT64_STAGES = 4, }; /* Registers for keeping data from stage to stage */ @@ -256,6 +256,13 @@ int mlx5dr_action_alloc_single_stc(struct mlx5dr_context *ctx, void mlx5dr_action_free_single_stc(struct mlx5dr_context *ctx, uint32_t table_type, struct mlx5dr_pool_chunk *stc); +struct mlx5dr_action * +mlx5dr_action_create_modify_header_reparse(struct mlx5dr_context *ctx, + uint8_t num_of_patterns, + struct mlx5dr_action_mh_pattern *patterns, + uint32_t log_bulk_size, + uint32_t flags, uint32_t reparse); + static inline void mlx5dr_action_setter_default_single(struct mlx5dr_actions_apply_data *apply,