diff mbox series

[v3,4/4] eal: describe Arm CPU features including WFXT

Message ID 20240715225305.18563-4-wathsala.vithanage@arm.com (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers
Series [v3,1/4] eal: expand the availability of WFE and related instructions |

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Commit Message

Wathsala Wathawana Vithanage July 15, 2024, 10:53 p.m. UTC 
RTE_CPUFALG_WFXT indicates the availability of WFET and WFIT
instructions. To preserve consistency across the rte_cpu_flag_t
enumeration, add descriptive comments to each Arm feature listed.

Signed-off-by: Wathsala Vithanage <wathsala.vithanage@arm.com>
Reviewed-by: Dhruv Tripathi <dhruv.tripathi@arm.com>
---
 lib/eal/arm/include/rte_cpuflags_64.h | 48 +++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

Comments

Honnappa Nagarahalli July 16, 2024, 1:02 a.m. UTC | #1 
> On Jul 15, 2024, at 5:53 PM, Wathsala Vithanage <wathsala.vithanage@arm.com> wrote:
> 
> RTE_CPUFALG_WFXT indicates the availability of WFET and WFIT
> instructions. To preserve consistency across the rte_cpu_flag_t
> enumeration, add descriptive comments to each Arm feature listed.
IMO, above can be simpler. “Add descriptive comments to each Arm feature listed in rte_cpu_flag_t"

> 
> Signed-off-by: Wathsala Vithanage <wathsala.vithanage@arm.com>
> Reviewed-by: Dhruv Tripathi <dhruv.tripathi@arm.com>
Otherwise, looks good.

Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>

> ---
> lib/eal/arm/include/rte_cpuflags_64.h | 48 +++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
> 
> diff --git a/lib/eal/arm/include/rte_cpuflags_64.h b/lib/eal/arm/include/rte_cpuflags_64.h
> index 993d980a02..eed67bf6ec 100644
> --- a/lib/eal/arm/include/rte_cpuflags_64.h
> +++ b/lib/eal/arm/include/rte_cpuflags_64.h
> @@ -13,28 +13,76 @@ extern "C" {
>  * Enumeration of all CPU features supported
>  */
> enum rte_cpu_flag_t {
> + /* Floating point capability */
> RTE_CPUFLAG_FP = 0,
> +
> + /* Arm Neon extension */
> RTE_CPUFLAG_NEON,
> +
> + /* Generic timer event stream */
> RTE_CPUFLAG_EVTSTRM,
> +
> + /* AES instructions */
> RTE_CPUFLAG_AES,
> +
> + /* Polynomial multiply long instruction */
> RTE_CPUFLAG_PMULL,
> +
> + /* SHA1 instructions */
> RTE_CPUFLAG_SHA1,
> +
> + /* SHA2 instructions */
> RTE_CPUFLAG_SHA2,
> +
> + /* CRC32 instruction */
> RTE_CPUFLAG_CRC32,
> +
> + /*
> + * LDADD, LDCLR, LDEOR, LDSET, LDSMAX, LDSMIN, LDUMAX, LDUMIN, CAS,
> + * CASP, and SWP instructions
> + */
> RTE_CPUFLAG_ATOMICS,
> +
> + /* Arm SVE extension */
> RTE_CPUFLAG_SVE,
> +
> + /* Arm SVE2 extension */
> RTE_CPUFLAG_SVE2,
> +
> + /* SVE-AES instructions */
> RTE_CPUFLAG_SVEAES,
> +
> + /* SVE-PMULL instruction */
> RTE_CPUFLAG_SVEPMULL,
> +
> + /* SVE bit permute instructions */
> RTE_CPUFLAG_SVEBITPERM,
> +
> + /* SVE-SHA3 instructions */
> RTE_CPUFLAG_SVESHA3,
> +
> + /* SVE-SM4 instructions */
> RTE_CPUFLAG_SVESM4,
> +
> + /* CFINV, RMIF, SETF16, SETF8, AXFLAG, and XAFLAG instructions */
> RTE_CPUFLAG_FLAGM2,
> +
> + /* FRINT32Z, FRINT32X, FRINT64Z, and FRINT64X instructions */
> RTE_CPUFLAG_FRINT,
> +
> + /* SVE Int8 matrix multiplication instructions */
> RTE_CPUFLAG_SVEI8MM,
> +
> + /* SVE FP32 floating-point matrix multiplication instructions */
> RTE_CPUFLAG_SVEF32MM,
> +
> + /* SVE FP64 floating-point matrix multiplication instructions */
> RTE_CPUFLAG_SVEF64MM,
> +
> + /* SVE BFloat16 instructions */
> RTE_CPUFLAG_SVEBF16,
> +
> + /* 64 bit execution state of the Arm architecture */
> RTE_CPUFLAG_AARCH64,
> 
> /* WFET and WFIT instructions */
> -- 
> 2.34.1
>
diff mbox series

Patch

diff --git a/lib/eal/arm/include/rte_cpuflags_64.h b/lib/eal/arm/include/rte_cpuflags_64.h
index 993d980a02..eed67bf6ec 100644
--- a/lib/eal/arm/include/rte_cpuflags_64.h
+++ b/lib/eal/arm/include/rte_cpuflags_64.h
@@ -13,28 +13,76 @@  extern "C" {
  * Enumeration of all CPU features supported
  */
 enum rte_cpu_flag_t {
+	/* Floating point capability */
 	RTE_CPUFLAG_FP = 0,
+
+	/* Arm Neon extension */
 	RTE_CPUFLAG_NEON,
+
+	/* Generic timer event stream */
 	RTE_CPUFLAG_EVTSTRM,
+
+	/* AES instructions */
 	RTE_CPUFLAG_AES,
+
+	/* Polynomial multiply long instruction */
 	RTE_CPUFLAG_PMULL,
+
+	/* SHA1 instructions */
 	RTE_CPUFLAG_SHA1,
+
+	/* SHA2 instructions */
 	RTE_CPUFLAG_SHA2,
+
+	/* CRC32 instruction */
 	RTE_CPUFLAG_CRC32,
+
+	/*
+	 * LDADD, LDCLR, LDEOR, LDSET, LDSMAX, LDSMIN, LDUMAX, LDUMIN, CAS,
+	 * CASP, and SWP instructions
+	 */
 	RTE_CPUFLAG_ATOMICS,
+
+	/* Arm SVE extension */
 	RTE_CPUFLAG_SVE,
+
+	/* Arm SVE2 extension */
 	RTE_CPUFLAG_SVE2,
+
+	/* SVE-AES instructions */
 	RTE_CPUFLAG_SVEAES,
+
+	/* SVE-PMULL instruction */
 	RTE_CPUFLAG_SVEPMULL,
+
+	/* SVE bit permute instructions */
 	RTE_CPUFLAG_SVEBITPERM,
+
+	/* SVE-SHA3 instructions */
 	RTE_CPUFLAG_SVESHA3,
+
+	/* SVE-SM4 instructions */
 	RTE_CPUFLAG_SVESM4,
+
+	/* CFINV, RMIF, SETF16, SETF8, AXFLAG, and XAFLAG instructions */
 	RTE_CPUFLAG_FLAGM2,
+
+	/* FRINT32Z, FRINT32X, FRINT64Z, and FRINT64X instructions */
 	RTE_CPUFLAG_FRINT,
+
+	/* SVE Int8 matrix multiplication instructions */
 	RTE_CPUFLAG_SVEI8MM,
+
+	/* SVE FP32 floating-point matrix multiplication instructions */
 	RTE_CPUFLAG_SVEF32MM,
+
+	/* SVE FP64 floating-point matrix multiplication instructions */
 	RTE_CPUFLAG_SVEF64MM,
+
+	/* SVE BFloat16 instructions */
 	RTE_CPUFLAG_SVEBF16,
+
+	/* 64 bit execution state of the Arm architecture */
 	RTE_CPUFLAG_AARCH64,
 
 	/* WFET and WFIT instructions */