diff mbox series

net/mlx5: fix NVGRE item validation for template API

Message ID 20240726014958.43843-1-jiaweiw@nvidia.com (mailing list archive)
State Awaiting Upstream
Delegated to: Raslan Darawsheh
Headers
Series net/mlx5: fix NVGRE item validation for template API |

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ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
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Commit Message

Jiawei Wang July 26, 2024, 1:49 a.m. UTC 
The template API NVGRE item can support full mask.
This patch updates default NVGRE item mask for the template API.

Fixes: 80c676259a04 ("net/mlx5: validate HWS template items")
Cc: stable@dpdk.org

Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

Comments

Raslan Darawsheh Aug. 29, 2024, 9 a.m. UTC | #1 
Hi,

From: Jiawei(Jonny) Wang <jiaweiw@nvidia.com>
Sent: Friday, July 26, 2024 4:49 AM
To: Bing Zhao; Slava Ovsiienko; Dariusz Sosnowski; Ori Kam; Suanming Mou; Matan Azrad; Gregory Etelson
Cc: dev@dpdk.org; Raslan Darawsheh; stable@dpdk.org
Subject: [PATCH] net/mlx5: fix NVGRE item validation for template API

The template API NVGRE item can support full mask.
This patch updates default NVGRE item mask for the template API.

Fixes: 80c676259a04 ("net/mlx5: validate HWS template items")
Cc: stable@dpdk.org

Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 72fb3a55ba..14720f54ab 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -3867,6 +3867,15 @@  mlx5_flow_validate_item_nvgre(const struct rte_eth_dev *dev,
 	const struct rte_flow_item_nvgre *mask = item->mask;
 	int ret;
 
+	const struct rte_flow_item_nvgre hws_nic_mask = {
+		.c_k_s_rsvd0_ver = RTE_BE16(0xB000),
+		.protocol = RTE_BE16(UINT16_MAX),
+		.tni = {0xff, 0xff, 0xff},
+		.flow_id = 0xff
+	};
+	const struct rte_flow_item_nvgre *nic_mask = !mlx5_hws_active(dev) ?
+		&rte_flow_item_nvgre_mask : &hws_nic_mask;
+
 	if (target_protocol != 0xff && target_protocol != IPPROTO_GRE)
 		return rte_flow_error_set(error, EINVAL,
 					  RTE_FLOW_ERROR_TYPE_ITEM, item,
@@ -3884,10 +3893,10 @@  mlx5_flow_validate_item_nvgre(const struct rte_eth_dev *dev,
 						  item, "L3 Layer is missing");
 	}
 	if (!mask)
-		mask = &rte_flow_item_nvgre_mask;
+		mask = nic_mask;
 	ret = mlx5_flow_item_acceptable
 		(dev, item, (const uint8_t *)mask,
-		 (const uint8_t *)&rte_flow_item_nvgre_mask,
+		 (const uint8_t *)nic_mask,
 		 sizeof(struct rte_flow_item_nvgre),
 		 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
 	if (ret < 0)