From patchwork Fri Jul 26 17:15:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wathsala Wathawana Vithanage X-Patchwork-Id: 142738 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B55E3456A3; Fri, 26 Jul 2024 19:15:55 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 97F4942FF9; Fri, 26 Jul 2024 19:15:46 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 1DE0E410F6 for ; Fri, 26 Jul 2024 19:15:43 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E4471165C; Fri, 26 Jul 2024 10:16:07 -0700 (PDT) Received: from ampere-altra-2-1.usa.Arm.com (ampere-altra-2-1.usa.arm.com [10.118.91.158]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 29C8B3F8A4; Fri, 26 Jul 2024 10:15:42 -0700 (PDT) From: Wathsala Vithanage To: Ruifeng Wang Cc: honnappa.nagarahalli@arm.com, dev@dpdk.org, Wathsala Vithanage , Dhruv Tripathi Subject: [PATCH v4 4/4] eal: describe Arm CPU features including WFXT Date: Fri, 26 Jul 2024 17:15:27 +0000 Message-Id: <20240726171528.2245682-4-wathsala.vithanage@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240726171528.2245682-1-wathsala.vithanage@arm.com> References: <20240604044401.3577707-1-wathsala.vithanage@arm.com> <20240726171528.2245682-1-wathsala.vithanage@arm.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add descriptive comments to each Arm feature listed in rte_cpu_flag_t. Signed-off-by: Wathsala Vithanage Reviewed-by: Honnappa Nagarahalli Reviewed-by: Dhruv Tripathi --- lib/eal/arm/include/rte_cpuflags_64.h | 48 +++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/lib/eal/arm/include/rte_cpuflags_64.h b/lib/eal/arm/include/rte_cpuflags_64.h index 993d980a02..eed67bf6ec 100644 --- a/lib/eal/arm/include/rte_cpuflags_64.h +++ b/lib/eal/arm/include/rte_cpuflags_64.h @@ -13,28 +13,76 @@ extern "C" { * Enumeration of all CPU features supported */ enum rte_cpu_flag_t { + /* Floating point capability */ RTE_CPUFLAG_FP = 0, + + /* Arm Neon extension */ RTE_CPUFLAG_NEON, + + /* Generic timer event stream */ RTE_CPUFLAG_EVTSTRM, + + /* AES instructions */ RTE_CPUFLAG_AES, + + /* Polynomial multiply long instruction */ RTE_CPUFLAG_PMULL, + + /* SHA1 instructions */ RTE_CPUFLAG_SHA1, + + /* SHA2 instructions */ RTE_CPUFLAG_SHA2, + + /* CRC32 instruction */ RTE_CPUFLAG_CRC32, + + /* + * LDADD, LDCLR, LDEOR, LDSET, LDSMAX, LDSMIN, LDUMAX, LDUMIN, CAS, + * CASP, and SWP instructions + */ RTE_CPUFLAG_ATOMICS, + + /* Arm SVE extension */ RTE_CPUFLAG_SVE, + + /* Arm SVE2 extension */ RTE_CPUFLAG_SVE2, + + /* SVE-AES instructions */ RTE_CPUFLAG_SVEAES, + + /* SVE-PMULL instruction */ RTE_CPUFLAG_SVEPMULL, + + /* SVE bit permute instructions */ RTE_CPUFLAG_SVEBITPERM, + + /* SVE-SHA3 instructions */ RTE_CPUFLAG_SVESHA3, + + /* SVE-SM4 instructions */ RTE_CPUFLAG_SVESM4, + + /* CFINV, RMIF, SETF16, SETF8, AXFLAG, and XAFLAG instructions */ RTE_CPUFLAG_FLAGM2, + + /* FRINT32Z, FRINT32X, FRINT64Z, and FRINT64X instructions */ RTE_CPUFLAG_FRINT, + + /* SVE Int8 matrix multiplication instructions */ RTE_CPUFLAG_SVEI8MM, + + /* SVE FP32 floating-point matrix multiplication instructions */ RTE_CPUFLAG_SVEF32MM, + + /* SVE FP64 floating-point matrix multiplication instructions */ RTE_CPUFLAG_SVEF64MM, + + /* SVE BFloat16 instructions */ RTE_CPUFLAG_SVEBF16, + + /* 64 bit execution state of the Arm architecture */ RTE_CPUFLAG_AARCH64, /* WFET and WFIT instructions */