From patchwork Thu Aug 8 06:14:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hyong Youb Kim X-Patchwork-Id: 143015 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BB89E45767; Thu, 8 Aug 2024 08:15:44 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AC53B42790; Thu, 8 Aug 2024 08:15:44 +0200 (CEST) Received: from alln-iport-7.cisco.com (alln-iport-7.cisco.com [173.37.142.94]) by mails.dpdk.org (Postfix) with ESMTP id DFE524278F for ; Thu, 8 Aug 2024 08:15:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cisco.com; i=@cisco.com; l=2032; q=dns/txt; s=iport; t=1723097743; x=1724307343; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=joYDe/K3KMwFJyC5ZgVHvJrMz+EYUmqf7Tq8c6rFWsw=; b=gVe+eHqxDqYXDwzMTv6EwcAuIjJ8dFsFBV56MuV8/51rX1bsED4ul4B2 UK0kGfMkl9ZsNkrPk0ThBXeTKRGe7ZGYzrwwmcNRVtL0YBqCwtIVyaIG9 KvxJPzIPnTkzmKfLAF9WR/thMDot93rqRyRCJcIfRQDevyI0AW7MIcCxn 0=; X-CSE-ConnectionGUID: EL8jH/XZSOuaWaqElTViTw== X-CSE-MsgGUID: 4htLCBkVRQKXGRNv4OrH/w== X-IronPort-AV: E=Sophos;i="6.09,272,1716249600"; d="scan'208";a="328750468" Received: from rcdn-core-5.cisco.com ([173.37.93.156]) by alln-iport-7.cisco.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2024 06:15:41 +0000 Received: from cisco.com (savbu-usnic-a.cisco.com [10.193.184.48]) by rcdn-core-5.cisco.com (8.15.2/8.15.2) with ESMTP id 4786FfWC008028; Thu, 8 Aug 2024 06:15:41 GMT Received: by cisco.com (Postfix, from userid 508933) id 42EF93FAB9BC; Wed, 7 Aug 2024 23:15:41 -0700 (PDT) From: Hyong Youb Kim To: Ferruh Yigit Cc: dev@dpdk.org, John Daley , Hyong Youb Kim Subject: [PATCH v2 2/3] net/enic: add speed capabilities for newer models Date: Wed, 7 Aug 2024 23:14:32 -0700 Message-Id: <20240808061433.14971-3-hyonkim@cisco.com> X-Mailer: git-send-email 2.35.2 In-Reply-To: <20240808061433.14971-1-hyonkim@cisco.com> References: <20240808041838.31367-4-hyonkim@cisco.com> <20240808061433.14971-1-hyonkim@cisco.com> MIME-Version: 1.0 X-Outbound-SMTP-Client: 10.193.184.48, savbu-usnic-a.cisco.com X-Outbound-Node: rcdn-core-5.cisco.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add 1400/14000 and 15000 models to the speed_capa list. Signed-off-by: Hyong Youb Kim Reviewed-by: John Daley --- drivers/net/enic/enic_ethdev.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/net/enic/enic_ethdev.c b/drivers/net/enic/enic_ethdev.c index 5c967677fb..62c8751d09 100644 --- a/drivers/net/enic/enic_ethdev.c +++ b/drivers/net/enic/enic_ethdev.c @@ -62,6 +62,27 @@ static const struct vic_speed_capa { { 0x021a, RTE_ETH_LINK_SPEED_40G }, /* 1487 MLOM */ { 0x024a, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G }, /* 1495 PCIe */ { 0x024b, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G }, /* 1497 MLOM */ + { 0x02af, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G }, /* 1467 MLOM */ + { 0x02b0, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G }, /* 1477 MLOM */ + { 0x02cf, RTE_ETH_LINK_SPEED_25G }, /* 14425 MLOM */ + { 0x02d0, RTE_ETH_LINK_SPEED_25G }, /* 14825 Mezz */ + { 0x02db, RTE_ETH_LINK_SPEED_100G }, /* 15231 MLOM */ + { 0x02dc, RTE_ETH_LINK_SPEED_10G }, /* 15411 MLOM */ + { 0x02dd, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G | + RTE_ETH_LINK_SPEED_50G }, /* 15428 MLOM */ + { 0x02de, RTE_ETH_LINK_SPEED_25G }, /* 15420 MLOM */ + { 0x02e8, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G | + RTE_ETH_LINK_SPEED_200G}, /* 15238 MLOM */ + { 0x02e0, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G | + RTE_ETH_LINK_SPEED_50G }, /* 15427 MLOM */ + { 0x02df, RTE_ETH_LINK_SPEED_50G | RTE_ETH_LINK_SPEED_100G }, /* 15230 MLOM */ + { 0x02e1, RTE_ETH_LINK_SPEED_25G | RTE_ETH_LINK_SPEED_50G }, /* 15422 Mezz */ + { 0x02e4, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G | + RTE_ETH_LINK_SPEED_200G }, /* 15235 PCIe */ + { 0x02f2, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G | + RTE_ETH_LINK_SPEED_50G }, /* 15425 PCIe */ + { 0x02f3, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G | + RTE_ETH_LINK_SPEED_200G }, /* 15237 MLOM */ { 0, 0 }, /* End marker */ };