From patchwork Mon Aug 12 12:49:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Mattias_R=C3=B6nnblom?= X-Patchwork-Id: 143074 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5F7BD457A1; Mon, 12 Aug 2024 14:59:44 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CB71B40698; Mon, 12 Aug 2024 14:59:14 +0200 (CEST) Received: from EUR03-DBA-obe.outbound.protection.outlook.com (mail-dbaeur03on2084.outbound.protection.outlook.com [40.107.104.84]) by mails.dpdk.org (Postfix) with ESMTP id C214840695 for ; Mon, 12 Aug 2024 14:59:10 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=P1nRFG3Uf88sPcf/WkaNH84tf4pDw18m1UlCxQg7RrpP1Z2MLv5jbE3NV2LJyYCdOwdAuWXHjQiwHKaVWkknzzWpCXZWMZuRYXnuVl50G7kYNL/NFzhRccLZu92H/meve63V5ZBsSScQGNXg9qj1fAD7Rn/WXIy1s9ZnSnq1qGWg0HAy9+EH8HDAPDHt3tCQ+fJLJ3/W6rigkE9ZhpGFpFPBet6n/I2OfRTL1Ge0EKWCKHQQ36v6fcgxwSVXcz7DIE9N0jWnR0ASXRJtg8hKnHlwfG3EHs2au+RaGAatCHPvdqDctnxQpmEVfm3fRMV47svZAfhPBr0r7ANwCJKZmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=a5WMo7gTsm2Qr9ZTxjtFLLnl+2HwDjGCyFIPlASvPhI=; b=F2Lczouat2I08c9sbfL4Wom7Xe2O3M4islFyIm44vYDBOb58FqVPJjm2Ujh8dEtwvfdT8JJixrawpM9pded9lE54MrpgMWcY+x6UpEhvh3MG+M/xg5YA0KClTPlMuvYt6EZKKTkjwBpJrYqexXWC6O7jU3kSQ5ENE95o+gTlXcjX6AZgh7VxQS6AiTwoNFYN8rRbLaN/h1WkTzcB55+GT3QQ0uBvUErhFr9Sxp97lxVybcnjm629vnjvVpt0tZvTmFnNDJ788x9XpEyqtP8VuYcw7EazR2AAjzq2fpc82pfDK9+wC92V7pLLA9U1v+1ThXbe8Qks7Jh0eGOqsL47YA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 192.176.1.74) smtp.rcpttodomain=dpdk.org smtp.mailfrom=ericsson.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=ericsson.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ericsson.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=a5WMo7gTsm2Qr9ZTxjtFLLnl+2HwDjGCyFIPlASvPhI=; b=KiRtyBZZ/eNbea9zOAnrjAmQSiAk7M58E3EpGswLf3E2PJDEZzZB/FqPs9oZsmbhVzt4bja6EI8ysjc3h5LUf+Axx+1MVf283Na2ORmi1VpsiKEcHm1StTYFDlKgS+OKTI1Vm5GOpSsPFUAM7TR0rF2CrHgNFv22oLPp+XhxE4ep4DrwEHTMDBuyPnXm7ZrU20pnVz8SffdVsvqTMKzShasIVSc4zB/TnyZtDQLyJ/+/9EZVPjXosAekMGhxzSeJ2o9WNiIoFFkgV6Dumk2NYCYmobpQ9LsTpyAaLzf+KBQc3vzOUdTm3b5EGEB5RDNImloB2QArLpLqQ7Gy5ph1XA== Received: from AS4P189CA0015.EURP189.PROD.OUTLOOK.COM (2603:10a6:20b:5d7::19) by PA4PR07MB7293.eurprd07.prod.outlook.com (2603:10a6:102:f6::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.20; Mon, 12 Aug 2024 12:59:05 +0000 Received: from AM3PEPF0000A796.eurprd04.prod.outlook.com (2603:10a6:20b:5d7:cafe::6) by AS4P189CA0015.outlook.office365.com (2603:10a6:20b:5d7::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.20 via Frontend Transport; Mon, 12 Aug 2024 12:59:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 192.176.1.74) smtp.mailfrom=ericsson.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ericsson.com; Received-SPF: Pass (protection.outlook.com: domain of ericsson.com designates 192.176.1.74 as permitted sender) receiver=protection.outlook.com; client-ip=192.176.1.74; helo=oa.msg.ericsson.com; pr=C Received: from oa.msg.ericsson.com (192.176.1.74) by AM3PEPF0000A796.mail.protection.outlook.com (10.167.16.101) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.8 via Frontend Transport; Mon, 12 Aug 2024 12:59:05 +0000 Received: from seliicinfr00049.seli.gic.ericsson.se (153.88.142.248) by smtp-central.internal.ericsson.com (100.87.178.62) with Microsoft SMTP Server id 15.2.1544.11; Mon, 12 Aug 2024 14:59:03 +0200 Received: from breslau.. (seliicwb00002.seli.gic.ericsson.se [10.156.25.100]) by seliicinfr00049.seli.gic.ericsson.se (Postfix) with ESMTP id 26F9338007D; Mon, 12 Aug 2024 14:59:03 +0200 (CEST) From: =?utf-8?q?Mattias_R=C3=B6nnblom?= To: CC: , Heng Wang , "Stephen Hemminger" , Tyler Retzlaff , =?utf-8?q?Morten_Br=C3=B8rup?= , Jack Bond-Preston , =?utf-8?q?Mattias_R?= =?utf-8?q?=C3=B6nnblom?= Subject: [PATCH v3 4/5] eal: add unit tests for atomic bit access functions Date: Mon, 12 Aug 2024 14:49:29 +0200 Message-ID: <20240812124930.604796-5-mattias.ronnblom@ericsson.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240812124930.604796-1-mattias.ronnblom@ericsson.com> References: <20240809095829.589396-2-mattias.ronnblom@ericsson.com> <20240812124930.604796-1-mattias.ronnblom@ericsson.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM3PEPF0000A796:EE_|PA4PR07MB7293:EE_ X-MS-Office365-Filtering-Correlation-Id: 60315ba9-8964-422b-134a-08dcbace8bd8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?q?kxnWA8IX+P2bniCeSgwJmSHotm+DtZA?= =?utf-8?q?syDE6nPSHi/LtYuTn1+BxN+spIal7R2T0opVDolyJKqa3e1WOFFBZlanJycwSHLT1?= =?utf-8?q?0Meq4VEvN/StqDGD9pfbI+Rylpel7bPeJSma+NRRivvg/wzPvK6g3zY3suu5a/tT2?= =?utf-8?q?JL3nOi5u95AxcO4m51V2Lz+2sCH+n5eCapo4oQmeCnr6Tg7aUml2uWkAIJJfaIn1M?= =?utf-8?q?dQ2antQExPDeEebibLUbiy1+M7x6h7rD9ZDR9G2v918duUWk8nJEnW06TLAVvZc5j?= =?utf-8?q?NqHZaNEUUrli66n6/6NDfA9YbyfOucCjHrTtNAfYCnqFUMUviaqLAGpX59AnKFHhS?= =?utf-8?q?JqTQytQTK5v1VYGcqk6RBIwvVrpUVLb7+yr5h6q5UkQMikCDC9vEvDxXc2qMOz9IG?= =?utf-8?q?qS9rsYBUed1BsnVSbSkwOuvT9EI0PbvkoF2UiziCHhBy2+IYlxlsIDMNWBhRvF8wI?= =?utf-8?q?/aaah8agzgoVCzjoWxmCO/+DafMb38beI5MOnO2m7MtbdFMSLIK+DKAyMKFhVOntl?= =?utf-8?q?yTu7m7HkbAFtkLgOEHsFsvttZQQOgl8SjwhsLWfw7BmCpf/0l3F5xXFCZ3VaaSpiq?= =?utf-8?q?wqUEyxpywIE/0qH5UOqwjVWcT8iAlO8k5OSjDiLXUpopYYOAkPT+/PsNjtbUh+Mri?= =?utf-8?q?7lhoO0ufUqa6FZhom/yGwVyTtOgjulIAtezCqMlzdP9MVIDRVkuFtY0xYLLaacrF0?= =?utf-8?q?vJAv24dR3n2P1RRup8AhmHD4foWo4qg1ODKKs4wbTvzFGFE/S0E5VKm2G38ZevAy2?= =?utf-8?q?VBMvAYI55pv77NbAm/zrNjX2mF2PNndmuqZ/KQZEbght4vwH86RA4aIjzqAuRxZEg?= =?utf-8?q?RoeD6Nj4gr5ecCB3QJCYw6MSMcOtzS5PZOnAviWq4ZhWLAur9uhqtC9HsLtLlPdY4?= =?utf-8?q?tM+yoyz9jsvzivXsiT4X2mX+AhNXO95rUFqvmx19GRaRN9r4wBa0AYYQjg6YxwzZe?= =?utf-8?q?5QDiMjuUvdhPgbt3TAYEVPZpuVhVgqkOSxVf5BxGTlIG6NcAYCJv1c0UIO/BiweKw?= =?utf-8?q?H2J+xwXaKE2I5lp7lEqUvs8+uUQXoX5uXLPUA93yL/4ugKHaygMcJxlkRuZx+LTqX?= =?utf-8?q?5+D/5LOja/oT1bw7uBjY5wxjDA6JqsrmT2UI+sIEswiFNLtH8HOSM576dh5vWveMR?= =?utf-8?q?b4dR6xfvxwYVapH2zGFAm+EMRYg5FT/0y8dILSBeD6rpOkszORlBnc0Qtk6N+gZbB?= =?utf-8?q?1LYyToAkx1KE+R3pZQ9mzGYmzOgFN2lplSaRwY7Awloc0FZ7ilqmM2FhQ3BoIHR3K?= =?utf-8?q?pUMCnHxoGs732kCNgLVqxDwAPkjmUWYEZHLCXCTq6p8d4rbhmgRQC3cHheg9IY+VI?= =?utf-8?q?yIcoHjUdlIJLEbmXvVzPXMR7xDu77KcJWg=3D=3D?= X-Forefront-Antispam-Report: CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: ericsson.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2024 12:59:05.1522 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 60315ba9-8964-422b-134a-08dcbace8bd8 X-MS-Exchange-CrossTenant-Id: 92e84ceb-fbfd-47ab-be52-080c6b87953f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74]; Helo=[oa.msg.ericsson.com] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A796.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR07MB7293 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Extend bitops tests to cover the rte_bit_atomic_*() family of functions. Signed-off-by: Mattias Rönnblom Acked-by: Morten Brørup Acked-by: Tyler Retzlaff Acked-by: Jack Bond-Preston --- RFC v4: * Add atomicity test for atomic bit flip. RFC v3: * Rename variable 'main' to make ICC happy. --- app/test/test_bitops.c | 313 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 312 insertions(+), 1 deletion(-) diff --git a/app/test/test_bitops.c b/app/test/test_bitops.c index 322f58c066..b80216a0a1 100644 --- a/app/test/test_bitops.c +++ b/app/test/test_bitops.c @@ -3,10 +3,13 @@ * Copyright(c) 2024 Ericsson AB */ +#include #include -#include #include +#include +#include +#include #include #include "test.h" @@ -61,6 +64,304 @@ GEN_TEST_BIT_ACCESS(test_bit_access32, rte_bit_set, rte_bit_clear, GEN_TEST_BIT_ACCESS(test_bit_access64, rte_bit_set, rte_bit_clear, rte_bit_assign, rte_bit_flip, rte_bit_test, 64) +#define bit_atomic_set(addr, nr) \ + rte_bit_atomic_set(addr, nr, rte_memory_order_relaxed) + +#define bit_atomic_clear(addr, nr) \ + rte_bit_atomic_clear(addr, nr, rte_memory_order_relaxed) + +#define bit_atomic_assign(addr, nr, value) \ + rte_bit_atomic_assign(addr, nr, value, rte_memory_order_relaxed) + +#define bit_atomic_flip(addr, nr) \ + rte_bit_atomic_flip(addr, nr, rte_memory_order_relaxed) + +#define bit_atomic_test(addr, nr) \ + rte_bit_atomic_test(addr, nr, rte_memory_order_relaxed) + +GEN_TEST_BIT_ACCESS(test_bit_atomic_access32, bit_atomic_set, + bit_atomic_clear, bit_atomic_assign, + bit_atomic_flip, bit_atomic_test, 32) + +GEN_TEST_BIT_ACCESS(test_bit_atomic_access64, bit_atomic_set, + bit_atomic_clear, bit_atomic_assign, + bit_atomic_flip, bit_atomic_test, 64) + +#define PARALLEL_TEST_RUNTIME 0.25 + +#define GEN_TEST_BIT_PARALLEL_ASSIGN(size) \ + \ + struct parallel_access_lcore ## size \ + { \ + unsigned int bit; \ + uint ## size ##_t *word; \ + bool failed; \ + }; \ + \ + static int \ + run_parallel_assign ## size(void *arg) \ + { \ + struct parallel_access_lcore ## size *lcore = arg; \ + uint64_t deadline = rte_get_timer_cycles() + \ + PARALLEL_TEST_RUNTIME * rte_get_timer_hz(); \ + bool value = false; \ + \ + do { \ + bool new_value = rte_rand() & 1; \ + bool use_test_and_modify = rte_rand() & 1; \ + bool use_assign = rte_rand() & 1; \ + \ + if (rte_bit_atomic_test(lcore->word, lcore->bit, \ + rte_memory_order_relaxed) != value) { \ + lcore->failed = true; \ + break; \ + } \ + \ + if (use_test_and_modify) { \ + bool old_value; \ + if (use_assign) \ + old_value = rte_bit_atomic_test_and_assign( \ + lcore->word, lcore->bit, new_value, \ + rte_memory_order_relaxed); \ + else { \ + old_value = new_value ? \ + rte_bit_atomic_test_and_set( \ + lcore->word, lcore->bit, \ + rte_memory_order_relaxed) : \ + rte_bit_atomic_test_and_clear( \ + lcore->word, lcore->bit, \ + rte_memory_order_relaxed); \ + } \ + if (old_value != value) { \ + lcore->failed = true; \ + break; \ + } \ + } else { \ + if (use_assign) \ + rte_bit_atomic_assign(lcore->word, lcore->bit, \ + new_value, \ + rte_memory_order_relaxed); \ + else { \ + if (new_value) \ + rte_bit_atomic_set( \ + lcore->word, lcore->bit, \ + rte_memory_order_relaxed); \ + else \ + rte_bit_atomic_clear( \ + lcore->word, lcore->bit, \ + rte_memory_order_relaxed); \ + } \ + } \ + \ + value = new_value; \ + } while (rte_get_timer_cycles() < deadline); \ + \ + return 0; \ + } \ + \ + static int \ + test_bit_atomic_parallel_assign ## size(void) \ + { \ + unsigned int worker_lcore_id; \ + uint ## size ## _t word = 0; \ + struct parallel_access_lcore ## size lmain = { \ + .word = &word \ + }; \ + struct parallel_access_lcore ## size lworker = { \ + .word = &word \ + }; \ + \ + if (rte_lcore_count() < 2) { \ + printf("Need multiple cores to run parallel test.\n"); \ + return TEST_SKIPPED; \ + } \ + \ + worker_lcore_id = rte_get_next_lcore(-1, 1, 0); \ + \ + lmain.bit = rte_rand_max(size); \ + do { \ + lworker.bit = rte_rand_max(size); \ + } while (lworker.bit == lmain.bit); \ + \ + int rc = rte_eal_remote_launch(run_parallel_assign ## size, \ + &lworker, worker_lcore_id); \ + TEST_ASSERT(rc == 0, "Worker thread launch failed"); \ + \ + run_parallel_assign ## size(&lmain); \ + \ + rte_eal_mp_wait_lcore(); \ + \ + TEST_ASSERT(!lmain.failed, "Main lcore atomic access failed"); \ + TEST_ASSERT(!lworker.failed, "Worker lcore atomic access " \ + "failed"); \ + \ + return TEST_SUCCESS; \ + } + +GEN_TEST_BIT_PARALLEL_ASSIGN(32) +GEN_TEST_BIT_PARALLEL_ASSIGN(64) + +#define GEN_TEST_BIT_PARALLEL_TEST_AND_MODIFY(size) \ + \ + struct parallel_test_and_set_lcore ## size \ + { \ + uint ## size ##_t *word; \ + unsigned int bit; \ + uint64_t flips; \ + }; \ + \ + static int \ + run_parallel_test_and_modify ## size(void *arg) \ + { \ + struct parallel_test_and_set_lcore ## size *lcore = arg; \ + uint64_t deadline = rte_get_timer_cycles() + \ + PARALLEL_TEST_RUNTIME * rte_get_timer_hz(); \ + do { \ + bool old_value; \ + bool new_value = rte_rand() & 1; \ + bool use_assign = rte_rand() & 1; \ + \ + if (use_assign) \ + old_value = rte_bit_atomic_test_and_assign( \ + lcore->word, lcore->bit, new_value, \ + rte_memory_order_relaxed); \ + else \ + old_value = new_value ? \ + rte_bit_atomic_test_and_set( \ + lcore->word, lcore->bit, \ + rte_memory_order_relaxed) : \ + rte_bit_atomic_test_and_clear( \ + lcore->word, lcore->bit, \ + rte_memory_order_relaxed); \ + if (old_value != new_value) \ + lcore->flips++; \ + } while (rte_get_timer_cycles() < deadline); \ + \ + return 0; \ + } \ + \ + static int \ + test_bit_atomic_parallel_test_and_modify ## size(void) \ + { \ + unsigned int worker_lcore_id; \ + uint ## size ## _t word = 0; \ + unsigned int bit = rte_rand_max(size); \ + struct parallel_test_and_set_lcore ## size lmain = { \ + .word = &word, \ + .bit = bit \ + }; \ + struct parallel_test_and_set_lcore ## size lworker = { \ + .word = &word, \ + .bit = bit \ + }; \ + \ + if (rte_lcore_count() < 2) { \ + printf("Need multiple cores to run parallel test.\n"); \ + return TEST_SKIPPED; \ + } \ + \ + worker_lcore_id = rte_get_next_lcore(-1, 1, 0); \ + \ + int rc = rte_eal_remote_launch(run_parallel_test_and_modify ## size, \ + &lworker, worker_lcore_id); \ + TEST_ASSERT(rc == 0, "Worker thread launch failed"); \ + \ + run_parallel_test_and_modify ## size(&lmain); \ + \ + rte_eal_mp_wait_lcore(); \ + \ + uint64_t total_flips = lmain.flips + lworker.flips; \ + bool expected_value = total_flips % 2; \ + \ + TEST_ASSERT(expected_value == rte_bit_test(&word, bit), \ + "After %"PRId64" flips, the bit value " \ + "should be %d", total_flips, expected_value); \ + \ + uint64_t expected_word = 0; \ + rte_bit_assign(&expected_word, bit, expected_value); \ + \ + TEST_ASSERT(expected_word == word, "Untouched bits have " \ + "changed value"); \ + \ + return TEST_SUCCESS; \ + } + +GEN_TEST_BIT_PARALLEL_TEST_AND_MODIFY(32) +GEN_TEST_BIT_PARALLEL_TEST_AND_MODIFY(64) + +#define GEN_TEST_BIT_PARALLEL_FLIP(size) \ + \ + struct parallel_flip_lcore ## size \ + { \ + uint ## size ##_t *word; \ + unsigned int bit; \ + uint64_t flips; \ + }; \ + \ + static int \ + run_parallel_flip ## size(void *arg) \ + { \ + struct parallel_flip_lcore ## size *lcore = arg; \ + uint64_t deadline = rte_get_timer_cycles() + \ + PARALLEL_TEST_RUNTIME * rte_get_timer_hz(); \ + do { \ + rte_bit_atomic_flip(lcore->word, lcore->bit, \ + rte_memory_order_relaxed); \ + lcore->flips++; \ + } while (rte_get_timer_cycles() < deadline); \ + \ + return 0; \ + } \ + \ + static int \ + test_bit_atomic_parallel_flip ## size(void) \ + { \ + unsigned int worker_lcore_id; \ + uint ## size ## _t word = 0; \ + unsigned int bit = rte_rand_max(size); \ + struct parallel_flip_lcore ## size lmain = { \ + .word = &word, \ + .bit = bit \ + }; \ + struct parallel_flip_lcore ## size lworker = { \ + .word = &word, \ + .bit = bit \ + }; \ + \ + if (rte_lcore_count() < 2) { \ + printf("Need multiple cores to run parallel test.\n"); \ + return TEST_SKIPPED; \ + } \ + \ + worker_lcore_id = rte_get_next_lcore(-1, 1, 0); \ + \ + int rc = rte_eal_remote_launch(run_parallel_flip ## size, \ + &lworker, worker_lcore_id); \ + TEST_ASSERT(rc == 0, "Worker thread launch failed"); \ + \ + run_parallel_flip ## size(&lmain); \ + \ + rte_eal_mp_wait_lcore(); \ + \ + uint64_t total_flips = lmain.flips + lworker.flips; \ + bool expected_value = total_flips % 2; \ + \ + TEST_ASSERT(expected_value == rte_bit_test(&word, bit), \ + "After %"PRId64" flips, the bit value " \ + "should be %d", total_flips, expected_value); \ + \ + uint64_t expected_word = 0; \ + rte_bit_assign(&expected_word, bit, expected_value); \ + \ + TEST_ASSERT(expected_word == word, "Untouched bits have " \ + "changed value"); \ + \ + return TEST_SUCCESS; \ + } + +GEN_TEST_BIT_PARALLEL_FLIP(32) +GEN_TEST_BIT_PARALLEL_FLIP(64) + static uint32_t val32; static uint64_t val64; @@ -177,6 +478,16 @@ static struct unit_test_suite test_suite = { .unit_test_cases = { TEST_CASE(test_bit_access32), TEST_CASE(test_bit_access64), + TEST_CASE(test_bit_access32), + TEST_CASE(test_bit_access64), + TEST_CASE(test_bit_atomic_access32), + TEST_CASE(test_bit_atomic_access64), + TEST_CASE(test_bit_atomic_parallel_assign32), + TEST_CASE(test_bit_atomic_parallel_assign64), + TEST_CASE(test_bit_atomic_parallel_test_and_modify32), + TEST_CASE(test_bit_atomic_parallel_test_and_modify64), + TEST_CASE(test_bit_atomic_parallel_flip32), + TEST_CASE(test_bit_atomic_parallel_flip64), TEST_CASE(test_bit_relaxed_set), TEST_CASE(test_bit_relaxed_clear), TEST_CASE(test_bit_relaxed_test_set_clear),