From: Anoob Joseph <anoobj@marvell.com>
Instead of calling abort() return error code so that the caller can
handle as required.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
---
drivers/common/cnxk/roc_cpt.c | 2 +-
drivers/crypto/cnxk/cn10k_ipsec.c | 12 ++++++++++--
drivers/crypto/cnxk/cn10k_tls.c | 12 ++++++++++--
3 files changed, 21 insertions(+), 5 deletions(-)
@@ -826,7 +826,7 @@ roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, void *cptr, bool inval)
if (err.s.flush_st_flt) {
plt_err("CTX flush could not complete due to store fault");
- abort();
+ return -EFAULT;
}
return 0;
@@ -135,7 +135,11 @@ cn10k_ipsec_outb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf,
}
/* Trigger CTX flush so that data is written back to DRAM */
- roc_cpt_lf_ctx_flush(lf, out_sa, false);
+ ret = roc_cpt_lf_ctx_flush(lf, out_sa, false);
+ if (ret == -EFAULT) {
+ plt_err("Could not flush outbound session");
+ goto sa_dptr_free;
+ }
sec_sess->proto = RTE_SECURITY_PROTOCOL_IPSEC;
plt_atomic_thread_fence(__ATOMIC_SEQ_CST);
@@ -236,7 +240,11 @@ cn10k_ipsec_inb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf,
}
/* Trigger CTX flush so that data is written back to DRAM */
- roc_cpt_lf_ctx_flush(lf, in_sa, true);
+ ret = roc_cpt_lf_ctx_flush(lf, in_sa, true);
+ if (ret == -EFAULT) {
+ plt_err("Could not flush inbound session");
+ goto sa_dptr_free;
+ }
sec_sess->proto = RTE_SECURITY_PROTOCOL_IPSEC;
plt_atomic_thread_fence(__ATOMIC_SEQ_CST);
@@ -707,7 +707,11 @@ cn10k_tls_read_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf,
}
/* Trigger CTX flush so that data is written back to DRAM */
- roc_cpt_lf_ctx_flush(lf, read_sa, true);
+ ret = roc_cpt_lf_ctx_flush(lf, read_sa, true);
+ if (ret == -EFAULT) {
+ plt_err("Could not flush TLS read session to hardware");
+ goto sa_dptr_free;
+ }
rte_atomic_thread_fence(rte_memory_order_seq_cst);
@@ -796,7 +800,11 @@ cn10k_tls_write_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf,
}
/* Trigger CTX flush so that data is written back to DRAM */
- roc_cpt_lf_ctx_flush(lf, write_sa, false);
+ ret = roc_cpt_lf_ctx_flush(lf, write_sa, false);
+ if (ret == -EFAULT) {
+ plt_err("Could not flush TLS write session to hardware");
+ goto sa_dptr_free;
+ }
rte_atomic_thread_fence(rte_memory_order_seq_cst);