diff mbox series

[v2] net/sxe: add net driver sxe

Message ID 20240906233821.1423-1-liujie5@linkdatatechnology.com (mailing list archive)
State Changes Requested
Delegated to: Ferruh Yigit
Headers
Series [v2] net/sxe: add net driver sxe |

Checks

Context Check Description
ci/checkpatch warning coding style issues
ci/loongarch-compilation warning apply patch failure
ci/Intel-compilation warning apply issues
ci/iol-testing warning apply patch failure

Commit Message

Jie Liu Sept. 6, 2024, 11:38 p.m. UTC 
Adjust code implementation according to code style requirements.

Signed-off-by: Jie Liu <liujie5@linkdatatechnology.com>
---
 MAINTAINERS                                |    2 +-
 doc/guides/nics/features/sxe.ini           |    1 +
 drivers/net/sxe-dpdk-0.0.0.0-src.tar.gz    |  Bin 0 -> 196888 bytes
 drivers/net/sxe.zip                        |  Bin 0 -> 193908 bytes
 drivers/net/sxe/Makefile                   |   14 +
 drivers/net/sxe/base/docker_version        |    4 -
 drivers/net/sxe/base/sxe_common.c          |   18 +-
 drivers/net/sxe/base/sxe_compat_platform.h |   23 +-
 drivers/net/sxe/base/sxe_compat_version.h  |  303 +-
 drivers/net/sxe/base/sxe_errno.h           |   78 +-
 drivers/net/sxe/base/sxe_hw.c              | 1263 +++------
 drivers/net/sxe/base/sxe_hw.h              |  928 +++---
 drivers/net/sxe/base/sxe_logs.h            |  132 +-
 drivers/net/sxe/base/sxe_offload_common.c  |    9 +-
 drivers/net/sxe/base/sxe_queue_common.c    |   97 +-
 drivers/net/sxe/base/sxe_queue_common.h    |  177 +-
 drivers/net/sxe/base/sxe_rx_common.c       |   79 +-
 drivers/net/sxe/base/sxe_rx_common.h       |    3 +-
 drivers/net/sxe/base/sxe_tx_common.c       |    6 +-
 drivers/net/sxe/base/sxe_types.h           |    2 +-
 drivers/net/sxe/base/sxevf_hw.c            |  238 +-
 drivers/net/sxe/base/sxevf_hw.h            |  139 +-
 drivers/net/sxe/base/sxevf_regs.h          |  182 +-
 drivers/net/sxe/include/drv_msg.h          |    6 +-
 drivers/net/sxe/include/sxe/mgl/sxe_port.h |   37 +-
 drivers/net/sxe/include/sxe/sxe_cli.h      |  247 +-
 drivers/net/sxe/include/sxe/sxe_hdc.h      |   46 +-
 drivers/net/sxe/include/sxe/sxe_ioctl.h    |   10 +-
 drivers/net/sxe/include/sxe/sxe_msg.h      |  124 +-
 drivers/net/sxe/include/sxe/sxe_regs.h     |  880 +++---
 drivers/net/sxe/include/sxe_type.h         |  820 +++---
 drivers/net/sxe/include/sxe_version.h      |   31 +-
 drivers/net/sxe/meson.build                |   14 +
 drivers/net/sxe/pf/sxe.h                   |   30 +-
 drivers/net/sxe/pf/sxe_dcb.c               |  147 +-
 drivers/net/sxe/pf/sxe_dcb.h               |   48 +-
 drivers/net/sxe/pf/sxe_ethdev.c            |  117 +-
 drivers/net/sxe/pf/sxe_ethdev.h            |   11 +-
 drivers/net/sxe/pf/sxe_filter.c            |  125 +-
 drivers/net/sxe/pf/sxe_filter.h            |   40 +-
 drivers/net/sxe/pf/sxe_filter_ctrl.c       | 2951 ++++++++++++++++++++
 drivers/net/sxe/pf/sxe_filter_ctrl.h       |  153 +
 drivers/net/sxe/pf/sxe_flow_ctrl.c         |   13 +-
 drivers/net/sxe/pf/sxe_flow_ctrl.h         |    6 +-
 drivers/net/sxe/pf/sxe_fnav.c              |  507 ++++
 drivers/net/sxe/pf/sxe_fnav.h              |   80 +
 drivers/net/sxe/pf/sxe_irq.c               |  116 +-
 drivers/net/sxe/pf/sxe_irq.h               |   15 +-
 drivers/net/sxe/pf/sxe_macsec.c            |  260 ++
 drivers/net/sxe/pf/sxe_macsec.h            |   20 +
 drivers/net/sxe/pf/sxe_main.c              |   27 +-
 drivers/net/sxe/pf/sxe_offload.c           |   74 +-
 drivers/net/sxe/pf/sxe_offload.h           |    4 +-
 drivers/net/sxe/pf/sxe_phy.c               |  166 +-
 drivers/net/sxe/pf/sxe_phy.h               |   57 +-
 drivers/net/sxe/pf/sxe_pmd_hdc.c           |  168 +-
 drivers/net/sxe/pf/sxe_pmd_hdc.h           |   28 +-
 drivers/net/sxe/pf/sxe_ptp.c               |   14 +-
 drivers/net/sxe/pf/sxe_ptp.h               |    4 +-
 drivers/net/sxe/pf/sxe_queue.c             |  196 +-
 drivers/net/sxe/pf/sxe_queue.h             |   34 +-
 drivers/net/sxe/pf/sxe_rx.c                |  274 +-
 drivers/net/sxe/pf/sxe_rx.h                |   41 +-
 drivers/net/sxe/pf/sxe_stats.c             |   63 +-
 drivers/net/sxe/pf/sxe_stats.h             |    8 +-
 drivers/net/sxe/pf/sxe_tm.c                | 1115 ++++++++
 drivers/net/sxe/pf/sxe_tm.h                |   59 +
 drivers/net/sxe/pf/sxe_tx.c                |  208 +-
 drivers/net/sxe/pf/sxe_tx.h                |    2 +-
 drivers/net/sxe/pf/sxe_vec_common.h        |  328 +++
 drivers/net/sxe/pf/sxe_vec_neon.c          |  606 ++++
 drivers/net/sxe/pf/sxe_vec_sse.c           |  634 +++++
 drivers/net/sxe/pf/sxe_vf.c                |  247 +-
 drivers/net/sxe/pf/sxe_vf.h                |  114 +-
 drivers/net/sxe/rte_pmd_sxe_version.map    |    2 +-
 drivers/net/sxe/version.map                |    6 +-
 drivers/net/sxe/vf/sxevf.h                 |    8 +-
 drivers/net/sxe/vf/sxevf_ethdev.c          |  169 +-
 drivers/net/sxe/vf/sxevf_filter.c          |  119 +-
 drivers/net/sxe/vf/sxevf_filter.h          |   35 +-
 drivers/net/sxe/vf/sxevf_irq.c             |   90 +-
 drivers/net/sxe/vf/sxevf_irq.h             |    4 +-
 drivers/net/sxe/vf/sxevf_main.c            |   14 +-
 drivers/net/sxe/vf/sxevf_msg.c             |   78 +-
 drivers/net/sxe/vf/sxevf_msg.h             |   76 +-
 drivers/net/sxe/vf/sxevf_queue.c           |   20 +-
 drivers/net/sxe/vf/sxevf_queue.h           |    8 +-
 drivers/net/sxe/vf/sxevf_rx.c              |   28 +-
 drivers/net/sxe/vf/sxevf_stats.c           |   14 +-
 drivers/net/sxe/vf/sxevf_tx.c              |    1 -
 90 files changed, 10798 insertions(+), 4897 deletions(-)
 create mode 100644 drivers/net/sxe-dpdk-0.0.0.0-src.tar.gz
 create mode 100644 drivers/net/sxe.zip
 delete mode 100644 drivers/net/sxe/base/docker_version
 create mode 100644 drivers/net/sxe/pf/sxe_filter_ctrl.c
 create mode 100644 drivers/net/sxe/pf/sxe_filter_ctrl.h
 create mode 100644 drivers/net/sxe/pf/sxe_fnav.c
 create mode 100644 drivers/net/sxe/pf/sxe_fnav.h
 create mode 100644 drivers/net/sxe/pf/sxe_macsec.c
 create mode 100644 drivers/net/sxe/pf/sxe_macsec.h
 create mode 100644 drivers/net/sxe/pf/sxe_tm.c
 create mode 100644 drivers/net/sxe/pf/sxe_tm.h
 create mode 100644 drivers/net/sxe/pf/sxe_vec_common.h
 create mode 100644 drivers/net/sxe/pf/sxe_vec_neon.c
 create mode 100644 drivers/net/sxe/pf/sxe_vec_sse.c

new file mode 100644
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HcmV?d00001
diff mbox series

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 03adb4036f..e3d5c35093 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -982,7 +982,7 @@  F: doc/guides/nics/sfc_efx.rst
 F: doc/guides/nics/features/sfc.ini
 
 Linkdata sxe
-M: Jie Liu <liujie5@linkdatatechnology.com>
+M: Jie Li <lijie@linkdatatechnology.com>
 F: drivers/net/sxe/
 F: doc/guides/nics/sxe.rst
 F: doc/guides/nics/features/sxe*.ini
diff --git a/doc/guides/nics/features/sxe.ini b/doc/guides/nics/features/sxe.ini
index 5a18808ccf..b61ad7c699 100644
--- a/doc/guides/nics/features/sxe.ini
+++ b/doc/guides/nics/features/sxe.ini
@@ -35,6 +35,7 @@  VLAN offload         = P
 QinQ offload         = P
 L3 checksum offload  = P
 L4 checksum offload  = P
+MACsec offload       = P
 Inner L3 checksum    = P
 Inner L4 checksum    = P
 Packet type parsing  = Y
diff --git a/drivers/net/sxe-dpdk-0.0.0.0-src.tar.gz b/drivers/net/sxe-dpdk-0.0.0.0-src.tar.gz
new file mode 100644
index 0000000000000000000000000000000000000000..44a4c97fb4812e5dfaccd076888a8c016231f80e
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literal 0
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diff --git a/drivers/net/sxe.zip b/drivers/net/sxe.zip
diff --git a/drivers/net/sxe/Makefile b/drivers/net/sxe/Makefile
index 5e2870fdc4..fd8213701d 100644
--- a/drivers/net/sxe/Makefile
+++ b/drivers/net/sxe/Makefile
@@ -13,6 +13,10 @@  CFLAGS += -DSXE_DPDK
 CFLAGS += -DSXE_HOST_DRIVER
 CFLAGS += -DSXE_DPDK_L4_FEATURES
 CFLAGS += -DSXE_DPDK_SRIOV
+CFLAGS += -DSXE_DPDK_FILTER_CTRL
+CFLAGS += -DSXE_DPDK_MACSEC
+CFLAGS += -DSXE_DPDK_TM
+CFLAGS += -DSXE_DPDK_SIMD
 CFLAGS += -O3
 CFLAGS += $(WERROR_FLAGS)
 
@@ -86,6 +90,16 @@  SRCS-$(CONFIG_RTE_LIBRTE_SXE_PMD) += sxe_stats.c
 SRCS-$(CONFIG_RTE_LIBRTE_SXE_PMD) += sxe_tx.c
 SRCS-$(CONFIG_RTE_LIBRTE_SXE_PMD) += sxe_vf.c
 
+ifeq ($(CONFIG_RTE_ARCH_ARM64),y)
+SRCS-$(CONFIG_RTE_LIBRTE_SXE_PMD) += sxe_vec_neon.c
+else
+SRCS-$(CONFIG_RTE_LIBRTE_SXE_PMD) += sxe_vec_sse.c
+endif
+SRCS-$(CONFIG_RTE_LIBRTE_SXE_PMD) += sxe_filter_ctrl.c
+SRCS-$(CONFIG_RTE_LIBRTE_SXE_PMD) += sxe_fnav.c
+SRCS-$(CONFIG_RTE_LIBRTE_SXE_PMD) += sxe_macsec.c
+SRCS-$(CONFIG_RTE_LIBRTE_SXE_PMD) += sxe_tm.c
+
 SRCS-$(CONFIG_RTE_LIBRTE_SXE_PMD) += sxevf_main.c
 SRCS-$(CONFIG_RTE_LIBRTE_SXE_PMD) += sxevf_filter.c
 SRCS-$(CONFIG_RTE_LIBRTE_SXE_PMD) += sxevf_msg.c
diff --git a/drivers/net/sxe/base/docker_version b/drivers/net/sxe/base/docker_version
deleted file mode 100644
index 33ecb22479..0000000000
--- a/drivers/net/sxe/base/docker_version
+++ /dev/null
@@ -1,4 +0,0 @@ 
-dpdk_images_v0.1:
-只包含dodk源码,源码目录：/usr/src/dpdk
-dpdk_images_v0.2：
-包含dpdk源码和build下的原生编译产物
diff --git a/drivers/net/sxe/base/sxe_common.c b/drivers/net/sxe/base/sxe_common.c
index 62f76ccf3f..0a3c53e3ca 100644
--- a/drivers/net/sxe/base/sxe_common.c
+++ b/drivers/net/sxe/base/sxe_common.c
@@ -11,9 +11,9 @@ 
 #include "sxe_common.h"
 
 #define SXE_TRACE_ID_COUNT_MASK  0x00000000000000FFLLU
-#define SXE_TRACE_ID_TID_MASK    0x0000000000FFFF00LLU
+#define SXE_TRACE_ID_TID_MASK	0x0000000000FFFF00LLU
 #define SXE_TRACE_ID_TIME_MASK   0x00FFFFFFFF000000LLU
-#define SXE_TRACE_ID_FLAG        0xFF00000000000000LLU
+#define SXE_TRACE_ID_FLAG		0xFF00000000000000LLU
 
 #define SXE_TRACE_ID_COUNT_SHIFT 0
 #define SXE_TRACE_ID_TID_SHIFT   8
@@ -22,18 +22,17 @@ 
 #define SXE_SEC_TO_MS(sec) (sec * 1000ULL)
 #define SXE_SEC_TO_NS(sec) (sec * 1000000000ULL)
 
-#define SXE_USEC_PER_MS          1000
+#define SXE_USEC_PER_MS		  1000
 
-static u64 sxe_trace_id      = 0;
+u64 sxe_trace_id;
 
 u64 sxe_time_get_real_ms(void)
 {
 	u64 ms = 0;
-	struct timeval      tv = { 0 };
+	struct timeval	  tv = { 0 };
 	s32 ret = gettimeofday(&tv, NULL);
-	if(ret < 0) {
+	if (ret < 0)
 		goto l_end;
-	}
 
 	ms = SXE_SEC_TO_MS(tv.tv_sec) + tv.tv_usec / SXE_USEC_PER_MS;
 
@@ -43,8 +42,8 @@  u64 sxe_time_get_real_ms(void)
 
 u64 sxe_trace_id_gen(void)
 {
-	u64 tid       = getpid() + (pthread_self() << 20);
-	u64 index     = 0;
+	u64 tid	   = getpid() + (pthread_self() << 20);
+	u64 index	 = 0;
 	u64 timestamp = sxe_time_get_real_ms();
 
 	sxe_trace_id = (SXE_TRACE_ID_FLAG)
@@ -57,7 +56,6 @@  u64 sxe_trace_id_gen(void)
 void sxe_trace_id_clean(void)
 {
 	sxe_trace_id = 0;
-	return;
 }
 
 u64 sxe_trace_id_get(void)
diff --git a/drivers/net/sxe/base/sxe_compat_platform.h b/drivers/net/sxe/base/sxe_compat_platform.h
index 8509f3cf0c..a870585567 100644
--- a/drivers/net/sxe/base/sxe_compat_platform.h
+++ b/drivers/net/sxe/base/sxe_compat_platform.h
@@ -19,27 +19,27 @@ 
 #ifdef SXE_TEST
 #define STATIC
 #else
-#define STATIC static
+#define static static
 #endif
 
 #ifndef DIV_ROUND_UP
-#define DIV_ROUND_UP(n, d)      (((n) + (d) - 1) / (d))
+#define DIV_ROUND_UP(n, d)	  (((n) + (d) - 1) / (d))
 #endif
 
 #define __iomem
 #define __force
 
-#define min(a,b)	RTE_MIN(a,b)
+#define min(a, b)	RTE_MIN(a, b)
 
 #ifdef __has_attribute
 #if __has_attribute(__fallthrough__)
 # define fallthrough __attribute__((__fallthrough__))
 #else
-# define fallthrough do {} while (0)  
-#endif 
+# define fallthrough do {} while (0)
+#endif
 #else
-# define fallthrough do {} while (0)  
-#endif 
+# define fallthrough do {} while (0)
+#endif
 
 #define __swab32(_value) \
 	(((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
@@ -74,7 +74,7 @@ 
 #define mdelay rte_delay_ms
 #define udelay rte_delay_us
 #define usleep_range(min, max) rte_delay_us(min)
-#define msleep(x)             rte_delay_us(x*1000)
+#define msleep(x)			 rte_delay_us(x*1000)
 
 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
 #define BIT(x)	(1UL << (x))
@@ -82,15 +82,15 @@ 
 
 #define NSEC_PER_SEC	1000000000L
 
-#define ETH_P_1588	0x88F7		
+#define ETH_P_1588	0x88F7
 
 #define VLAN_PRIO_SHIFT		13
 
 static inline void
 set_bit(unsigned long nr, void *addr)
 {
-        int *m = ((int *)addr) + (nr >> 5);
-        *m |= 1 << (nr & 31);
+	int *m = ((int *)addr) + (nr >> 5);
+	*m |= 1 << (nr & 31);
 }
 
 static inline int
@@ -137,7 +137,6 @@  static inline u32 sxe_read_addr(const volatile void *addr)
 static inline void  sxe_write_addr(u32 value, volatile void *addr)
 {
 	rte_write32((rte_cpu_to_le_32(value)), addr);
-	return;
 }
 
 #endif
diff --git a/drivers/net/sxe/base/sxe_compat_version.h b/drivers/net/sxe/base/sxe_compat_version.h
index 32d1a0862a..cf253309d8 100644
--- a/drivers/net/sxe/base/sxe_compat_version.h
+++ b/drivers/net/sxe/base/sxe_compat_version.h
@@ -19,7 +19,7 @@  int sxe_eth_dev_callback_process(struct rte_eth_dev *dev,
 
 #define __rte_cold __attribute__((cold))
 
-#define ETH_SPEED_NUM_UNKNOWN UINT32_MAX 
+#define ETH_SPEED_NUM_UNKNOWN UINT32_MAX
 #ifdef RTE_ARCH_ARM64
 #define RTE_ARCH_ARM
 #endif
@@ -38,131 +38,129 @@  int sxe_eth_dev_callback_process(struct rte_eth_dev *dev,
 
 #if defined DPDK_20_11_5 || defined DPDK_19_11_6
 
-#define    RTE_ETH_RSS_IPV4                ETH_RSS_IPV4
-#define    RTE_ETH_RSS_NONFRAG_IPV4_TCP    ETH_RSS_NONFRAG_IPV4_TCP
-#define    RTE_ETH_RSS_NONFRAG_IPV4_UDP    ETH_RSS_NONFRAG_IPV4_UDP
-#define    RTE_ETH_RSS_IPV6                ETH_RSS_IPV6
-#define    RTE_ETH_RSS_NONFRAG_IPV6_TCP    ETH_RSS_NONFRAG_IPV6_TCP
-#define    RTE_ETH_RSS_NONFRAG_IPV6_UDP    ETH_RSS_NONFRAG_IPV6_UDP
-#define    RTE_ETH_RSS_IPV6_EX             ETH_RSS_IPV6_EX
-#define    RTE_ETH_RSS_IPV6_TCP_EX         ETH_RSS_IPV6_TCP_EX
-#define    RTE_ETH_RSS_IPV6_UDP_EX         ETH_RSS_IPV6_UDP_EX
+#define	RTE_ETH_RSS_IPV4				ETH_RSS_IPV4
+#define	RTE_ETH_RSS_NONFRAG_IPV4_TCP	ETH_RSS_NONFRAG_IPV4_TCP
+#define	RTE_ETH_RSS_NONFRAG_IPV4_UDP	ETH_RSS_NONFRAG_IPV4_UDP
+#define	RTE_ETH_RSS_IPV6				ETH_RSS_IPV6
+#define	RTE_ETH_RSS_NONFRAG_IPV6_TCP	ETH_RSS_NONFRAG_IPV6_TCP
+#define	RTE_ETH_RSS_NONFRAG_IPV6_UDP	ETH_RSS_NONFRAG_IPV6_UDP
+#define	RTE_ETH_RSS_IPV6_EX			 ETH_RSS_IPV6_EX
+#define	RTE_ETH_RSS_IPV6_TCP_EX		 ETH_RSS_IPV6_TCP_EX
+#define	RTE_ETH_RSS_IPV6_UDP_EX		 ETH_RSS_IPV6_UDP_EX
 
 
-#define    RTE_ETH_VLAN_TYPE_UNKNOWN       ETH_VLAN_TYPE_UNKNOWN
-#define    RTE_ETH_VLAN_TYPE_INNER         ETH_VLAN_TYPE_INNER
-#define    RTE_ETH_VLAN_TYPE_OUTER         ETH_VLAN_TYPE_OUTER
-#define    RTE_ETH_VLAN_TYPE_MAX           ETH_VLAN_TYPE_MAX
+#define	RTE_ETH_VLAN_TYPE_UNKNOWN	   ETH_VLAN_TYPE_UNKNOWN
+#define	RTE_ETH_VLAN_TYPE_INNER		 ETH_VLAN_TYPE_INNER
+#define	RTE_ETH_VLAN_TYPE_OUTER		 ETH_VLAN_TYPE_OUTER
+#define	RTE_ETH_VLAN_TYPE_MAX		   ETH_VLAN_TYPE_MAX
 
 
-#define    RTE_ETH_8_POOLS        ETH_8_POOLS
-#define    RTE_ETH_16_POOLS       ETH_16_POOLS
-#define    RTE_ETH_32_POOLS       ETH_32_POOLS
-#define    RTE_ETH_64_POOLS       ETH_64_POOLS
+#define	RTE_ETH_8_POOLS		ETH_8_POOLS
+#define	RTE_ETH_16_POOLS	   ETH_16_POOLS
+#define	RTE_ETH_32_POOLS	   ETH_32_POOLS
+#define	RTE_ETH_64_POOLS	   ETH_64_POOLS
 
 
-#define RTE_ETH_4_TCS       ETH_4_TCS
-#define RTE_ETH_8_TCS       ETH_8_TCS
+#define RTE_ETH_4_TCS	   ETH_4_TCS
+#define RTE_ETH_8_TCS	   ETH_8_TCS
 
 
-#define RTE_ETH_MQ_RX_NONE          ETH_MQ_RX_NONE
-#define RTE_ETH_MQ_RX_RSS           ETH_MQ_RX_RSS
-#define RTE_ETH_MQ_RX_DCB           ETH_MQ_RX_DCB
-#define RTE_ETH_MQ_RX_DCB_RSS       ETH_MQ_RX_DCB_RSS
-#define RTE_ETH_MQ_RX_VMDQ_ONLY     ETH_MQ_RX_VMDQ_ONLY
-#define RTE_ETH_MQ_RX_VMDQ_RSS      ETH_MQ_RX_VMDQ_RSS
-#define RTE_ETH_MQ_RX_VMDQ_DCB      ETH_MQ_RX_VMDQ_DCB
+#define RTE_ETH_MQ_RX_NONE		  ETH_MQ_RX_NONE
+#define RTE_ETH_MQ_RX_RSS		   ETH_MQ_RX_RSS
+#define RTE_ETH_MQ_RX_DCB		   ETH_MQ_RX_DCB
+#define RTE_ETH_MQ_RX_DCB_RSS	   ETH_MQ_RX_DCB_RSS
+#define RTE_ETH_MQ_RX_VMDQ_ONLY	 ETH_MQ_RX_VMDQ_ONLY
+#define RTE_ETH_MQ_RX_VMDQ_RSS	  ETH_MQ_RX_VMDQ_RSS
+#define RTE_ETH_MQ_RX_VMDQ_DCB	  ETH_MQ_RX_VMDQ_DCB
 #define RTE_ETH_MQ_RX_VMDQ_DCB_RSS  ETH_MQ_RX_VMDQ_DCB_RSS
 
 
-#define RTE_ETH_MQ_TX_NONE          ETH_MQ_TX_NONE
-#define RTE_ETH_MQ_TX_DCB           ETH_MQ_TX_DCB
-#define RTE_ETH_MQ_TX_VMDQ_DCB      ETH_MQ_TX_VMDQ_DCB
-#define RTE_ETH_MQ_TX_VMDQ_ONLY     ETH_MQ_TX_VMDQ_ONLY
+#define RTE_ETH_MQ_TX_NONE		  ETH_MQ_TX_NONE
+#define RTE_ETH_MQ_TX_DCB		   ETH_MQ_TX_DCB
+#define RTE_ETH_MQ_TX_VMDQ_DCB	  ETH_MQ_TX_VMDQ_DCB
+#define RTE_ETH_MQ_TX_VMDQ_ONLY	 ETH_MQ_TX_VMDQ_ONLY
 
 
-#define RTE_ETH_FC_NONE         RTE_FC_NONE
-#define RTE_ETH_FC_RX_PAUSE     RTE_FC_RX_PAUSE
-#define RTE_ETH_FC_TX_PAUSE     RTE_FC_TX_PAUSE
-#define RTE_ETH_FC_FULL         RTE_FC_FULL
+#define RTE_ETH_FC_NONE		 RTE_FC_NONE
+#define RTE_ETH_FC_RX_PAUSE	 RTE_FC_RX_PAUSE
+#define RTE_ETH_FC_TX_PAUSE	 RTE_FC_TX_PAUSE
+#define RTE_ETH_FC_FULL		 RTE_FC_FULL
 
 
-#define RTE_ETH_MQ_RX_RSS_FLAG      ETH_MQ_RX_RSS_FLAG
-#define RTE_ETH_MQ_RX_DCB_FLAG      ETH_MQ_RX_DCB_FLAG
-#define RTE_ETH_MQ_RX_VMDQ_FLAG     ETH_MQ_RX_VMDQ_FLAG
+#define RTE_ETH_MQ_RX_RSS_FLAG	  ETH_MQ_RX_RSS_FLAG
+#define RTE_ETH_MQ_RX_DCB_FLAG	  ETH_MQ_RX_DCB_FLAG
+#define RTE_ETH_MQ_RX_VMDQ_FLAG	 ETH_MQ_RX_VMDQ_FLAG
 
 
-#define RTE_ETH_RX_OFFLOAD_VLAN_STRIP       DEV_RX_OFFLOAD_VLAN_STRIP
-#define RTE_ETH_RX_OFFLOAD_IPV4_CKSUM       DEV_RX_OFFLOAD_IPV4_CKSUM
-#define RTE_ETH_RX_OFFLOAD_UDP_CKSUM        DEV_RX_OFFLOAD_UDP_CKSUM
-#define RTE_ETH_RX_OFFLOAD_TCP_CKSUM        DEV_RX_OFFLOAD_TCP_CKSUM
-#define RTE_ETH_RX_OFFLOAD_TCP_LRO          DEV_RX_OFFLOAD_TCP_LRO
-#define RTE_ETH_RX_OFFLOAD_QINQ_STRIP       DEV_RX_OFFLOAD_QINQ_STRIP
+#define RTE_ETH_RX_OFFLOAD_VLAN_STRIP	   DEV_RX_OFFLOAD_VLAN_STRIP
+#define RTE_ETH_RX_OFFLOAD_IPV4_CKSUM	   DEV_RX_OFFLOAD_IPV4_CKSUM
+#define RTE_ETH_RX_OFFLOAD_UDP_CKSUM		DEV_RX_OFFLOAD_UDP_CKSUM
+#define RTE_ETH_RX_OFFLOAD_TCP_CKSUM		DEV_RX_OFFLOAD_TCP_CKSUM
+#define RTE_ETH_RX_OFFLOAD_TCP_LRO		  DEV_RX_OFFLOAD_TCP_LRO
+#define RTE_ETH_RX_OFFLOAD_QINQ_STRIP	   DEV_RX_OFFLOAD_QINQ_STRIP
 #define RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM
-#define RTE_ETH_RX_OFFLOAD_MACSEC_STRIP     DEV_RX_OFFLOAD_MACSEC_STRIP
-#define RTE_ETH_RX_OFFLOAD_VLAN_FILTER      DEV_RX_OFFLOAD_VLAN_FILTER
-#define RTE_ETH_RX_OFFLOAD_VLAN_EXTEND      DEV_RX_OFFLOAD_VLAN_EXTEND
-#define RTE_ETH_RX_OFFLOAD_SCATTER          DEV_RX_OFFLOAD_SCATTER
-#define RTE_ETH_RX_OFFLOAD_TIMESTAMP        DEV_RX_OFFLOAD_TIMESTAMP
-#define RTE_ETH_RX_OFFLOAD_SECURITY         DEV_RX_OFFLOAD_SECURITY
-#define RTE_ETH_RX_OFFLOAD_KEEP_CRC         DEV_RX_OFFLOAD_KEEP_CRC
-#define RTE_ETH_RX_OFFLOAD_SCTP_CKSUM       DEV_RX_OFFLOAD_SCTP_CKSUM
+#define RTE_ETH_RX_OFFLOAD_MACSEC_STRIP	 DEV_RX_OFFLOAD_MACSEC_STRIP
+#define RTE_ETH_RX_OFFLOAD_VLAN_FILTER	  DEV_RX_OFFLOAD_VLAN_FILTER
+#define RTE_ETH_RX_OFFLOAD_VLAN_EXTEND	  DEV_RX_OFFLOAD_VLAN_EXTEND
+#define RTE_ETH_RX_OFFLOAD_SCATTER		  DEV_RX_OFFLOAD_SCATTER
+#define RTE_ETH_RX_OFFLOAD_TIMESTAMP		DEV_RX_OFFLOAD_TIMESTAMP
+#define RTE_ETH_RX_OFFLOAD_SECURITY		 DEV_RX_OFFLOAD_SECURITY
+#define RTE_ETH_RX_OFFLOAD_KEEP_CRC		 DEV_RX_OFFLOAD_KEEP_CRC
+#define RTE_ETH_RX_OFFLOAD_SCTP_CKSUM	   DEV_RX_OFFLOAD_SCTP_CKSUM
 #define RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM
-#define RTE_ETH_RX_OFFLOAD_RSS_HASH         DEV_RX_OFFLOAD_RSS_HASH
+#define RTE_ETH_RX_OFFLOAD_RSS_HASH		 DEV_RX_OFFLOAD_RSS_HASH
 
 
-#define RTE_ETH_TX_OFFLOAD_VLAN_INSERT      DEV_TX_OFFLOAD_VLAN_INSERT
-#define RTE_ETH_TX_OFFLOAD_IPV4_CKSUM       DEV_TX_OFFLOAD_IPV4_CKSUM
-#define RTE_ETH_TX_OFFLOAD_UDP_CKSUM        DEV_TX_OFFLOAD_UDP_CKSUM
-#define RTE_ETH_TX_OFFLOAD_TCP_CKSUM        DEV_TX_OFFLOAD_TCP_CKSUM
-#define RTE_ETH_TX_OFFLOAD_SCTP_CKSUM       DEV_TX_OFFLOAD_SCTP_CKSUM
-#define RTE_ETH_TX_OFFLOAD_TCP_TSO          DEV_TX_OFFLOAD_TCP_TSO
-#define RTE_ETH_TX_OFFLOAD_UDP_TSO          DEV_TX_OFFLOAD_UDP_TSO
+#define RTE_ETH_TX_OFFLOAD_VLAN_INSERT	  DEV_TX_OFFLOAD_VLAN_INSERT
+#define RTE_ETH_TX_OFFLOAD_IPV4_CKSUM	   DEV_TX_OFFLOAD_IPV4_CKSUM
+#define RTE_ETH_TX_OFFLOAD_UDP_CKSUM		DEV_TX_OFFLOAD_UDP_CKSUM
+#define RTE_ETH_TX_OFFLOAD_TCP_CKSUM		DEV_TX_OFFLOAD_TCP_CKSUM
+#define RTE_ETH_TX_OFFLOAD_SCTP_CKSUM	   DEV_TX_OFFLOAD_SCTP_CKSUM
+#define RTE_ETH_TX_OFFLOAD_TCP_TSO		  DEV_TX_OFFLOAD_TCP_TSO
+#define RTE_ETH_TX_OFFLOAD_UDP_TSO		  DEV_TX_OFFLOAD_UDP_TSO
 #define RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM
-#define RTE_ETH_TX_OFFLOAD_QINQ_INSERT      DEV_TX_OFFLOAD_QINQ_INSERT
-#define RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO    DEV_TX_OFFLOAD_VXLAN_TNL_TSO
-#define RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO      DEV_TX_OFFLOAD_GRE_TNL_TSO
-#define RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO     DEV_TX_OFFLOAD_IPIP_TNL_TSO
+#define RTE_ETH_TX_OFFLOAD_QINQ_INSERT	  DEV_TX_OFFLOAD_QINQ_INSERT
+#define RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO	DEV_TX_OFFLOAD_VXLAN_TNL_TSO
+#define RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO	  DEV_TX_OFFLOAD_GRE_TNL_TSO
+#define RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO	 DEV_TX_OFFLOAD_IPIP_TNL_TSO
 #define RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO   DEV_TX_OFFLOAD_GENEVE_TNL_TSO
-#define RTE_ETH_TX_OFFLOAD_MACSEC_INSERT    DEV_TX_OFFLOAD_MACSEC_INSERT
-#define RTE_ETH_TX_OFFLOAD_MT_LOCKFREE      DEV_TX_OFFLOAD_MT_LOCKFREE
-#define RTE_ETH_TX_OFFLOAD_MULTI_SEGS       DEV_TX_OFFLOAD_MULTI_SEGS
+#define RTE_ETH_TX_OFFLOAD_MACSEC_INSERT	DEV_TX_OFFLOAD_MACSEC_INSERT
+#define RTE_ETH_TX_OFFLOAD_MT_LOCKFREE	  DEV_TX_OFFLOAD_MT_LOCKFREE
+#define RTE_ETH_TX_OFFLOAD_MULTI_SEGS	   DEV_TX_OFFLOAD_MULTI_SEGS
 #define RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE   DEV_TX_OFFLOAD_MBUF_FAST_FREE
-#define RTE_ETH_TX_OFFLOAD_SECURITY         DEV_TX_OFFLOAD_SECURITY
-#define RTE_ETH_TX_OFFLOAD_UDP_TNL_TSO      DEV_TX_OFFLOAD_UDP_TNL_TSO
-#define RTE_ETH_TX_OFFLOAD_IP_TNL_TSO       DEV_TX_OFFLOAD_IP_TNL_TSO
+#define RTE_ETH_TX_OFFLOAD_SECURITY		 DEV_TX_OFFLOAD_SECURITY
+#define RTE_ETH_TX_OFFLOAD_UDP_TNL_TSO	  DEV_TX_OFFLOAD_UDP_TNL_TSO
+#define RTE_ETH_TX_OFFLOAD_IP_TNL_TSO	   DEV_TX_OFFLOAD_IP_TNL_TSO
 #define RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM  DEV_TX_OFFLOAD_OUTER_UDP_CKSUM
 #define RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP
 
 
-#define RTE_ETH_LINK_SPEED_AUTONEG      ETH_LINK_SPEED_AUTONEG
-#define RTE_ETH_LINK_SPEED_FIXED        ETH_LINK_SPEED_FIXED
-#define RTE_ETH_LINK_SPEED_1G           ETH_LINK_SPEED_1G
-#define RTE_ETH_LINK_SPEED_10G          ETH_LINK_SPEED_10G
+#define RTE_ETH_LINK_SPEED_AUTONEG	  ETH_LINK_SPEED_AUTONEG
+#define RTE_ETH_LINK_SPEED_FIXED		ETH_LINK_SPEED_FIXED
+#define RTE_ETH_LINK_SPEED_1G		   ETH_LINK_SPEED_1G
+#define RTE_ETH_LINK_SPEED_10G		  ETH_LINK_SPEED_10G
 
-#define RTE_ETH_SPEED_NUM_NONE          ETH_SPEED_NUM_NONE
-#define RTE_ETH_SPEED_NUM_1G            ETH_SPEED_NUM_1G  
-#define RTE_ETH_SPEED_NUM_10G           ETH_SPEED_NUM_10G
-#define RTE_ETH_SPEED_NUM_UNKNOWN       ETH_SPEED_NUM_UNKNOWN
+#define RTE_ETH_SPEED_NUM_NONE		  ETH_SPEED_NUM_NONE
+#define RTE_ETH_SPEED_NUM_1G			ETH_SPEED_NUM_1G
+#define RTE_ETH_SPEED_NUM_10G		   ETH_SPEED_NUM_10G
+#define RTE_ETH_SPEED_NUM_UNKNOWN	   ETH_SPEED_NUM_UNKNOWN
 
 
-#define RTE_ETH_LINK_HALF_DUPLEX        ETH_LINK_HALF_DUPLEX
-#define RTE_ETH_LINK_FULL_DUPLEX        ETH_LINK_FULL_DUPLEX
-#define RTE_ETH_LINK_DOWN               ETH_LINK_DOWN       
-#define RTE_ETH_LINK_UP                 ETH_LINK_UP 
+#define RTE_ETH_LINK_HALF_DUPLEX		ETH_LINK_HALF_DUPLEX
+#define RTE_ETH_LINK_FULL_DUPLEX		ETH_LINK_FULL_DUPLEX
+#define RTE_ETH_LINK_DOWN			   ETH_LINK_DOWN
+#define RTE_ETH_LINK_UP				 ETH_LINK_UP
 
 
-#define RTE_ETH_RSS_RETA_SIZE_128       ETH_RSS_RETA_SIZE_128
-#define RTE_ETH_RETA_GROUP_SIZE         RTE_RETA_GROUP_SIZE
-
+#define RTE_ETH_RSS_RETA_SIZE_128	   ETH_RSS_RETA_SIZE_128
+#define RTE_ETH_RETA_GROUP_SIZE		 RTE_RETA_GROUP_SIZE
 
 #define RTE_ETH_VMDQ_MAX_VLAN_FILTERS   ETH_VMDQ_MAX_VLAN_FILTERS
 #define RTE_ETH_DCB_NUM_USER_PRIORITIES ETH_DCB_NUM_USER_PRIORITIES
-#define RTE_ETH_VMDQ_DCB_NUM_QUEUES     ETH_VMDQ_DCB_NUM_QUEUES
-#define RTE_ETH_DCB_NUM_QUEUES          ETH_DCB_NUM_QUEUES
-
+#define RTE_ETH_VMDQ_DCB_NUM_QUEUES	 ETH_VMDQ_DCB_NUM_QUEUES
+#define RTE_ETH_DCB_NUM_QUEUES		  ETH_DCB_NUM_QUEUES
 
-#define RTE_ETH_DCB_PFC_SUPPORT     ETH_DCB_PFC_SUPPORT
+#define RTE_ETH_DCB_PFC_SUPPORT	 ETH_DCB_PFC_SUPPORT
 
 
 #define RTE_ETH_VLAN_STRIP_OFFLOAD   ETH_VLAN_STRIP_OFFLOAD
@@ -170,74 +168,73 @@  int sxe_eth_dev_callback_process(struct rte_eth_dev *dev,
 #define RTE_ETH_VLAN_EXTEND_OFFLOAD  ETH_VLAN_EXTEND_OFFLOAD
 #define RTE_ETH_QINQ_STRIP_OFFLOAD   ETH_QINQ_STRIP_OFFLOAD
 
-#define RTE_ETH_VLAN_STRIP_MASK      ETH_VLAN_STRIP_MASK
-#define RTE_ETH_VLAN_FILTER_MASK     ETH_VLAN_FILTER_MASK
-#define RTE_ETH_VLAN_EXTEND_MASK     ETH_VLAN_EXTEND_MASK
-#define RTE_ETH_QINQ_STRIP_MASK      ETH_QINQ_STRIP_MASK
-#define RTE_ETH_VLAN_ID_MAX          ETH_VLAN_ID_MAX
+#define RTE_ETH_VLAN_STRIP_MASK	  ETH_VLAN_STRIP_MASK
+#define RTE_ETH_VLAN_FILTER_MASK	 ETH_VLAN_FILTER_MASK
+#define RTE_ETH_VLAN_EXTEND_MASK	 ETH_VLAN_EXTEND_MASK
+#define RTE_ETH_QINQ_STRIP_MASK	  ETH_QINQ_STRIP_MASK
+#define RTE_ETH_VLAN_ID_MAX		  ETH_VLAN_ID_MAX
 
 
 #define RTE_ETH_NUM_RECEIVE_MAC_ADDR   ETH_NUM_RECEIVE_MAC_ADDR
 #define RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY ETH_VMDQ_NUM_UC_HASH_ARRAY
 
-#define RTE_ETH_VMDQ_ACCEPT_UNTAG      ETH_VMDQ_ACCEPT_UNTAG
-#define RTE_ETH_VMDQ_ACCEPT_HASH_MC    ETH_VMDQ_ACCEPT_HASH_MC
-#define RTE_ETH_VMDQ_ACCEPT_HASH_UC    ETH_VMDQ_ACCEPT_HASH_UC
+#define RTE_ETH_VMDQ_ACCEPT_UNTAG	  ETH_VMDQ_ACCEPT_UNTAG
+#define RTE_ETH_VMDQ_ACCEPT_HASH_MC	ETH_VMDQ_ACCEPT_HASH_MC
+#define RTE_ETH_VMDQ_ACCEPT_HASH_UC	ETH_VMDQ_ACCEPT_HASH_UC
 #define RTE_ETH_VMDQ_ACCEPT_BROADCAST  ETH_VMDQ_ACCEPT_BROADCAST
 #define RTE_ETH_VMDQ_ACCEPT_MULTICAST  ETH_VMDQ_ACCEPT_MULTICAST
 
-#define RTE_VLAN_HLEN       4  
-
-
-#define RTE_MBUF_F_RX_VLAN                  PKT_RX_VLAN
-#define RTE_MBUF_F_RX_RSS_HASH              PKT_RX_RSS_HASH
-#define RTE_MBUF_F_RX_FDIR                  PKT_RX_FDIR
-#define RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD    PKT_RX_EIP_CKSUM_BAD
-#define RTE_MBUF_F_RX_VLAN_STRIPPED         PKT_RX_VLAN_STRIPPED
-#define RTE_MBUF_F_RX_IP_CKSUM_MASK         PKT_RX_IP_CKSUM_MASK
-#define RTE_MBUF_F_RX_IP_CKSUM_UNKNOWN      PKT_RX_IP_CKSUM_UNKNOWN
-#define RTE_MBUF_F_RX_IP_CKSUM_BAD          PKT_RX_IP_CKSUM_BAD
-#define RTE_MBUF_F_RX_IP_CKSUM_GOOD         PKT_RX_IP_CKSUM_GOOD
-#define RTE_MBUF_F_RX_IP_CKSUM_NONE         PKT_RX_IP_CKSUM_NONE
-#define RTE_MBUF_F_RX_L4_CKSUM_MASK         PKT_RX_L4_CKSUM_MASK
-#define RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN      PKT_RX_L4_CKSUM_UNKNOWN
-#define RTE_MBUF_F_RX_L4_CKSUM_BAD          PKT_RX_L4_CKSUM_BAD
-#define RTE_MBUF_F_RX_L4_CKSUM_GOOD         PKT_RX_L4_CKSUM_GOOD
-#define RTE_MBUF_F_RX_L4_CKSUM_NONE         PKT_RX_L4_CKSUM_NONE
-#define RTE_MBUF_F_RX_IEEE1588_PTP          PKT_RX_IEEE1588_PTP
-#define RTE_MBUF_F_RX_IEEE1588_TMST         PKT_RX_IEEE1588_TMST
-#define RTE_MBUF_F_RX_FDIR_ID               PKT_RX_FDIR_ID
-#define RTE_MBUF_F_RX_FDIR_FLX              PKT_RX_FDIR_FLX
-#define RTE_MBUF_F_RX_QINQ_STRIPPED         PKT_RX_QINQ_STRIPPED
-#define RTE_MBUF_F_RX_LRO                   PKT_RX_LRO
-#define RTE_MBUF_F_RX_SEC_OFFLOAD	        PKT_RX_SEC_OFFLOAD
+#define RTE_VLAN_HLEN	   4
+
+#define RTE_MBUF_F_RX_VLAN				  PKT_RX_VLAN
+#define RTE_MBUF_F_RX_RSS_HASH			  PKT_RX_RSS_HASH
+#define RTE_MBUF_F_RX_FDIR				  PKT_RX_FDIR
+#define RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD	PKT_RX_EIP_CKSUM_BAD
+#define RTE_MBUF_F_RX_VLAN_STRIPPED		 PKT_RX_VLAN_STRIPPED
+#define RTE_MBUF_F_RX_IP_CKSUM_MASK		 PKT_RX_IP_CKSUM_MASK
+#define RTE_MBUF_F_RX_IP_CKSUM_UNKNOWN	  PKT_RX_IP_CKSUM_UNKNOWN
+#define RTE_MBUF_F_RX_IP_CKSUM_BAD		  PKT_RX_IP_CKSUM_BAD
+#define RTE_MBUF_F_RX_IP_CKSUM_GOOD		 PKT_RX_IP_CKSUM_GOOD
+#define RTE_MBUF_F_RX_IP_CKSUM_NONE		 PKT_RX_IP_CKSUM_NONE
+#define RTE_MBUF_F_RX_L4_CKSUM_MASK		 PKT_RX_L4_CKSUM_MASK
+#define RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN	  PKT_RX_L4_CKSUM_UNKNOWN
+#define RTE_MBUF_F_RX_L4_CKSUM_BAD		  PKT_RX_L4_CKSUM_BAD
+#define RTE_MBUF_F_RX_L4_CKSUM_GOOD		 PKT_RX_L4_CKSUM_GOOD
+#define RTE_MBUF_F_RX_L4_CKSUM_NONE		 PKT_RX_L4_CKSUM_NONE
+#define RTE_MBUF_F_RX_IEEE1588_PTP		  PKT_RX_IEEE1588_PTP
+#define RTE_MBUF_F_RX_IEEE1588_TMST		 PKT_RX_IEEE1588_TMST
+#define RTE_MBUF_F_RX_FDIR_ID			   PKT_RX_FDIR_ID
+#define RTE_MBUF_F_RX_FDIR_FLX			  PKT_RX_FDIR_FLX
+#define RTE_MBUF_F_RX_QINQ_STRIPPED		 PKT_RX_QINQ_STRIPPED
+#define RTE_MBUF_F_RX_LRO				   PKT_RX_LRO
+#define RTE_MBUF_F_RX_SEC_OFFLOAD			PKT_RX_SEC_OFFLOAD
 #define RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED	PKT_RX_SEC_OFFLOAD_FAILED
-#define RTE_MBUF_F_RX_QINQ                  PKT_RX_QINQ
-
-#define RTE_MBUF_F_TX_SEC_OFFLOAD	        PKT_TX_SEC_OFFLOAD
-#define RTE_MBUF_F_TX_MACSEC                PKT_TX_MACSEC
-#define RTE_MBUF_F_TX_QINQ                  PKT_TX_QINQ
-#define RTE_MBUF_F_TX_TCP_SEG               PKT_TX_TCP_SEG
-#define RTE_MBUF_F_TX_IEEE1588_TMST         PKT_TX_IEEE1588_TMST
-#define RTE_MBUF_F_TX_L4_NO_CKSUM           PKT_TX_L4_NO_CKSUM
-#define RTE_MBUF_F_TX_TCP_CKSUM             PKT_TX_TCP_CKSUM
-#define RTE_MBUF_F_TX_SCTP_CKSUM            PKT_TX_SCTP_CKSUM
-#define RTE_MBUF_F_TX_UDP_CKSUM             PKT_TX_UDP_CKSUM
-#define RTE_MBUF_F_TX_L4_MASK               PKT_TX_L4_MASK
-#define RTE_MBUF_F_TX_IP_CKSUM              PKT_TX_IP_CKSUM
-#define RTE_MBUF_F_TX_IPV4                  PKT_TX_IPV4
-#define RTE_MBUF_F_TX_IPV6                  PKT_TX_IPV6
-#define RTE_MBUF_F_TX_VLAN                  PKT_TX_VLAN
-#define RTE_MBUF_F_TX_OUTER_IP_CKSUM        PKT_TX_OUTER_IP_CKSUM
-#define RTE_MBUF_F_TX_OUTER_IPV4            PKT_TX_OUTER_IPV4
-#define RTE_MBUF_F_TX_OUTER_IPV6            PKT_TX_OUTER_IPV6
-
-#define RTE_MBUF_F_TX_OFFLOAD_MASK          PKT_TX_OFFLOAD_MASK
-
-#define RTE_ETH_8_POOLS                     ETH_8_POOLS
-#define RTE_ETH_16_POOLS                    ETH_16_POOLS
-#define RTE_ETH_32_POOLS                    ETH_32_POOLS
-#define RTE_ETH_64_POOLS                    ETH_64_POOLS
+#define RTE_MBUF_F_RX_QINQ				  PKT_RX_QINQ
+
+#define RTE_MBUF_F_TX_SEC_OFFLOAD			PKT_TX_SEC_OFFLOAD
+#define RTE_MBUF_F_TX_MACSEC				PKT_TX_MACSEC
+#define RTE_MBUF_F_TX_QINQ				  PKT_TX_QINQ
+#define RTE_MBUF_F_TX_TCP_SEG			   PKT_TX_TCP_SEG
+#define RTE_MBUF_F_TX_IEEE1588_TMST		 PKT_TX_IEEE1588_TMST
+#define RTE_MBUF_F_TX_L4_NO_CKSUM		   PKT_TX_L4_NO_CKSUM
+#define RTE_MBUF_F_TX_TCP_CKSUM			 PKT_TX_TCP_CKSUM
+#define RTE_MBUF_F_TX_SCTP_CKSUM			PKT_TX_SCTP_CKSUM
+#define RTE_MBUF_F_TX_UDP_CKSUM			 PKT_TX_UDP_CKSUM
+#define RTE_MBUF_F_TX_L4_MASK			   PKT_TX_L4_MASK
+#define RTE_MBUF_F_TX_IP_CKSUM			  PKT_TX_IP_CKSUM
+#define RTE_MBUF_F_TX_IPV4				  PKT_TX_IPV4
+#define RTE_MBUF_F_TX_IPV6				  PKT_TX_IPV6
+#define RTE_MBUF_F_TX_VLAN				  PKT_TX_VLAN
+#define RTE_MBUF_F_TX_OUTER_IP_CKSUM		PKT_TX_OUTER_IP_CKSUM
+#define RTE_MBUF_F_TX_OUTER_IPV4			PKT_TX_OUTER_IPV4
+#define RTE_MBUF_F_TX_OUTER_IPV6			PKT_TX_OUTER_IPV6
+
+#define RTE_MBUF_F_TX_OFFLOAD_MASK		  PKT_TX_OFFLOAD_MASK
+
+#define RTE_ETH_8_POOLS					 ETH_8_POOLS
+#define RTE_ETH_16_POOLS					ETH_16_POOLS
+#define RTE_ETH_32_POOLS					ETH_32_POOLS
+#define RTE_ETH_64_POOLS					ETH_64_POOLS
 
 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
 #define RTE_ETHDEV_DEBUG_RX
@@ -248,7 +245,7 @@  int sxe_eth_dev_callback_process(struct rte_eth_dev *dev,
 
 #if defined DPDK_20_11_5 || defined DPDK_19_11_6
 #define rte_eth_fdir_pballoc_type   rte_fdir_pballoc_type
-#define rte_eth_fdir_conf 			rte_fdir_conf
+#define rte_eth_fdir_conf			rte_fdir_conf
 
 #define RTE_ETH_FDIR_PBALLOC_64K   RTE_FDIR_PBALLOC_64K
 #define RTE_ETH_FDIR_PBALLOC_128K  RTE_FDIR_PBALLOC_128K
@@ -261,15 +258,15 @@  int sxe_eth_dev_callback_process(struct rte_eth_dev *dev,
 	(&((pci_dev)->intr_handle))
 
 #define SXE_DEV_FNAV_CONF(dev) \
-	(&((dev)->data->dev_conf.fdir_conf)) 
+	(&((dev)->data->dev_conf.fdir_conf))
 #define SXE_GET_FRAME_SIZE(dev) \
 	(dev->data->dev_conf.rxmode.max_rx_pkt_len)
-	
+
 #elif defined DPDK_21_11_5
 #define SXE_PCI_INTR_HANDLE(pci_dev) \
 	((pci_dev)->intr_handle)
 #define SXE_DEV_FNAV_CONF(dev) \
-	(&((dev)->data->dev_conf.fdir_conf)) 
+	(&((dev)->data->dev_conf.fdir_conf))
 #define SXE_GET_FRAME_SIZE(dev) \
 	(dev->data->mtu + SXE_ETH_OVERHEAD)
 
@@ -277,7 +274,7 @@  int sxe_eth_dev_callback_process(struct rte_eth_dev *dev,
 #define SXE_PCI_INTR_HANDLE(pci_dev) \
 	((pci_dev)->intr_handle)
 #define SXE_DEV_FNAV_CONF(dev) \
-	(&((struct sxe_adapter *)(dev)->data->dev_private)->fnav_conf) 
+	(&((struct sxe_adapter *)(dev)->data->dev_private)->fnav_conf)
 #define RTE_ADAPTER_HAVE_FNAV_CONF
 #define SXE_GET_FRAME_SIZE(dev) \
 	(dev->data->mtu + SXE_ETH_OVERHEAD)
diff --git a/drivers/net/sxe/base/sxe_errno.h b/drivers/net/sxe/base/sxe_errno.h
index e4de8bef29..3d14e0794c 100644
--- a/drivers/net/sxe/base/sxe_errno.h
+++ b/drivers/net/sxe/base/sxe_errno.h
@@ -17,45 +17,45 @@ 
 #define SXE_ERR_VF(errcode)		SXE_ERR_MODULE(SXE_ERR_MODULE_VF, errcode)
 #define SXE_ERR_HDC(errcode)	SXE_ERR_MODULE(SXE_ERR_MODULE_HDC, errcode)
 
-#define SXE_ERR_CONFIG                        EINVAL
-#define SXE_ERR_PARAM                         EINVAL
-#define SXE_ERR_RESET_FAILED                  EPERM
-#define SXE_ERR_NO_SPACE                      ENOSPC
-#define SXE_ERR_FNAV_CMD_INCOMPLETE           EBUSY
-#define SXE_ERR_MBX_LOCK_FAIL                 EBUSY
-#define SXE_ERR_OPRATION_NOT_PERM             EPERM
-#define SXE_ERR_LINK_STATUS_INVALID           EINVAL
-#define SXE_ERR_LINK_SPEED_INVALID            EINVAL
-#define SXE_ERR_DEVICE_NOT_SUPPORTED          EOPNOTSUPP
-#define SXE_ERR_HDC_LOCK_BUSY                 EBUSY
-#define SXE_ERR_HDC_FW_OV_TIMEOUT             ETIMEDOUT
-#define SXE_ERR_MDIO_CMD_TIMEOUT              ETIMEDOUT
-#define SXE_ERR_INVALID_LINK_SETTINGS         EINVAL
-#define SXE_ERR_FNAV_REINIT_FAILED            EIO
-#define SXE_ERR_CLI_FAILED                    EIO
-#define SXE_ERR_MASTER_REQUESTS_PENDING       SXE_ERR_PF(1)
-#define SXE_ERR_SFP_NO_INIT_SEQ_PRESENT       SXE_ERR_PF(2)
-#define SXE_ERR_ENABLE_SRIOV_FAIL             SXE_ERR_PF(3)
-#define SXE_ERR_IPSEC_SA_STATE_NOT_EXSIT      SXE_ERR_PF(4)
-#define SXE_ERR_SFP_NOT_PERSENT               SXE_ERR_PF(5)
-#define SXE_ERR_PHY_NOT_PERSENT               SXE_ERR_PF(6)
-#define SXE_ERR_PHY_RESET_FAIL                SXE_ERR_PF(7)
-#define SXE_ERR_FC_NOT_NEGOTIATED             SXE_ERR_PF(8)
-#define SXE_ERR_SFF_NOT_SUPPORTED             SXE_ERR_PF(9)
+#define SXE_ERR_CONFIG						EINVAL
+#define SXE_ERR_PARAM						 EINVAL
+#define SXE_ERR_RESET_FAILED				  EPERM
+#define SXE_ERR_NO_SPACE					  ENOSPC
+#define SXE_ERR_FNAV_CMD_INCOMPLETE		   EBUSY
+#define SXE_ERR_MBX_LOCK_FAIL				 EBUSY
+#define SXE_ERR_OPRATION_NOT_PERM			 EPERM
+#define SXE_ERR_LINK_STATUS_INVALID		   EINVAL
+#define SXE_ERR_LINK_SPEED_INVALID			EINVAL
+#define SXE_ERR_DEVICE_NOT_SUPPORTED		  EOPNOTSUPP
+#define SXE_ERR_HDC_LOCK_BUSY				 EBUSY
+#define SXE_ERR_HDC_FW_OV_TIMEOUT			 ETIMEDOUT
+#define SXE_ERR_MDIO_CMD_TIMEOUT			  ETIMEDOUT
+#define SXE_ERR_INVALID_LINK_SETTINGS		 EINVAL
+#define SXE_ERR_FNAV_REINIT_FAILED			EIO
+#define SXE_ERR_CLI_FAILED					EIO
+#define SXE_ERR_MASTER_REQUESTS_PENDING	   SXE_ERR_PF(1)
+#define SXE_ERR_SFP_NO_INIT_SEQ_PRESENT	   SXE_ERR_PF(2)
+#define SXE_ERR_ENABLE_SRIOV_FAIL			 SXE_ERR_PF(3)
+#define SXE_ERR_IPSEC_SA_STATE_NOT_EXSIT	  SXE_ERR_PF(4)
+#define SXE_ERR_SFP_NOT_PERSENT			   SXE_ERR_PF(5)
+#define SXE_ERR_PHY_NOT_PERSENT			   SXE_ERR_PF(6)
+#define SXE_ERR_PHY_RESET_FAIL				SXE_ERR_PF(7)
+#define SXE_ERR_FC_NOT_NEGOTIATED			 SXE_ERR_PF(8)
+#define SXE_ERR_SFF_NOT_SUPPORTED			 SXE_ERR_PF(9)
 
-#define SXEVF_ERR_MAC_ADDR_INVALID              EINVAL
-#define SXEVF_ERR_RESET_FAILED                  EIO
-#define SXEVF_ERR_ARGUMENT_INVALID              EINVAL
-#define SXEVF_ERR_NOT_READY                     EBUSY
-#define SXEVF_ERR_POLL_ACK_FAIL                 EIO
-#define SXEVF_ERR_POLL_MSG_FAIL                 EIO
-#define SXEVF_ERR_MBX_LOCK_FAIL                 EBUSY
-#define SXEVF_ERR_REPLY_INVALID                 EINVAL
-#define SXEVF_ERR_IRQ_NUM_INVALID               EINVAL
-#define SXEVF_ERR_PARAM                         EINVAL
-#define SXEVF_ERR_MAILBOX_FAIL                  SXE_ERR_VF(1)
-#define SXEVF_ERR_MSG_HANDLE_ERR                SXE_ERR_VF(2)
-#define SXEVF_ERR_DEVICE_NOT_SUPPORTED          SXE_ERR_VF(3)
-#define SXEVF_ERR_IPSEC_SA_STATE_NOT_EXSIT      SXE_ERR_VF(4)
+#define SXEVF_ERR_MAC_ADDR_INVALID			  EINVAL
+#define SXEVF_ERR_RESET_FAILED				  EIO
+#define SXEVF_ERR_ARGUMENT_INVALID			  EINVAL
+#define SXEVF_ERR_NOT_READY					 EBUSY
+#define SXEVF_ERR_POLL_ACK_FAIL				 EIO
+#define SXEVF_ERR_POLL_MSG_FAIL				 EIO
+#define SXEVF_ERR_MBX_LOCK_FAIL				 EBUSY
+#define SXEVF_ERR_REPLY_INVALID				 EINVAL
+#define SXEVF_ERR_IRQ_NUM_INVALID			   EINVAL
+#define SXEVF_ERR_PARAM						 EINVAL
+#define SXEVF_ERR_MAILBOX_FAIL				  SXE_ERR_VF(1)
+#define SXEVF_ERR_MSG_HANDLE_ERR				SXE_ERR_VF(2)
+#define SXEVF_ERR_DEVICE_NOT_SUPPORTED		  SXE_ERR_VF(3)
+#define SXEVF_ERR_IPSEC_SA_STATE_NOT_EXSIT	  SXE_ERR_VF(4)
 
 #endif
diff --git a/drivers/net/sxe/base/sxe_hw.c b/drivers/net/sxe/base/sxe_hw.c
index 14d1d67456..78c56d2bd9 100644
--- a/drivers/net/sxe/base/sxe_hw.c
+++ b/drivers/net/sxe/base/sxe_hw.c
@@ -4,7 +4,7 @@ 
 #ifdef SXE_PHY_CONFIGURE
 #include <linux/mdio.h>
 #endif
-#if defined (__KERNEL__) || defined (SXE_KERNEL_TEST)
+#if defined(__KERNEL__) || defined(SXE_KERNEL_TEST)
 #include "sxe_pci.h"
 #include "sxe_log.h"
 #include "sxe_debug.h"
@@ -24,25 +24,25 @@ 
 
 #define SXE_MSGID_MASK  (0xFFFFFFFF)
 
-#define SXE_CTRL_MSG_MASK          (0x700)
+#define SXE_CTRL_MSG_MASK		  (0x700)
 
-#define SXE_RING_WAIT_LOOP        10
-#define SXE_REG_NAME_LEN          16
+#define SXE_RING_WAIT_LOOP		10
+#define SXE_REG_NAME_LEN		  16
 #define SXE_DUMP_REG_STRING_LEN   73
-#define SXE_DUMP_REGS_NUM         64
-#define SXE_MAX_RX_DESC_POLL      10
-#define SXE_LPBK_EN               0x00000001
-#define SXE_MACADDR_LOW_4_BYTE    4
+#define SXE_DUMP_REGS_NUM		 64
+#define SXE_MAX_RX_DESC_POLL	  10
+#define SXE_LPBK_EN			   0x00000001
+#define SXE_MACADDR_LOW_4_BYTE	4
 #define SXE_MACADDR_HIGH_2_BYTE   2
-#define SXE_RSS_FIELD_MASK        0xffff0000
-#define SXE_MRQE_MASK             0x0000000f
+#define SXE_RSS_FIELD_MASK		0xffff0000
+#define SXE_MRQE_MASK			 0x0000000f
 
-#define SXE_HDC_DATA_LEN_MAX         256
+#define SXE_HDC_DATA_LEN_MAX		 256
 
 #define SXE_8_TC_MSB				(0x11111111)
 
-STATIC u32 sxe_read_reg(struct sxe_hw *hw, u32 reg);
-STATIC void sxe_write_reg(struct sxe_hw *hw, u32 reg, u32 value);
+static u32 sxe_read_reg(struct sxe_hw *hw, u32 reg);
+static void sxe_write_reg(struct sxe_hw *hw, u32 reg, u32 value);
 static void sxe_write_reg64(struct sxe_hw *hw, u32 reg, u64 value);
 
 #define SXE_WRITE_REG_ARRAY_32(a, reg, offset, value) \
@@ -50,7 +50,7 @@  static void sxe_write_reg64(struct sxe_hw *hw, u32 reg, u64 value);
 #define SXE_READ_REG_ARRAY_32(a, reg, offset) \
 	sxe_read_reg(a, reg + (offset << 2))
 
-#define SXE_REG_READ(hw, addr)        sxe_read_reg(hw, addr)
+#define SXE_REG_READ(hw, addr)		sxe_read_reg(hw, addr)
 #define SXE_REG_WRITE(hw, reg, value) sxe_write_reg(hw, reg, value)
 #define SXE_WRITE_FLUSH(a) sxe_read_reg(a, SXE_STATUS)
 #define SXE_REG_WRITE_ARRAY(hw, reg, offset, value) \
@@ -90,26 +90,21 @@  u16 sxe_mac_reg_num_get(void)
 }
 
 
-#ifndef SXE_DPDK 
+#ifndef SXE_DPDK
 
 void sxe_hw_fault_handle(struct sxe_hw *hw)
 {
 	struct sxe_adapter *adapter = hw->adapter;
 
-	if (test_bit(SXE_HW_FAULT, &hw->state)) {
-		goto l_ret;
-	}
+	if (test_bit(SXE_HW_FAULT, &hw->state))
+		return;
 
 	set_bit(SXE_HW_FAULT, &hw->state);
 
 	LOG_DEV_ERR("sxe nic hw fault\n");
 
-	if ((hw->fault_handle != NULL) && (hw->priv != NULL) ) {
+	if ((hw->fault_handle != NULL) && (hw->priv != NULL))
 		hw->fault_handle(hw->priv);
-	}
-
-l_ret:
-	return;
 }
 
 static u32 sxe_hw_fault_check(struct sxe_hw *hw, u32 reg)
@@ -118,32 +113,29 @@  static u32 sxe_hw_fault_check(struct sxe_hw *hw, u32 reg)
 	u8  __iomem *base_addr = hw->reg_base_addr;
 	struct sxe_adapter *adapter = hw->adapter;
 
-	if (sxe_is_hw_fault(hw)) {
+	if (sxe_is_hw_fault(hw))
 		goto l_out;
-	}
 
 	for (i = 0; i < SXE_REG_READ_RETRY; i++) {
 		value = hw->reg_read(base_addr + SXE_STATUS);
-		if (value != SXE_REG_READ_FAIL) {
+		if (value != SXE_REG_READ_FAIL)
 			break;
-		}
 
 		mdelay(3);
 	}
 
-	if (SXE_REG_READ_FAIL == value) {
+	if (value == SXE_REG_READ_FAIL) {
 		LOG_ERROR_BDF("read registers multiple times failed, ret=%#x\n", value);
 		sxe_hw_fault_handle(hw);
-	} else {
+	} else
 		value = hw->reg_read(base_addr + reg);
-	}
 
 	return value;
 l_out:
 	return SXE_REG_READ_FAIL;
 }
 
-STATIC u32 sxe_read_reg(struct sxe_hw *hw, u32 reg)
+static u32 sxe_read_reg(struct sxe_hw *hw, u32 reg)
 {
 	u32 value;
 	u8  __iomem *base_addr = hw->reg_base_addr;
@@ -155,7 +147,7 @@  STATIC u32 sxe_read_reg(struct sxe_hw *hw, u32 reg)
 	}
 
 	value = hw->reg_read(base_addr + reg);
-	if (unlikely(SXE_REG_READ_FAIL == value)) {
+	if (unlikely(value == SXE_REG_READ_FAIL)) {
 		LOG_ERROR_BDF("reg[0x%x] read failed, ret=%#x\n", reg, value);
 		value = sxe_hw_fault_check(hw, reg);
 	}
@@ -164,32 +156,29 @@  STATIC u32 sxe_read_reg(struct sxe_hw *hw, u32 reg)
 	return value;
 }
 
-STATIC void sxe_write_reg(struct sxe_hw *hw, u32 reg, u32 value)
+static void sxe_write_reg(struct sxe_hw *hw, u32 reg, u32 value)
 {
 	u8 __iomem *base_addr = hw->reg_base_addr;
 
-	if (sxe_is_hw_fault(hw)) {
-		goto l_ret;
-	}
+	if (sxe_is_hw_fault(hw))
+		return;
 
 	hw->reg_write(value, base_addr + reg);
 
-l_ret:
-	return;
 }
 
-#else 
+#else
 
-STATIC u32 sxe_read_reg(struct sxe_hw *hw, u32 reg)
+static u32 sxe_read_reg(struct sxe_hw *hw, u32 reg)
 {
 	u32 i, value;
 	u8  __iomem *base_addr = hw->reg_base_addr;
 
 	value = rte_le_to_cpu_32(rte_read32(base_addr + reg));
-	if (unlikely(SXE_REG_READ_FAIL == value)) {
+	if (unlikely(value == SXE_REG_READ_FAIL)) {
 
 		value = rte_le_to_cpu_32(rte_read32(base_addr + SXE_STATUS));
-		if (unlikely(SXE_REG_READ_FAIL != value)) {
+		if (unlikely(value != SXE_REG_READ_FAIL)) {
 
 			value = rte_le_to_cpu_32(rte_read32(base_addr + reg));
 		} else {
@@ -198,16 +187,15 @@  STATIC u32 sxe_read_reg(struct sxe_hw *hw, u32 reg)
 			for (i = 0; i < SXE_REG_READ_RETRY; i++) {
 
 				value = rte_le_to_cpu_32(rte_read32(base_addr + SXE_STATUS));
-				if (unlikely(SXE_REG_READ_FAIL != value)) {
+				if (unlikely(value != SXE_REG_READ_FAIL)) {
 
 					value = rte_le_to_cpu_32(rte_read32(base_addr + reg));
 					LOG_INFO("reg[0x%x] read ok, value=%#x\n",
 									reg, value);
 					break;
-				} else {
-					LOG_ERROR("reg[0x%x] and reg[0x%x] read failed, ret=%#x\n",
-							reg, SXE_STATUS, value);
 				}
+				LOG_ERROR("reg[0x%x] and reg[0x%x] read failed, ret=%#x\n",
+						reg, SXE_STATUS, value);
 
 				mdelay(3);
 			}
@@ -217,13 +205,12 @@  STATIC u32 sxe_read_reg(struct sxe_hw *hw, u32 reg)
 	return value;
 }
 
-STATIC void sxe_write_reg(struct sxe_hw *hw, u32 reg, u32 value)
+static void sxe_write_reg(struct sxe_hw *hw, u32 reg, u32 value)
 {
 	u8 __iomem *base_addr = hw->reg_base_addr;
 
 	rte_write32((rte_cpu_to_le_32(value)), (base_addr + reg));
 
-	return;
 }
 #endif
 
@@ -231,14 +218,11 @@  static void sxe_write_reg64(struct sxe_hw *hw, u32 reg, u64 value)
 {
 	u8 __iomem *reg_addr = hw->reg_base_addr;
 
-	if (sxe_is_hw_fault(hw)) {
-		goto l_ret;
-	}
+	if (sxe_is_hw_fault(hw))
+		return;
 
 	writeq(value, reg_addr + reg);
 
-l_ret:
-	return;
 }
 
 
@@ -251,7 +235,6 @@  void sxe_hw_no_snoop_disable(struct sxe_hw *hw)
 	SXE_REG_WRITE(hw, SXE_CTRL_EXT, ctrl_ext);
 	SXE_WRITE_FLUSH(hw);
 
-	return;
 }
 
 s32 sxe_hw_uc_addr_pool_enable(struct sxe_hw *hw,
@@ -291,21 +274,19 @@  static s32 sxe_hw_uc_addr_pool_disable(struct sxe_hw *hw, u8 rar_idx)
 	hi = SXE_REG_READ(hw, SXE_MPSAR_HIGH(rar_idx));
 	low = SXE_REG_READ(hw, SXE_MPSAR_LOW(rar_idx));
 
-	if (sxe_is_hw_fault(hw)) {
+	if (sxe_is_hw_fault(hw))
 		goto l_end;
-	}
 
 	if (!hi & !low) {
 		LOG_DEBUG_BDF("no need clear rar-pool relation register.\n");
 		goto l_end;
 	}
 
-	if (low) {
+	if (low)
 		SXE_REG_WRITE(hw, SXE_MPSAR_LOW(rar_idx), 0);
-	}
-	if (hi) {
+
+	if (hi)
 		SXE_REG_WRITE(hw, SXE_MPSAR_HIGH(rar_idx), 0);
-	}
 
 
 l_end:
@@ -328,9 +309,9 @@  s32 sxe_hw_nic_reset(struct sxe_hw *hw)
 
 	for (i = 0; i < 10; i++) {
 		ctrl = SXE_REG_READ(hw, SXE_CTRL);
-		if (!(ctrl & SXE_CTRL_RST_MASK)) {
+		if (!(ctrl & SXE_CTRL_RST_MASK))
 			break;
-		}
+
 		udelay(1);
 	}
 
@@ -350,13 +331,11 @@  void sxe_hw_pf_rst_done_set(struct sxe_hw *hw)
 	value |= SXE_CTRL_EXT_PFRSTD;
 	SXE_REG_WRITE(hw, SXE_CTRL_EXT, value);
 
-	return;
 }
 
 static void sxe_hw_regs_flush(struct sxe_hw *hw)
 {
 	SXE_WRITE_FLUSH(hw);
-	return;
 }
 
 static const struct sxe_reg_info sxe_reg_info_tbl[] = {
@@ -397,74 +376,74 @@  static void sxe_hw_reg_print(struct sxe_hw *hw,
 
 	switch (reginfo->addr) {
 	case SXE_SRRCTL(0):
-		for (i = 0; i < SXE_DUMP_REGS_NUM; i++) {
+		for (i = 0; i < SXE_DUMP_REGS_NUM; i++)
 			regs[i] = SXE_REG_READ(hw, SXE_SRRCTL(i));
-		}
+
 		break;
 	case SXE_RDLEN(0):
-		for (i = 0; i < SXE_DUMP_REGS_NUM; i++) {
+		for (i = 0; i < SXE_DUMP_REGS_NUM; i++)
 			regs[i] = SXE_REG_READ(hw, SXE_RDLEN(i));
-		}
+
 		break;
 	case SXE_RDH(0):
-		for (i = 0; i < SXE_DUMP_REGS_NUM; i++) {
+		for (i = 0; i < SXE_DUMP_REGS_NUM; i++)
 			regs[i] = SXE_REG_READ(hw, SXE_RDH(i));
-		}
+
 		break;
 	case SXE_RDT(0):
-		for (i = 0; i < SXE_DUMP_REGS_NUM; i++) {
+		for (i = 0; i < SXE_DUMP_REGS_NUM; i++)
 			regs[i] = SXE_REG_READ(hw, SXE_RDT(i));
-		}
+
 		break;
 	case SXE_RXDCTL(0):
-		for (i = 0; i < SXE_DUMP_REGS_NUM; i++) {
+		for (i = 0; i < SXE_DUMP_REGS_NUM; i++)
 			regs[i] = SXE_REG_READ(hw, SXE_RXDCTL(i));
-		}
+
 		break;
 	case SXE_RDBAL(0):
-		for (i = 0; i < SXE_DUMP_REGS_NUM; i++) {
+		for (i = 0; i < SXE_DUMP_REGS_NUM; i++)
 			regs[i] = SXE_REG_READ(hw, SXE_RDBAL(i));
-		}
+
 		break;
 	case SXE_RDBAH(0):
-		for (i = 0; i < SXE_DUMP_REGS_NUM; i++) {
+		for (i = 0; i < SXE_DUMP_REGS_NUM; i++)
 			regs[i] = SXE_REG_READ(hw, SXE_RDBAH(i));
-		}
+
 		break;
 	case SXE_TDBAL(0):
-		for (i = 0; i < SXE_DUMP_REGS_NUM; i++) {
+		for (i = 0; i < SXE_DUMP_REGS_NUM; i++)
 			regs[i] = SXE_REG_READ(hw, SXE_TDBAL(i));
-		}
+
 		break;
 	case SXE_TDBAH(0):
-		for (i = 0; i < SXE_DUMP_REGS_NUM; i++) {
+		for (i = 0; i < SXE_DUMP_REGS_NUM; i++)
 			regs[i] = SXE_REG_READ(hw, SXE_TDBAH(i));
-		}
+
 		break;
 	case SXE_TDLEN(0):
-		for (i = 0; i < SXE_DUMP_REGS_NUM; i++) {
+		for (i = 0; i < SXE_DUMP_REGS_NUM; i++)
 			regs[i] = SXE_REG_READ(hw, SXE_TDLEN(i));
-		}
+
 		break;
 	case SXE_TDH(0):
-		for (i = 0; i < SXE_DUMP_REGS_NUM; i++) {
+		for (i = 0; i < SXE_DUMP_REGS_NUM; i++)
 			regs[i] = SXE_REG_READ(hw, SXE_TDH(i));
-		}
+
 		break;
 	case SXE_TDT(0):
-		for (i = 0; i < SXE_DUMP_REGS_NUM; i++) {
+		for (i = 0; i < SXE_DUMP_REGS_NUM; i++)
 			regs[i] = SXE_REG_READ(hw, SXE_TDT(i));
-		}
+
 		break;
 	case SXE_TXDCTL(0):
-		for (i = 0; i < SXE_DUMP_REGS_NUM; i++) {
+		for (i = 0; i < SXE_DUMP_REGS_NUM; i++)
 			regs[i] = SXE_REG_READ(hw, SXE_TXDCTL(i));
-		}
+
 		break;
 	default:
 		LOG_DEV_INFO("%-15s %08x\n",
 			reginfo->name, SXE_REG_READ(hw, reginfo->addr));
-		goto l_end;
+		return;
 	}
 
 	while (first_reg_idx < SXE_DUMP_REGS_NUM) {
@@ -473,15 +452,12 @@  static void sxe_hw_reg_print(struct sxe_hw *hw,
 			"%s[%d-%d]", reginfo->name,
 			first_reg_idx, (first_reg_idx + 7));
 
-		for (j = 0; j < 8; j++) {
+		for (j = 0; j < 8; j++)
 			value += sprintf(value, " %08x", regs[first_reg_idx++]);
-		}
 
 		LOG_DEV_ERR("%-15s%s\n", reg_name, buf);
 	}
 
-l_end:
-	return;
 }
 
 static void sxe_hw_reg_dump(struct sxe_hw *hw)
@@ -489,11 +465,10 @@  static void sxe_hw_reg_dump(struct sxe_hw *hw)
 	const struct sxe_reg_info *reginfo;
 
 	for (reginfo = (const struct sxe_reg_info *)sxe_reg_info_tbl;
-	     reginfo->name; reginfo++) {
+		 reginfo->name; reginfo++) {
 		sxe_hw_reg_print(hw, reginfo);
 	}
 
-	return;
 }
 
 static s32 sxe_hw_status_reg_test(struct sxe_hw *hw)
@@ -539,22 +514,22 @@  struct sxe_self_test_reg {
 static const struct sxe_self_test_reg self_test_reg[] = {
 	{ SXE_FCRTL(0),  1,   PATTERN_TEST, 0x8007FFE0, 0x8007FFF0 },
 	{ SXE_FCRTH(0),  1,   PATTERN_TEST, 0x8007FFE0, 0x8007FFF0 },
-	{ SXE_PFCTOP,    1,   PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
+	{ SXE_PFCTOP,	1,   PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 	{ SXE_FCTTV(0),  1,   PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 	{ SXE_VLNCTRL,   1,   PATTERN_TEST, 0x00000000, 0x00000000 },
 	{ SXE_RDBAL(0),  4,   PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
 	{ SXE_RDBAH(0),  4,   PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 	{ SXE_RDLEN(0),  4,   PATTERN_TEST, 0x000FFFFF, 0x000FFFFF },
 	{ SXE_RXDCTL(0), 4,   WRITE_NO_TEST, 0, SXE_RXDCTL_ENABLE },
-	{ SXE_RDT(0),    4,   PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
+	{ SXE_RDT(0),	4,   PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 	{ SXE_RXDCTL(0), 4,   WRITE_NO_TEST, 0, 0 },
 	{ SXE_TDBAL(0),  4,   PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 	{ SXE_TDBAH(0),  4,   PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 	{ SXE_TDLEN(0),  4,   PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
-	{ SXE_RXCTRL,    1,   SET_READ_TEST, 0x00000001, 0x00000001 },
-	{ SXE_RAL(0),    16,  TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
-	{ SXE_RAL(0),    16,  TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
-	{ SXE_MTA(0),    128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
+	{ SXE_RXCTRL,	1,   SET_READ_TEST, 0x00000001, 0x00000001 },
+	{ SXE_RAL(0),	16,  TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
+	{ SXE_RAL(0),	16,  TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
+	{ SXE_MTA(0),	128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 	{ .reg = 0 }
 };
 
@@ -625,7 +600,7 @@  static s32 sxe_hw_reg_set_and_check(struct sxe_hw *hw, int reg,
 	return ret;
 }
 
-STATIC s32 sxe_hw_regs_test(struct sxe_hw *hw)
+static s32 sxe_hw_regs_test(struct sxe_hw *hw)
 {
 	u32 i;
 	s32 ret = 0;
@@ -676,9 +651,8 @@  STATIC s32 sxe_hw_regs_test(struct sxe_hw *hw)
 				break;
 			}
 
-			if (ret) {
+			if (ret)
 				goto l_end;
-			}
 
 		}
 		test++;
@@ -716,7 +690,6 @@  static void sxe_hw_ring_irq_enable(struct sxe_hw *hw, u64 qmask)
 		SXE_REG_WRITE(hw, SXE_EIMS_EX(1), mask1);
 	}
 
-	return;
 }
 
 u32 sxe_hw_pending_irq_read_clear(struct sxe_hw *hw)
@@ -727,7 +700,6 @@  u32 sxe_hw_pending_irq_read_clear(struct sxe_hw *hw)
 void sxe_hw_pending_irq_write_clear(struct sxe_hw *hw, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_EICR, value);
-	return;
 }
 
 u32 sxe_hw_irq_cause_get(struct sxe_hw *hw)
@@ -739,7 +711,6 @@  static void sxe_hw_event_irq_trigger(struct sxe_hw *hw)
 {
 	SXE_REG_WRITE(hw, SXE_EICS, (SXE_EICS_TCP_TIMER | SXE_EICS_OTHER));
 
-	return;
 }
 
 static void sxe_hw_ring_irq_trigger(struct sxe_hw *hw, u64 eics)
@@ -750,7 +721,6 @@  static void sxe_hw_ring_irq_trigger(struct sxe_hw *hw, u64 eics)
 	SXE_REG_WRITE(hw, SXE_EICS_EX(0), mask);
 	mask = (eics >> 32);
 	SXE_REG_WRITE(hw, SXE_EICS_EX(1), mask);
-	return;
 }
 
 void sxe_hw_ring_irq_auto_disable(struct sxe_hw *hw,
@@ -763,14 +733,12 @@  void sxe_hw_ring_irq_auto_disable(struct sxe_hw *hw,
 		SXE_REG_WRITE(hw, SXE_EIAM, SXE_EICS_RTX_QUEUE);
 	}
 
-	return;
 }
 
 void sxe_hw_irq_general_reg_set(struct sxe_hw *hw, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_GPIE, value);
 
-	return;
 }
 
 u32 sxe_hw_irq_general_reg_get(struct sxe_hw *hw)
@@ -782,7 +750,6 @@  static void sxe_hw_set_eitrsel(struct sxe_hw *hw, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_EITRSEL, value);
 
-	return;
 }
 
 void sxe_hw_event_irq_map(struct sxe_hw *hw, u8 offset, u16 irq_idx)
@@ -800,7 +767,6 @@  void sxe_hw_event_irq_map(struct sxe_hw *hw, u8 offset, u16 irq_idx)
 
 	SXE_REG_WRITE(hw, SXE_IVAR_MISC, ivar);
 
-	return;
 }
 
 void sxe_hw_ring_irq_map(struct sxe_hw *hw, bool is_tx,
@@ -819,7 +785,6 @@  void sxe_hw_ring_irq_map(struct sxe_hw *hw, bool is_tx,
 
 	SXE_REG_WRITE(hw, SXE_IVAR(reg_idx >> 1), ivar);
 
-	return;
 }
 
 void sxe_hw_ring_irq_interval_set(struct sxe_hw *hw,
@@ -831,7 +796,6 @@  void sxe_hw_ring_irq_interval_set(struct sxe_hw *hw,
 
 	SXE_REG_WRITE(hw, SXE_EITR(irq_idx), eitr);
 
-	return;
 }
 
 static void sxe_hw_event_irq_interval_set(struct sxe_hw *hw,
@@ -839,28 +803,24 @@  static void sxe_hw_event_irq_interval_set(struct sxe_hw *hw,
 {
 	SXE_REG_WRITE(hw, SXE_EITR(irq_idx), value);
 
-	return;
 }
 
 void sxe_hw_event_irq_auto_clear_set(struct sxe_hw *hw, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_EIAC, value);
 
-	return;
 }
 
 void sxe_hw_specific_irq_disable(struct sxe_hw *hw, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_EIMC, value);
 
-	return;
 }
 
 void sxe_hw_specific_irq_enable(struct sxe_hw *hw, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_EIMS, value);
 
-	return;
 }
 
 void sxe_hw_all_irq_disable(struct sxe_hw *hw)
@@ -872,7 +832,6 @@  void sxe_hw_all_irq_disable(struct sxe_hw *hw)
 
 	SXE_WRITE_FLUSH(hw);
 
-	return;
 }
 
 static void sxe_hw_spp_configure(struct sxe_hw *hw, u32 hw_spp_proc_delay_us)
@@ -882,7 +841,6 @@  static void sxe_hw_spp_configure(struct sxe_hw *hw, u32 hw_spp_proc_delay_us)
 			~SXE_SPP_PROC_DELAY_US_MASK) |
 			hw_spp_proc_delay_us);
 
-	return;
 }
 
 static s32 sxe_hw_irq_test(struct sxe_hw *hw, u32 *icr, bool shared)
@@ -985,13 +943,12 @@  u32 sxe_hw_link_speed_get(struct sxe_hw *hw)
 	struct sxe_adapter *adapter = hw->adapter;
 	value = SXE_REG_READ(hw, SXE_COMCTRL);
 
-	if ((value & SXE_COMCTRL_SPEED_10G) == SXE_COMCTRL_SPEED_10G) {
+	if ((value & SXE_COMCTRL_SPEED_10G) == SXE_COMCTRL_SPEED_10G)
 		speed = SXE_LINK_SPEED_10GB_FULL;
-	} else if ((value & SXE_COMCTRL_SPEED_1G) == SXE_COMCTRL_SPEED_1G) {
+	else if ((value & SXE_COMCTRL_SPEED_1G) == SXE_COMCTRL_SPEED_1G)
 		speed = SXE_LINK_SPEED_1GB_FULL;
-	} else {
+	else
 		speed = SXE_LINK_SPEED_UNKNOWN;
-	}
 
 	LOG_DEBUG_BDF("hw link speed=%x, (0x80=10G, 0x20=1G)\n, reg=%x",
 			speed, value);
@@ -1005,18 +962,17 @@  void sxe_hw_link_speed_set(struct sxe_hw *hw, u32 speed)
 
 	ctrl = SXE_REG_READ(hw, SXE_COMCTRL);
 
-	if (SXE_LINK_SPEED_1GB_FULL == speed) {
+	if (speed == SXE_LINK_SPEED_1GB_FULL) {
 		ctrl |= SXE_COMCTRL_SPEED_1G;
-	} else if (SXE_LINK_SPEED_10GB_FULL == speed) {
+	} else if (speed == SXE_LINK_SPEED_10GB_FULL) {
 		ctrl |= SXE_COMCTRL_SPEED_10G;
 	}
 
 	SXE_REG_WRITE(hw, SXE_COMCTRL, ctrl);
 
-	return;
 }
 
-STATIC bool sxe_hw_1g_link_up_check(struct sxe_hw *hw)
+static bool sxe_hw_1g_link_up_check(struct sxe_hw *hw)
 {
 	return (SXE_REG_READ(hw, SXE_LINKS) & SXE_LINKS_UP) ? true : false;
 }
@@ -1036,9 +992,9 @@  bool sxe_hw_is_link_state_up(struct sxe_hw *hw)
 
 		link_speed = sxe_hw_link_speed_get(hw);
 		if ((link_speed == SXE_LINK_SPEED_10GB_FULL) &&
-		    (links_reg & SXE_10G_LINKS_DOWN)) {
+			(links_reg & SXE_10G_LINKS_DOWN))
 			ret = false;
-		}
+
 	}
 
 	return ret;
@@ -1052,7 +1008,6 @@  void sxe_hw_mac_pad_enable(struct sxe_hw *hw)
 	ctl |= SXE_MACCFG_PAD_EN;
 	SXE_REG_WRITE(hw, SXE_MACCFG, ctl);
 
-	return;
 }
 
 s32 sxe_hw_fc_enable(struct sxe_hw *hw)
@@ -1066,7 +1021,7 @@  s32 sxe_hw_fc_enable(struct sxe_hw *hw)
 
 	flctrl_val = SXE_REG_READ(hw, SXE_FLCTRL);
 	flctrl_val &= ~(SXE_FCTRL_TFCE_MASK | SXE_FCTRL_RFCE_MASK |
-		       SXE_FCTRL_TFCE_FCEN_MASK | SXE_FCTRL_TFCE_XONE_MASK);
+			   SXE_FCTRL_TFCE_FCEN_MASK | SXE_FCTRL_TFCE_XONE_MASK);
 
 	switch (hw->fc.current_mode) {
 	case SXE_FC_NONE:
@@ -1089,7 +1044,7 @@  s32 sxe_hw_fc_enable(struct sxe_hw *hw)
 
 	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
 		if ((hw->fc.current_mode & SXE_FC_TX_PAUSE) &&
-		    hw->fc.high_water[i]) {
+			hw->fc.high_water[i]) {
 			fcrtl = (hw->fc.low_water[i] << 9) | SXE_FCRTL_XONE;
 			SXE_REG_WRITE(hw, SXE_FCRTL(i), fcrtl);
 			fcrth = (hw->fc.high_water[i] << 9) | SXE_FCRTH_FCEN;
@@ -1103,9 +1058,8 @@  s32 sxe_hw_fc_enable(struct sxe_hw *hw)
 
 	flctrl_val |= SXE_FCTRL_TFCE_DPF_EN;
 
-	if ((hw->fc.current_mode & SXE_FC_TX_PAUSE)) {
+	if ((hw->fc.current_mode & SXE_FC_TX_PAUSE))
 		flctrl_val |= (SXE_FCTRL_TFCE_FCEN_MASK | SXE_FCTRL_TFCE_XONE_MASK);
-	}
 
 	SXE_REG_WRITE(hw, SXE_FLCTRL, flctrl_val);
 
@@ -1116,9 +1070,8 @@  s32 sxe_hw_fc_enable(struct sxe_hw *hw)
 	SXE_REG_WRITE(hw, SXE_PFCTOP, reg);
 
 	reg = hw->fc.pause_time * 0x00010001U;
-	for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) {
+	for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
 		SXE_REG_WRITE(hw, SXE_FCTTV(i), reg);
-	}
 
 	SXE_REG_WRITE(hw, SXE_FCRTV, hw->fc.pause_time / 2);
 
@@ -1130,9 +1083,8 @@  void sxe_fc_autoneg_localcap_set(struct sxe_hw *hw)
 {
 	u32 reg = 0;
 
-	if (hw->fc.requested_mode == SXE_FC_DEFAULT) {
+	if (hw->fc.requested_mode == SXE_FC_DEFAULT)
 		hw->fc.requested_mode = SXE_FC_FULL;
-	}
 
 	reg = SXE_REG_READ(hw, SXE_PCS1GANA);
 
@@ -1154,7 +1106,6 @@  void sxe_fc_autoneg_localcap_set(struct sxe_hw *hw)
 	}
 
 	SXE_REG_WRITE(hw, SXE_PCS1GANA, reg);
-	return;
 }
 
 s32 sxe_hw_pfc_enable(struct sxe_hw *hw, u8 tc_idx)
@@ -1169,20 +1120,18 @@  s32 sxe_hw_pfc_enable(struct sxe_hw *hw, u8 tc_idx)
 
 	flctrl_val = SXE_REG_READ(hw, SXE_FLCTRL);
 	flctrl_val &= ~(SXE_FCTRL_TFCE_MASK | SXE_FCTRL_RFCE_MASK |
-		       SXE_FCTRL_TFCE_FCEN_MASK | SXE_FCTRL_TFCE_XONE_MASK);
+			   SXE_FCTRL_TFCE_FCEN_MASK | SXE_FCTRL_TFCE_XONE_MASK);
 
 	switch (hw->fc.current_mode) {
 	case SXE_FC_NONE:
 		rx_en_num = 0;
 		for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
 			reg = SXE_REG_READ(hw, SXE_FCRTH(i));
-			if (reg & SXE_FCRTH_FCEN) {
+			if (reg & SXE_FCRTH_FCEN)
 				rx_en_num++;
-			}
 		}
-		if (rx_en_num > 1) {
+		if (rx_en_num > 1)
 			flctrl_val |= SXE_FCTRL_TFCE_PFC_EN;
-		}
 
 		break;
 
@@ -1192,14 +1141,12 @@  s32 sxe_hw_pfc_enable(struct sxe_hw *hw, u8 tc_idx)
 		rx_en_num = 0;
 		for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
 			reg = SXE_REG_READ(hw, SXE_FCRTH(i));
-			if (reg & SXE_FCRTH_FCEN) {
+			if (reg & SXE_FCRTH_FCEN)
 				rx_en_num++;
-			}
 		}
 
-		if (rx_en_num > 1) {
+		if (rx_en_num > 1)
 			flctrl_val |= SXE_FCTRL_TFCE_PFC_EN;
-		}
 
 		break;
 	case SXE_FC_TX_PAUSE:
@@ -1216,7 +1163,7 @@  s32 sxe_hw_pfc_enable(struct sxe_hw *hw, u8 tc_idx)
 	}
 
 	if ((hw->fc.current_mode & SXE_FC_TX_PAUSE) &&
-	    hw->fc.high_water[tc_idx]) {
+		hw->fc.high_water[tc_idx]) {
 		fcrtl = (hw->fc.low_water[tc_idx] << 9) | SXE_FCRTL_XONE;
 		SXE_REG_WRITE(hw, SXE_FCRTL(tc_idx), fcrtl);
 		fcrth = (hw->fc.high_water[tc_idx] << 9) | SXE_FCRTH_FCEN;
@@ -1243,9 +1190,8 @@  s32 sxe_hw_pfc_enable(struct sxe_hw *hw, u8 tc_idx)
 	SXE_REG_WRITE(hw, SXE_PFCTOP, reg);
 
 	reg = hw->fc.pause_time * 0x00010001U;
-	for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) {
+	for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
 		SXE_REG_WRITE(hw, SXE_FCTTV(i), reg);
-	}
 
 	SXE_REG_WRITE(hw, SXE_FCRTV, hw->fc.pause_time / 2);
 
@@ -1260,7 +1206,6 @@  void sxe_hw_crc_configure(struct sxe_hw *hw)
 	ctrl |=  SXE_PCCTRL_TXCE | SXE_PCCTRL_RXCE | SXE_PCCTRL_PCSC_ALL;
 	SXE_REG_WRITE(hw, SXE_PCCTRL, ctrl);
 
-	return;
 }
 
 void sxe_hw_loopback_switch(struct sxe_hw *hw, bool is_enable)
@@ -1271,7 +1216,6 @@  void sxe_hw_loopback_switch(struct sxe_hw *hw, bool is_enable)
 
 	SXE_REG_WRITE(hw, SXE_LPBKCTRL, value);
 
-	return;
 }
 
 void sxe_hw_mac_txrx_enable(struct sxe_hw *hw)
@@ -1282,7 +1226,6 @@  void sxe_hw_mac_txrx_enable(struct sxe_hw *hw)
 	ctl |= SXE_COMCTRL_TXEN | SXE_COMCTRL_RXEN | SXE_COMCTRL_EDSEL;
 	SXE_REG_WRITE(hw, SXE_COMCTRL, ctl);
 
-	return;
 }
 
 void sxe_hw_mac_max_frame_set(struct sxe_hw *hw, u32 max_frame)
@@ -1297,7 +1240,6 @@  void sxe_hw_mac_max_frame_set(struct sxe_hw *hw, u32 max_frame)
 	maxfs |=  SXE_MAXFS_RFSEL | SXE_MAXFS_TFSEL;
 	SXE_REG_WRITE(hw, SXE_MAXFS, maxfs);
 
-	return;
 }
 
 u32 sxe_hw_mac_max_frame_get(struct sxe_hw *hw)
@@ -1324,14 +1266,13 @@  bool sxe_device_supports_autoneg_fc(struct sxe_hw *hw)
 	return supported;
 }
 
-STATIC void sxe_hw_fc_param_init(struct sxe_hw *hw)
+static void sxe_hw_fc_param_init(struct sxe_hw *hw)
 {
 	hw->fc.requested_mode = SXE_FC_FULL;
-	hw->fc.current_mode = SXE_FC_FULL;	
+	hw->fc.current_mode = SXE_FC_FULL;
 	hw->fc.pause_time = SXE_DEFAULT_FCPAUSE;
 
 	hw->fc.disable_fc_autoneg = true;
-	return;
 }
 
 void sxe_hw_fc_tc_high_water_mark_set(struct sxe_hw *hw,
@@ -1339,7 +1280,6 @@  void sxe_hw_fc_tc_high_water_mark_set(struct sxe_hw *hw,
 {
 	hw->fc.high_water[tc_idx] = mark;
 
-	return;
 }
 
 void sxe_hw_fc_tc_low_water_mark_set(struct sxe_hw *hw,
@@ -1347,7 +1287,6 @@  void sxe_hw_fc_tc_low_water_mark_set(struct sxe_hw *hw,
 {
 	hw->fc.low_water[tc_idx] = mark;
 
-	return;
 }
 
 bool sxe_hw_is_fc_autoneg_disabled(struct sxe_hw *hw)
@@ -1359,7 +1298,6 @@  void sxe_hw_fc_autoneg_disable_set(struct sxe_hw *hw,
 							bool is_disabled)
 {
 	hw->fc.disable_fc_autoneg = is_disabled;
-	return;
 }
 
 static enum sxe_fc_mode sxe_hw_fc_current_mode_get(struct sxe_hw *hw)
@@ -1376,7 +1314,6 @@  void sxe_hw_fc_requested_mode_set(struct sxe_hw *hw,
 						enum sxe_fc_mode mode)
 {
 	hw->fc.requested_mode = mode;
-	return;
 }
 
 static const struct sxe_mac_operations sxe_mac_ops = {
@@ -1415,14 +1352,12 @@  u32 sxe_hw_pool_rx_mode_get(struct sxe_hw *hw, u16 pool_idx)
 void sxe_hw_rx_mode_set(struct sxe_hw *hw, u32 filter_ctrl)
 {
 	SXE_REG_WRITE(hw, SXE_FCTRL, filter_ctrl);
-	return;
 }
 
 void sxe_hw_pool_rx_mode_set(struct sxe_hw *hw,
 						u32 vmolr, u16 pool_idx)
 {
 	SXE_REG_WRITE(hw, SXE_VMOLR(pool_idx), vmolr);
-	return;
 }
 
 void sxe_hw_rx_lro_enable(struct sxe_hw *hw, bool is_enable)
@@ -1430,12 +1365,10 @@  void sxe_hw_rx_lro_enable(struct sxe_hw *hw, bool is_enable)
 	u32 rfctl = SXE_REG_READ(hw, SXE_RFCTL);
 	rfctl &= ~SXE_RFCTL_LRO_DIS;
 
-	if (!is_enable) {
+	if (!is_enable)
 		rfctl |= SXE_RFCTL_LRO_DIS;
-	}
 
 	SXE_REG_WRITE(hw, SXE_RFCTL, rfctl);
-	return;
 }
 
 void sxe_hw_rx_nfs_filter_disable(struct sxe_hw *hw)
@@ -1444,7 +1377,6 @@  void sxe_hw_rx_nfs_filter_disable(struct sxe_hw *hw)
 
 	rfctl |= (SXE_RFCTL_NFSW_DIS | SXE_RFCTL_NFSR_DIS);
 	SXE_REG_WRITE(hw, SXE_RFCTL, rfctl);
-	return;
 }
 
 void sxe_hw_rx_udp_frag_checksum_disable(struct sxe_hw *hw)
@@ -1454,7 +1386,6 @@  void sxe_hw_rx_udp_frag_checksum_disable(struct sxe_hw *hw)
 	rxcsum = SXE_REG_READ(hw, SXE_RXCSUM);
 	rxcsum |= SXE_RXCSUM_PCSD;
 	SXE_REG_WRITE(hw, SXE_RXCSUM, rxcsum);
-	return;
 }
 
 void sxe_hw_fc_mac_addr_set(struct sxe_hw *hw, u8 *mac_addr)
@@ -1462,16 +1393,15 @@  void sxe_hw_fc_mac_addr_set(struct sxe_hw *hw, u8 *mac_addr)
 	u32 mac_addr_h, mac_addr_l;
 
 	mac_addr_l = ((u32)mac_addr[5] |
-		    ((u32)mac_addr[4] << 8) |
-		    ((u32)mac_addr[3] << 16) |
-		    ((u32)mac_addr[2] << 24));
+			((u32)mac_addr[4] << 8) |
+			((u32)mac_addr[3] << 16) |
+			((u32)mac_addr[2] << 24));
 	mac_addr_h = (((u32)mac_addr[1] << 16) |
-		    ((u32)mac_addr[0] << 24));
+			((u32)mac_addr[0] << 24));
 
 	SXE_REG_WRITE(hw, SXE_SACONH, mac_addr_h);
 	SXE_REG_WRITE(hw, SXE_SACONL, mac_addr_l);
 
-	return;
 }
 
 s32 sxe_hw_uc_addr_add(struct sxe_hw *hw, u32 rar_idx,
@@ -1542,7 +1472,6 @@  void sxe_hw_mta_hash_table_set(struct sxe_hw *hw,
 						u8 index, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_MTA(index), value);
-	return;
 }
 
 void sxe_hw_mta_hash_table_update(struct sxe_hw *hw,
@@ -1555,7 +1484,6 @@  void sxe_hw_mta_hash_table_update(struct sxe_hw *hw,
 	LOG_INFO("mta update value:0x%x.\n", value);
 	SXE_REG_WRITE(hw, SXE_MTA(reg_idx), value);
 
-	return;
 }
 
 void sxe_hw_mc_filter_enable(struct sxe_hw *hw)
@@ -1564,7 +1492,6 @@  void sxe_hw_mc_filter_enable(struct sxe_hw *hw)
 
 	SXE_REG_WRITE(hw, SXE_MCSTCTRL, value);
 
-	return;
 }
 
 static void sxe_hw_mc_filter_disable(struct sxe_hw *hw)
@@ -1575,7 +1502,6 @@  static void sxe_hw_mc_filter_disable(struct sxe_hw *hw)
 
 	SXE_REG_WRITE(hw, SXE_MCSTCTRL, value);
 
-	return;
 }
 
 void sxe_hw_uc_addr_clear(struct sxe_hw *hw)
@@ -1594,26 +1520,22 @@  void sxe_hw_uc_addr_clear(struct sxe_hw *hw)
 
 	LOG_DEV_DEBUG("clear %u uta filter addr register\n",
 			SXE_UTA_ENTRY_NUM_MAX);
-	for (i = 0; i < SXE_UTA_ENTRY_NUM_MAX; i++) {
+	for (i = 0; i < SXE_UTA_ENTRY_NUM_MAX; i++)
 		SXE_REG_WRITE(hw, SXE_UTA(i), 0);
-	}
 
 	SXE_REG_WRITE(hw, SXE_MCSTCTRL, SXE_MC_FILTER_TYPE0);
 
 	LOG_DEV_DEBUG("clear %u mta filter addr register\n",
 			SXE_MTA_ENTRY_NUM_MAX);
-	for (i = 0; i < SXE_MTA_ENTRY_NUM_MAX; i++) {
+	for (i = 0; i < SXE_MTA_ENTRY_NUM_MAX; i++)
 		SXE_REG_WRITE(hw, SXE_MTA(i), 0);
-	}
 
-	return;
 }
 
 static void sxe_hw_ethertype_filter_set(struct sxe_hw *hw,
 						u8 filter_type, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_ETQF(filter_type), value);
-	return;
 }
 
 void sxe_hw_vt_ctrl_cfg(struct sxe_hw *hw, u8 default_pool)
@@ -1622,14 +1544,13 @@  void sxe_hw_vt_ctrl_cfg(struct sxe_hw *hw, u8 default_pool)
 
 	ctrl = SXE_REG_READ(hw, SXE_VT_CTL);
 
-	ctrl |= SXE_VT_CTL_VT_ENABLE; 
+	ctrl |= SXE_VT_CTL_VT_ENABLE;
 	ctrl &= ~SXE_VT_CTL_POOL_MASK;
 	ctrl |= default_pool << SXE_VT_CTL_POOL_SHIFT;
-	ctrl |= SXE_VT_CTL_REPLEN; 
+	ctrl |= SXE_VT_CTL_REPLEN;
 
 	SXE_REG_WRITE(hw, SXE_VT_CTL, ctrl);
 
-	return;
 }
 
 void sxe_hw_vt_disable(struct sxe_hw *hw)
@@ -1640,7 +1561,6 @@  void sxe_hw_vt_disable(struct sxe_hw *hw)
 	vmdctl &= ~SXE_VMD_CTL_POOL_EN;
 	SXE_REG_WRITE(hw, SXE_VT_CTL, vmdctl);
 
-	return;
 }
 
 #ifdef SXE_WOL_CONFIGURE
@@ -1649,7 +1569,6 @@  static void sxe_hw_wol_status_set(struct sxe_hw *hw)
 {
 	SXE_REG_WRITE(hw, SXE_WUS, ~0);
 
-	return;
 }
 
 static void sxe_hw_wol_mode_set(struct sxe_hw *hw, u32 wol_status)
@@ -1660,16 +1579,14 @@  static void sxe_hw_wol_mode_set(struct sxe_hw *hw, u32 wol_status)
 
 	fctrl = SXE_REG_READ(hw, SXE_FCTRL);
 	fctrl |= SXE_FCTRL_BAM;
-	if (wol_status & SXE_WUFC_MC) {
+	if (wol_status & SXE_WUFC_MC)
 		fctrl |= SXE_FCTRL_MPE;
-	}
 
 	SXE_REG_WRITE(hw, SXE_FCTRL, fctrl);
 
 	SXE_REG_WRITE(hw, SXE_WUFC, wol_status);
 	sxe_hw_wol_status_set(hw);
 
-	return;
 }
 
 static void sxe_hw_wol_mode_clean(struct sxe_hw *hw)
@@ -1677,7 +1594,6 @@  static void sxe_hw_wol_mode_clean(struct sxe_hw *hw)
 	SXE_REG_WRITE(hw, SXE_WUC, 0);
 	SXE_REG_WRITE(hw, SXE_WUFC, 0);
 
-	return;
 }
 #endif
 
@@ -1708,7 +1624,7 @@  static const struct sxe_filter_mac_operations sxe_filter_mac_ops = {
 	.wol_status_set			= sxe_hw_wol_status_set,
 #endif
 
-	.vt_disable                     = sxe_hw_vt_disable,
+	.vt_disable					 = sxe_hw_vt_disable,
 };
 
 u32 sxe_hw_vlan_pool_filter_read(struct sxe_hw *hw, u16 reg_index)
@@ -1720,7 +1636,6 @@  static void sxe_hw_vlan_pool_filter_write(struct sxe_hw *hw,
 						u16 reg_index, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_VLVF(reg_index), value);
-	return;
 }
 
 static u32 sxe_hw_vlan_pool_filter_bitmap_read(struct sxe_hw *hw,
@@ -1733,14 +1648,12 @@  static void sxe_hw_vlan_pool_filter_bitmap_write(struct sxe_hw *hw,
 						u16 reg_index, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_VLVFB(reg_index), value);
-	return;
 }
 
 void sxe_hw_vlan_filter_array_write(struct sxe_hw *hw,
 					u16 reg_index, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_VFTA(reg_index), value);
-	return;
 }
 
 u32 sxe_hw_vlan_filter_array_read(struct sxe_hw *hw, u16 reg_index)
@@ -1753,14 +1666,12 @@  void sxe_hw_vlan_filter_switch(struct sxe_hw *hw, bool is_enable)
 	u32 vlnctrl;
 
 	vlnctrl = SXE_REG_READ(hw, SXE_VLNCTRL);
-	if (is_enable) {
+	if (is_enable)
 		vlnctrl |= SXE_VLNCTRL_VFE;
-	} else {
+	else
 		vlnctrl &= ~SXE_VLNCTRL_VFE;
-	}
 
 	SXE_REG_WRITE(hw, SXE_VLNCTRL, vlnctrl);
-	return;
 }
 
 static void sxe_hw_vlan_untagged_pkts_rcv_switch(struct sxe_hw *hw,
@@ -1768,15 +1679,13 @@  static void sxe_hw_vlan_untagged_pkts_rcv_switch(struct sxe_hw *hw,
 {
 	u32 vmolr = SXE_REG_READ(hw, SXE_VMOLR(vf));
 	vmolr |= SXE_VMOLR_BAM;
-	if (accept) {
+	if (accept)
 		vmolr |= SXE_VMOLR_AUPE;
-	} else {
+	else
 		vmolr &= ~SXE_VMOLR_AUPE;
-	}
 
 	LOG_WARN("vf:%u value:0x%x.\n", vf, vmolr);
 	SXE_REG_WRITE(hw, SXE_VMOLR(vf), vmolr);
-	return;
 }
 
 s32 sxe_hw_vlvf_slot_find(struct sxe_hw *hw, u32 vlan, bool vlvf_bypass)
@@ -1801,14 +1710,12 @@  s32 sxe_hw_vlvf_slot_find(struct sxe_hw *hw, u32 vlan, bool vlvf_bypass)
 			goto l_end;
 		}
 
-		if (!first_empty_slot && !bits) {
+		if (!first_empty_slot && !bits)
 			first_empty_slot = regindex;
-		}
 	}
 
-	if (!first_empty_slot) {
+	if (!first_empty_slot)
 		LOG_DEV_WARN("no space in VLVF.\n");
-	}
 
 	ret = first_empty_slot ? : -SXE_ERR_NO_SPACE;
 l_end:
@@ -1839,15 +1746,13 @@  s32 sxe_hw_vlan_filter_configure(struct sxe_hw *hw,
 	vfta_delta &= vlan_on ? ~vfta : vfta;
 	vfta ^= vfta_delta;
 
-	if (!(SXE_REG_READ(hw, SXE_VT_CTL) & SXE_VT_CTL_VT_ENABLE)) {
+	if (!(SXE_REG_READ(hw, SXE_VT_CTL) & SXE_VT_CTL_VT_ENABLE))
 		goto vfta_update;
-	}
 
 	vlvf_index = sxe_hw_vlvf_slot_find(hw, vid, vlvf_bypass);
 	if (vlvf_index < 0) {
-		if (vlvf_bypass) {
+		if (vlvf_bypass)
 			goto vfta_update;
-		}
 
 		ret = vlvf_index;
 		goto l_end;
@@ -1856,17 +1761,15 @@  s32 sxe_hw_vlan_filter_configure(struct sxe_hw *hw,
 	bits = SXE_REG_READ(hw, SXE_VLVFB(vlvf_index * 2 + pool / 32));
 
 	bits |= BIT(pool % 32);
-	if (vlan_on) {
+	if (vlan_on)
 		goto vlvf_update;
-	}
 
 	bits ^= BIT(pool % 32);
 
 	if (!bits &&
-	    !SXE_REG_READ(hw, SXE_VLVFB(vlvf_index * 2 + 1 - pool / 32))) {
-		if (vfta_delta) {
+		!SXE_REG_READ(hw, SXE_VLVFB(vlvf_index * 2 + 1 - pool / 32))) {
+		if (vfta_delta)
 			SXE_REG_WRITE(hw, SXE_VFTA(regidx), vfta);
-		}
 
 		SXE_REG_WRITE(hw, SXE_VLVF(vlvf_index), 0);
 		SXE_REG_WRITE(hw, SXE_VLVFB(vlvf_index * 2 + pool / 32), 0);
@@ -1881,9 +1784,8 @@  s32 sxe_hw_vlan_filter_configure(struct sxe_hw *hw,
 	SXE_REG_WRITE(hw, SXE_VLVF(vlvf_index), SXE_VLVF_VIEN | vid);
 
 vfta_update:
-	if (vfta_delta) {
+	if (vfta_delta)
 		SXE_REG_WRITE(hw, SXE_VFTA(regidx), vfta);
-	}
 
 l_end:
 	return ret;
@@ -1893,9 +1795,8 @@  void sxe_hw_vlan_filter_array_clear(struct sxe_hw *hw)
 {
 	u32 offset;
 
-	for (offset = 0; offset < SXE_VFT_TBL_SIZE; offset++) {
+	for (offset = 0; offset < SXE_VFT_TBL_SIZE; offset++)
 		SXE_REG_WRITE(hw, SXE_VFTA(offset), 0);
-	}
 
 	for (offset = 0; offset < SXE_VLVF_ENTRIES; offset++) {
 		SXE_REG_WRITE(hw, SXE_VLVF(offset), 0);
@@ -1903,7 +1804,6 @@  void sxe_hw_vlan_filter_array_clear(struct sxe_hw *hw)
 		SXE_REG_WRITE(hw, SXE_VLVFB(offset * 2 + 1), 0);
 	}
 
-	return;
 }
 
 static const struct sxe_filter_vlan_operations sxe_filter_vlan_ops = {
@@ -1924,56 +1824,51 @@  static void sxe_hw_rx_pkt_buf_switch(struct sxe_hw *hw, bool is_on)
 {
 	u32 dbucfg = SXE_REG_READ(hw, SXE_DRXCFG);
 
-	if (is_on) {
+	if (is_on)
 		dbucfg |= SXE_DRXCFG_DBURX_START;
-	} else {
+	else
 		dbucfg &= ~SXE_DRXCFG_DBURX_START;
-	}
 
 	SXE_REG_WRITE(hw, SXE_DRXCFG, dbucfg);
 
-	return;
 }
 
 static void sxe_hw_rx_pkt_buf_size_configure(struct sxe_hw *hw,
-			     u8 num_pb,
-			     u32 headroom,
-			     u16 strategy)
+				 u8 num_pb,
+				 u32 headroom,
+				 u16 strategy)
 {
 	u16 total_buf_size = (SXE_RX_PKT_BUF_SIZE - headroom);
 	u32 rx_buf_size;
 	u16 i = 0;
 
-	if (!num_pb) {
+	if (!num_pb)
 		num_pb = 1;
-	}
 
 	switch (strategy) {
 	case (PBA_STRATEGY_WEIGHTED):
 		rx_buf_size = ((total_buf_size * 5 * 2) / (num_pb * 8));
 		total_buf_size -= rx_buf_size * (num_pb / 2);
 		rx_buf_size <<= SXE_RX_PKT_BUF_SIZE_SHIFT;
-		for (i = 0; i < (num_pb / 2); i++) {
+		for (i = 0; i < (num_pb / 2); i++)
 			SXE_REG_WRITE(hw, SXE_RXPBSIZE(i), rx_buf_size);
-		}
+
 		fallthrough;
 	case (PBA_STRATEGY_EQUAL):
 		rx_buf_size = (total_buf_size / (num_pb - i))
 				<< SXE_RX_PKT_BUF_SIZE_SHIFT;
-		for (; i < num_pb; i++) {
+		for (; i < num_pb; i++)
 			SXE_REG_WRITE(hw, SXE_RXPBSIZE(i), rx_buf_size);
-		}
+
 		break;
 
 	default:
 		break;
 	}
 
-	for (; i < SXE_PKG_BUF_NUM_MAX; i++) {
+	for (; i < SXE_PKG_BUF_NUM_MAX; i++)
 		SXE_REG_WRITE(hw, SXE_RXPBSIZE(i), 0);
-	}
 
-	return;
 }
 
 u32 sxe_hw_rx_pkt_buf_size_get(struct sxe_hw *hw, u8 pb)
@@ -1990,28 +1885,27 @@  void sxe_hw_rx_multi_ring_configure(struct sxe_hw *hw,
 	mrqc &= ~SXE_MRQE_MASK;
 
 	if (sriov_enable) {
-		if (tcs > 4) {
-			mrqc |= SXE_MRQC_VMDQRT8TCEN;	
-		} else if (tcs > 1) {
-			mrqc |= SXE_MRQC_VMDQRT4TCEN;	
-		} else if (is_4q_per_pool == true) {
+		if (tcs > 4)
+			mrqc |= SXE_MRQC_VMDQRT8TCEN;
+		else if (tcs > 1)
+			mrqc |= SXE_MRQC_VMDQRT4TCEN;
+		else if (is_4q_per_pool == true)
 			mrqc |= SXE_MRQC_VMDQRSS32EN;
-		} else {
+		else
 			mrqc |= SXE_MRQC_VMDQRSS64EN;
-		}
+
 	} else {
-		if (tcs > 4) {
+		if (tcs > 4)
 			mrqc |= SXE_MRQC_RTRSS8TCEN;
-		} else if (tcs > 1) {
+		else if (tcs > 1)
 			mrqc |= SXE_MRQC_RTRSS4TCEN;
-		} else {
+		else
 			mrqc |= SXE_MRQC_RSSEN;
-		}
+
 	}
 
 	SXE_REG_WRITE(hw, SXE_MRQC, mrqc);
 
-	return;
 }
 
 static void sxe_hw_rss_hash_pkt_type_set(struct sxe_hw *hw, u32 version)
@@ -2020,21 +1914,19 @@  static void sxe_hw_rss_hash_pkt_type_set(struct sxe_hw *hw, u32 version)
 	u32 rss_field = 0;
 
 	rss_field |= SXE_MRQC_RSS_FIELD_IPV4 |
-		     SXE_MRQC_RSS_FIELD_IPV4_TCP |
-		     SXE_MRQC_RSS_FIELD_IPV6 |
-		     SXE_MRQC_RSS_FIELD_IPV6_TCP;
+			 SXE_MRQC_RSS_FIELD_IPV4_TCP |
+			 SXE_MRQC_RSS_FIELD_IPV6 |
+			 SXE_MRQC_RSS_FIELD_IPV6_TCP;
 
-	if (version == SXE_RSS_IP_VER_4) {
+	if (version == SXE_RSS_IP_VER_4)
 		rss_field |= SXE_MRQC_RSS_FIELD_IPV4_UDP;
-	}
-	if (version == SXE_RSS_IP_VER_6) {
+
+	if (version == SXE_RSS_IP_VER_6)
 		rss_field |= SXE_MRQC_RSS_FIELD_IPV6_UDP;
-	}
 
 	mrqc |= rss_field;
 	SXE_REG_WRITE(hw, SXE_MRQC, mrqc);
 
-	return;
 }
 
 static void sxe_hw_rss_hash_pkt_type_update(struct sxe_hw *hw,
@@ -2045,23 +1937,21 @@  static void sxe_hw_rss_hash_pkt_type_update(struct sxe_hw *hw,
 	mrqc = SXE_REG_READ(hw, SXE_MRQC);
 
 	mrqc |= SXE_MRQC_RSS_FIELD_IPV4
-	      | SXE_MRQC_RSS_FIELD_IPV4_TCP
-	      | SXE_MRQC_RSS_FIELD_IPV6
-	      | SXE_MRQC_RSS_FIELD_IPV6_TCP;
+		  | SXE_MRQC_RSS_FIELD_IPV4_TCP
+		  | SXE_MRQC_RSS_FIELD_IPV6
+		  | SXE_MRQC_RSS_FIELD_IPV6_TCP;
 
 	mrqc &= ~(SXE_MRQC_RSS_FIELD_IPV4_UDP |
 		  SXE_MRQC_RSS_FIELD_IPV6_UDP);
 
-	if (version == SXE_RSS_IP_VER_4) {
+	if (version == SXE_RSS_IP_VER_4)
 		mrqc |= SXE_MRQC_RSS_FIELD_IPV4_UDP;
-	}
-	if (version == SXE_RSS_IP_VER_6) {
+
+	if (version == SXE_RSS_IP_VER_6)
 		mrqc |= SXE_MRQC_RSS_FIELD_IPV6_UDP;
-	}
 
 	SXE_REG_WRITE(hw, SXE_MRQC, mrqc);
 
-	return;
 }
 
 static void sxe_hw_rss_rings_used_set(struct sxe_hw *hw, u32 rss_num,
@@ -2069,35 +1959,29 @@  static void sxe_hw_rss_rings_used_set(struct sxe_hw *hw, u32 rss_num,
 {
 	u32 psrtype = 0;
 
-	if (rss_num > 3) {
+	if (rss_num > 3)
 		psrtype |= 2u << 29;
-	} else if (rss_num > 1) {
+	else if (rss_num > 1)
 		psrtype |= 1u << 29;
-	}
 
-	while (pool--) {
+	while (pool--)
 		SXE_REG_WRITE(hw, SXE_PSRTYPE(pf_offset + pool), psrtype);
-	}
 
-	return;
 }
 
 void sxe_hw_rss_key_set_all(struct sxe_hw *hw, u32 *rss_key)
 {
 	u32 i;
 
-	for (i = 0; i < SXE_MAX_RSS_KEY_ENTRIES; i++) {
+	for (i = 0; i < SXE_MAX_RSS_KEY_ENTRIES; i++)
 		SXE_REG_WRITE(hw, SXE_RSSRK(i), rss_key[i]);
-	}
 
-	return;
 }
 
 void sxe_hw_rss_redir_tbl_reg_write(struct sxe_hw *hw,
 						u16 reg_idx, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_RETA(reg_idx >> 2), value);
-	return;
 }
 
 void sxe_hw_rss_redir_tbl_set_all(struct sxe_hw *hw, u8 *redir_tbl)
@@ -2114,7 +1998,6 @@  void sxe_hw_rss_redir_tbl_set_all(struct sxe_hw *hw, u8 *redir_tbl)
 			tbl = 0;
 		}
 	}
-	return;
 }
 
 void sxe_hw_rx_cap_switch_on(struct sxe_hw *hw)
@@ -2132,7 +2015,6 @@  void sxe_hw_rx_cap_switch_on(struct sxe_hw *hw)
 	rxctrl |= SXE_RXCTRL_RXEN;
 	SXE_REG_WRITE(hw, SXE_RXCTRL, rxctrl);
 
-	return;
 }
 
 void sxe_hw_rx_cap_switch_off(struct sxe_hw *hw)
@@ -2153,7 +2035,6 @@  void sxe_hw_rx_cap_switch_off(struct sxe_hw *hw)
 		SXE_REG_WRITE(hw, SXE_RXCTRL, rxctrl);
 	}
 
-	return;
 }
 
 static void sxe_hw_rx_func_switch_on(struct sxe_hw *hw)
@@ -2164,7 +2045,6 @@  static void sxe_hw_rx_func_switch_on(struct sxe_hw *hw)
 	rxctrl |= SXE_COMCTRL_RXEN | SXE_COMCTRL_EDSEL;
 	SXE_REG_WRITE(hw, SXE_COMCTRL, rxctrl);
 
-	return;
 }
 
 void sxe_hw_tx_pkt_buf_switch(struct sxe_hw *hw, bool is_on)
@@ -2182,27 +2062,22 @@  void sxe_hw_tx_pkt_buf_switch(struct sxe_hw *hw, bool is_on)
 		SXE_REG_WRITE(hw, SXE_DTXCFG, dbucfg);
 	}
 
-	return;
 }
 
 void sxe_hw_tx_pkt_buf_size_configure(struct sxe_hw *hw, u8 num_pb)
 {
 	u32 i, tx_pkt_size;
 
-	if (!num_pb){
+	if (!num_pb)
 		num_pb = 1;
-	}
 
 	tx_pkt_size = SXE_TX_PBSIZE_MAX / num_pb;
-	for (i = 0; i < num_pb; i++) {
+	for (i = 0; i < num_pb; i++)
 		SXE_REG_WRITE(hw, SXE_TXPBSIZE(i), tx_pkt_size);
-	}
 
-	for (; i < SXE_PKG_BUF_NUM_MAX; i++) {
+	for (; i < SXE_PKG_BUF_NUM_MAX; i++)
 		SXE_REG_WRITE(hw, SXE_TXPBSIZE(i), 0);
-	}
 
-	return;
 }
 
 void sxe_hw_rx_lro_ack_switch(struct sxe_hw *hw, bool is_on)
@@ -2217,7 +2092,6 @@  void sxe_hw_rx_lro_ack_switch(struct sxe_hw *hw, bool is_on)
 
 	SXE_REG_WRITE(hw, SXE_LRODBU, lro_dbu);
 
-	return;
 }
 
 static void sxe_hw_vf_rx_switch(struct sxe_hw *hw,
@@ -2232,10 +2106,9 @@  static void sxe_hw_vf_rx_switch(struct sxe_hw *hw,
 
 	SXE_REG_WRITE(hw, SXE_VFRE(reg_offset), vfre);
 
-	return;
 }
 
-STATIC s32 sxe_hw_fnav_wait_init_done(struct sxe_hw *hw)
+static s32 sxe_hw_fnav_wait_init_done(struct sxe_hw *hw)
 {
 	u32 i;
 	s32 ret = 0;
@@ -2266,16 +2139,15 @@  void sxe_hw_fnav_enable(struct sxe_hw *hw, u32 fnavctrl)
 	SXE_REG_WRITE(hw, SXE_FNAVSKEY, SXE_FNAV_SAMPLE_HASH_KEY);
 
 	fnavctrl_ori = SXE_REG_READ(hw, SXE_FNAVCTRL);
-	if((fnavctrl_ori & 0x13) != (fnavctrl & 0x13)) {
+	if ((fnavctrl_ori & 0x13) != (fnavctrl & 0x13))
 		is_clear_stat = true;
-	}
 
 	SXE_REG_WRITE(hw, SXE_FNAVCTRL, fnavctrl);
 	SXE_WRITE_FLUSH(hw);
 
 	sxe_hw_fnav_wait_init_done(hw);
 
-	if(is_clear_stat) {
+	if (is_clear_stat) {
 		SXE_REG_READ(hw, SXE_FNAVUSTAT);
 		SXE_REG_READ(hw, SXE_FNAVFSTAT);
 		SXE_REG_READ(hw, SXE_FNAVMATCH);
@@ -2283,7 +2155,6 @@  void sxe_hw_fnav_enable(struct sxe_hw *hw, u32 fnavctrl)
 		SXE_REG_READ(hw, SXE_FNAVLEN);
 	}
 
-	return;
 }
 
 static s32 sxe_hw_fnav_mode_init(struct sxe_hw *hw,
@@ -2295,8 +2166,8 @@  static s32 sxe_hw_fnav_mode_init(struct sxe_hw *hw,
 
 	if ((sxe_fnav_mode != SXE_FNAV_SAMPLE_MODE) &&
 		(sxe_fnav_mode != SXE_FNAV_SPECIFIC_MODE)) {
-		LOG_ERROR_BDF("mode[%u] a error fnav mode, fnav do not work. please use"
-			"SXE_FNAV_SAMPLE_MODE or SXE_FNAV_SPECIFIC_MODE\n",
+		LOG_ERROR_BDF("mode[%u] a error fnav mode, fnav do not work. please"
+			" use SXE_FNAV_SAMPLE_MODE or SXE_FNAV_SPECIFIC_MODE\n",
 			sxe_fnav_mode);
 		goto l_end;
 	}
@@ -2307,8 +2178,8 @@  static s32 sxe_hw_fnav_mode_init(struct sxe_hw *hw,
 	}
 
 	fnavctrl |= (0x6 << SXE_FNAVCTRL_FLEX_SHIFT) |
-		    (0xA << SXE_FNAVCTRL_MAX_LENGTH_SHIFT) |
-		    (4 << SXE_FNAVCTRL_FULL_THRESH_SHIFT);
+			(0xA << SXE_FNAVCTRL_MAX_LENGTH_SHIFT) |
+			(4 << SXE_FNAVCTRL_FULL_THRESH_SHIFT);
 
 	sxe_hw_fnav_enable(hw, fnavctrl);
 
@@ -2359,7 +2230,7 @@  static s32 sxe_hw_fnav_flow_type_mask_get(struct sxe_hw *hw,
 	case 0x0:
 		*fnavm |= SXE_FNAVM_L4P;
 		if (input_mask->ntuple.dst_port ||
-		    input_mask->ntuple.src_port) {
+			input_mask->ntuple.src_port) {
 			LOG_DEV_ERR("error on src/dst port mask\n");
 			ret = -SXE_ERR_CONFIG;
 			goto l_ret;
@@ -2423,7 +2294,7 @@  static s32 sxe_hw_fnav_flex_bytes_mask_get(struct sxe_hw *hw,
 }
 
 s32 sxe_hw_fnav_specific_rule_mask_set(struct sxe_hw *hw,
-				    union sxe_fnav_rule_info *input_mask)
+					union sxe_fnav_rule_info *input_mask)
 {
 	s32 ret;
 	u32 fnavm = SXE_FNAVM_DIPv6;
@@ -2431,44 +2302,39 @@  s32 sxe_hw_fnav_specific_rule_mask_set(struct sxe_hw *hw,
 	struct sxe_adapter *adapter = hw->adapter;
 
 
-	if (input_mask->ntuple.bkt_hash) {
+	if (input_mask->ntuple.bkt_hash)
 		LOG_DEV_ERR("bucket hash should always be 0 in mask\n");
-	}
 
 	ret = sxe_hw_fnav_vm_pool_mask_get(hw, input_mask->ntuple.vm_pool, &fnavm);
-	if (ret) {
+	if (ret)
 		goto l_err_config;
-	}
 
 	ret = sxe_hw_fnav_flow_type_mask_get(hw, input_mask,  &fnavm);
-	if (ret) {
+	if (ret)
 		goto l_err_config;
-	}
 
 	ret = sxe_hw_fnav_vlan_mask_get(hw, input_mask->ntuple.vlan_id, &fnavm);
-	if (ret) {
+	if (ret)
 		goto l_err_config;
-	}
 
 	ret = sxe_hw_fnav_flex_bytes_mask_get(hw, input_mask->ntuple.flex_bytes, &fnavm);
-	if (ret) {
+	if (ret)
 		goto l_err_config;
-	}
 
 	LOG_DEBUG_BDF("fnavm = 0x%x\n", fnavm);
 	SXE_REG_WRITE(hw, SXE_FNAVM, fnavm);
 
 	fnavtcpm = sxe_hw_fnav_port_mask_get(input_mask->ntuple.src_port,
-					     input_mask->ntuple.dst_port);
+						 input_mask->ntuple.dst_port);
 
 	LOG_DEBUG_BDF("fnavtcpm = 0x%x\n", fnavtcpm);
 	SXE_REG_WRITE(hw, SXE_FNAVTCPM, ~fnavtcpm);
 	SXE_REG_WRITE(hw, SXE_FNAVUDPM, ~fnavtcpm);
 
 	SXE_REG_WRITE_BE32(hw, SXE_FNAVSIP4M,
-			     ~input_mask->ntuple.src_ip[0]);
+				 ~input_mask->ntuple.src_ip[0]);
 	SXE_REG_WRITE_BE32(hw, SXE_FNAVDIP4M,
-			     ~input_mask->ntuple.dst_ip[0]);
+				 ~input_mask->ntuple.dst_ip[0]);
 
 	return 0;
 
@@ -2476,16 +2342,15 @@  s32 sxe_hw_fnav_specific_rule_mask_set(struct sxe_hw *hw,
 	return -SXE_ERR_CONFIG;
 }
 
-STATIC s32 sxe_hw_fnav_cmd_complete_check(struct sxe_hw *hw,
+static s32 sxe_hw_fnav_cmd_complete_check(struct sxe_hw *hw,
 							u32 *fnavcmd)
 {
 	u32 i;
 
 	for (i = 0; i < SXE_FNAVCMD_CMD_POLL * 10; i++) {
 		*fnavcmd = SXE_REG_READ(hw, SXE_FNAVCMD);
-		if (!(*fnavcmd & SXE_FNAVCMD_CMD_MASK)) {
+		if (!(*fnavcmd & SXE_FNAVCMD_CMD_MASK))
 			return 0;
-		}
 
 		udelay(10);
 	}
@@ -2497,17 +2362,16 @@  static void sxe_hw_fnav_filter_ip_set(struct sxe_hw *hw,
 					union sxe_fnav_rule_info *input)
 {
 	SXE_REG_WRITE_BE32(hw, SXE_FNAVSIPv6(0),
-			     input->ntuple.src_ip[0]);
+				 input->ntuple.src_ip[0]);
 	SXE_REG_WRITE_BE32(hw, SXE_FNAVSIPv6(1),
-			     input->ntuple.src_ip[1]);
+				 input->ntuple.src_ip[1]);
 	SXE_REG_WRITE_BE32(hw, SXE_FNAVSIPv6(2),
-			     input->ntuple.src_ip[2]);
+				 input->ntuple.src_ip[2]);
 
 	SXE_REG_WRITE_BE32(hw, SXE_FNAVIPSA, input->ntuple.src_ip[0]);
 
 	SXE_REG_WRITE_BE32(hw, SXE_FNAVIPDA, input->ntuple.dst_ip[0]);
 
-	return;
 }
 
 static void sxe_hw_fnav_filter_port_set(struct sxe_hw *hw,
@@ -2520,7 +2384,6 @@  static void sxe_hw_fnav_filter_port_set(struct sxe_hw *hw,
 	fnavport |= be16_to_cpu(input->ntuple.src_port);
 	SXE_REG_WRITE(hw, SXE_FNAVPORT, fnavport);
 
-	return;
 }
 
 static void sxe_hw_fnav_filter_vlan_set(struct sxe_hw *hw,
@@ -2533,7 +2396,6 @@  static void sxe_hw_fnav_filter_vlan_set(struct sxe_hw *hw,
 	fnavvlan |= ntohs(input->ntuple.vlan_id);
 	SXE_REG_WRITE(hw, SXE_FNAVVLAN, fnavvlan);
 
-	return;
 }
 
 static void sxe_hw_fnav_filter_bkt_hash_set(struct sxe_hw *hw,
@@ -2546,7 +2408,6 @@  static void sxe_hw_fnav_filter_bkt_hash_set(struct sxe_hw *hw,
 	fnavhash |= soft_id << SXE_FNAVHASH_SIG_SW_INDEX_SHIFT;
 	SXE_REG_WRITE(hw, SXE_FNAVHASH, fnavhash);
 
-	return;
 }
 
 static s32 sxe_hw_fnav_filter_cmd_set(struct sxe_hw *hw,
@@ -2561,9 +2422,8 @@  static s32 sxe_hw_fnav_filter_cmd_set(struct sxe_hw *hw,
 		  SXE_FNAVCMD_LAST | SXE_FNAVCMD_QUEUE_EN;
 
 #ifndef SXE_DPDK
-	if (queue == SXE_FNAV_DROP_QUEUE) {
+	if (queue == SXE_FNAV_DROP_QUEUE)
 		fnavcmd |= SXE_FNAVCMD_DROP;
-	}
 #endif
 
 	fnavcmd |= input->ntuple.flow_type << SXE_FNAVCMD_FLOW_TYPE_SHIFT;
@@ -2572,9 +2432,8 @@  static s32 sxe_hw_fnav_filter_cmd_set(struct sxe_hw *hw,
 
 	SXE_REG_WRITE(hw, SXE_FNAVCMD, fnavcmd);
 	ret = sxe_hw_fnav_cmd_complete_check(hw, &fnavcmd);
-	if (ret) {
+	if (ret)
 		LOG_DEV_ERR("flow navigator command did not complete!\n");
-	}
 
 	return ret;
 }
@@ -2597,9 +2456,8 @@  s32 sxe_hw_fnav_specific_rule_add(struct sxe_hw *hw,
 	SXE_WRITE_FLUSH(hw);
 
 	ret = sxe_hw_fnav_filter_cmd_set(hw, input, queue);
-	if (ret) {
+	if (ret)
 		LOG_ERROR_BDF("set fnav filter cmd error. ret=%d\n", ret);
-	}
 
 	return ret;
 }
@@ -2656,7 +2514,6 @@  void sxe_hw_fnav_sample_rule_configure(struct sxe_hw *hw,
 
 	LOG_DEV_DEBUG("tx queue=%x hash=%x\n", queue, (u32)fnavhashcmd);
 
-	return;
 }
 
 static u64 sxe_hw_fnav_sample_rule_hash_get(struct sxe_hw *hw,
@@ -2787,7 +2644,6 @@  static void sxe_hw_fnav_sample_stats_reinit(struct sxe_hw *hw)
 	SXE_REG_READ(hw, SXE_FNAVMISS);
 	SXE_REG_READ(hw, SXE_FNAVLEN);
 
-	return;
 }
 
 static void sxe_hw_ptp_freq_adjust(struct sxe_hw *hw, u32 adj_freq)
@@ -2796,7 +2652,6 @@  static void sxe_hw_ptp_freq_adjust(struct sxe_hw *hw, u32 adj_freq)
 	SXE_REG_WRITE(hw, SXE_TIMADJH, adj_freq);
 	SXE_WRITE_FLUSH(hw);
 
-	return;
 }
 
 u64 sxe_hw_ptp_systime_get(struct sxe_hw *hw)
@@ -2822,7 +2677,6 @@  void sxe_hw_ptp_systime_init(struct sxe_hw *hw)
 	SXE_REG_WRITE(hw, SXE_SYSTIMH, 0);
 
 	SXE_WRITE_FLUSH(hw);
-	return;
 }
 
 void sxe_hw_ptp_init(struct sxe_hw *hw)
@@ -2834,21 +2688,19 @@  void sxe_hw_ptp_init(struct sxe_hw *hw)
 	SXE_TSCTRL_L4_UNICAST;
 
 	regval = SXE_REG_READ(hw, SXE_TSCTRL);
-	regval &= ~SXE_TSCTRL_ONESTEP;	
-	regval &= ~SXE_TSCTRL_CSEN;	
+	regval &= ~SXE_TSCTRL_ONESTEP;
+	regval &= ~SXE_TSCTRL_CSEN;
 	regval |= tsctl;
 	SXE_REG_WRITE(hw, SXE_TSCTRL, regval);
 
 	SXE_REG_WRITE(hw, SXE_TIMINC,
 			SXE_TIMINC_SET(SXE_INCPD, SXE_IV_NS, SXE_IV_SNS));
 
-	return;
 }
 
 void sxe_hw_ptp_rx_timestamp_clear(struct sxe_hw *hw)
 {
 	SXE_REG_READ(hw, SXE_RXSTMPH);
-	return;
 }
 
 void sxe_hw_ptp_tx_timestamp_get(struct sxe_hw *hw,
@@ -2878,13 +2730,11 @@  void sxe_hw_ptp_tx_timestamp_get(struct sxe_hw *hw,
 	*ts_ns  = (sec_8bit << 24) | ((reg_ns & 0xFFFFFF00) >> 8);
 
 	if (unlikely((sec_24bit - systimm_24bit) >= 0x00FFFFF0)) {
-		if (systimm_8bit >= 1) {
+		if (systimm_8bit >= 1)
 			systimm_8bit -= 1;
-		}
 	}
 
 	*ts_sec = systimm_8bit | sec_24bit;
-	return;
 }
 
 u64 sxe_hw_ptp_rx_timestamp_get(struct sxe_hw *hw)
@@ -2909,9 +2759,8 @@  bool sxe_hw_ptp_is_rx_timestamp_valid(struct sxe_hw *hw)
 	u32 tsyncrxctl;
 
 	tsyncrxctl = SXE_REG_READ(hw, SXE_TSYNCRXCTL);
-	if (tsyncrxctl & SXE_TSYNCRXCTL_RXTT) {
+	if (tsyncrxctl & SXE_TSYNCRXCTL_RXTT)
 		rx_tmstamp_valid = true;
-	}
 
 	return rx_tmstamp_valid;
 }
@@ -2923,9 +2772,9 @@  void sxe_hw_ptp_timestamp_mode_set(struct sxe_hw *hw,
 
 	if (is_l2) {
 		SXE_REG_WRITE(hw, SXE_ETQF(SXE_ETQF_FILTER_1588),
-			(SXE_ETQF_FILTER_EN |   
-			 SXE_ETQF_1588 |	
-			 ETH_P_1588));		
+			(SXE_ETQF_FILTER_EN |
+			 SXE_ETQF_1588 |
+			 ETH_P_1588));
 	} else {
 		SXE_REG_WRITE(hw, SXE_ETQF(SXE_ETQF_FILTER_1588), 0);
 	}
@@ -2940,7 +2789,6 @@  void sxe_hw_ptp_timestamp_mode_set(struct sxe_hw *hw,
 
 	SXE_WRITE_FLUSH(hw);
 
-	return;
 }
 
 void sxe_hw_ptp_timestamp_enable(struct sxe_hw *hw)
@@ -2954,7 +2802,6 @@  void sxe_hw_ptp_timestamp_enable(struct sxe_hw *hw)
 			SXE_TSYNCRXCTL_REN));
 	SXE_WRITE_FLUSH(hw);
 
-	return;
 }
 
 static void sxe_hw_dcb_tc_rss_configure(struct sxe_hw *hw, u16 rss)
@@ -2991,9 +2838,8 @@  static void sxe_hw_tx_ring_disable(struct sxe_hw *hw, u8 reg_idx,
 		wait_delay += delay_interval * 2;
 		txdctl = SXE_REG_READ(hw, SXE_TXDCTL(reg_idx));
 
-		if (!(txdctl & SXE_TXDCTL_ENABLE)) {
+		if (!(txdctl & SXE_TXDCTL_ENABLE))
 			return;
-		}
 	}
 
 	LOG_MSG_ERR(drv, "register TXDCTL.ENABLE not cleared within the polling period\n");
@@ -3037,7 +2883,6 @@  static u32 sxe_hw_tx_dbu_fc_status_get(struct sxe_hw *hw)
 static void sxe_hw_fnav_sample_hash_set(struct sxe_hw *hw, u64 hash)
 {
 	SXE_REG64_WRITE(hw, SXE_FNAVHASH, hash);
-	return;
 }
 
 static const struct sxe_dbu_operations sxe_dbu_ops = {
@@ -3088,19 +2933,12 @@  static const struct sxe_dbu_operations sxe_dbu_ops = {
 };
 
 
-void sxe_hw_rx_dma_ctrl_init(struct sxe_hw *hw, bool crc_strip_on)
+void sxe_hw_rx_dma_ctrl_init(struct sxe_hw *hw)
 {
 	u32 rx_dma_ctrl = SXE_REG_READ(hw, SXE_RDRXCTL);
 
-	if (crc_strip_on) {
-		rx_dma_ctrl |= SXE_RDRXCTL_CRCSTRIP;
-	} else {
-		rx_dma_ctrl &= ~SXE_RDRXCTL_CRCSTRIP;
-	}
-
 	rx_dma_ctrl &= ~SXE_RDRXCTL_LROFRSTSIZE;
 	SXE_REG_WRITE(hw, SXE_RDRXCTL, rx_dma_ctrl);
-	return;
 }
 
 void sxe_hw_rx_dma_lro_ctrl_set(struct sxe_hw *hw)
@@ -3109,7 +2947,6 @@  void sxe_hw_rx_dma_lro_ctrl_set(struct sxe_hw *hw)
 
 	rx_dma_ctrl |= SXE_RDRXCTL_LROACKC;
 	SXE_REG_WRITE(hw, SXE_RDRXCTL, rx_dma_ctrl);
-	return;
 }
 
 void sxe_hw_rx_desc_thresh_set(struct sxe_hw *hw, u8 reg_idx)
@@ -3121,7 +2958,6 @@  void sxe_hw_rx_desc_thresh_set(struct sxe_hw *hw, u8 reg_idx)
 	rxdctl |= 0x10;
 	SXE_REG_WRITE(hw, SXE_RXDCTL(reg_idx), rxdctl);
 
-	return;
 }
 
 void sxe_hw_rx_ring_switch(struct sxe_hw *hw, u8 reg_idx, bool is_on)
@@ -3156,7 +2992,6 @@  void sxe_hw_rx_ring_switch(struct sxe_hw *hw, u8 reg_idx, bool is_on)
 			  "the polling period\n", reg_idx, is_on);
 	}
 
-	return;
 }
 
 void sxe_hw_rx_ring_switch_not_polling(struct sxe_hw *hw, u8 reg_idx, bool is_on)
@@ -3172,7 +3007,6 @@  void sxe_hw_rx_ring_switch_not_polling(struct sxe_hw *hw, u8 reg_idx, bool is_on
 
 	SXE_WRITE_FLUSH(hw);
 
-	return;
 }
 
 void sxe_hw_rx_queue_desc_reg_configure(struct sxe_hw *hw,
@@ -3181,21 +3015,18 @@  void sxe_hw_rx_queue_desc_reg_configure(struct sxe_hw *hw,
 {
 	SXE_REG_WRITE(hw, SXE_RDH(reg_idx), rdh_value);
 	SXE_REG_WRITE(hw, SXE_RDT(reg_idx), rdt_value);
-	return;
 }
 
 static void sxe_hw_rx_ring_head_init(struct sxe_hw *hw, u8 reg_idx)
 {
 	SXE_REG_WRITE(hw, SXE_RDH(reg_idx), 0);
 
-	return;
 }
 
 static void sxe_hw_rx_ring_tail_init(struct sxe_hw *hw, u8 reg_idx)
 {
 	SXE_REG_WRITE(hw, SXE_RDT(reg_idx), 0);
 
-	return;
 }
 
 void sxe_hw_rx_ring_desc_configure(struct sxe_hw *hw,
@@ -3212,12 +3043,10 @@  void sxe_hw_rx_ring_desc_configure(struct sxe_hw *hw,
 	sxe_hw_rx_ring_head_init(hw, reg_idx);
 	sxe_hw_rx_ring_tail_init(hw, reg_idx);
 
-	return;
 }
 
 void sxe_hw_rx_rcv_ctl_configure(struct sxe_hw *hw, u8 reg_idx,
-				   u32 header_buf_len, u32 pkg_buf_len
-				   )
+				   u32 header_buf_len, u32 pkg_buf_len)
 {
 	u32 srrctl;
 
@@ -3228,7 +3057,6 @@  void sxe_hw_rx_rcv_ctl_configure(struct sxe_hw *hw, u8 reg_idx,
 
 	SXE_REG_WRITE(hw, SXE_SRRCTL(reg_idx), srrctl);
 
-	return;
 }
 
 void sxe_hw_rx_lro_ctl_configure(struct sxe_hw *hw,
@@ -3240,7 +3068,6 @@  void sxe_hw_rx_lro_ctl_configure(struct sxe_hw *hw,
 	lroctrl |= max_desc;
 	SXE_REG_WRITE(hw, SXE_LROCTL(reg_idx), lroctrl);
 
-	return;
 }
 
 static u32 sxe_hw_rx_desc_ctrl_get(struct sxe_hw *hw, u8 reg_idx)
@@ -3264,7 +3091,6 @@  static void sxe_hw_dcb_arbiter_set(struct sxe_hw *hw, bool is_enable)
 		SXE_REG_WRITE(hw, SXE_RTTDCS, rttdcs);
 	}
 
-	return;
 }
 
 
@@ -3291,11 +3117,10 @@  static void sxe_hw_tx_multi_ring_configure(struct sxe_hw *hw, u8 tcs,
 		} else if (tcs > SXE_DCB_1_TC) {
 			mtqc = SXE_MTQC_RT_ENA | SXE_MTQC_4TC_4TQ;
 		} else {
-			if (max_txq > 63) {
+			if (max_txq > 63)
 				mtqc = SXE_MTQC_RT_ENA | SXE_MTQC_4TC_4TQ;
-			} else {
+			else
 				mtqc = SXE_MTQC_64Q_1PB;
-			}
 		}
 	}
 
@@ -3303,21 +3128,18 @@  static void sxe_hw_tx_multi_ring_configure(struct sxe_hw *hw, u8 tcs,
 
 	sxe_hw_dcb_arbiter_set(hw, true);
 
-	return;
 }
 
 void sxe_hw_tx_ring_head_init(struct sxe_hw *hw, u8 reg_idx)
 {
 	SXE_REG_WRITE(hw, SXE_TDH(reg_idx), 0);
 
-	return;
 }
 
 void sxe_hw_tx_ring_tail_init(struct sxe_hw *hw, u8 reg_idx)
 {
 	SXE_REG_WRITE(hw, SXE_TDT(reg_idx), 0);
 
-	return;
 }
 
 void sxe_hw_tx_ring_desc_configure(struct sxe_hw *hw,
@@ -3328,14 +3150,12 @@  void sxe_hw_tx_ring_desc_configure(struct sxe_hw *hw,
 
 	SXE_WRITE_FLUSH(hw);
 
-	SXE_REG_WRITE(hw, SXE_TDBAL(reg_idx), (desc_dma_addr & \
-						DMA_BIT_MASK(32)));
+	SXE_REG_WRITE(hw, SXE_TDBAL(reg_idx), (desc_dma_addr & DMA_BIT_MASK(32)));
 	SXE_REG_WRITE(hw, SXE_TDBAH(reg_idx), (desc_dma_addr >> 32));
 	SXE_REG_WRITE(hw, SXE_TDLEN(reg_idx), desc_mem_len);
 	sxe_hw_tx_ring_head_init(hw, reg_idx);
 	sxe_hw_tx_ring_tail_init(hw, reg_idx);
 
-	return;
 }
 
 void sxe_hw_tx_desc_thresh_set(
@@ -3352,7 +3172,6 @@  void sxe_hw_tx_desc_thresh_set(
 
 	SXE_REG_WRITE(hw, SXE_TXDCTL(reg_idx), txdctl);
 
-	return;
 }
 
 void sxe_hw_all_ring_disable(struct sxe_hw *hw, u32 ring_max)
@@ -3372,7 +3191,6 @@  void sxe_hw_all_ring_disable(struct sxe_hw *hw, u32 ring_max)
 	SXE_WRITE_FLUSH(hw);
 	usleep_range(1000, 2000);
 
-	return;
 }
 
 void sxe_hw_tx_ring_switch(struct sxe_hw *hw, u8 reg_idx, bool is_on)
@@ -3404,7 +3222,6 @@  void sxe_hw_tx_ring_switch(struct sxe_hw *hw, u8 reg_idx, bool is_on)
 			  "the polling period\n", reg_idx, is_on);
 	}
 
-	return;
 }
 
 void sxe_hw_tx_ring_switch_not_polling(struct sxe_hw *hw, u8 reg_idx, bool is_on)
@@ -3418,7 +3235,6 @@  void sxe_hw_tx_ring_switch_not_polling(struct sxe_hw *hw, u8 reg_idx, bool is_on
 		SXE_REG_WRITE(hw, SXE_TXDCTL(reg_idx), txdctl);
 	}
 
-	return;
 }
 
 void sxe_hw_tx_pkt_buf_thresh_configure(struct sxe_hw *hw,
@@ -3426,26 +3242,21 @@  void sxe_hw_tx_pkt_buf_thresh_configure(struct sxe_hw *hw,
 {
 	u32 i, tx_pkt_size, tx_pb_thresh;
 
-	if (!num_pb){
+	if (!num_pb)
 		num_pb = 1;
-	}
 
 	tx_pkt_size = SXE_TX_PBSIZE_MAX / num_pb;
-	if (true == dcb_enable) {
+	if (true == dcb_enable)
 		tx_pb_thresh = (tx_pkt_size / 1024) - SXE_TX_PKT_SIZE_MAX;
-	} else {
+	else
 		tx_pb_thresh = (tx_pkt_size / 1024) - SXE_NODCB_TX_PKT_SIZE_MAX;
-	}
 
-	for (i = 0; i < num_pb; i++) {
+	for (i = 0; i < num_pb; i++)
 		SXE_REG_WRITE(hw, SXE_TXPBTHRESH(i), tx_pb_thresh);
-	}
 
-	for (; i < SXE_PKG_BUF_NUM_MAX; i++) {
+	for (; i < SXE_PKG_BUF_NUM_MAX; i++)
 		SXE_REG_WRITE(hw, SXE_TXPBTHRESH(i), 0);
-	}
 
-	return;
 }
 
 void sxe_hw_tx_enable(struct sxe_hw *hw)
@@ -3456,7 +3267,6 @@  void sxe_hw_tx_enable(struct sxe_hw *hw)
 	ctl |= SXE_DMATXCTL_TE;
 	SXE_REG_WRITE(hw, SXE_DMATXCTL, ctl);
 
-	return;
 }
 
 static u32 sxe_hw_tx_desc_ctrl_get(struct sxe_hw *hw, u8 reg_idx)
@@ -3476,7 +3286,6 @@  static void sxe_hw_tx_desc_wb_thresh_clear(struct sxe_hw *hw, u8 reg_idx)
 	reg_data |= SXE_TXDCTL_ENABLE;
 	SXE_REG_WRITE(hw, SXE_TXDCTL(reg_idx), reg_data);
 
-	return;
 }
 
 void sxe_hw_vlan_tag_strip_switch(struct sxe_hw *hw,
@@ -3486,15 +3295,13 @@  void sxe_hw_vlan_tag_strip_switch(struct sxe_hw *hw,
 
 	rxdctl = SXE_REG_READ(hw, SXE_RXDCTL(reg_index));
 
-	if (is_enable) {
+	if (is_enable)
 		rxdctl |= SXE_RXDCTL_VME;
-	} else {
+	else
 		rxdctl &= ~SXE_RXDCTL_VME;
-	}
 
 	SXE_REG_WRITE(hw, SXE_RXDCTL(reg_index), rxdctl);
 
-	return;
 }
 
 static void sxe_hw_tx_vlan_tag_set(struct sxe_hw *hw,
@@ -3503,13 +3310,11 @@  static void sxe_hw_tx_vlan_tag_set(struct sxe_hw *hw,
 	u32 vmvir = vid | (qos << VLAN_PRIO_SHIFT) | SXE_VMVIR_VLANA_DEFAULT;
 
 	SXE_REG_WRITE(hw, SXE_VMVIR(vf), vmvir);
-	return;
 }
 
 void sxe_hw_tx_vlan_tag_clear(struct sxe_hw *hw, u32 vf)
 {
 	SXE_REG_WRITE(hw, SXE_VMVIR(vf), 0);
-	return;
 }
 
 u32 sxe_hw_tx_vlan_insert_get(struct sxe_hw *hw, u32 vf)
@@ -3523,42 +3328,39 @@  void sxe_hw_tx_ring_info_get(struct sxe_hw *hw,
 	*head = SXE_REG_READ(hw, SXE_TDH(idx));
 	*tail = SXE_REG_READ(hw, SXE_TDT(idx));
 
-	return;
 }
 
 void sxe_hw_dcb_rx_bw_alloc_configure(struct sxe_hw *hw,
-				      u16 *refill,
-				      u16 *max,
-				      u8 *bwg_id,
-				      u8 *prio_type,
-				      u8 *prio_tc,
-				      u8 max_priority)
-{
-	u32    reg;
-	u32    credit_refill;
-	u32    credit_max;
-	u8     i;
+					  u16 *refill,
+					  u16 *max,
+					  u8 *bwg_id,
+					  u8 *prio_type,
+					  u8 *prio_tc,
+					  u8 max_priority)
+{
+	u32	reg;
+	u32	credit_refill;
+	u32	credit_max;
+	u8	 i;
 
 	reg = SXE_RTRPCS_RRM | SXE_RTRPCS_RAC | SXE_RTRPCS_ARBDIS;
 	SXE_REG_WRITE(hw, SXE_RTRPCS, reg);
 
 	reg = 0;
-	for (i = 0; i < max_priority; i++) {
+	for (i = 0; i < max_priority; i++)
 		reg |= (prio_tc[i] << (i * SXE_RTRUP2TC_UP_SHIFT));
-	}
 
 	SXE_REG_WRITE(hw, SXE_RTRUP2TC, reg);
 
 	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
 		credit_refill = refill[i];
-		credit_max    = max[i];
+		credit_max	= max[i];
 		reg = credit_refill | (credit_max << SXE_RTRPT4C_MCL_SHIFT);
 
 		reg |= (u32)(bwg_id[i]) << SXE_RTRPT4C_BWG_SHIFT;
 
-		if (prio_type[i] == PRIO_LINK) {
+		if (prio_type[i] == PRIO_LINK)
 			reg |= SXE_RTRPT4C_LSP;
-		}
 
 		SXE_REG_WRITE(hw, SXE_RTRPT4C(i), reg);
 	}
@@ -3566,7 +3368,6 @@  void sxe_hw_dcb_rx_bw_alloc_configure(struct sxe_hw *hw,
 	reg = SXE_RTRPCS_RRM | SXE_RTRPCS_RAC;
 	SXE_REG_WRITE(hw, SXE_RTRPCS, reg);
 
-	return;
 }
 
 void sxe_hw_dcb_tx_desc_bw_alloc_configure(struct sxe_hw *hw,
@@ -3575,8 +3376,8 @@  void sxe_hw_dcb_tx_desc_bw_alloc_configure(struct sxe_hw *hw,
 					   u8 *bwg_id,
 					   u8 *prio_type)
 {
-	u32    reg, max_credits;
-	u8     i;
+	u32	reg, max_credits;
+	u8	 i;
 
 	for (i = 0; i < 128; i++) {
 		SXE_REG_WRITE(hw, SXE_RTTDQSEL, i);
@@ -3589,13 +3390,11 @@  void sxe_hw_dcb_tx_desc_bw_alloc_configure(struct sxe_hw *hw,
 		reg |= refill[i];
 		reg |= (u32)(bwg_id[i]) << SXE_RTTDT2C_BWG_SHIFT;
 
-		if (prio_type[i] == PRIO_GROUP) {
+		if (prio_type[i] == PRIO_GROUP)
 			reg |= SXE_RTTDT2C_GSP;
-		}
 
-		if (prio_type[i] == PRIO_LINK) {
+		if (prio_type[i] == PRIO_LINK)
 			reg |= SXE_RTTDT2C_LSP;
-		}
 
 		SXE_REG_WRITE(hw, SXE_RTTDT2C(i), reg);
 	}
@@ -3603,7 +3402,6 @@  void sxe_hw_dcb_tx_desc_bw_alloc_configure(struct sxe_hw *hw,
 	reg = SXE_RTTDCS_TDPAC | SXE_RTTDCS_TDRM;
 	SXE_REG_WRITE(hw, SXE_RTTDCS, reg);
 
-	return;
 }
 
 void sxe_hw_dcb_tx_data_bw_alloc_configure(struct sxe_hw *hw,
@@ -3618,14 +3416,13 @@  void sxe_hw_dcb_tx_data_bw_alloc_configure(struct sxe_hw *hw,
 	u8 i;
 
 	reg = SXE_RTTPCS_TPPAC | SXE_RTTPCS_TPRM |
-	      (SXE_RTTPCS_ARBD_DCB << SXE_RTTPCS_ARBD_SHIFT) |
-	      SXE_RTTPCS_ARBDIS;
+		  (SXE_RTTPCS_ARBD_DCB << SXE_RTTPCS_ARBD_SHIFT) |
+		  SXE_RTTPCS_ARBDIS;
 	SXE_REG_WRITE(hw, SXE_RTTPCS, reg);
 
 	reg = 0;
-	for (i = 0; i < max_priority; i++) {
+	for (i = 0; i < max_priority; i++)
 		reg |= (prio_tc[i] << (i * SXE_RTTUP2TC_UP_SHIFT));
-	}
 
 	SXE_REG_WRITE(hw, SXE_RTTUP2TC, reg);
 
@@ -3634,22 +3431,19 @@  void sxe_hw_dcb_tx_data_bw_alloc_configure(struct sxe_hw *hw,
 		reg |= (u32)(max[i]) << SXE_RTTPT2C_MCL_SHIFT;
 		reg |= (u32)(bwg_id[i]) << SXE_RTTPT2C_BWG_SHIFT;
 
-		if (prio_type[i] == PRIO_GROUP) {
+		if (prio_type[i] == PRIO_GROUP)
 			reg |= SXE_RTTPT2C_GSP;
-		}
 
-		if (prio_type[i] == PRIO_LINK) {
+		if (prio_type[i] == PRIO_LINK)
 			reg |= SXE_RTTPT2C_LSP;
-		}
 
 		SXE_REG_WRITE(hw, SXE_RTTPT2C(i), reg);
 	}
 
 	reg = SXE_RTTPCS_TPPAC | SXE_RTTPCS_TPRM |
-	      (SXE_RTTPCS_ARBD_DCB << SXE_RTTPCS_ARBD_SHIFT);
+		  (SXE_RTTPCS_ARBD_DCB << SXE_RTTPCS_ARBD_SHIFT);
 	SXE_REG_WRITE(hw, SXE_RTTPCS, reg);
 
-	return;
 }
 
 void sxe_hw_dcb_pfc_configure(struct sxe_hw *hw,
@@ -3682,9 +3476,8 @@  void sxe_hw_dcb_pfc_configure(struct sxe_hw *hw,
 	SXE_REG_WRITE(hw, SXE_PFCTOP, reg_val);
 
 	for (i = 0; i < max_priority; i++) {
-		if (prio_tc[i] > max_tc) {
+		if (prio_tc[i] > max_tc)
 			max_tc = prio_tc[i];
-		}
 	}
 
 	for (i = 0; i <= max_tc; i++) {
@@ -3716,13 +3509,11 @@  void sxe_hw_dcb_pfc_configure(struct sxe_hw *hw,
 	}
 
 	reg = hw->fc.pause_time * 0x00010001;
-	for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) {
+	for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
 		SXE_REG_WRITE(hw, SXE_FCTTV(i), reg);
-	}
 
 	SXE_REG_WRITE(hw, SXE_FCRTV, hw->fc.pause_time / 2);
 
-	return;
 }
 
 static void sxe_hw_dcb_8tc_vmdq_off_stats_configure(struct sxe_hw *hw)
@@ -3736,28 +3527,26 @@  static void sxe_hw_dcb_8tc_vmdq_off_stats_configure(struct sxe_hw *hw)
 	}
 
 	for (i = 0; i < 32; i++) {
-		if (i < 8) {
+		if (i < 8)
 			reg = 0x00000000;
-		} else if (i < 16) {
+		else if (i < 16)
 			reg = 0x01010101;
-		} else if (i < 20) {
+		else if (i < 20)
 			reg = 0x02020202;
-		} else if (i < 24) {
+		else if (i < 24)
 			reg = 0x03030303;
-		} else if (i < 26) {
+		else if (i < 26)
 			reg = 0x04040404;
-		} else if (i < 28) {
+		else if (i < 28)
 			reg = 0x05050505;
-		} else if (i < 30) {
+		else if (i < 30)
 			reg = 0x06060606;
-		} else {
+		else
 			reg = 0x07070707;
-		}
 
 		SXE_REG_WRITE(hw, SXE_TQSM(i), reg);
 	}
 
-	return;
 }
 
 static void sxe_hw_dcb_rx_up_tc_map_set(struct sxe_hw *hw, u8 tc)
@@ -3771,28 +3560,23 @@  static void sxe_hw_dcb_rx_up_tc_map_set(struct sxe_hw *hw, u8 tc)
 	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
 		u8 up2tc = reg >> (i * SXE_RTRUP2TC_UP_SHIFT);
 
-		if (up2tc > tc) {
+		if (up2tc > tc)
 			reg &= ~(0x7 << SXE_RTRUP2TC_UP_MASK);
-		}
 	}
 
-	if (reg != rsave) {
+	if (reg != rsave)
 		SXE_REG_WRITE(hw, SXE_RTRUP2TC, reg);
-	}
 
-	return;
 }
 
 void sxe_hw_vt_pool_loopback_switch(struct sxe_hw *hw,
 							bool is_enable)
 {
-	if (true == is_enable) {
+	if (true == is_enable)
 		SXE_REG_WRITE(hw, SXE_PFDTXGSWC, SXE_PFDTXGSWC_VT_LBEN);
-	} else {
+	else
 		SXE_REG_WRITE(hw, SXE_PFDTXGSWC, 0);
-	}
 
-	return;
 }
 
 void sxe_hw_pool_rx_ring_drop_enable(struct sxe_hw *hw, u8 vf_idx,
@@ -3801,12 +3585,10 @@  void sxe_hw_pool_rx_ring_drop_enable(struct sxe_hw *hw, u8 vf_idx,
 	u32 qde = SXE_QDE_ENABLE;
 	u8 i;
 
-	if (pf_vlan) {
+	if (pf_vlan)
 		qde |= SXE_QDE_HIDE_VLAN;
-	}
 
-	for (i = (vf_idx * ring_per_pool); i < ((vf_idx + 1) * ring_per_pool); i++)
-	{
+	for (i = (vf_idx * ring_per_pool); i < ((vf_idx + 1) * ring_per_pool); i++) {
 		u32 value;
 
 		SXE_WRITE_FLUSH(hw);
@@ -3817,7 +3599,6 @@  void sxe_hw_pool_rx_ring_drop_enable(struct sxe_hw *hw, u8 vf_idx,
 		SXE_REG_WRITE(hw, SXE_QDE, value);
 	}
 
-	return;
 }
 
 u32 sxe_hw_rx_pool_bitmap_get(struct sxe_hw *hw, u8 reg_idx)
@@ -3830,7 +3611,6 @@  void sxe_hw_rx_pool_bitmap_set(struct sxe_hw *hw,
 {
 	SXE_REG_WRITE(hw, SXE_VFRE(reg_idx), bitmap);
 
-	return;
 }
 
 u32 sxe_hw_tx_pool_bitmap_get(struct sxe_hw *hw, u8 reg_idx)
@@ -3843,14 +3623,12 @@  void sxe_hw_tx_pool_bitmap_set(struct sxe_hw *hw,
 {
 	SXE_REG_WRITE(hw, SXE_VFTE(reg_idx), bitmap);
 
-	return;
 }
 
 void sxe_hw_dcb_max_mem_window_set(struct sxe_hw *hw, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_RTTBCNRM, value);
 
-	return;
 }
 
 void sxe_hw_dcb_tx_ring_rate_factor_set(struct sxe_hw *hw,
@@ -3859,7 +3637,6 @@  void sxe_hw_dcb_tx_ring_rate_factor_set(struct sxe_hw *hw,
 	SXE_REG_WRITE(hw, SXE_RTTDQSEL, ring_idx);
 	SXE_REG_WRITE(hw, SXE_RTTBCNRC, rate);
 
-	return;
 }
 
 void sxe_hw_spoof_count_enable(struct sxe_hw *hw,
@@ -3871,7 +3648,6 @@  void sxe_hw_spoof_count_enable(struct sxe_hw *hw,
 
 	SXE_REG_WRITE(hw, SXE_VMECM(reg_idx), value);
 
-	return;
 }
 
 void sxe_hw_pool_mac_anti_spoof_set(struct sxe_hw *hw,
@@ -3883,15 +3659,13 @@  void sxe_hw_pool_mac_anti_spoof_set(struct sxe_hw *hw,
 
 	value = SXE_REG_READ(hw, SXE_SPOOF(reg_index));
 
-	if (status) {
+	if (status)
 		value |= BIT(bit_index);
-	} else {
+	else
 		value &= ~BIT(bit_index);
-	}
 
 	SXE_REG_WRITE(hw, SXE_SPOOF(reg_index), value);
 
-	return;
 }
 
 static void sxe_hw_dcb_rx_up_tc_map_get(struct sxe_hw *hw, u8 *map)
@@ -3904,22 +3678,19 @@  static void sxe_hw_dcb_rx_up_tc_map_get(struct sxe_hw *hw, u8 *map)
 			(reg >> (i * SXE_RTRUP2TC_UP_SHIFT));
 	}
 
-	return;
 }
 
 void sxe_hw_rx_drop_switch(struct sxe_hw *hw, u8 idx, bool is_enable)
 {
 	u32 srrctl = SXE_REG_READ(hw, SXE_SRRCTL(idx));
 
-	if (true == is_enable) {
+	if (true == is_enable)
 		srrctl |= SXE_SRRCTL_DROP_EN;
-	} else {
+	else
 		srrctl &= ~SXE_SRRCTL_DROP_EN;
-	}
 
 	SXE_REG_WRITE(hw, SXE_SRRCTL(idx), srrctl);
 
-	return;
 }
 
 static void sxe_hw_pool_vlan_anti_spoof_set(struct sxe_hw *hw,
@@ -3931,15 +3702,13 @@  static void sxe_hw_pool_vlan_anti_spoof_set(struct sxe_hw *hw,
 
 	value = SXE_REG_READ(hw, SXE_SPOOF(reg_index));
 
-	if (status) {
+	if (status)
 		value |= BIT(bit_index);
-	} else {
+	else
 		value &= ~BIT(bit_index);
-	}
 
 	SXE_REG_WRITE(hw, SXE_SPOOF(reg_index), value);
 
-	return;
 }
 
 static void sxe_hw_vf_tx_desc_addr_clear(struct sxe_hw *hw,
@@ -3952,7 +3721,6 @@  static void sxe_hw_vf_tx_desc_addr_clear(struct sxe_hw *hw,
 		SXE_REG_WRITE(hw, SXE_PVFTDWBAH_N(ring_per_pool, vf_idx, i), 0);
 	}
 
-	return;
 }
 
 static void sxe_hw_vf_tx_ring_disable(struct sxe_hw *hw,
@@ -3974,7 +3742,6 @@  static void sxe_hw_vf_tx_ring_disable(struct sxe_hw *hw,
 
 	SXE_WRITE_FLUSH(hw);
 
-	return;
 }
 
 void sxe_hw_dcb_rate_limiter_clear(struct sxe_hw *hw, u8 ring_max)
@@ -3987,7 +3754,6 @@  void sxe_hw_dcb_rate_limiter_clear(struct sxe_hw *hw, u8 ring_max)
 	}
 	SXE_WRITE_FLUSH(hw);
 
-	return;
 }
 
 static void sxe_hw_tx_tph_update(struct sxe_hw *hw, u8 ring_idx, u8 cpu)
@@ -3996,12 +3762,11 @@  static void sxe_hw_tx_tph_update(struct sxe_hw *hw, u8 ring_idx, u8 cpu)
 
 	value <<= SXE_TPH_TXCTRL_CPUID_SHIFT;
 
-	value |= SXE_TPH_TXCTRL_DESC_RRO_EN | \
-		 SXE_TPH_TXCTRL_DATA_RRO_EN | \
-		 SXE_TPH_TXCTRL_DESC_TPH_EN;
+	value |= (SXE_TPH_TXCTRL_DESC_RRO_EN |
+		 SXE_TPH_TXCTRL_DATA_RRO_EN |
+		 SXE_TPH_TXCTRL_DESC_TPH_EN);
 
 	SXE_REG_WRITE(hw, SXE_TPH_TXCTRL(ring_idx), value);
-	return;
 }
 
 static void sxe_hw_rx_tph_update(struct sxe_hw *hw, u8 ring_idx, u8 cpu)
@@ -4010,29 +3775,26 @@  static void sxe_hw_rx_tph_update(struct sxe_hw *hw, u8 ring_idx, u8 cpu)
 
 	value <<= SXE_TPH_RXCTRL_CPUID_SHIFT;
 
-	value |= SXE_TPH_RXCTRL_DESC_RRO_EN | \
-		 SXE_TPH_RXCTRL_DATA_TPH_EN | \
-		 SXE_TPH_RXCTRL_DESC_TPH_EN;
+	value |= (SXE_TPH_RXCTRL_DESC_RRO_EN |
+		 SXE_TPH_RXCTRL_DATA_TPH_EN |
+		 SXE_TPH_RXCTRL_DESC_TPH_EN);
 
 	SXE_REG_WRITE(hw, SXE_TPH_RXCTRL(ring_idx), value);
-	return;
 }
 
 static void sxe_hw_tph_switch(struct sxe_hw *hw, bool is_enable)
 {
-	if (is_enable == true) {
+	if (is_enable == true)
 		SXE_REG_WRITE(hw, SXE_TPH_CTRL, SXE_TPH_CTRL_MODE_CB2);
-	} else {
+	else
 		SXE_REG_WRITE(hw, SXE_TPH_CTRL, SXE_TPH_CTRL_DISABLE);
-	}
 
-	return;
 }
 
 static const struct sxe_dma_operations sxe_dma_ops = {
-	.rx_dma_ctrl_init		= sxe_hw_rx_dma_ctrl_init,
-	.rx_ring_switch			= sxe_hw_rx_ring_switch,
-	.rx_ring_switch_not_polling	= sxe_hw_rx_ring_switch_not_polling,
+	.rx_dma_ctrl_init	   = sxe_hw_rx_dma_ctrl_init,
+	.rx_ring_switch		 = sxe_hw_rx_ring_switch,
+	.rx_ring_switch_not_polling = sxe_hw_rx_ring_switch_not_polling,
 	.rx_ring_desc_configure		= sxe_hw_rx_ring_desc_configure,
 	.rx_desc_thresh_set		= sxe_hw_rx_desc_thresh_set,
 	.rx_rcv_ctl_configure		= sxe_hw_rx_rcv_ctl_configure,
@@ -4049,7 +3811,7 @@  static const struct sxe_dma_operations sxe_dma_ops = {
 	.tx_desc_thresh_set		= sxe_hw_tx_desc_thresh_set,
 	.tx_desc_wb_thresh_clear	= sxe_hw_tx_desc_wb_thresh_clear,
 	.tx_ring_switch			= sxe_hw_tx_ring_switch,
-	.tx_ring_switch_not_polling     = sxe_hw_tx_ring_switch_not_polling,
+	.tx_ring_switch_not_polling	 = sxe_hw_tx_ring_switch_not_polling,
 	.tx_pkt_buf_thresh_configure	= sxe_hw_tx_pkt_buf_thresh_configure,
 	.tx_desc_ctrl_get		= sxe_hw_tx_desc_ctrl_get,
 	.tx_ring_info_get		= sxe_hw_tx_ring_info_get,
@@ -4084,9 +3846,9 @@  static const struct sxe_dma_operations sxe_dma_ops = {
 	.max_dcb_memory_window_set	= sxe_hw_dcb_max_mem_window_set,
 	.spoof_count_enable		= sxe_hw_spoof_count_enable,
 
-	.vf_tx_ring_disable	        = sxe_hw_vf_tx_ring_disable,
-	.all_ring_disable               = sxe_hw_all_ring_disable,
-	.tx_ring_tail_init 	        = sxe_hw_tx_ring_tail_init,
+	.vf_tx_ring_disable		 = sxe_hw_vf_tx_ring_disable,
+	.all_ring_disable		   = sxe_hw_all_ring_disable,
+	.tx_ring_tail_init		  = sxe_hw_tx_ring_tail_init,
 };
 
 
@@ -4099,16 +3861,15 @@  static void sxe_hw_ipsec_rx_sa_load(struct sxe_hw *hw, u16 idx,
 
 	reg &= SXE_RXTXIDX_IPS_EN;
 	reg |= type << SXE_RXIDX_TBL_SHIFT |
-	       idx << SXE_RXTXIDX_IDX_SHIFT |
-	       SXE_RXTXIDX_WRITE;
+		   idx << SXE_RXTXIDX_IDX_SHIFT |
+		   SXE_RXTXIDX_WRITE;
 	SXE_REG_WRITE(hw, SXE_IPSRXIDX, reg);
 	SXE_WRITE_FLUSH(hw);
 
-	return;
 }
 
 static void sxe_hw_ipsec_rx_ip_store(struct sxe_hw *hw,
-					     __be32 *ip_addr, u8 ip_len, u8 ip_idx)
+						 __be32 *ip_addr, u8 ip_len, u8 ip_idx)
 {
 	u8 i;
 
@@ -4119,11 +3880,10 @@  static void sxe_hw_ipsec_rx_ip_store(struct sxe_hw *hw,
 	SXE_WRITE_FLUSH(hw);
 	sxe_hw_ipsec_rx_sa_load(hw, ip_idx, SXE_IPSEC_IP_TABLE);
 
-	return;
 }
 
 static void sxe_hw_ipsec_rx_spi_store(struct sxe_hw *hw,
-					     __be32 spi, u8 ip_idx, u16 sa_idx)
+						 __be32 spi, u8 ip_idx, u16 sa_idx)
 {
 	SXE_REG_WRITE(hw, SXE_IPSRXSPI, (__force u32)cpu_to_le32((__force u32)spi));
 
@@ -4133,7 +3893,6 @@  static void sxe_hw_ipsec_rx_spi_store(struct sxe_hw *hw,
 
 	sxe_hw_ipsec_rx_sa_load(hw, sa_idx, SXE_IPSEC_SPI_TABLE);
 
-	return;
 }
 
 static void sxe_hw_ipsec_rx_key_store(struct sxe_hw *hw,
@@ -4152,7 +3911,6 @@  static void sxe_hw_ipsec_rx_key_store(struct sxe_hw *hw,
 
 	sxe_hw_ipsec_rx_sa_load(hw, sa_idx, SXE_IPSEC_KEY_TABLE);
 
-	return;
 }
 
 static void sxe_hw_ipsec_tx_sa_load(struct sxe_hw *hw, u16 idx)
@@ -4164,7 +3922,6 @@  static void sxe_hw_ipsec_tx_sa_load(struct sxe_hw *hw, u16 idx)
 	SXE_REG_WRITE(hw, SXE_IPSTXIDX, reg);
 	SXE_WRITE_FLUSH(hw);
 
-	return;
 }
 
 static void sxe_hw_ipsec_tx_key_store(struct sxe_hw *hw, u32 *key,
@@ -4181,7 +3938,6 @@  static void sxe_hw_ipsec_tx_key_store(struct sxe_hw *hw, u32 *key,
 
 	sxe_hw_ipsec_tx_sa_load(hw, sa_idx);
 
-	return;
 }
 
 static void sxe_hw_ipsec_sec_data_stop(struct sxe_hw *hw, bool is_linkup)
@@ -4200,9 +3956,8 @@  static void sxe_hw_ipsec_sec_data_stop(struct sxe_hw *hw, bool is_linkup)
 
 	tx_empty = SXE_REG_READ(hw, SXE_SECTXSTAT) & SXE_SECTXSTAT_SECTX_RDY;
 	rx_empty = SXE_REG_READ(hw, SXE_SECRXSTAT) & SXE_SECRXSTAT_SECRX_RDY;
-	if (tx_empty && rx_empty) {
-		goto l_out;
-	}
+	if (tx_empty && rx_empty)
+		return;
 
 	if (!is_linkup) {
 		SXE_REG_WRITE(hw, SXE_LPBKCTRL, SXE_LPBKCTRL_EN);
@@ -4213,11 +3968,11 @@  static void sxe_hw_ipsec_sec_data_stop(struct sxe_hw *hw, bool is_linkup)
 
 	limit = 20;
 	do {
-	   mdelay(10);
-	   tx_empty = SXE_REG_READ(hw, SXE_SECTXSTAT) &
-		   SXE_SECTXSTAT_SECTX_RDY;
+		mdelay(10);
+		tx_empty = SXE_REG_READ(hw, SXE_SECTXSTAT) &
+			SXE_SECTXSTAT_SECTX_RDY;
 	   rx_empty = SXE_REG_READ(hw, SXE_SECRXSTAT) &
-		   SXE_SECRXSTAT_SECRX_RDY;
+			SXE_SECRXSTAT_SECRX_RDY;
 	} while (!(tx_empty && rx_empty) && limit--);
 
 	if (!is_linkup) {
@@ -4226,8 +3981,6 @@  static void sxe_hw_ipsec_sec_data_stop(struct sxe_hw *hw, bool is_linkup)
 		SXE_WRITE_FLUSH(hw);
 	}
 
-l_out:
-	return;
 }
 
 static void sxe_hw_ipsec_engine_start(struct sxe_hw *hw, bool is_linkup)
@@ -4252,7 +4005,6 @@  static void sxe_hw_ipsec_engine_start(struct sxe_hw *hw, bool is_linkup)
 
 	SXE_WRITE_FLUSH(hw);
 
-	return;
 }
 
 static void sxe_hw_ipsec_engine_stop(struct sxe_hw *hw, bool is_linkup)
@@ -4273,18 +4025,17 @@  static void sxe_hw_ipsec_engine_stop(struct sxe_hw *hw, bool is_linkup)
 	reg |= SXE_SECRXCTRL_SECRX_DIS;
 	SXE_REG_WRITE(hw, SXE_SECRXCTRL, reg);
 
-	 SXE_REG_WRITE(hw, SXE_SECTXBUFFAF, 0x250);
+	SXE_REG_WRITE(hw, SXE_SECTXBUFFAF, 0x250);
 
-	 reg = SXE_REG_READ(hw, SXE_SECTXMINIFG);
-	 reg = (reg & 0xfffffff0) | 0x1;
-	 SXE_REG_WRITE(hw, SXE_SECTXMINIFG, reg);
+	reg = SXE_REG_READ(hw, SXE_SECTXMINIFG);
+	reg = (reg & 0xfffffff0) | 0x1;
+	SXE_REG_WRITE(hw, SXE_SECTXMINIFG, reg);
 
-	 SXE_REG_WRITE(hw, SXE_SECTXCTRL, SXE_SECTXCTRL_SECTX_DIS);
-	 SXE_REG_WRITE(hw, SXE_SECRXCTRL, SXE_SECRXCTRL_SECRX_DIS);
+	SXE_REG_WRITE(hw, SXE_SECTXCTRL, SXE_SECTXCTRL_SECTX_DIS);
+	SXE_REG_WRITE(hw, SXE_SECRXCTRL, SXE_SECRXCTRL_SECRX_DIS);
 
-	 SXE_WRITE_FLUSH(hw);
+	SXE_WRITE_FLUSH(hw);
 
-	 return;
 }
 
 bool sxe_hw_ipsec_offload_is_disable(struct sxe_hw *hw)
@@ -4294,7 +4045,7 @@  bool sxe_hw_ipsec_offload_is_disable(struct sxe_hw *hw)
 	bool ret = false;
 
 	if ((tx_dis & SXE_SECTXSTAT_SECTX_OFF_DIS) ||
-	    (rx_dis & SXE_SECRXSTAT_SECRX_OFF_DIS)) {
+		(rx_dis & SXE_SECRXSTAT_SECRX_OFF_DIS)) {
 		ret = true;
 	}
 
@@ -4306,7 +4057,6 @@  void sxe_hw_ipsec_sa_disable(struct sxe_hw *hw)
 	SXE_REG_WRITE(hw, SXE_IPSRXIDX, 0);
 	SXE_REG_WRITE(hw, SXE_IPSTXIDX, 0);
 
-	return;
 }
 
 static const struct sxe_sec_operations sxe_sec_ops = {
@@ -4344,18 +4094,18 @@  void sxe_hw_stats_regs_clean(struct sxe_hw *hw)
 	SXE_REG_READ(hw, SXE_TXDGPC);
 	SXE_REG_READ(hw, SXE_TXDGBCH);
 	SXE_REG_READ(hw, SXE_TXDGBCL);
-	SXE_REG_READ(hw,SXE_RXDDGPC);
+	SXE_REG_READ(hw, SXE_RXDDGPC);
 	SXE_REG_READ(hw, SXE_RXDDGBCH);
-	SXE_REG_READ(hw,SXE_RXDDGBCL);
-	SXE_REG_READ(hw,SXE_RXLPBKGPC);
+	SXE_REG_READ(hw, SXE_RXDDGBCL);
+	SXE_REG_READ(hw, SXE_RXLPBKGPC);
 	SXE_REG_READ(hw, SXE_RXLPBKGBCH);
-	SXE_REG_READ(hw,SXE_RXLPBKGBCL);
-	SXE_REG_READ(hw,SXE_RXDLPBKGPC);
+	SXE_REG_READ(hw, SXE_RXLPBKGBCL);
+	SXE_REG_READ(hw, SXE_RXDLPBKGPC);
 	SXE_REG_READ(hw, SXE_RXDLPBKGBCH);
-	SXE_REG_READ(hw,SXE_RXDLPBKGBCL);
-	SXE_REG_READ(hw,SXE_RXTPCIN);
-	SXE_REG_READ(hw,SXE_RXTPCOUT);
-	SXE_REG_READ(hw,SXE_RXPRDDC);
+	SXE_REG_READ(hw, SXE_RXDLPBKGBCL);
+	SXE_REG_READ(hw, SXE_RXTPCIN);
+	SXE_REG_READ(hw, SXE_RXTPCOUT);
+	SXE_REG_READ(hw, SXE_RXPRDDC);
 	SXE_REG_READ(hw, SXE_TXSWERR);
 	SXE_REG_READ(hw, SXE_TXSWITCH);
 	SXE_REG_READ(hw, SXE_TXREPEAT);
@@ -4382,9 +4132,9 @@  void sxe_hw_stats_regs_clean(struct sxe_hw *hw)
 	SXE_REG_READ(hw, SXE_RFC);
 	SXE_REG_READ(hw, SXE_ROC);
 	SXE_REG_READ(hw, SXE_RJC);
-	for (i = 0; i < 8; i++) {
+	for (i = 0; i < 8; i++)
 		SXE_REG_READ(hw, SXE_PRCPF(i));
-	}
+
 	SXE_REG_READ(hw, SXE_TORL);
 	SXE_REG_READ(hw, SXE_TORH);
 	SXE_REG_READ(hw, SXE_TPR);
@@ -4397,11 +4147,9 @@  void sxe_hw_stats_regs_clean(struct sxe_hw *hw)
 	SXE_REG_READ(hw, SXE_PTC1522);
 	SXE_REG_READ(hw, SXE_MPTC);
 	SXE_REG_READ(hw, SXE_BPTC);
-	for (i = 0; i < 8; i++) {
+	for (i = 0; i < 8; i++)
 		SXE_REG_READ(hw, SXE_PFCT(i));
-	}
 
-	return;
 }
 
 static void sxe_hw_stats_seq_get(struct sxe_hw *hw, struct sxe_mac_stats *stats)
@@ -4414,8 +4162,8 @@  static void sxe_hw_stats_seq_get(struct sxe_hw *hw, struct sxe_mac_stats *stats)
 #endif
 
 	for (i = 0; i < 8; i++) {
-		stats->prcpf[i] += SXE_REG_READ(hw,SXE_PRCPF(i));
-		tx_pfc_num = SXE_REG_READ(hw,SXE_PFCT(i));
+		stats->prcpf[i] += SXE_REG_READ(hw, SXE_PRCPF(i));
+		tx_pfc_num = SXE_REG_READ(hw, SXE_PFCT(i));
 		stats->pfct[i] += tx_pfc_num;
 		stats->total_tx_pause += tx_pfc_num;
 	}
@@ -4433,7 +4181,6 @@  static void sxe_hw_stats_seq_get(struct sxe_hw *hw, struct sxe_mac_stats *stats)
 	}
 #endif
 
-	return;
 }
 
 void sxe_hw_stats_seq_clean(struct sxe_hw *hw, struct sxe_mac_stats *stats)
@@ -4453,15 +4200,13 @@  void sxe_hw_stats_seq_clean(struct sxe_hw *hw, struct sxe_mac_stats *stats)
 	if (gotch != 0) {
 		LOG_INFO("GOTCH is not clear!\n");
 	}
-	
 	for (i = 0; i < 8; i++) {
-		stats->prcpf[i] += SXE_REG_READ(hw,SXE_PRCPF(i));
-		tx_pfc_num = SXE_REG_READ(hw,SXE_PFCT(i));
+		stats->prcpf[i] += SXE_REG_READ(hw, SXE_PRCPF(i));
+		tx_pfc_num = SXE_REG_READ(hw, SXE_PFCT(i));
 		stats->pfct[i] += tx_pfc_num;
 		stats->total_tx_pause += tx_pfc_num;
 	}
 
-	return;
 }
 
 void sxe_hw_stats_get(struct sxe_hw *hw, struct sxe_mac_stats *stats)
@@ -4497,20 +4242,20 @@  void sxe_hw_stats_get(struct sxe_hw *hw, struct sxe_mac_stats *stats)
 	stats->txdgbc += (((u64)SXE_REG_READ(hw, SXE_TXDGBCH) << 32) +
 				SXE_REG_READ(hw, SXE_TXDGBCL));
 
-	stats->rxddpc += SXE_REG_READ(hw,SXE_RXDDGPC);
+	stats->rxddpc += SXE_REG_READ(hw, SXE_RXDDGPC);
 	stats->rxddbc += ((u64)SXE_REG_READ(hw, SXE_RXDDGBCH) << 32) +
-				(SXE_REG_READ(hw,SXE_RXDDGBCL));
+				(SXE_REG_READ(hw, SXE_RXDDGBCL));
 
-	stats->rxlpbkpc += SXE_REG_READ(hw,SXE_RXLPBKGPC);
+	stats->rxlpbkpc += SXE_REG_READ(hw, SXE_RXLPBKGPC);
 	stats->rxlpbkbc += ((u64)SXE_REG_READ(hw, SXE_RXLPBKGBCH) << 32) +
-			(SXE_REG_READ(hw,SXE_RXLPBKGBCL));
+			(SXE_REG_READ(hw, SXE_RXLPBKGBCL));
 
-	stats->rxdlpbkpc += SXE_REG_READ(hw,SXE_RXDLPBKGPC);
+	stats->rxdlpbkpc += SXE_REG_READ(hw, SXE_RXDLPBKGPC);
 	stats->rxdlpbkbc += ((u64)SXE_REG_READ(hw, SXE_RXDLPBKGBCH) << 32) +
-				(SXE_REG_READ(hw,SXE_RXDLPBKGBCL));
-	stats->rxtpcing += SXE_REG_READ(hw,SXE_RXTPCIN);
-	stats->rxtpceng += SXE_REG_READ(hw,SXE_RXTPCOUT);
-	stats->prddc += SXE_REG_READ(hw,SXE_RXPRDDC);
+				(SXE_REG_READ(hw, SXE_RXDLPBKGBCL));
+	stats->rxtpcing += SXE_REG_READ(hw, SXE_RXTPCIN);
+	stats->rxtpceng += SXE_REG_READ(hw, SXE_RXTPCOUT);
+	stats->prddc += SXE_REG_READ(hw, SXE_RXPRDDC);
 	stats->txswerr += SXE_REG_READ(hw, SXE_TXSWERR);
 	stats->txswitch += SXE_REG_READ(hw, SXE_TXSWITCH);
 	stats->txrepeat += SXE_REG_READ(hw, SXE_TXREPEAT);
@@ -4522,8 +4267,8 @@  void sxe_hw_stats_get(struct sxe_hw *hw, struct sxe_mac_stats *stats)
 		stats->dburxgdreecnt[i] += SXE_REG_READ(hw, SXE_DBUDREECNT(i));
 		rx_dbu_drop = SXE_REG_READ(hw, SXE_DBUDROFPCNT(i));
 		stats->dburxdrofpcnt[i] += rx_dbu_drop;
-		stats->dbutxtcin[i] += SXE_REG_READ(hw,SXE_DBUDTTCICNT(i));
-		stats->dbutxtcout[i] += SXE_REG_READ(hw,SXE_DBUDTTCOCNT(i));
+		stats->dbutxtcin[i] += SXE_REG_READ(hw, SXE_DBUDTTCICNT(i));
+		stats->dbutxtcout[i] += SXE_REG_READ(hw, SXE_DBUDTTCOCNT(i));
 	}
 
 	stats->fnavadd += (SXE_REG_READ(hw, SXE_FNAVUSTAT) & 0xFFFF);
@@ -4602,7 +4347,6 @@  void sxe_hw_stats_get(struct sxe_hw *hw, struct sxe_mac_stats *stats)
 	stats->gotc = stats->total_gotc;
 #endif
 
-	return;
 }
 
 static u32 sxe_hw_tx_packets_num_get(struct sxe_hw *hw)
@@ -4620,9 +4364,8 @@  static u32 sxe_hw_mac_stats_dump(struct sxe_hw *hw, u32 *regs_buff, u32 buf_size
 	u32 i;
 	u32 regs_num = buf_size / sizeof(u32);
 
-	for (i = 0; i < regs_num; i++) {
+	for (i = 0; i < regs_num; i++)
 		regs_buff[i] = SXE_REG_READ(hw, mac_regs[i]);
-	}
 
 	return i;
 }
@@ -4649,11 +4392,10 @@  void sxe_hw_mbx_init(struct sxe_hw *hw)
 
 	hw->mbx.stats.rcv_msgs   = 0;
 	hw->mbx.stats.send_msgs  = 0;
-	hw->mbx.stats.acks       = 0;
-	hw->mbx.stats.reqs       = 0;
-	hw->mbx.stats.rsts       = 0;
+	hw->mbx.stats.acks	   = 0;
+	hw->mbx.stats.reqs	   = 0;
+	hw->mbx.stats.rsts	   = 0;
 
-	return;
 }
 
 static bool sxe_hw_vf_irq_check(struct sxe_hw *hw, u32 mask, u32 index)
@@ -4752,7 +4494,7 @@  s32 sxe_hw_rcv_msg_from_vf(struct sxe_hw *hw, u32 *msg,
 	for (i = 0; i < msg_entry; i++) {
 		msg[i] = SXE_REG_READ(hw, (SXE_PFMBMEM(index) + (i << 2)));
 		LOG_DEBUG_BDF("vf_idx:%u read mbx mem[%u]:0x%x.\n",
-			      index, i, msg[i]);
+				  index, i, msg[i]);
 	}
 
 	SXE_REG_WRITE(hw, SXE_PFMAILBOX(index), SXE_PFMAILBOX_ACK);
@@ -4788,16 +4530,15 @@  s32 sxe_hw_send_msg_to_vf(struct sxe_hw *hw, u32 *msg,
 
 	old = SXE_REG_READ(hw, (SXE_PFMBMEM(index)));
 	LOG_DEBUG_BDF("original send msg:0x%x. mbx mem[0]:0x%x\n", *msg, old);
-	if (msg[0] & SXE_CTRL_MSG_MASK) {
+	if (msg[0] & SXE_CTRL_MSG_MASK)
 		msg[0] |= (old & SXE_MSGID_MASK);
-	} else {
+	else
 		msg[0] |= (old & SXE_PFMSG_MASK);
-	}
 
 	for (i = 0; i < msg_len; i++) {
 		SXE_REG_WRITE(hw, (SXE_PFMBMEM(index) + (i << 2)), msg[i]);
 		LOG_DEBUG_BDF("vf_idx:%u write mbx mem[%u]:0x%x.\n",
-			      index, i, msg[i]);
+				  index, i, msg[i]);
 	}
 
 	SXE_REG_WRITE(hw, SXE_PFMAILBOX(index), SXE_PFMAILBOX_STS);
@@ -4811,14 +4552,12 @@  void sxe_hw_mbx_mem_clear(struct sxe_hw *hw, u8 vf_idx)
 {
 	u8 msg_idx;
 	struct sxe_adapter *adapter = hw->adapter;
-	for (msg_idx = 0; msg_idx < hw->mbx.msg_len; msg_idx++) {
+	for (msg_idx = 0; msg_idx < hw->mbx.msg_len; msg_idx++)
 		SXE_REG_WRITE_ARRAY(hw, SXE_PFMBMEM(vf_idx), msg_idx, 0);
-	}
 
 	SXE_WRITE_FLUSH(hw);
 
 	LOG_INFO_BDF("vf_idx:%u clear mbx mem.\n", vf_idx);
-	return;
 }
 
 static const struct sxe_mbx_operations sxe_mbx_ops = {
@@ -4838,7 +4577,6 @@  void sxe_hw_pcie_vt_mode_set(struct sxe_hw *hw, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_GCR_EXT, value);
 
-	return;
 }
 
 static const struct sxe_pcie_operations sxe_pcie_ops = {
@@ -4857,9 +4595,8 @@  s32 sxe_hw_hdc_lock_get(struct sxe_hw *hw, u32 trylock)
 
 	for (i = 0; i < trylock; i++) {
 		val = SXE_REG_READ(hw, SXE_HDC_SW_LK) & SXE_HDC_SW_LK_BIT;
-		if (!val) {
+		if (!val)
 			break;
-		}
 
 		udelay(10);
 	}
@@ -4898,9 +4635,8 @@  void sxe_hw_hdc_lock_release(struct sxe_hw *hw, u32 retry_cnt)
 			hw->hdc.pf_lock_val = 0;
 			break;
 		}
-	} while((retry_cnt--) > 0);
+	} while ((retry_cnt--) > 0);
 
-	return;
 }
 
 void sxe_hw_hdc_fw_ov_clear(struct sxe_hw *hw)
@@ -4912,9 +4648,8 @@  bool sxe_hw_hdc_is_fw_over_set(struct sxe_hw *hw)
 {
 	bool fw_ov = false;
 
-	if (SXE_REG_READ(hw, SXE_HDC_FW_OV) & SXE_HDC_FW_OV_BIT) {
+	if (SXE_REG_READ(hw, SXE_HDC_FW_OV) & SXE_HDC_FW_OV_BIT)
 		fw_ov = true;
-	}
 
 	return fw_ov;
 }
@@ -4924,21 +4659,18 @@  void sxe_hw_hdc_packet_send_done(struct sxe_hw *hw)
 	SXE_REG_WRITE(hw, SXE_HDC_SW_OV, SXE_HDC_SW_OV_BIT);
 	SXE_WRITE_FLUSH(hw);
 
-	return;
 }
 
 void sxe_hw_hdc_packet_header_send(struct sxe_hw *hw, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_HDC_PACKET_HEAD0, value);
 
-	return;
 }
 
 void sxe_hw_hdc_packet_data_dword_send(struct sxe_hw *hw,
 						u16 dword_index, u32 value)
 {
 	SXE_WRITE_REG_ARRAY_32(hw, SXE_HDC_PACKET_DATA0, dword_index, value);
-	return;
 }
 
 u32 sxe_hw_hdc_fw_ack_header_get(struct sxe_hw *hw)
@@ -4965,7 +4697,6 @@  u32 sxe_hw_hdc_fw_status_get(struct sxe_hw *hw)
 void sxe_hw_hdc_drv_status_set(struct sxe_hw *hw, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_DRV_STATUS_REG, value);
-	return;
 }
 
 u32 sxe_hw_hdc_channel_state_get(struct sxe_hw *hw)
@@ -4979,7 +4710,7 @@  u32 sxe_hw_hdc_channel_state_get(struct sxe_hw *hw)
 	return state;
 }
 
-STATIC u32 sxe_hw_hdc_irq_event_get(struct sxe_hw *hw)
+static u32 sxe_hw_hdc_irq_event_get(struct sxe_hw *hw)
 {
 	u32 status = SXE_REG_READ(hw, SXE_HDC_MSI_STATUS_REG);
 	struct sxe_adapter *adapter = hw->adapter;
@@ -4999,7 +4730,6 @@  static void sxe_hw_hdc_irq_event_clear(struct sxe_hw *hw, u32 event)
 	status &= ~event;
 	SXE_REG_WRITE(hw, SXE_HDC_MSI_STATUS_REG, status);
 
-	return;
 }
 
 static void sxe_hw_hdc_resource_clean(struct sxe_hw *hw)
@@ -5008,33 +4738,31 @@  static void sxe_hw_hdc_resource_clean(struct sxe_hw *hw)
 
 	SXE_REG_WRITE(hw, SXE_HDC_SW_LK, 0x0);
 	SXE_REG_WRITE(hw, SXE_HDC_PACKET_HEAD0, 0x0);
-	for (i = 0; i < SXE_HDC_DATA_LEN_MAX; i++) {
+	for (i = 0; i < SXE_HDC_DATA_LEN_MAX; i++)
 		SXE_WRITE_REG_ARRAY_32(hw, SXE_HDC_PACKET_DATA0, i, 0x0);
-	}
 
-	return;
 }
 
 static const struct sxe_hdc_operations sxe_hdc_ops = {
-	.pf_lock_get            = sxe_hw_hdc_lock_get,
-	.pf_lock_release        = sxe_hw_hdc_lock_release,
-	.is_fw_over_set         = sxe_hw_hdc_is_fw_over_set,
-	.fw_ack_header_rcv      = sxe_hw_hdc_fw_ack_header_get,
-	.packet_send_done       = sxe_hw_hdc_packet_send_done,
-	.packet_header_send     = sxe_hw_hdc_packet_header_send,
+	.pf_lock_get			= sxe_hw_hdc_lock_get,
+	.pf_lock_release		= sxe_hw_hdc_lock_release,
+	.is_fw_over_set		 = sxe_hw_hdc_is_fw_over_set,
+	.fw_ack_header_rcv	  = sxe_hw_hdc_fw_ack_header_get,
+	.packet_send_done	   = sxe_hw_hdc_packet_send_done,
+	.packet_header_send	 = sxe_hw_hdc_packet_header_send,
 	.packet_data_dword_send = sxe_hw_hdc_packet_data_dword_send,
 	.packet_data_dword_rcv  = sxe_hw_hdc_packet_data_dword_rcv,
-	.fw_status_get          = sxe_hw_hdc_fw_status_get,
-	.drv_status_set         = sxe_hw_hdc_drv_status_set,
-	.irq_event_get          = sxe_hw_hdc_irq_event_get,
-	.irq_event_clear        = sxe_hw_hdc_irq_event_clear,
-	.fw_ov_clear            = sxe_hw_hdc_fw_ov_clear,
-	.channel_state_get      = sxe_hw_hdc_channel_state_get,
-	.resource_clean         = sxe_hw_hdc_resource_clean,
+	.fw_status_get		  = sxe_hw_hdc_fw_status_get,
+	.drv_status_set		 = sxe_hw_hdc_drv_status_set,
+	.irq_event_get		  = sxe_hw_hdc_irq_event_get,
+	.irq_event_clear		= sxe_hw_hdc_irq_event_clear,
+	.fw_ov_clear			= sxe_hw_hdc_fw_ov_clear,
+	.channel_state_get	  = sxe_hw_hdc_channel_state_get,
+	.resource_clean		 = sxe_hw_hdc_resource_clean,
 };
 
 #ifdef SXE_PHY_CONFIGURE
-#define SXE_MDIO_COMMAND_TIMEOUT 100 
+#define SXE_MDIO_COMMAND_TIMEOUT 100
 
 static s32 sxe_hw_phy_reg_write(struct sxe_hw *hw, s32 prtad, u32 reg_addr,
 				u32 device_type, u16 phy_data)
@@ -5056,9 +4784,9 @@  static s32 sxe_hw_phy_reg_write(struct sxe_hw *hw, s32 prtad, u32 reg_addr,
 		udelay(10);
 
 		command = SXE_REG_READ(hw, SXE_MSCA);
-		if ((command & SXE_MSCA_MDI_CMD_ON_PROG) == 0) {
+		if ((command & SXE_MSCA_MDI_CMD_ON_PROG) == 0)
 			break;
-		}
+
 	}
 
 	if ((command & SXE_MSCA_MDI_CMD_ON_PROG) != 0) {
@@ -5079,9 +4807,8 @@  static s32 sxe_hw_phy_reg_write(struct sxe_hw *hw, s32 prtad, u32 reg_addr,
 		udelay(10);
 
 		command = SXE_REG_READ(hw, SXE_MSCA);
-		if ((command & SXE_MSCA_MDI_CMD_ON_PROG) == 0) {
+		if ((command & SXE_MSCA_MDI_CMD_ON_PROG) == 0)
 			break;
-		}
 	}
 
 	if ((command & SXE_MSCA_MDI_CMD_ON_PROG) != 0) {
@@ -5112,9 +4839,8 @@  static s32 sxe_hw_phy_reg_read(struct sxe_hw *hw, s32 prtad, u32 reg_addr,
 		udelay(10);
 
 		command = SXE_REG_READ(hw, SXE_MSCA);
-		if ((command & SXE_MSCA_MDI_CMD_ON_PROG) == 0) {
+		if ((command & SXE_MSCA_MDI_CMD_ON_PROG) == 0)
 			break;
-		}
 	}
 
 	if ((command & SXE_MSCA_MDI_CMD_ON_PROG) != 0) {
@@ -5166,7 +4892,7 @@  static s32 sxe_hw_phy_id_get(struct sxe_hw *hw, u32 prtad, u32 *id)
 
 
 	ret = sxe_hw_phy_reg_read(hw, prtad, MDIO_DEVID1, MDIO_MMD_PMAPMD,
-				      &phy_id_low);
+					  &phy_id_low);
 
 	if (ret) {
 		LOG_ERROR("get phy id upper 16 bits failed, prtad=%d\n", prtad);
@@ -5193,7 +4919,7 @@  s32 sxe_hw_phy_link_cap_get(struct sxe_hw *hw, u32 prtad, u32 *speed)
 	u16 speed_ability;
 
 	ret = hw->phy.ops->reg_read(hw, prtad, MDIO_SPEED, MDIO_MMD_PMAPMD,
-				      &speed_ability);
+					  &speed_ability);
 	if (ret) {
 		*speed = 0;
 		LOG_ERROR("get phy link cap failed, ret=%d, prtad=%d\n",
@@ -5201,17 +4927,14 @@  s32 sxe_hw_phy_link_cap_get(struct sxe_hw *hw, u32 prtad, u32 *speed)
 		goto l_end;
 	}
 
-	if (speed_ability & MDIO_SPEED_10G) {
+	if (speed_ability & MDIO_SPEED_10G)
 		*speed |= SXE_LINK_SPEED_10GB_FULL;
-	}
 
-	if (speed_ability & MDIO_PMA_SPEED_1000) {
+	if (speed_ability & MDIO_PMA_SPEED_1000)
 		*speed |= SXE_LINK_SPEED_1GB_FULL;
-	}
 
-	if (speed_ability & MDIO_PMA_SPEED_100) {
+	if (speed_ability & MDIO_PMA_SPEED_100)
 		*speed |= SXE_LINK_SPEED_100_FULL;
-	}
 
 l_end:
 	return ret;
@@ -5234,9 +4957,8 @@  static s32 sxe_hw_phy_ctrl_reset(struct sxe_hw *hw, u32 prtad)
 		msleep(100);
 		ret = sxe_hw_phy_reg_read(hw, prtad, MDIO_CTRL1,
 					MDIO_MMD_PHYXS, &ctrl);
-		if (ret) {
+		if (ret)
 			goto l_end;
-		}
 
 		if (!(ctrl & MDIO_CTRL1_RESET)) {
 			udelay(2);
@@ -5275,23 +4997,21 @@  void sxe_hw_ops_init(struct sxe_hw *hw)
 	hw->pcie.ops	= &sxe_pcie_ops;
 	hw->hdc.ops	= &sxe_hdc_ops;
 #ifdef SXE_PHY_CONFIGURE
-	hw->phy.ops     = &sxe_phy_hw_ops;
+	hw->phy.ops	 = &sxe_phy_hw_ops;
 #endif
 
 	hw->filter.mac.ops	= &sxe_filter_mac_ops;
 	hw->filter.vlan.ops	= &sxe_filter_vlan_ops;
-	return;
 }
 
 u32 sxe_hw_rss_key_get_by_idx(struct sxe_hw *hw, u8 reg_idx)
 {
 	u32 rss_key;
 
-	if (reg_idx >= SXE_MAX_RSS_KEY_ENTRIES) {
+	if (reg_idx >= SXE_MAX_RSS_KEY_ENTRIES)
 		rss_key = 0;
-	} else {
+	else
 		rss_key = SXE_REG_READ(hw, SXE_RSSRK(reg_idx));
-	}
 
 	return rss_key;
 }
@@ -5300,9 +5020,8 @@  bool sxe_hw_is_rss_enabled(struct sxe_hw *hw)
 {
 	bool rss_enable = false;
 	u32 mrqc = SXE_REG_READ(hw, SXE_MRQC);
-	if (mrqc & SXE_MRQC_RSSEN) {
+	if (mrqc & SXE_MRQC_RSSEN)
 		rss_enable = true;
-	}
 
 	return rss_enable;
 }
@@ -5318,15 +5037,28 @@  u32 sxe_hw_rss_field_get(struct sxe_hw *hw)
 	return (mrqc & SXE_RSS_FIELD_MASK);
 }
 
-#ifdef SXE_DPDK 
+#ifdef SXE_DPDK
 
 #define SXE_TRAFFIC_CLASS_MAX  8
 
-#define SXE_MR_VLAN_MSB_REG_OFFSET         4
+#define SXE_MR_VLAN_MSB_REG_OFFSET		 4
 #define SXE_MR_VIRTUAL_POOL_MSB_REG_OFFSET 4
 
-#define SXE_MR_TYPE_MASK                   0x0F
-#define SXE_MR_DST_POOL_OFFSET             8
+#define SXE_MR_TYPE_MASK				   0x0F
+#define SXE_MR_DST_POOL_OFFSET			 8
+
+void sxe_hw_crc_strip_config(struct sxe_hw *hw, bool keep_crc)
+{
+	u32 crcflag = SXE_REG_READ(hw, SXE_CRC_STRIP_REG);
+
+	if (keep_crc) {
+		crcflag |= SXE_KEEP_CRC_EN;
+	} else {
+		crcflag &= ~SXE_KEEP_CRC_EN;
+	}
+
+	SXE_REG_WRITE(hw, SXE_CRC_STRIP_REG, crcflag);
+}
 
 void sxe_hw_rx_pkt_buf_size_set(struct sxe_hw *hw, u8 tc_idx, u16 pbsize)
 {
@@ -5336,7 +5068,6 @@  void sxe_hw_rx_pkt_buf_size_set(struct sxe_hw *hw, u8 tc_idx, u16 pbsize)
 	SXE_REG_WRITE(hw, SXE_RXPBSIZE(tc_idx), rxpbsize);
 	sxe_hw_rx_pkt_buf_switch(hw, true);
 
-	return;
 }
 
 void sxe_hw_dcb_vmdq_mq_configure(struct sxe_hw *hw, u8 num_pools)
@@ -5349,13 +5080,11 @@  void sxe_hw_dcb_vmdq_mq_configure(struct sxe_hw *hw, u8 num_pools)
 
 	pbsize = (u8)(SXE_RX_PKT_BUF_SIZE / nb_tcs);
 
-	for (i = 0; i < nb_tcs; i++) {
+	for (i = 0; i < nb_tcs; i++)
 		sxe_hw_rx_pkt_buf_size_set(hw, i, pbsize);
-	}
 
-	for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
+	for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
 		sxe_hw_rx_pkt_buf_size_set(hw, i, 0);
-	}
 
 	mrqc = (num_pools == RTE_ETH_16_POOLS) ?
 		SXE_MRQC_VMDQRT8TCEN : SXE_MRQC_VMDQRT4TCEN;
@@ -5363,7 +5092,6 @@  void sxe_hw_dcb_vmdq_mq_configure(struct sxe_hw *hw, u8 num_pools)
 
 	SXE_REG_WRITE(hw, SXE_RTRPCS, SXE_RTRPCS_RRM);
 
-	return;
 }
 
 static const struct sxe_reg_info sxe_regs_general_group[] = {
@@ -5468,9 +5196,8 @@  static u32 sxe_regs_group_count(const struct sxe_reg_info *regs)
 	int i = 0;
 	int count = 0;
 
-	while (regs[i].count) {
+	while (regs[i].count)
 		count += regs[i++].count;
-	}
 
 	return count;
 };
@@ -5487,7 +5214,7 @@  static u32 sxe_hw_regs_group_read(struct sxe_hw *hw,
 			reg_buf[count + j] = SXE_REG_READ(hw,
 					regs[i].addr + j * regs[i].stride);
 			LOG_INFO("regs= %s, regs_addr=%x, regs_value=%04x\n",
-				regs[i].name , regs[i].addr, reg_buf[count + j]);
+				regs[i].name, regs[i].addr, reg_buf[count + j]);
 		}
 
 		i++;
@@ -5504,9 +5231,8 @@  u32 sxe_hw_all_regs_group_num_get(void)
 	const struct sxe_reg_info *reg_group;
 	const struct sxe_reg_info **reg_set = sxe_regs_group;
 
-	while ((reg_group = reg_set[i++])) {
+	while ((reg_group = reg_set[i++]))
 		count += sxe_regs_group_count(reg_group);
-	}
 
 	return count;
 }
@@ -5517,14 +5243,12 @@  void sxe_hw_all_regs_group_read(struct sxe_hw *hw, u32 *data)
 	const struct sxe_reg_info *reg_group;
 	const struct sxe_reg_info **reg_set = sxe_regs_group;
 
-	while ((reg_group = reg_set[i++])) {
+	while ((reg_group = reg_set[i++]))
 		count += sxe_hw_regs_group_read(hw, reg_group, &data[count]);
-	}
 
 	LOG_INFO("read regs cnt=%u, regs num=%u\n",
 				count, sxe_hw_all_regs_group_num_get());
 
-	return;
 }
 
 static void sxe_hw_default_pool_configure(struct sxe_hw *hw,
@@ -5534,14 +5258,12 @@  static void sxe_hw_default_pool_configure(struct sxe_hw *hw,
 	u32 vt_ctl;
 
 	vt_ctl = SXE_VT_CTL_VT_ENABLE | SXE_VT_CTL_REPLEN;
-	if (default_pool_enabled) {
+	if (default_pool_enabled)
 		vt_ctl |= (default_pool_idx << SXE_VT_CTL_POOL_SHIFT);
-	} else {
+	else
 		vt_ctl |= SXE_VT_CTL_DIS_DEFPL;
-	}
 
 	SXE_REG_WRITE(hw, SXE_VT_CTL, vt_ctl);
-	return;
 }
 
 void sxe_hw_dcb_vmdq_default_pool_configure(struct sxe_hw *hw,
@@ -5549,31 +5271,27 @@  void sxe_hw_dcb_vmdq_default_pool_configure(struct sxe_hw *hw,
 						u8 default_pool_idx)
 {
 	sxe_hw_default_pool_configure(hw, default_pool_enabled, default_pool_idx);
-	return;
 }
 
 u32 sxe_hw_ring_irq_switch_get(struct sxe_hw *hw, u8 idx)
 {
 	u32 mask;
 
-	if (idx == 0) {
+	if (idx == 0)
 		mask = SXE_REG_READ(hw, SXE_EIMS_EX(0));
-	} else {
+	else
 		mask = SXE_REG_READ(hw, SXE_EIMS_EX(1));
-	}
 
 	return mask;
 }
 
 void sxe_hw_ring_irq_switch_set(struct sxe_hw *hw, u8 idx, u32 value)
 {
-	if (idx == 0) {
+	if (idx == 0)
 		SXE_REG_WRITE(hw, SXE_EIMS_EX(0), value);
-	} else {
+	else
 		SXE_REG_WRITE(hw, SXE_EIMS_EX(1), value);
-	}
 
-	return;
 }
 
 void sxe_hw_dcb_vmdq_up_2_tc_configure(struct sxe_hw *hw,
@@ -5583,13 +5301,11 @@  void sxe_hw_dcb_vmdq_up_2_tc_configure(struct sxe_hw *hw,
 	u8 i;
 
 	up2tc = 0;
-	for (i = 0; i < MAX_USER_PRIORITY; i++) {
+	for (i = 0; i < MAX_USER_PRIORITY; i++)
 		up2tc |= ((tc_arr[i] & 0x07) << (i * 3));
-	}
 
 	SXE_REG_WRITE(hw, SXE_RTRUP2TC, up2tc);
 
-	return;
 }
 
 u32 sxe_hw_uta_hash_table_get(struct sxe_hw *hw, u8 reg_idx)
@@ -5602,7 +5318,6 @@  void sxe_hw_uta_hash_table_set(struct sxe_hw *hw,
 {
 	SXE_REG_WRITE(hw, SXE_UTA(reg_idx), value);
 
-	return;
 }
 
 u32 sxe_hw_vlan_type_get(struct sxe_hw *hw)
@@ -5613,7 +5328,6 @@  u32 sxe_hw_vlan_type_get(struct sxe_hw *hw)
 void sxe_hw_vlan_type_set(struct sxe_hw *hw, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_VLNCTRL, value);
-	return;
 }
 
 void sxe_hw_dcb_vmdq_vlan_configure(struct sxe_hw *hw,
@@ -5626,9 +5340,8 @@  void sxe_hw_dcb_vmdq_vlan_configure(struct sxe_hw *hw,
 	vlanctrl |= SXE_VLNCTRL_VFE;
 	SXE_REG_WRITE(hw, SXE_VLNCTRL, vlanctrl);
 
-	for (i = 0; i < SXE_VFT_TBL_SIZE; i++) {
+	for (i = 0; i < SXE_VFT_TBL_SIZE; i++)
 		SXE_REG_WRITE(hw, SXE_VFTA(i), 0xFFFFFFFF);
-	}
 
 	SXE_REG_WRITE(hw, SXE_VFRE(0),
 			num_pools == RTE_ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
@@ -5636,13 +5349,11 @@  void sxe_hw_dcb_vmdq_vlan_configure(struct sxe_hw *hw,
 	SXE_REG_WRITE(hw, SXE_MPSAR_LOW(0), 0xFFFFFFFF);
 	SXE_REG_WRITE(hw, SXE_MPSAR_HIGH(0), 0xFFFFFFFF);
 
-	return;
 }
 
 void sxe_hw_vlan_ext_type_set(struct sxe_hw *hw, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_EXVET, value);
-	return;
 }
 
 u32 sxe_hw_txctl_vlan_type_get(struct sxe_hw *hw)
@@ -5653,7 +5364,6 @@  u32 sxe_hw_txctl_vlan_type_get(struct sxe_hw *hw)
 void sxe_hw_txctl_vlan_type_set(struct sxe_hw *hw, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_DMATXCTL, value);
-	return;
 }
 
 u32 sxe_hw_ext_vlan_get(struct sxe_hw *hw)
@@ -5664,13 +5374,11 @@  u32 sxe_hw_ext_vlan_get(struct sxe_hw *hw)
 void sxe_hw_ext_vlan_set(struct sxe_hw *hw, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_CTRL_EXT, value);
-	return;
 }
 
 void sxe_hw_rxq_stat_map_set(struct sxe_hw *hw, u8 idx, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_RQSMR(idx), value);
-	return;
 }
 
 void sxe_hw_dcb_vmdq_pool_configure(struct sxe_hw *hw,
@@ -5682,13 +5390,11 @@  void sxe_hw_dcb_vmdq_pool_configure(struct sxe_hw *hw,
 
 	SXE_REG_WRITE(hw, SXE_VLVFB(pool_idx * 2), pools_map);
 
-	return;
 }
 
 void sxe_hw_txq_stat_map_set(struct sxe_hw *hw, u8 idx, u32 value)
 {
 	SXE_REG_WRITE(hw, SXE_TQSM(idx), value);
-	return;
 }
 
 void sxe_hw_dcb_rx_configure(struct sxe_hw *hw, bool is_vt_on,
@@ -5746,14 +5452,12 @@  void sxe_hw_dcb_rx_configure(struct sxe_hw *hw, bool is_vt_on,
 	vlanctrl |= SXE_VLNCTRL_VFE;
 	SXE_REG_WRITE(hw, SXE_VLNCTRL, vlanctrl);
 
-	for (i = 0; i < SXE_VFT_TBL_SIZE; i++) {
+	for (i = 0; i < SXE_VFT_TBL_SIZE; i++)
 		SXE_REG_WRITE(hw, SXE_VFTA(i), 0xFFFFFFFF);
-	}
 
 	reg = SXE_RTRPCS_RRM | SXE_RTRPCS_RAC;
 	SXE_REG_WRITE(hw, SXE_RTRPCS, reg);
 
-	return;
 }
 
 void sxe_hw_fc_status_get(struct sxe_hw *hw,
@@ -5762,19 +5466,16 @@  void sxe_hw_fc_status_get(struct sxe_hw *hw,
 	u32 flctrl;
 
 	flctrl = SXE_REG_READ(hw, SXE_FLCTRL);
-	if (flctrl & (SXE_FCTRL_RFCE_PFC_EN | SXE_FCTRL_RFCE_LFC_EN)) {
+	if (flctrl & (SXE_FCTRL_RFCE_PFC_EN | SXE_FCTRL_RFCE_LFC_EN))
 		*rx_pause_on = true;
-	} else {
+	else
 		*rx_pause_on = false;
-	}
 
-	if (flctrl & (SXE_FCTRL_TFCE_PFC_EN | SXE_FCTRL_TFCE_LFC_EN)) {
+	if (flctrl & (SXE_FCTRL_TFCE_PFC_EN | SXE_FCTRL_TFCE_LFC_EN))
 		*tx_pause_on = true;
-	} else {
+	else
 		*tx_pause_on = false;
-	}
 
-	return;
 }
 
 void sxe_hw_fc_base_init(struct sxe_hw *hw)
@@ -5792,7 +5493,6 @@  void sxe_hw_fc_base_init(struct sxe_hw *hw)
 	}
 
 	hw->fc.send_xon = 1;
-	return;
 }
 
 u32 sxe_hw_fc_tc_high_water_mark_get(struct sxe_hw *hw, u8 tc_idx)
@@ -5813,7 +5513,6 @@  u16 sxe_hw_fc_send_xon_get(struct sxe_hw *hw)
 void sxe_hw_fc_send_xon_set(struct sxe_hw *hw, u16 send_xon)
 {
 	hw->fc.send_xon = send_xon;
-	return;
 }
 
 u16 sxe_hw_fc_pause_time_get(struct sxe_hw *hw)
@@ -5824,7 +5523,6 @@  u16 sxe_hw_fc_pause_time_get(struct sxe_hw *hw)
 void sxe_hw_fc_pause_time_set(struct sxe_hw *hw, u16 pause_time)
 {
 	hw->fc.pause_time = pause_time;
-	return;
 }
 
 void sxe_hw_dcb_tx_configure(struct sxe_hw *hw, bool is_vt_on, u8 tc_num)
@@ -5835,15 +5533,13 @@  void sxe_hw_dcb_tx_configure(struct sxe_hw *hw, bool is_vt_on, u8 tc_num)
 	reg |= SXE_RTTDCS_ARBDIS;
 	SXE_REG_WRITE(hw, SXE_RTTDCS, reg);
 
-	if (tc_num == 8) {
+	if (tc_num == 8)
 		reg = SXE_MTQC_RT_ENA | SXE_MTQC_8TC_8TQ;
-	} else {
+	else
 		reg = SXE_MTQC_RT_ENA | SXE_MTQC_4TC_4TQ;
-	}
 
-	if (is_vt_on) {
+	if (is_vt_on)
 		reg |= SXE_MTQC_VT_ENA;
-	}
 
 	SXE_REG_WRITE(hw, SXE_MTQC, reg);
 
@@ -5852,7 +5548,6 @@  void sxe_hw_dcb_tx_configure(struct sxe_hw *hw, bool is_vt_on, u8 tc_num)
 	SXE_REG_WRITE(hw, SXE_RTTDCS, reg);
 
 
-	return;
 }
 
 void sxe_hw_rx_ip_checksum_offload_switch(struct sxe_hw *hw,
@@ -5861,36 +5556,31 @@  void sxe_hw_rx_ip_checksum_offload_switch(struct sxe_hw *hw,
 	u32 rxcsum;
 
 	rxcsum = SXE_REG_READ(hw, SXE_RXCSUM);
-	if (is_on) {
+	if (is_on)
 		rxcsum |= SXE_RXCSUM_IPPCSE;
-	} else {
+	else
 		rxcsum &= ~SXE_RXCSUM_IPPCSE;
-	}
 
 	SXE_REG_WRITE(hw, SXE_RXCSUM, rxcsum);
 
-	return;
 }
 
 void sxe_hw_rss_cap_switch(struct sxe_hw *hw, bool is_on)
 {
 	u32 mrqc = SXE_REG_READ(hw, SXE_MRQC);
-	if (is_on) {
+	if (is_on)
 		mrqc |= SXE_MRQC_RSSEN;
-	} else {
+	else
 		mrqc &= ~SXE_MRQC_RSSEN;
-	}
 
 	SXE_REG_WRITE(hw, SXE_MRQC, mrqc);
 
-	return;
 }
 
 void sxe_hw_pool_xmit_enable(struct sxe_hw *hw, u16 reg_idx, u8 pool_num)
 {
 	SXE_REG_WRITE(hw, SXE_VFTE(reg_idx),
 		pool_num == RTE_ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
-	return;
 }
 
 void sxe_hw_rss_field_set(struct sxe_hw *hw, u32 rss_field)
@@ -5901,7 +5591,6 @@  void sxe_hw_rss_field_set(struct sxe_hw *hw, u32 rss_field)
 	mrqc |= rss_field;
 	SXE_REG_WRITE(hw, SXE_MRQC, mrqc);
 
-	return;
 }
 
 static void sxe_hw_dcb_4tc_vmdq_off_stats_configure(struct sxe_hw *hw)
@@ -5910,44 +5599,38 @@  static void sxe_hw_dcb_4tc_vmdq_off_stats_configure(struct sxe_hw *hw)
 	u8  i;
 
 	for (i = 0; i < 32; i++) {
-		if (i % 8 > 3) {
+		if (i % 8 > 3)
 			continue;
-		}
 
 		reg = 0x01010101 * (i / 8);
 		SXE_REG_WRITE(hw, SXE_RQSMR(i), reg);
 	}
 	for (i = 0; i < 32; i++) {
-		if (i < 16) {
+		if (i < 16)
 			reg = 0x00000000;
-		} else if (i < 24) {
+		else if (i < 24)
 			reg = 0x01010101;
-		} else if (i < 28) {
+		else if (i < 28)
 			reg = 0x02020202;
-		} else {
+		else
 			reg = 0x03030303;
-		}
 
 		SXE_REG_WRITE(hw, SXE_TQSM(i), reg);
 	}
 
-	return;
 }
 
 static void sxe_hw_dcb_4tc_vmdq_on_stats_configure(struct sxe_hw *hw)
 {
 	u8  i;
 
-	for (i = 0; i < 32; i++) {
+	for (i = 0; i < 32; i++)
 		SXE_REG_WRITE(hw, SXE_RQSMR(i), 0x03020100);
-	}
 
 
-	for (i = 0; i < 32; i++) {
+	for (i = 0; i < 32; i++)
 		SXE_REG_WRITE(hw, SXE_TQSM(i), 0x03020100);
-	}
 
-	return;
 }
 
 void sxe_hw_rss_redir_tbl_set_by_idx(struct sxe_hw *hw,
@@ -5969,21 +5652,18 @@  u32 sxe_hw_rss_redir_tbl_get_by_idx(struct sxe_hw *hw, u16 reg_idx)
 void sxe_hw_ptp_time_inc_stop(struct sxe_hw *hw)
 {
 	SXE_REG_WRITE(hw, SXE_TIMINC, 0);
-	return;
 }
 
 void sxe_hw_dcb_tc_stats_configure(struct sxe_hw *hw,
 					u8 tc_num, bool vmdq_active)
 {
-	if (tc_num == 8 && vmdq_active == false) {
+	if (tc_num == 8 && vmdq_active == false)
 		sxe_hw_dcb_8tc_vmdq_off_stats_configure(hw);
-	} else if (tc_num == 4 && vmdq_active == false) {
+	else if (tc_num == 4 && vmdq_active == false)
 		sxe_hw_dcb_4tc_vmdq_off_stats_configure(hw);
-	} else if (tc_num == 4 && vmdq_active == true) {
+	else if (tc_num == 4 && vmdq_active == true)
 		sxe_hw_dcb_4tc_vmdq_on_stats_configure(hw);
-	}
 
-	return;
 }
 
 void sxe_hw_ptp_timestamp_disable(struct sxe_hw *hw)
@@ -5997,7 +5677,6 @@  void sxe_hw_ptp_timestamp_disable(struct sxe_hw *hw)
 			~SXE_TSYNCRXCTL_REN));
 	SXE_WRITE_FLUSH(hw);
 
-	return;
 }
 
 void sxe_hw_mac_pool_clear(struct sxe_hw *hw, u8 rar_idx)
@@ -6007,14 +5686,12 @@  void sxe_hw_mac_pool_clear(struct sxe_hw *hw, u8 rar_idx)
 	if (rar_idx > SXE_UC_ENTRY_NUM_MAX) {
 		LOG_ERROR_BDF("rar_idx:%d invalid.(err:%d)\n",
 			  rar_idx, SXE_ERR_PARAM);
-		goto l_end;
+		return;
 	}
 
 	SXE_REG_WRITE(hw, SXE_MPSAR_LOW(rar_idx), 0);
 	SXE_REG_WRITE(hw, SXE_MPSAR_HIGH(rar_idx), 0);
 
-l_end:
-	return;
 }
 
 void sxe_hw_vmdq_mq_configure(struct sxe_hw *hw)
@@ -6024,7 +5701,6 @@  void sxe_hw_vmdq_mq_configure(struct sxe_hw *hw)
 	mrqc = SXE_MRQC_VMDQEN;
 	SXE_REG_WRITE(hw, SXE_MRQC, mrqc);
 
-	return;
 }
 
 void sxe_hw_vmdq_default_pool_configure(struct sxe_hw *hw,
@@ -6032,7 +5708,6 @@  void sxe_hw_vmdq_default_pool_configure(struct sxe_hw *hw,
 						u8 default_pool_idx)
 {
 	sxe_hw_default_pool_configure(hw, default_pool_enabled, default_pool_idx);
-	return;
 }
 
 void sxe_hw_vmdq_vlan_configure(struct sxe_hw *hw,
@@ -6045,24 +5720,20 @@  void sxe_hw_vmdq_vlan_configure(struct sxe_hw *hw,
 	vlanctrl |= SXE_VLNCTRL_VFE;
 	SXE_REG_WRITE(hw, SXE_VLNCTRL, vlanctrl);
 
-	for (i = 0; i < SXE_VFT_TBL_SIZE; i++) {
+	for (i = 0; i < SXE_VFT_TBL_SIZE; i++)
 		SXE_REG_WRITE(hw, SXE_VFTA(i), 0xFFFFFFFF);
-	}
 
 	SXE_REG_WRITE(hw, SXE_VFRE(0), 0xFFFFFFFF);
-	if (num_pools == RTE_ETH_64_POOLS) {
+	if (num_pools == RTE_ETH_64_POOLS)
 		SXE_REG_WRITE(hw, SXE_VFRE(1), 0xFFFFFFFF);
-	}
 
-	for (i = 0; i < num_pools; i++) {
+	for (i = 0; i < num_pools; i++)
 		SXE_REG_WRITE(hw, SXE_VMOLR(i), rx_mode);
-	}
 
 	SXE_REG_WRITE(hw, SXE_MPSAR_LOW(0), 0xFFFFFFFF);
 	SXE_REG_WRITE(hw, SXE_MPSAR_HIGH(0), 0xFFFFFFFF);
 
 	SXE_WRITE_FLUSH(hw);
-	return;
 }
 
 u32 sxe_hw_pcie_vt_mode_get(struct sxe_hw *hw)
@@ -6082,7 +5753,6 @@  void sxe_rx_fc_threshold_set(struct sxe_hw *hw)
 		SXE_REG_WRITE(hw, SXE_FCRTH(i), high);
 	}
 
-	return;
 }
 
 void sxe_hw_vmdq_pool_configure(struct sxe_hw *hw,
@@ -6101,19 +5771,16 @@  void sxe_hw_vmdq_pool_configure(struct sxe_hw *hw,
 	}
 
 	SXE_WRITE_FLUSH(hw);
-	return;
 }
 
 void sxe_hw_vmdq_loopback_configure(struct sxe_hw *hw)
 {
 	u8 i;
 	SXE_REG_WRITE(hw, SXE_PFDTXGSWC, SXE_PFDTXGSWC_VT_LBEN);
-	for (i = 0; i < SXE_VMTXSW_REGISTER_COUNT; i++) {
+	for (i = 0; i < SXE_VMTXSW_REGISTER_COUNT; i++)
 		SXE_REG_WRITE(hw, SXE_VMTXSW(i), 0xFFFFFFFF);
-	}
 
 	SXE_WRITE_FLUSH(hw);
-	return;
 }
 
 void sxe_hw_tx_multi_queue_configure(struct sxe_hw *hw,
@@ -6145,7 +5812,7 @@  void sxe_hw_tx_multi_queue_configure(struct sxe_hw *hw,
 			SXE_REG_WRITE(hw, SXE_VFTE(1), UINT32_MAX);
 
 			for (queue_idx = 0; queue_idx < SXE_HW_TXRX_RING_NUM_MAX;
-			    queue_idx++) {
+				queue_idx++) {
 				SXE_REG_WRITE(hw, SXE_QDE,
 					(SXE_QDE_WRITE |
 					(queue_idx << SXE_QDE_IDX_SHIFT)));
@@ -6161,7 +5828,6 @@  void sxe_hw_tx_multi_queue_configure(struct sxe_hw *hw,
 
 	sxe_hw_dcb_arbiter_set(hw, true);
 
-	return;
 }
 
 void sxe_hw_vf_queue_drop_enable(struct sxe_hw *hw, u8 vf_idx,
@@ -6170,8 +5836,7 @@  void sxe_hw_vf_queue_drop_enable(struct sxe_hw *hw, u8 vf_idx,
 	u32 value;
 	u8 i;
 
-	for (i = (vf_idx * ring_per_pool); i < ((vf_idx + 1) * ring_per_pool); i++)
-	{
+	for (i = (vf_idx * ring_per_pool); i < ((vf_idx + 1) * ring_per_pool); i++) {
 		value = SXE_QDE_ENABLE | SXE_QDE_WRITE;
 		SXE_WRITE_FLUSH(hw);
 
@@ -6180,7 +5845,6 @@  void sxe_hw_vf_queue_drop_enable(struct sxe_hw *hw, u8 vf_idx,
 		SXE_REG_WRITE(hw, SXE_QDE, value);
 	}
 
-	return;
 }
 
 bool sxe_hw_vt_status(struct sxe_hw *hw)
@@ -6188,17 +5852,16 @@  bool sxe_hw_vt_status(struct sxe_hw *hw)
 	bool ret;
 	u32 vt_ctl = SXE_REG_READ(hw, SXE_VT_CTL);
 
-	if (vt_ctl & SXE_VMD_CTL_POOL_EN) {
+	if (vt_ctl & SXE_VMD_CTL_POOL_EN)
 		ret = true;
-	} else {
+	else
 		ret = false;
-	}
 
 	return ret;
 }
 
 void sxe_hw_mirror_ctl_set(struct sxe_hw *hw, u8 rule_id,
-				    u8 mirror_type, u8 dst_pool, bool on)
+					u8 mirror_type, u8 dst_pool, bool on)
 {
 	u32 mr_ctl;
 
@@ -6214,23 +5877,20 @@  void sxe_hw_mirror_ctl_set(struct sxe_hw *hw, u8 rule_id,
 
 	SXE_REG_WRITE(hw, SXE_MRCTL(rule_id), mr_ctl);
 
-	return;
 }
 
-void sxe_hw_mirror_virtual_pool_set(struct sxe_hw *hw, u8 rule_id,u32 lsb, u32 msb)
+void sxe_hw_mirror_virtual_pool_set(struct sxe_hw *hw, u8 rule_id, u32 lsb, u32 msb)
 {
 	SXE_REG_WRITE(hw, SXE_VMRVM(rule_id), lsb);
 	SXE_REG_WRITE(hw, SXE_VMRVM(rule_id  + SXE_MR_VIRTUAL_POOL_MSB_REG_OFFSET), msb);
 
-	return;
 }
 
-void sxe_hw_mirror_vlan_set(struct sxe_hw *hw, u8 rule_id,u32 lsb, u32 msb)
+void sxe_hw_mirror_vlan_set(struct sxe_hw *hw, u8 rule_id, u32 lsb, u32 msb)
 {
 	SXE_REG_WRITE(hw, SXE_VMRVLAN(rule_id), lsb);
 	SXE_REG_WRITE(hw, SXE_VMRVLAN(rule_id  + SXE_MR_VLAN_MSB_REG_OFFSET), msb);
 
-	return;
 }
 
 void sxe_hw_mirror_rule_clear(struct sxe_hw *hw, u8 rule_id)
@@ -6243,7 +5903,6 @@  void sxe_hw_mirror_rule_clear(struct sxe_hw *hw, u8 rule_id)
 	SXE_REG_WRITE(hw, SXE_VMRVM(rule_id), 0);
 	SXE_REG_WRITE(hw, SXE_VMRVM(rule_id  + SXE_MR_VIRTUAL_POOL_MSB_REG_OFFSET), 0);
 
-	return;
 }
 
 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_FILTER_CTRL
@@ -6266,28 +5925,29 @@  void sxe_hw_fivetuple_filter_add(struct rte_eth_dev *dev,
 	ftqf |= (u32)((filter->filter_info.priority &
 			SXE_FTQF_PRIORITY_MASK) << SXE_FTQF_PRIORITY_SHIFT);
 
-	if (filter->filter_info.src_ip_mask == 0) {
+	if (filter->filter_info.src_ip_mask == 0)
 		mask &= SXE_FTQF_SOURCE_ADDR_MASK;
-	}
-	if (filter->filter_info.dst_ip_mask == 0) {
+
+	if (filter->filter_info.dst_ip_mask == 0)
 		mask &= SXE_FTQF_DEST_ADDR_MASK;
-	}
-	if (filter->filter_info.src_port_mask == 0) {
+
+	if (filter->filter_info.src_port_mask == 0)
 		mask &= SXE_FTQF_SOURCE_PORT_MASK;
-	}
-	if (filter->filter_info.dst_port_mask == 0) {
+
+	if (filter->filter_info.dst_port_mask == 0)
 		mask &= SXE_FTQF_DEST_PORT_MASK;
-	}
-	if (filter->filter_info.proto_mask == 0) {
+
+	if (filter->filter_info.proto_mask == 0)
 		mask &= SXE_FTQF_PROTOCOL_COMP_MASK;
-	}
+
 	ftqf |= mask << SXE_FTQF_5TUPLE_MASK_SHIFT;
 	ftqf |= SXE_FTQF_POOL_MASK_EN;
 	ftqf |= SXE_FTQF_QUEUE_ENABLE;
 
 	LOG_DEBUG("add fivetuple filter, index[%u], src_ip[0x%x], dst_ip[0x%x]"
-		"src_port[%u], dst_port[%u], ftqf[0x%x], queue[%u]", i, filter->filter_info.src_ip,
-		filter->filter_info.dst_ip, filter->filter_info.src_port, filter->filter_info.dst_port,
+		"src_port[%u], dst_port[%u], ftqf[0x%x], queue[%u]", i,
+		filter->filter_info.src_ip, filter->filter_info.dst_ip,
+		filter->filter_info.src_port, filter->filter_info.dst_port,
 		ftqf, filter->queue);
 
 	SXE_REG_WRITE(hw, SXE_DAQF(i), filter->filter_info.dst_ip);
@@ -6299,7 +5959,6 @@  void sxe_hw_fivetuple_filter_add(struct rte_eth_dev *dev,
 	l34timir |= (u32)(filter->queue << SXE_L34T_IMIR_QUEUE_SHIFT);
 	SXE_REG_WRITE(hw, SXE_L34T_IMIR(i), l34timir);
 
-	return;
 }
 
 void sxe_hw_fivetuple_filter_del(struct sxe_hw *hw, u16 reg_index)
@@ -6310,7 +5969,6 @@  void sxe_hw_fivetuple_filter_del(struct sxe_hw *hw, u16 reg_index)
 	SXE_REG_WRITE(hw, SXE_FTQF(reg_index), 0);
 	SXE_REG_WRITE(hw, SXE_L34T_IMIR(reg_index), 0);
 
-	return;
 }
 
 void sxe_hw_ethertype_filter_add(struct sxe_hw *hw,
@@ -6329,7 +5987,6 @@  void sxe_hw_ethertype_filter_add(struct sxe_hw *hw,
 	SXE_REG_WRITE(hw, SXE_ETQS(reg_index), etqs);
 	SXE_WRITE_FLUSH(hw);
 
-	return;
 }
 
 void sxe_hw_ethertype_filter_del(struct sxe_hw *hw, u8 filter_type)
@@ -6338,7 +5995,6 @@  void sxe_hw_ethertype_filter_del(struct sxe_hw *hw, u8 filter_type)
 	SXE_REG_WRITE(hw, SXE_ETQS(filter_type), 0);
 	SXE_WRITE_FLUSH(hw);
 
-	return;
 }
 
 void sxe_hw_syn_filter_add(struct sxe_hw *hw, u16 queue, u8 priority)
@@ -6348,16 +6004,14 @@  void sxe_hw_syn_filter_add(struct sxe_hw *hw, u16 queue, u8 priority)
 	synqf = (u32)(((queue << SXE_SYN_FILTER_QUEUE_SHIFT) &
 			SXE_SYN_FILTER_QUEUE) | SXE_SYN_FILTER_ENABLE);
 
-	if (priority) {
+	if (priority)
 		synqf |= SXE_SYN_FILTER_SYNQFP;
-	} else {
+	else
 		synqf &= ~SXE_SYN_FILTER_SYNQFP;
-	}
 
 	SXE_REG_WRITE(hw, SXE_SYNQF, synqf);
 	SXE_WRITE_FLUSH(hw);
 
-	return;
 }
 
 void sxe_hw_syn_filter_del(struct sxe_hw *hw)
@@ -6370,7 +6024,6 @@  void sxe_hw_syn_filter_del(struct sxe_hw *hw)
 	SXE_REG_WRITE(hw, SXE_SYNQF, synqf);
 	SXE_WRITE_FLUSH(hw);
 
-	return;
 }
 
 void sxe_hw_fnav_rx_pkt_buf_size_reset(struct sxe_hw *hw, u32 pbsize)
@@ -6378,11 +6031,9 @@  void sxe_hw_fnav_rx_pkt_buf_size_reset(struct sxe_hw *hw, u32 pbsize)
 	S32 i;
 
 	SXE_REG_WRITE(hw, SXE_RXPBSIZE(0), (SXE_REG_READ(hw, SXE_RXPBSIZE(0)) - pbsize));
-	for (i = 1; i < 8; i++) {
+	for (i = 1; i < 8; i++)
 		SXE_REG_WRITE(hw, SXE_RXPBSIZE(i), 0);
-	}
 
-	return;
 }
 
 void sxe_hw_fnav_flex_mask_set(struct sxe_hw *hw, u16 flex_mask)
@@ -6390,12 +6041,10 @@  void sxe_hw_fnav_flex_mask_set(struct sxe_hw *hw, u16 flex_mask)
 	u32 fnavm;
 
 	fnavm = SXE_REG_READ(hw, SXE_FNAVM);
-	if (flex_mask == UINT16_MAX) {
+	if (flex_mask == UINT16_MAX)
 		fnavm &= ~SXE_FNAVM_FLEX;
-	}
 
 	SXE_REG_WRITE(hw, SXE_FNAVM, fnavm);
-	return;
 }
 
 void sxe_hw_fnav_ipv6_mask_set(struct sxe_hw *hw, u16 src_mask, u16 dst_mask)
@@ -6405,7 +6054,6 @@  void sxe_hw_fnav_ipv6_mask_set(struct sxe_hw *hw, u16 src_mask, u16 dst_mask)
 	fnavipv6m = (dst_mask << 16) | src_mask;
 	SXE_REG_WRITE(hw, SXE_FNAVIP6M, ~fnavipv6m);
 
-	return;
 }
 
 s32 sxe_hw_fnav_flex_offset_set(struct sxe_hw *hw, u16 offset)
@@ -6425,7 +6073,6 @@  s32 sxe_hw_fnav_flex_offset_set(struct sxe_hw *hw, u16 offset)
 	if (ret) {
 		LOG_ERROR("flow director signature poll time exceeded!\n");
 	}
-
 	return ret;
 }
 #endif
@@ -6450,9 +6097,9 @@  static void sxe_macsec_stop_data(struct sxe_hw *hw, bool link)
 		SXE_SECTXSTAT_SECTX_RDY;
 	r_rdy = SXE_REG_READ(hw, SXE_SECRXSTAT) &
 		SXE_SECRXSTAT_SECRX_RDY;
-	if (t_rdy && r_rdy)
+	if (t_rdy && r_rdy) {
 		return;
-
+	}
 	if (!link) {
 		SXE_REG_WRITE(hw, SXE_LPBKCTRL, 0x1);
 
@@ -6474,13 +6121,11 @@  static void sxe_macsec_stop_data(struct sxe_hw *hw, bool link)
 		SXE_WRITE_FLUSH(hw);
 	}
 
-	return;
 }
 void sxe_hw_rx_queue_mode_set(struct sxe_hw *hw, u32 mrqc)
 {
 	SXE_REG_WRITE(hw, SXE_MRQC, mrqc);
 
-	return;
 }
 
 void sxe_hw_macsec_enable(struct sxe_hw *hw, bool is_up, u32 tx_mode,
@@ -6527,7 +6172,6 @@  void sxe_hw_macsec_enable(struct sxe_hw *hw, bool is_up, u32 tx_mode,
 
 	SXE_WRITE_FLUSH(hw);
 
-	return;
 }
 
 void sxe_hw_macsec_disable(struct sxe_hw *hw, bool is_up)
@@ -6555,7 +6199,6 @@  void sxe_hw_macsec_disable(struct sxe_hw *hw, bool is_up)
 	SXE_REG_WRITE(hw, SXE_SECRXCTRL, SXE_SECRXCTRL_SECRX_DIS);
 
 	SXE_WRITE_FLUSH(hw);
-	return;
 }
 
 void sxe_hw_macsec_txsc_set(struct sxe_hw *hw, u32 scl, u32 sch)
@@ -6564,7 +6207,6 @@  void sxe_hw_macsec_txsc_set(struct sxe_hw *hw, u32 scl, u32 sch)
 	SXE_REG_WRITE(hw, SXE_LSECTXSCH, sch);
 
 	SXE_WRITE_FLUSH(hw);
-	return;
 }
 
 void sxe_hw_macsec_rxsc_set(struct sxe_hw *hw, u32 scl, u32 sch, u16 pi)
@@ -6577,7 +6219,6 @@  void sxe_hw_macsec_rxsc_set(struct sxe_hw *hw, u32 scl, u32 sch, u16 pi)
 	SXE_REG_WRITE(hw, SXE_LSECRXSCH, reg);
 
 	SXE_WRITE_FLUSH(hw);
-	return;
 
 }
 
@@ -6594,9 +6235,9 @@  void sxe_hw_macsec_tx_sa_configure(struct sxe_hw *hw, u8 sa_idx,
 	SXE_WRITE_FLUSH(hw);
 
 	SXE_REG_WRITE(hw, SXE_LSECTXPN(sa_idx), pn);
-	for (i = 0; i < 4; i++) {
+	for (i = 0; i < 4; i++)
 		SXE_REG_WRITE(hw, SXE_LSECTXKEY(sa_idx, i), keys[i]);
-	}
+
 	SXE_WRITE_FLUSH(hw);
 
 	reg = SXE_REG_READ(hw, SXE_LSECTXSA);
@@ -6613,7 +6254,6 @@  void sxe_hw_macsec_tx_sa_configure(struct sxe_hw *hw, u8 sa_idx,
 	}
 
 	SXE_WRITE_FLUSH(hw);
-	return;
 }
 
 void sxe_hw_macsec_rx_sa_configure(struct sxe_hw *hw, u8 sa_idx,
@@ -6632,16 +6272,15 @@  void sxe_hw_macsec_rx_sa_configure(struct sxe_hw *hw, u8 sa_idx,
 
 	SXE_REG_WRITE(hw, SXE_LSECRXPN(sa_idx), pn);
 
-	for (i = 0; i < 4; i++) {
+	for (i = 0; i < 4; i++)
 		SXE_REG_WRITE(hw, SXE_LSECRXKEY(sa_idx, i), keys[i]);
-	}
+
 	SXE_WRITE_FLUSH(hw);
 
 	reg = ((an << SXE_LSECRXSA_AN_SHIFT) & SXE_LSECRXSA_AN_MASK) | SXE_LSECRXSA_SAV;
 	SXE_REG_WRITE(hw, SXE_LSECRXSA(sa_idx), reg);
 	SXE_WRITE_FLUSH(hw);
-	return;
 }
-				
-#endif 
-#endif 
+
+#endif
+#endif
diff --git a/drivers/net/sxe/base/sxe_hw.h b/drivers/net/sxe/base/sxe_hw.h
index 8adc9fc15b..aa19817d96 100644
--- a/drivers/net/sxe/base/sxe_hw.h
+++ b/drivers/net/sxe/base/sxe_hw.h
@@ -5,7 +5,7 @@ 
 #ifndef __SXE_HW_H__
 #define __SXE_HW_H__
 
-#if defined (__KERNEL__) || defined (SXE_KERNEL_TEST)
+#if defined(__KERNEL__) || defined(SXE_KERNEL_TEST)
 #include <linux/types.h>
 #include <linux/kernel.h>
 #else
@@ -20,17 +20,17 @@ 
 
 #include "sxe_regs.h"
 
-#if defined (__KERNEL__) || defined (SXE_KERNEL_TEST)
+#if defined(__KERNEL__) || defined(SXE_KERNEL_TEST)
 #define SXE_PRIU64  "llu"
 #define SXE_PRIX64  "llx"
 #define SXE_PRID64  "lld"
-#define SXE_RMB()     rmb()
+#define SXE_RMB()	 rmb() /* verify reading before check ****/
 
 #else
 #define SXE_PRIU64  PRIu64
 #define SXE_PRIX64  PRIx64
 #define SXE_PRID64  PRId64
-#define SXE_RMB()     rte_rmb()
+#define SXE_RMB()	 rte_rmb()
 #endif
 
 struct sxe_hw;
@@ -40,29 +40,29 @@  struct sxe_fc_info;
 #define SXE_MAC_ADDR_LEN 6
 #define SXE_QUEUE_STATS_MAP_REG_NUM 32
 
-#define SXE_FC_DEFAULT_HIGH_WATER_MARK    0x80
-#define SXE_FC_DEFAULT_LOW_WATER_MARK     0x40
+#define SXE_FC_DEFAULT_HIGH_WATER_MARK	0x80
+#define SXE_FC_DEFAULT_LOW_WATER_MARK	 0x40
 
 #define  SXE_MC_ADDR_EXTRACT_MASK  (0xFFF)
-#define  SXE_MC_ADDR_SHIFT         (5)    
-#define  SXE_MC_ADDR_REG_MASK      (0x7F) 
-#define  SXE_MC_ADDR_BIT_MASK      (0x1F) 
+#define  SXE_MC_ADDR_SHIFT		 (5)
+#define  SXE_MC_ADDR_REG_MASK	  (0x7F)
+#define  SXE_MC_ADDR_BIT_MASK	  (0x1F)
 
 #define SXE_TXTS_POLL_CHECK		3
 #define SXE_TXTS_POLL			5
 #define SXE_TIME_TO_NS(ns, sec)	(((u64)(ns)) + (u64)(((u64)(sec)) * NSEC_PER_SEC))
 
 enum sxe_strict_prio_type {
-	PRIO_NONE = 0, 
-	PRIO_GROUP,    
-	PRIO_LINK      
+	PRIO_NONE = 0,
+	PRIO_GROUP,
+	PRIO_LINK
 };
 
 enum sxe_mc_filter_type {
-	SXE_MC_FILTER_TYPE0 = 0,  
-	SXE_MC_FILTER_TYPE1,      
-	SXE_MC_FILTER_TYPE2,      
-	SXE_MC_FILTER_TYPE3       
+	SXE_MC_FILTER_TYPE0 = 0,
+	SXE_MC_FILTER_TYPE1,
+	SXE_MC_FILTER_TYPE2,
+	SXE_MC_FILTER_TYPE3
 };
 
 #define SXE_POOLS_NUM_MAX 64
@@ -84,57 +84,57 @@  enum sxe_mc_filter_type {
 #define SXE_VF_NUM_16		16
 #define SXE_VF_NUM_32		32
 
-#define SXE_TX_DESC_EOP_MASK  0x01000000   
-#define SXE_TX_DESC_RS_MASK   0x08000000   
-#define SXE_TX_DESC_STAT_DD   0x00000001   
-#define SXE_TX_DESC_CMD       (SXE_TX_DESC_EOP_MASK | SXE_TX_DESC_RS_MASK)
-#define SXE_TX_DESC_TYPE_DATA 0x00300000   
-#define SXE_TX_DESC_DEXT      0x20000000   
-#define SXE_TX_DESC_IFCS      0x02000000   
-#define SXE_TX_DESC_VLE       0x40000000 
-#define SXE_TX_DESC_TSTAMP    0x00080000 
-#define SXE_TX_DESC_FLAGS     (SXE_TX_DESC_TYPE_DATA | \
+#define SXE_TX_DESC_EOP_MASK  0x01000000
+#define SXE_TX_DESC_RS_MASK   0x08000000
+#define SXE_TX_DESC_STAT_DD   0x00000001
+#define SXE_TX_DESC_CMD	   (SXE_TX_DESC_EOP_MASK | SXE_TX_DESC_RS_MASK)
+#define SXE_TX_DESC_TYPE_DATA 0x00300000
+#define SXE_TX_DESC_DEXT	  0x20000000
+#define SXE_TX_DESC_IFCS	  0x02000000
+#define SXE_TX_DESC_VLE	   0x40000000
+#define SXE_TX_DESC_TSTAMP	0x00080000
+#define SXE_TX_DESC_FLAGS	 (SXE_TX_DESC_TYPE_DATA | \
 				SXE_TX_DESC_IFCS | \
 				SXE_TX_DESC_DEXT| \
 				SXE_TX_DESC_EOP_MASK)
-#define SXE_TXD_DTYP_CTXT     0x00200000 
-#define SXE_TXD_DCMD_TSE      0x80000000 
-#define SXE_TXD_MAC_LINKSEC   0x00040000 
-#define SXE_TXD_MAC_1588      0x00080000 
-#define SXE_TX_DESC_PAYLEN_SHIFT     14
-#define SXE_TX_OUTERIPCS_SHIFT	17 
+#define SXE_TXD_DTYP_CTXT	 0x00200000
+#define SXE_TXD_DCMD_TSE	  0x80000000
+#define SXE_TXD_MAC_LINKSEC   0x00040000
+#define SXE_TXD_MAC_1588	  0x00080000
+#define SXE_TX_DESC_PAYLEN_SHIFT	 14
+#define SXE_TX_OUTERIPCS_SHIFT	17
 
 #define SXE_TX_POPTS_IXSM   0x01
 #define SXE_TX_POPTS_TXSM   0x02
-#define SXE_TXD_POPTS_SHIFT 8  
+#define SXE_TXD_POPTS_SHIFT 8
 #define SXE_TXD_POPTS_IXSM  (SXE_TX_POPTS_IXSM << SXE_TXD_POPTS_SHIFT)
 #define SXE_TXD_POPTS_TXSM  (SXE_TX_POPTS_TXSM << SXE_TXD_POPTS_SHIFT)
 #define SXE_TXD_POPTS_IPSEC (0x00000400)
 
-#define SXE_TX_CTXTD_DTYP_CTXT      0x00200000 
-#define SXE_TX_CTXTD_TUCMD_IPV6     0x00000000 
-#define SXE_TX_CTXTD_TUCMD_IPV4     0x00000400 
-#define SXE_TX_CTXTD_TUCMD_L4T_UDP  0x00000000 
-#define SXE_TX_CTXTD_TUCMD_L4T_TCP  0x00000800 
-#define SXE_TX_CTXTD_TUCMD_L4T_SCTP 0x00001000 
-#define SXE_TX_CTXTD_TUCMD_L4T_RSV  0x00001800 
-#define SXE_TX_CTXTD_TUCMD_IPSEC_TYPE_ESP   0x00002000 
-#define SXE_TX_CTXTD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 
-
-#define SXE_TX_CTXTD_L4LEN_SHIFT          8  
-#define SXE_TX_CTXTD_MSS_SHIFT            16 
-#define SXE_TX_CTXTD_MACLEN_SHIFT         9  
-#define SXE_TX_CTXTD_VLAN_SHIFT           16
-#define SXE_TX_CTXTD_VLAN_MASK            0xffff0000
-#define SXE_TX_CTXTD_MACLEN_MASK          0x0000fE00
-#define SXE_TX_CTXTD_OUTER_IPLEN_SHIFT    16 
-#define SXE_TX_CTXTD_TUNNEL_LEN_SHIFT     24 
-
-#define SXE_VLAN_TAG_SIZE     4
-
-#define SXE_RSS_KEY_SIZE                (40)  
-#define SXE_MAX_RSS_KEY_ENTRIES		(10)  
-#define SXE_MAX_RETA_ENTRIES            (128) 
+#define SXE_TX_CTXTD_DTYP_CTXT	  0x00200000
+#define SXE_TX_CTXTD_TUCMD_IPV6	 0x00000000
+#define SXE_TX_CTXTD_TUCMD_IPV4	 0x00000400
+#define SXE_TX_CTXTD_TUCMD_L4T_UDP  0x00000000
+#define SXE_TX_CTXTD_TUCMD_L4T_TCP  0x00000800
+#define SXE_TX_CTXTD_TUCMD_L4T_SCTP 0x00001000
+#define SXE_TX_CTXTD_TUCMD_L4T_RSV  0x00001800
+#define SXE_TX_CTXTD_TUCMD_IPSEC_TYPE_ESP   0x00002000
+#define SXE_TX_CTXTD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000
+
+#define SXE_TX_CTXTD_L4LEN_SHIFT		  8
+#define SXE_TX_CTXTD_MSS_SHIFT			16
+#define SXE_TX_CTXTD_MACLEN_SHIFT		 9
+#define SXE_TX_CTXTD_VLAN_SHIFT		   16
+#define SXE_TX_CTXTD_VLAN_MASK			0xffff0000
+#define SXE_TX_CTXTD_MACLEN_MASK		  0x0000fE00
+#define SXE_TX_CTXTD_OUTER_IPLEN_SHIFT	16
+#define SXE_TX_CTXTD_TUNNEL_LEN_SHIFT	 24
+
+#define SXE_VLAN_TAG_SIZE	 4
+
+#define SXE_RSS_KEY_SIZE				(40)
+#define SXE_MAX_RSS_KEY_ENTRIES		(10)
+#define SXE_MAX_RETA_ENTRIES			(128)
 
 #define SXE_TIMINC_IV_NS_SHIFT  8
 #define SXE_TIMINC_INCPD_SHIFT  24
@@ -142,49 +142,49 @@  enum sxe_mc_filter_type {
 	(((incpd) << SXE_TIMINC_INCPD_SHIFT) | \
 	((iv_ns) << SXE_TIMINC_IV_NS_SHIFT) | (iv_sns))
 
-#define PBA_STRATEGY_EQUAL       (0)    
-#define PBA_STRATEGY_WEIGHTED    (1)	
-#define SXE_PKG_BUF_NUM_MAX               (8)
+#define PBA_STRATEGY_EQUAL	   (0)
+#define PBA_STRATEGY_WEIGHTED	(1)
+#define SXE_PKG_BUF_NUM_MAX			   (8)
 #define SXE_HW_TXRX_RING_NUM_MAX 128
 #define SXE_VMDQ_DCB_NUM_QUEUES  SXE_HW_TXRX_RING_NUM_MAX
-#define SXE_RX_PKT_BUF_SIZE 			(512)
+#define SXE_RX_PKT_BUF_SIZE				(512)
 
 #define SXE_UC_ENTRY_NUM_MAX   128
 #define SXE_HW_TX_NONE_MODE_Q_NUM 64
 
-#define SXE_MBX_MSG_NUM    16
+#define SXE_MBX_MSG_NUM	16
 #define SXE_MBX_RETRY_INTERVAL   500
-#define SXE_MBX_RETRY_COUNT      2000
+#define SXE_MBX_RETRY_COUNT	  2000
 
 #define SXE_VF_UC_ENTRY_NUM_MAX 10
 #define SXE_VF_MC_ENTRY_NUM_MAX 30
 
 #define SXE_UTA_ENTRY_NUM_MAX   128
 #define SXE_MTA_ENTRY_NUM_MAX   128
-#define SXE_HASH_UC_NUM_MAX   4096 
+#define SXE_HASH_UC_NUM_MAX   4096
 
-#define  SXE_MAC_ADDR_EXTRACT_MASK  (0xFFF) 
-#define  SXE_MAC_ADDR_SHIFT         (5)     
-#define  SXE_MAC_ADDR_REG_MASK      (0x7F)  
-#define  SXE_MAC_ADDR_BIT_MASK      (0x1F)  
+#define  SXE_MAC_ADDR_EXTRACT_MASK  (0xFFF)
+#define  SXE_MAC_ADDR_SHIFT		 (5)
+#define  SXE_MAC_ADDR_REG_MASK	  (0x7F)
+#define  SXE_MAC_ADDR_BIT_MASK	  (0x1F)
 
-#define  SXE_VFT_TBL_SIZE          (128)   
-#define  SXE_VLAN_ID_SHIFT         (5)     
-#define  SXE_VLAN_ID_REG_MASK      (0x7F)  
-#define  SXE_VLAN_ID_BIT_MASK      (0x1F)  
+#define  SXE_VFT_TBL_SIZE		  (128)
+#define  SXE_VLAN_ID_SHIFT		 (5)
+#define  SXE_VLAN_ID_REG_MASK	  (0x7F)
+#define  SXE_VLAN_ID_BIT_MASK	  (0x1F)
 
-#define SXE_TX_PBSIZE_MAX    0x00028000 
-#define SXE_TX_PKT_SIZE_MAX  0xA        
-#define SXE_NODCB_TX_PKT_SIZE_MAX 0x14 
+#define SXE_TX_PBSIZE_MAX	0x00028000
+#define SXE_TX_PKT_SIZE_MAX  0xA
+#define SXE_NODCB_TX_PKT_SIZE_MAX 0x14
 #define SXE_RING_ENABLE_WAIT_LOOP 10
 
-#define VFTA_BLOCK_SIZE 		8
-#define VF_BLOCK_BITS 			(32)
+#define VFTA_BLOCK_SIZE		 8
+#define VF_BLOCK_BITS		   (32)
 #define SXE_MAX_MAC_HDR_LEN		127
 #define SXE_MAX_NETWORK_HDR_LEN		511
 #define SXE_MAC_ADDR_LEN		6
 
-#define SXE_FNAV_BUCKET_HASH_KEY    0x3DAD14E2
+#define SXE_FNAV_BUCKET_HASH_KEY	0x3DAD14E2
 #define SXE_FNAV_SAMPLE_HASH_KEY 0x174D3614
 #define SXE_SAMPLE_COMMON_HASH_KEY \
 		(SXE_FNAV_BUCKET_HASH_KEY & SXE_FNAV_SAMPLE_HASH_KEY)
@@ -202,11 +202,11 @@  enum sxe_mc_filter_type {
 #define SXE_SAMPLE_VLAN_MASK		0xEFFF
 #define SXE_SAMPLE_FLEX_BYTES_MASK	0xFFFF
 
-#define SXE_FNAV_INIT_DONE_POLL               10
-#define SXE_FNAV_DROP_QUEUE                   127
+#define SXE_FNAV_INIT_DONE_POLL			   10
+#define SXE_FNAV_DROP_QUEUE				   127
 
-#define MAX_TRAFFIC_CLASS        8
-#define DEF_TRAFFIC_CLASS        1
+#define MAX_TRAFFIC_CLASS		8
+#define DEF_TRAFFIC_CLASS		1
 
 #define SXE_LINK_SPEED_UNKNOWN   0
 #define SXE_LINK_SPEED_10_FULL   0x0002
@@ -245,176 +245,176 @@  enum sxe_sample_type {
 };
 
 enum {
-	SXE_DIAG_TEST_PASSED                = 0,
-	SXE_DIAG_TEST_BLOCKED               = 1,
-	SXE_DIAG_STATS_REG_TEST_ERR         = 2,
-	SXE_DIAG_REG_PATTERN_TEST_ERR       = 3,
-	SXE_DIAG_CHECK_REG_TEST_ERR         = 4,
-	SXE_DIAG_DISABLE_IRQ_TEST_ERR       = 5,
-	SXE_DIAG_ENABLE_IRQ_TEST_ERR        = 6,
+	SXE_DIAG_TEST_PASSED				= 0,
+	SXE_DIAG_TEST_BLOCKED			   = 1,
+	SXE_DIAG_STATS_REG_TEST_ERR		 = 2,
+	SXE_DIAG_REG_PATTERN_TEST_ERR	   = 3,
+	SXE_DIAG_CHECK_REG_TEST_ERR		 = 4,
+	SXE_DIAG_DISABLE_IRQ_TEST_ERR	   = 5,
+	SXE_DIAG_ENABLE_IRQ_TEST_ERR		= 6,
 	SXE_DIAG_DISABLE_OTHER_IRQ_TEST_ERR = 7,
-	SXE_DIAG_TX_RING_CONFIGURE_ERR      = 8,
-	SXE_DIAG_RX_RING_CONFIGURE_ERR      = 9,
-	SXE_DIAG_ALLOC_SKB_ERR              = 10,
-	SXE_DIAG_LOOPBACK_SEND_TEST_ERR     = 11,
-	SXE_DIAG_LOOPBACK_RECV_TEST_ERR     = 12,
+	SXE_DIAG_TX_RING_CONFIGURE_ERR	  = 8,
+	SXE_DIAG_RX_RING_CONFIGURE_ERR	  = 9,
+	SXE_DIAG_ALLOC_SKB_ERR			  = 10,
+	SXE_DIAG_LOOPBACK_SEND_TEST_ERR	 = 11,
+	SXE_DIAG_LOOPBACK_RECV_TEST_ERR	 = 12,
 };
 
-#define SXE_RXD_STAT_DD       0x01    
-#define SXE_RXD_STAT_EOP      0x02    
-#define SXE_RXD_STAT_FLM      0x04    
-#define SXE_RXD_STAT_VP       0x08    
-#define SXE_RXDADV_NEXTP_MASK   0x000FFFF0 
+#define SXE_RXD_STAT_DD	   0x01
+#define SXE_RXD_STAT_EOP	  0x02
+#define SXE_RXD_STAT_FLM	  0x04
+#define SXE_RXD_STAT_VP	   0x08
+#define SXE_RXDADV_NEXTP_MASK   0x000FFFF0
 #define SXE_RXDADV_NEXTP_SHIFT  0x00000004
-#define SXE_RXD_STAT_UDPCS    0x10    
-#define SXE_RXD_STAT_L4CS     0x20    
-#define SXE_RXD_STAT_IPCS     0x40    
-#define SXE_RXD_STAT_PIF      0x80    
-#define SXE_RXD_STAT_CRCV     0x100   
-#define SXE_RXD_STAT_OUTERIPCS  0x100 
-#define SXE_RXD_STAT_VEXT     0x200   
-#define SXE_RXD_STAT_UDPV     0x400   
-#define SXE_RXD_STAT_DYNINT   0x800   
-#define SXE_RXD_STAT_LLINT    0x800   
-#define SXE_RXD_STAT_TSIP     0x08000 
-#define SXE_RXD_STAT_TS       0x10000 
-#define SXE_RXD_STAT_SECP     0x20000 
-#define SXE_RXD_STAT_LB       0x40000 
-#define SXE_RXD_STAT_ACK      0x8000  
-#define SXE_RXD_ERR_CE        0x01    
-#define SXE_RXD_ERR_LE        0x02    
-#define SXE_RXD_ERR_PE        0x08    
-#define SXE_RXD_ERR_OSE       0x10    
-#define SXE_RXD_ERR_USE       0x20    
-#define SXE_RXD_ERR_TCPE      0x40    
-#define SXE_RXD_ERR_IPE       0x80    
-#define SXE_RXDADV_ERR_MASK           0xfff00000 
-#define SXE_RXDADV_ERR_SHIFT          20         
-#define SXE_RXDADV_ERR_OUTERIPER	0x04000000 
-#define SXE_RXDADV_ERR_FCEOFE         0x80000000 
-#define SXE_RXDADV_ERR_FCERR          0x00700000 
-#define SXE_RXDADV_ERR_FNAV_LEN       0x00100000 
-#define SXE_RXDADV_ERR_FNAV_DROP      0x00200000 
-#define SXE_RXDADV_ERR_FNAV_COLL      0x00400000 
-#define SXE_RXDADV_ERR_HBO    0x00800000 
-#define SXE_RXDADV_ERR_CE     0x01000000 
-#define SXE_RXDADV_ERR_LE     0x02000000 
-#define SXE_RXDADV_ERR_PE     0x08000000 
-#define SXE_RXDADV_ERR_OSE    0x10000000 
-#define SXE_RXDADV_ERR_IPSEC_INV_PROTOCOL  0x08000000 
-#define SXE_RXDADV_ERR_IPSEC_INV_LENGTH    0x10000000 
+#define SXE_RXD_STAT_UDPCS	0x10
+#define SXE_RXD_STAT_L4CS	 0x20
+#define SXE_RXD_STAT_IPCS	 0x40
+#define SXE_RXD_STAT_PIF	  0x80
+#define SXE_RXD_STAT_CRCV	 0x100
+#define SXE_RXD_STAT_OUTERIPCS  0x100
+#define SXE_RXD_STAT_VEXT	 0x200
+#define SXE_RXD_STAT_UDPV	 0x400
+#define SXE_RXD_STAT_DYNINT   0x800
+#define SXE_RXD_STAT_LLINT	0x800
+#define SXE_RXD_STAT_TSIP	 0x08000
+#define SXE_RXD_STAT_TS	   0x10000
+#define SXE_RXD_STAT_SECP	 0x20000
+#define SXE_RXD_STAT_LB	   0x40000
+#define SXE_RXD_STAT_ACK	  0x8000
+#define SXE_RXD_ERR_CE		0x01
+#define SXE_RXD_ERR_LE		0x02
+#define SXE_RXD_ERR_PE		0x08
+#define SXE_RXD_ERR_OSE	   0x10
+#define SXE_RXD_ERR_USE	   0x20
+#define SXE_RXD_ERR_TCPE	  0x40
+#define SXE_RXD_ERR_IPE	   0x80
+#define SXE_RXDADV_ERR_MASK		   0xfff00000
+#define SXE_RXDADV_ERR_SHIFT		  20
+#define SXE_RXDADV_ERR_OUTERIPER	0x04000000
+#define SXE_RXDADV_ERR_FCEOFE		 0x80000000
+#define SXE_RXDADV_ERR_FCERR		  0x00700000
+#define SXE_RXDADV_ERR_FNAV_LEN	   0x00100000
+#define SXE_RXDADV_ERR_FNAV_DROP	  0x00200000
+#define SXE_RXDADV_ERR_FNAV_COLL	  0x00400000
+#define SXE_RXDADV_ERR_HBO	0x00800000
+#define SXE_RXDADV_ERR_CE	 0x01000000
+#define SXE_RXDADV_ERR_LE	 0x02000000
+#define SXE_RXDADV_ERR_PE	 0x08000000
+#define SXE_RXDADV_ERR_OSE	0x10000000
+#define SXE_RXDADV_ERR_IPSEC_INV_PROTOCOL  0x08000000
+#define SXE_RXDADV_ERR_IPSEC_INV_LENGTH	0x10000000
 #define SXE_RXDADV_ERR_IPSEC_AUTH_FAILED   0x18000000
-#define SXE_RXDADV_ERR_USE    0x20000000 
-#define SXE_RXDADV_ERR_L4E    0x40000000 
-#define SXE_RXDADV_ERR_IPE    0x80000000 
-#define SXE_RXD_VLAN_ID_MASK  0x0FFF  
-#define SXE_RXD_PRI_MASK      0xE000  
-#define SXE_RXD_PRI_SHIFT     13
-#define SXE_RXD_CFI_MASK      0x1000  
-#define SXE_RXD_CFI_SHIFT     12
-#define SXE_RXDADV_LROCNT_MASK        0x001E0000
-#define SXE_RXDADV_LROCNT_SHIFT       17
-
-#define SXE_RXDADV_STAT_DD            SXE_RXD_STAT_DD  
-#define SXE_RXDADV_STAT_EOP           SXE_RXD_STAT_EOP 
-#define SXE_RXDADV_STAT_FLM           SXE_RXD_STAT_FLM 
-#define SXE_RXDADV_STAT_VP            SXE_RXD_STAT_VP  
-#define SXE_RXDADV_STAT_MASK          0x000fffff 
-#define SXE_RXDADV_STAT_TS		0x00010000 
-#define SXE_RXDADV_STAT_SECP		0x00020000 
-
-#define SXE_RXDADV_PKTTYPE_NONE       0x00000000
-#define SXE_RXDADV_PKTTYPE_IPV4       0x00000010 
-#define SXE_RXDADV_PKTTYPE_IPV4_EX    0x00000020 
-#define SXE_RXDADV_PKTTYPE_IPV6       0x00000040 
-#define SXE_RXDADV_PKTTYPE_IPV6_EX    0x00000080 
-#define SXE_RXDADV_PKTTYPE_TCP        0x00000100 
-#define SXE_RXDADV_PKTTYPE_UDP        0x00000200 
-#define SXE_RXDADV_PKTTYPE_SCTP       0x00000400 
-#define SXE_RXDADV_PKTTYPE_NFS        0x00000800 
-#define SXE_RXDADV_PKTTYPE_VXLAN      0x00000800 
-#define SXE_RXDADV_PKTTYPE_TUNNEL     0x00010000 
-#define SXE_RXDADV_PKTTYPE_IPSEC_ESP  0x00001000 
-#define SXE_RXDADV_PKTTYPE_IPSEC_AH   0x00002000 
-#define SXE_RXDADV_PKTTYPE_LINKSEC    0x00004000 
-#define SXE_RXDADV_PKTTYPE_ETQF       0x00008000 
-#define SXE_RXDADV_PKTTYPE_ETQF_MASK  0x00000070 
-#define SXE_RXDADV_PKTTYPE_ETQF_SHIFT 4          
+#define SXE_RXDADV_ERR_USE	0x20000000
+#define SXE_RXDADV_ERR_L4E	0x40000000
+#define SXE_RXDADV_ERR_IPE	0x80000000
+#define SXE_RXD_VLAN_ID_MASK  0x0FFF
+#define SXE_RXD_PRI_MASK	  0xE000
+#define SXE_RXD_PRI_SHIFT	 13
+#define SXE_RXD_CFI_MASK	  0x1000
+#define SXE_RXD_CFI_SHIFT	 12
+#define SXE_RXDADV_LROCNT_MASK		0x001E0000
+#define SXE_RXDADV_LROCNT_SHIFT	   17
+
+#define SXE_RXDADV_STAT_DD			SXE_RXD_STAT_DD
+#define SXE_RXDADV_STAT_EOP		   SXE_RXD_STAT_EOP
+#define SXE_RXDADV_STAT_FLM		   SXE_RXD_STAT_FLM
+#define SXE_RXDADV_STAT_VP			SXE_RXD_STAT_VP
+#define SXE_RXDADV_STAT_MASK		  0x000fffff
+#define SXE_RXDADV_STAT_TS		0x00010000
+#define SXE_RXDADV_STAT_SECP		0x00020000
+
+#define SXE_RXDADV_PKTTYPE_NONE	   0x00000000
+#define SXE_RXDADV_PKTTYPE_IPV4	   0x00000010
+#define SXE_RXDADV_PKTTYPE_IPV4_EX	0x00000020
+#define SXE_RXDADV_PKTTYPE_IPV6	   0x00000040
+#define SXE_RXDADV_PKTTYPE_IPV6_EX	0x00000080
+#define SXE_RXDADV_PKTTYPE_TCP		0x00000100
+#define SXE_RXDADV_PKTTYPE_UDP		0x00000200
+#define SXE_RXDADV_PKTTYPE_SCTP	   0x00000400
+#define SXE_RXDADV_PKTTYPE_NFS		0x00000800
+#define SXE_RXDADV_PKTTYPE_VXLAN	  0x00000800
+#define SXE_RXDADV_PKTTYPE_TUNNEL	 0x00010000
+#define SXE_RXDADV_PKTTYPE_IPSEC_ESP  0x00001000
+#define SXE_RXDADV_PKTTYPE_IPSEC_AH   0x00002000
+#define SXE_RXDADV_PKTTYPE_LINKSEC	0x00004000
+#define SXE_RXDADV_PKTTYPE_ETQF	   0x00008000
+#define SXE_RXDADV_PKTTYPE_ETQF_MASK  0x00000070
+#define SXE_RXDADV_PKTTYPE_ETQF_SHIFT 4
 
 struct sxe_mac_stats {
-	u64 crcerrs;           
-	u64 errbc;             
-	u64 rlec;              
-	u64 prc64;             
-	u64 prc127;            
-	u64 prc255;            
-	u64 prc511;            
-	u64 prc1023;           
-	u64 prc1522;           
-	u64 gprc;              
-	u64 bprc;              
-	u64 mprc;              
-	u64 gptc;              
-	u64 gorc;              
-	u64 gotc;              
-	u64 ruc;               
-	u64 rfc;               
-	u64 roc;               
-	u64 rjc;               
-	u64 tor;               
-	u64 tpr;               
-	u64 tpt;               
-	u64 ptc64;             
-	u64 ptc127;            
-	u64 ptc255;            
-	u64 ptc511;            
-	u64 ptc1023;           
-	u64 ptc1522;           
-	u64 mptc;              
-	u64 bptc;              
-	u64 qprc[16];          
-	u64 qptc[16];          
-	u64 qbrc[16];          
-	u64 qbtc[16];          
-	u64 qprdc[16];         
-	u64 dburxtcin[8];      
-	u64 dburxtcout[8];     
-	u64 dburxgdreecnt[8];  
-	u64 dburxdrofpcnt[8];  
-	u64 dbutxtcin[8];      
-	u64 dbutxtcout[8];     
-	u64 rxdgpc;            
-	u64 rxdgbc;            
-	u64 rxddpc;            
-	u64 rxddbc;            
-	u64 rxtpcing;          
-	u64 rxtpceng;          
-	u64 rxlpbkpc;          
-	u64 rxlpbkbc;          
-	u64 rxdlpbkpc;         
-	u64 rxdlpbkbc;         
-	u64 prddc;             
-	u64 txdgpc;            
-	u64 txdgbc;            
-	u64 txswerr;           
-	u64 txswitch;          
-	u64 txrepeat;          
-	u64 txdescerr;         
-
-	u64 fnavadd;           
-	u64 fnavrmv;           
-	u64 fnavadderr;        
-	u64 fnavrmverr;        
-	u64 fnavmatch;         
-	u64 fnavmiss;          
-	u64 hw_rx_no_dma_resources; 
-	u64 prcpf[8];          
-	u64 pfct[8];           
-	u64 mpc[8];            
-
-	u64 total_tx_pause;    
-	u64 total_gptc;        
-	u64 total_gotc;        
+	u64 crcerrs;
+	u64 errbc;
+	u64 rlec;
+	u64 prc64;
+	u64 prc127;
+	u64 prc255;
+	u64 prc511;
+	u64 prc1023;
+	u64 prc1522;
+	u64 gprc;
+	u64 bprc;
+	u64 mprc;
+	u64 gptc;
+	u64 gorc;
+	u64 gotc;
+	u64 ruc;
+	u64 rfc;
+	u64 roc;
+	u64 rjc;
+	u64 tor;
+	u64 tpr;
+	u64 tpt;
+	u64 ptc64;
+	u64 ptc127;
+	u64 ptc255;
+	u64 ptc511;
+	u64 ptc1023;
+	u64 ptc1522;
+	u64 mptc;
+	u64 bptc;
+	u64 qprc[16];
+	u64 qptc[16];
+	u64 qbrc[16];
+	u64 qbtc[16];
+	u64 qprdc[16];
+	u64 dburxtcin[8];
+	u64 dburxtcout[8];
+	u64 dburxgdreecnt[8];
+	u64 dburxdrofpcnt[8];
+	u64 dbutxtcin[8];
+	u64 dbutxtcout[8];
+	u64 rxdgpc;
+	u64 rxdgbc;
+	u64 rxddpc;
+	u64 rxddbc;
+	u64 rxtpcing;
+	u64 rxtpceng;
+	u64 rxlpbkpc;
+	u64 rxlpbkbc;
+	u64 rxdlpbkpc;
+	u64 rxdlpbkbc;
+	u64 prddc;
+	u64 txdgpc;
+	u64 txdgbc;
+	u64 txswerr;
+	u64 txswitch;
+	u64 txrepeat;
+	u64 txdescerr;
+
+	u64 fnavadd;
+	u64 fnavrmv;
+	u64 fnavadderr;
+	u64 fnavrmverr;
+	u64 fnavmatch;
+	u64 fnavmiss;
+	u64 hw_rx_no_dma_resources;
+	u64 prcpf[8];
+	u64 pfct[8];
+	u64 mpc[8];
+
+	u64 total_tx_pause;
+	u64 total_gptc;
+	u64 total_gotc;
 };
 
 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_FILTER_CTRL
@@ -440,16 +440,16 @@  struct sxe_fivetuple_filter_info {
 };
 
 struct sxe_fivetuple_node_info {
-	u16 index;  
-	u16 queue;  
+	u16 index;
+	u16 queue;
 	struct sxe_fivetuple_filter_info filter_info;
 };
 #endif
 
 union sxe_fnav_rule_info {
 	struct {
-		u8     vm_pool;
-		u8     flow_type;
+		u8	 vm_pool;
+		u8	 flow_type;
 		__be16 vlan_id;
 		__be32 dst_ip[4];
 		__be32 src_ip[4];
@@ -480,21 +480,21 @@  void sxe_hw_ops_init(struct sxe_hw *hw);
 
 
 struct sxe_reg_info {
-	u32 addr;        
-	u32 count;       
-	u32 stride;      
-	const s8 *name;  
+	u32 addr;
+	u32 count;
+	u32 stride;
+	const s8 *name;
 };
 
 struct sxe_setup_operations {
-	s32  (*reset)(struct sxe_hw *);
-	void (*pf_rst_done_set)(struct sxe_hw *);
-	void (*no_snoop_disable)(struct sxe_hw *);
-	u32  (*reg_read)(struct sxe_hw *, u32);
-	void (*reg_write)(struct sxe_hw *, u32, u32);
-	void (*regs_dump)(struct sxe_hw *);
-	void (*regs_flush)(struct sxe_hw *);
-	s32  (*regs_test)(struct sxe_hw *);
+	s32  (*reset)(struct sxe_hw *hw);
+	void (*pf_rst_done_set)(struct sxe_hw *hw);
+	void (*no_snoop_disable)(struct sxe_hw *hw);
+	u32  (*reg_read)(struct sxe_hw *hw, u32 reg);
+	void (*reg_write)(struct sxe_hw *hw, u32 reg, u32 val);
+	void (*regs_dump)(struct sxe_hw *hw);
+	void (*regs_flush)(struct sxe_hw *hw);
+	s32  (*regs_test)(struct sxe_hw *hw);
 };
 
 struct sxe_hw_setup {
@@ -503,20 +503,22 @@  struct sxe_hw_setup {
 
 struct sxe_irq_operations {
 	u32  (*pending_irq_read_clear)(struct sxe_hw *hw);
-	void (*pending_irq_write_clear)(struct sxe_hw * hw, u32 value);
+	void (*pending_irq_write_clear)(struct sxe_hw *hw, u32 value);
 	void (*irq_general_reg_set)(struct sxe_hw *hw, u32 value);
 	u32  (*irq_general_reg_get)(struct sxe_hw *hw);
 	void (*ring_irq_auto_disable)(struct sxe_hw *hw, bool is_misx);
 	void (*set_eitrsel)(struct sxe_hw *hw, u32 value);
-	void (*ring_irq_interval_set)(struct sxe_hw *hw, u16 irq_idx, u32 interval);
-	void (*event_irq_interval_set)(struct sxe_hw * hw, u16 irq_idx, u32 value);
+	void (*ring_irq_interval_set)(struct sxe_hw *hw, u16 irq_idx,
+			u32 interval);
+	void (*event_irq_interval_set)(struct sxe_hw *hw, u16 irq_idx,
+			u32 value);
 	void (*event_irq_auto_clear_set)(struct sxe_hw *hw, u32 value);
 	void (*ring_irq_map)(struct sxe_hw *hw, bool is_tx,
-                                u16 reg_idx, u16 irq_idx);
+							u16 reg_idx, u16 irq_idx);
 	void (*event_irq_map)(struct sxe_hw *hw, u8 offset, u16 irq_idx);
-	void (*ring_irq_enable)(struct sxe_hw * hw, u64 qmask);
-	u32  (*irq_cause_get)(struct sxe_hw * hw);
-	void (*event_irq_trigger)(struct sxe_hw * hw);
+	void (*ring_irq_enable)(struct sxe_hw *hw, u64 qmask);
+	u32  (*irq_cause_get)(struct sxe_hw *hw);
+	void (*event_irq_trigger)(struct sxe_hw *hw);
 	void (*ring_irq_trigger)(struct sxe_hw *hw, u64 eics);
 	void (*specific_irq_disable)(struct sxe_hw *hw, u32 value);
 	void (*specific_irq_enable)(struct sxe_hw *hw, u32 value);
@@ -530,26 +532,26 @@  struct sxe_irq_info {
 };
 
 struct sxe_mac_operations {
-	bool (*link_up_1g_check)(struct sxe_hw *);
-	bool (*link_state_is_up)(struct sxe_hw *);
-	u32  (*link_speed_get)(struct sxe_hw *);
-	void (*link_speed_set)(struct sxe_hw *, u32 speed);
-	void (*pad_enable)(struct sxe_hw *);
-	s32  (*fc_enable)(struct sxe_hw *);
-	void (*crc_configure)(struct sxe_hw *);
-	void (*loopback_switch)(struct sxe_hw *, bool);
+	bool (*link_up_1g_check)(struct sxe_hw *hw);
+	bool (*link_state_is_up)(struct sxe_hw *hw);
+	u32  (*link_speed_get)(struct sxe_hw *hw);
+	void (*link_speed_set)(struct sxe_hw *hw, u32 speed);
+	void (*pad_enable)(struct sxe_hw *hw);
+	s32  (*fc_enable)(struct sxe_hw *hw);
+	void (*crc_configure)(struct sxe_hw *hw);
+	void (*loopback_switch)(struct sxe_hw *hw, bool val);
 	void (*txrx_enable)(struct sxe_hw *hw);
-	void (*max_frame_set)(struct sxe_hw *, u32);
-	u32  (*max_frame_get)(struct sxe_hw *);
-	void (*fc_autoneg_localcap_set)(struct sxe_hw *);
-	void (*fc_tc_high_water_mark_set)(struct sxe_hw *, u8, u32);
-	void (*fc_tc_low_water_mark_set)(struct sxe_hw *, u8, u32);
-	void (*fc_param_init)(struct sxe_hw *);
-	enum sxe_fc_mode (*fc_current_mode_get)(struct sxe_hw *);
-	enum sxe_fc_mode (*fc_requested_mode_get)(struct sxe_hw *);
-	void (*fc_requested_mode_set)(struct sxe_hw *, enum sxe_fc_mode);
-	bool (*is_fc_autoneg_disabled)(struct sxe_hw *);
-	void (*fc_autoneg_disable_set)(struct sxe_hw *, bool);
+	void (*max_frame_set)(struct sxe_hw *hw, u32 val);
+	u32  (*max_frame_get)(struct sxe_hw *hw);
+	void (*fc_autoneg_localcap_set)(struct sxe_hw *hw);
+	void (*fc_tc_high_water_mark_set)(struct sxe_hw *hw, u8 tc_idx, u32 val);
+	void (*fc_tc_low_water_mark_set)(struct sxe_hw *hw, u8 tc_idx, u32 val);
+	void (*fc_param_init)(struct sxe_hw *hw);
+	enum sxe_fc_mode (*fc_current_mode_get)(struct sxe_hw *hw);
+	enum sxe_fc_mode (*fc_requested_mode_get)(struct sxe_hw *hw);
+	void (*fc_requested_mode_set)(struct sxe_hw *hw, enum sxe_fc_mode e);
+	bool (*is_fc_autoneg_disabled)(struct sxe_hw *hw);
+	void (*fc_autoneg_disable_set)(struct sxe_hw *hw, bool val);
 };
 
 #define SXE_FLAGS_DOUBLE_RESET_REQUIRED	0x01
@@ -562,25 +564,26 @@  struct sxe_mac_info {
 };
 
 struct sxe_filter_mac_operations {
-	u32 (*rx_mode_get)(struct sxe_hw *);
-	void (*rx_mode_set)(struct sxe_hw *, u32);
-	u32 (*pool_rx_mode_get)(struct sxe_hw *, u16);
-	void (*pool_rx_mode_set)(struct sxe_hw *, u32, u16);
-	void (*rx_lro_enable) (struct sxe_hw *, bool);
-	void (*rx_udp_frag_checksum_disable) (struct sxe_hw *);
-	s32  (*uc_addr_add)(struct sxe_hw *, u32, u8 *, u32);
-	s32  (*uc_addr_del)(struct sxe_hw *, u32);
-	void (*uc_addr_clear)(struct sxe_hw *);
+	u32 (*rx_mode_get)(struct sxe_hw *hw);
+	void (*rx_mode_set)(struct sxe_hw *hw, u32 filter_ctrl);
+	u32 (*pool_rx_mode_get)(struct sxe_hw *hw, u16 idx);
+	void (*pool_rx_mode_set)(struct sxe_hw *hw, u32 vmolr, u16 idx);
+	void (*rx_lro_enable)(struct sxe_hw *hw, bool is_enable);
+	void (*rx_udp_frag_checksum_disable)(struct sxe_hw *hw);
+	s32  (*uc_addr_add)(struct sxe_hw *hw, u32 rar_idx,
+							u8 *addr, u32 pool_idx);
+	s32  (*uc_addr_del)(struct sxe_hw *hw, u32 idx);
+	void (*uc_addr_clear)(struct sxe_hw *hw);
 	void (*mta_hash_table_set)(struct sxe_hw *hw, u8 index, u32 value);
 	void (*mta_hash_table_update)(struct sxe_hw *hw, u8 reg_idx, u8 bit_idx);
 	void (*fc_mac_addr_set)(struct sxe_hw *hw, u8 *mac_addr);
 
-	void (*mc_filter_enable)(struct sxe_hw *);
+	void (*mc_filter_enable)(struct sxe_hw *hw);
 
 	void (*mc_filter_disable)(struct sxe_hw *hw);
 
-	void (*rx_nfs_filter_disable)(struct sxe_hw *);
-	void (*ethertype_filter_set)(struct sxe_hw *, u8, u32);
+	void (*rx_nfs_filter_disable)(struct sxe_hw *hw);
+	void (*ethertype_filter_set)(struct sxe_hw *hw, u8 filter_type, u32 val);
 
 	void (*vt_ctrl_configure)(struct sxe_hw *hw, u8 num_vfs);
 
@@ -600,16 +603,17 @@  struct sxe_filter_mac {
 };
 
 struct sxe_filter_vlan_operations {
-	u32 (*pool_filter_read)(struct sxe_hw *, u16);
-	void (*pool_filter_write)(struct sxe_hw *, u16, u32);
-	u32 (*pool_filter_bitmap_read)(struct sxe_hw *, u16);
-	void (*pool_filter_bitmap_write)(struct sxe_hw *, u16, u32);
-	void (*filter_array_write)(struct sxe_hw *, u16, u32);
-	u32  (*filter_array_read)(struct sxe_hw *, u16);
-	void (*filter_array_clear)(struct sxe_hw *);
-	void (*filter_switch)(struct sxe_hw *,bool);
-	void (*untagged_pkts_rcv_switch)(struct sxe_hw *, u32, bool);
-	s32  (*filter_configure)(struct sxe_hw *, u32, u32, bool, bool);
+	u32 (*pool_filter_read)(struct sxe_hw *hw, u16 reg_idx);
+	void (*pool_filter_write)(struct sxe_hw *hw, u16 reg_idx, u32 val);
+	u32 (*pool_filter_bitmap_read)(struct sxe_hw *hw, u16 reg_idx);
+	void (*pool_filter_bitmap_write)(struct sxe_hw *hw, u16 reg_idx, u32 val);
+	void (*filter_array_write)(struct sxe_hw *hw, u16 reg_idx, u32 val);
+	u32  (*filter_array_read)(struct sxe_hw *hw, u16 reg_idx);
+	void (*filter_array_clear)(struct sxe_hw *hw);
+	void (*filter_switch)(struct sxe_hw *hw, bool enable);
+	void (*untagged_pkts_rcv_switch)(struct sxe_hw *hw, u32 vf, bool accept);
+	s32  (*filter_configure)(struct sxe_hw *hw, u32 vid, u32 pool,
+								bool vlan_on, bool vlvf_bypass);
 };
 
 struct sxe_filter_vlan {
@@ -622,55 +626,63 @@  struct sxe_filter_info {
 };
 
 struct sxe_dbu_operations {
-	void (*rx_pkt_buf_size_configure)(struct sxe_hw *, u8, u32, u16);
-	void (*rx_pkt_buf_switch)(struct sxe_hw *, bool);
-	void (*rx_multi_ring_configure)(struct sxe_hw *, u8, bool, bool);
-	void (*rss_key_set_all)(struct sxe_hw *, u32 *);
-	void (*rss_redir_tbl_set_all)(struct sxe_hw *, u8 *);
-	void (*rx_cap_switch_on)(struct sxe_hw *);
-	void (*rss_hash_pkt_type_set)(struct sxe_hw *, u32);
-	void (*rss_hash_pkt_type_update)(struct sxe_hw *, u32);
-	void (*rss_rings_used_set)(struct sxe_hw *, u32, u16, u16);
-	void (*lro_ack_switch)(struct sxe_hw *, bool);
-	void (*vf_rx_switch)(struct sxe_hw *, u32, u32, bool);
-
-	s32  (*fnav_mode_init)(struct sxe_hw *, u32, u32);
-	s32  (*fnav_specific_rule_mask_set)(struct sxe_hw *,
-						union sxe_fnav_rule_info *);
-	s32  (*fnav_specific_rule_add)(struct sxe_hw *,
-						union sxe_fnav_rule_info *,
-						u16, u8);
-	s32  (*fnav_specific_rule_del)(struct sxe_hw *,
-					  union sxe_fnav_rule_info *, u16);
-	s32  (*fnav_sample_hash_cmd_get)(struct sxe_hw *,
-						u8, u32, u8, u64 *);
+	void (*rx_pkt_buf_size_configure)(struct sxe_hw *hw, u8 num_pb,
+			u32 headroom, u16 strategy);
+	void (*rx_pkt_buf_switch)(struct sxe_hw *hw, bool is_on);
+	void (*rx_multi_ring_configure)(struct sxe_hw *hw, u8 tcs,
+			bool is_4q, bool sriov_enable);
+	void (*rss_key_set_all)(struct sxe_hw *hw, u32 *rss_key);
+	void (*rss_redir_tbl_set_all)(struct sxe_hw *hw, u8 *redir_tbl);
+	void (*rx_cap_switch_on)(struct sxe_hw *hw);
+	void (*rss_hash_pkt_type_set)(struct sxe_hw *hw, u32 version);
+	void (*rss_hash_pkt_type_update)(struct sxe_hw *hw, u32 version);
+	void (*rss_rings_used_set)(struct sxe_hw *hw, u32 rss_num,
+			u16 pool, u16 pf_offset);
+	void (*lro_ack_switch)(struct sxe_hw *hw, bool is_on);
+	void (*vf_rx_switch)(struct sxe_hw *hw, u32 reg_offset,
+			u32 vf_index, bool is_off);
+
+	s32  (*fnav_mode_init)(struct sxe_hw *hw, u32 fnavctrl, u32 fnav_mode);
+	s32  (*fnav_specific_rule_mask_set)(struct sxe_hw *hw,
+						union sxe_fnav_rule_info *mask);
+	s32  (*fnav_specific_rule_add)(struct sxe_hw *hw,
+						union sxe_fnav_rule_info *input,
+						u16 soft_id, u8 queue);
+	s32  (*fnav_specific_rule_del)(struct sxe_hw *hw,
+					  union sxe_fnav_rule_info *input, u16 soft_id);
+	s32  (*fnav_sample_hash_cmd_get)(struct sxe_hw *hw,
+						u8 flow_type, u32 hash_value,
+						u8 queue, u64 *hash_cmd);
 	void (*fnav_sample_stats_reinit)(struct sxe_hw *hw);
 	void (*fnav_sample_hash_set)(struct sxe_hw *hw, u64 hash);
-	s32  (*fnav_single_sample_rule_del)(struct sxe_hw *,u32);
-
-	void (*ptp_init)(struct sxe_hw *);
-	void (*ptp_freq_adjust)(struct sxe_hw *, u32);
-	void (*ptp_systime_init)(struct sxe_hw *);
-	u64  (*ptp_systime_get)(struct sxe_hw *);
-	void (*ptp_tx_timestamp_get)(struct sxe_hw *, u32 *ts_sec, u32 *ts_ns);
-	void (*ptp_timestamp_mode_set)(struct sxe_hw *, bool, u32, u32);
-	void (*ptp_rx_timestamp_clear)(struct sxe_hw *);
-	u64  (*ptp_rx_timestamp_get)(struct sxe_hw *);
-	bool (*ptp_is_rx_timestamp_valid)(struct sxe_hw *);
-	void (*ptp_timestamp_enable)(struct sxe_hw *);
-
-	void (*tx_pkt_buf_switch)(struct sxe_hw *, bool);
+	s32  (*fnav_single_sample_rule_del)(struct sxe_hw *hw, u32 hash);
+
+	void (*ptp_init)(struct sxe_hw *hw);
+	void (*ptp_freq_adjust)(struct sxe_hw *hw, u32 adj_freq);
+	void (*ptp_systime_init)(struct sxe_hw *hw);
+	u64  (*ptp_systime_get)(struct sxe_hw *hw);
+	void (*ptp_tx_timestamp_get)(struct sxe_hw *hw, u32 *ts_sec, u32 *ts_ns);
+	void (*ptp_timestamp_mode_set)(struct sxe_hw *hw, bool is_l2,
+			u32 tsctl, u32 tses);
+	void (*ptp_rx_timestamp_clear)(struct sxe_hw *hw);
+	u64  (*ptp_rx_timestamp_get)(struct sxe_hw *hw);
+	bool (*ptp_is_rx_timestamp_valid)(struct sxe_hw *hw);
+	void (*ptp_timestamp_enable)(struct sxe_hw *hw);
+
+	void (*tx_pkt_buf_switch)(struct sxe_hw *hw, bool is_on);
 
 	void (*dcb_tc_rss_configure)(struct sxe_hw *hw, u16 rss_i);
 
-	void (*tx_pkt_buf_size_configure)(struct sxe_hw *, u8);
+	void (*tx_pkt_buf_size_configure)(struct sxe_hw *hw, u8 num_pb);
 
-	void (*rx_cap_switch_off)(struct sxe_hw *);
-	u32  (*rx_pkt_buf_size_get)(struct sxe_hw *, u8);
+	void (*rx_cap_switch_off)(struct sxe_hw *hw);
+	u32  (*rx_pkt_buf_size_get)(struct sxe_hw *hw, u8 pb);
 	void (*rx_func_switch_on)(struct sxe_hw *hw);
 
-	void (*tx_ring_disable)(struct sxe_hw *, u8, unsigned long);
-	void (*rx_ring_disable)(struct sxe_hw *, u8, unsigned long);
+	void (*tx_ring_disable)(struct sxe_hw *hw, u8 reg_idx,
+			unsigned long timeout);
+	void (*rx_ring_disable)(struct sxe_hw *hw, u8 reg_idx,
+			unsigned long timeout);
 
 	u32  (*tx_dbu_fc_status_get)(struct sxe_hw *hw);
 };
@@ -681,44 +693,50 @@  struct sxe_dbu_info {
 
 
 struct sxe_dma_operations {
-	void (*rx_dma_ctrl_init)(struct sxe_hw *, bool);
-	void (*rx_ring_disable)(struct sxe_hw *, u8);
-	void (*rx_ring_switch)(struct sxe_hw *, u8, bool);
-	void (*rx_ring_switch_not_polling)(struct sxe_hw *, u8, bool);
-	void (*rx_ring_desc_configure)(struct sxe_hw *, u32, u64, u8);
-	void (*rx_desc_thresh_set)(struct sxe_hw *, u8);
-	void (*rx_rcv_ctl_configure)(struct sxe_hw *, u8, u32, u32);
-	void (*rx_lro_ctl_configure)(struct sxe_hw *, u8, u32);
-	u32  (*rx_desc_ctrl_get)(struct sxe_hw *, u8);
-	void (*rx_dma_lro_ctl_set)(struct sxe_hw *);
-	void (*rx_drop_switch)(struct sxe_hw *, u8, bool);
+	void (*rx_dma_ctrl_init)(struct sxe_hw *hw);
+	void (*rx_ring_disable)(struct sxe_hw *hw, u8 ring_idx);
+	void (*rx_ring_switch)(struct sxe_hw *hw, u8 reg_idx, bool is_on);
+	void (*rx_ring_switch_not_polling)(struct sxe_hw *hw, u8 reg_idx,
+										bool is_on);
+	void (*rx_ring_desc_configure)(struct sxe_hw *hw, u32 desc_mem_len,
+			u64 desc_dma_addr, u8 reg_idx);
+	void (*rx_desc_thresh_set)(struct sxe_hw *hw, u8 reg_idx);
+	void (*rx_rcv_ctl_configure)(struct sxe_hw *hw, u8 reg_idx,
+			u32 header_buf_len, u32 pkg_buf_len);
+	void (*rx_lro_ctl_configure)(struct sxe_hw *hw, u8 reg_idx, u32 max_desc);
+	u32  (*rx_desc_ctrl_get)(struct sxe_hw *hw, u8 reg_idx);
+	void (*rx_dma_lro_ctl_set)(struct sxe_hw *hw);
+	void (*rx_drop_switch)(struct sxe_hw *hw, u8 idx, bool is_enable);
 	void (*rx_tph_update)(struct sxe_hw *hw, u8 ring_idx, u8 cpu);
 
-	void (*tx_enable)(struct sxe_hw *);
-	void (*tx_multi_ring_configure)(struct sxe_hw *, u8, u16, bool, u16);
-	void (*tx_ring_desc_configure)(struct sxe_hw *, u32, u64, u8);
-	void (*tx_desc_thresh_set)(struct sxe_hw *, u8, u32, u32, u32);
-	void (*tx_ring_switch)(struct sxe_hw *, u8, bool);
-	void (*tx_ring_switch_not_polling)(struct sxe_hw *, u8, bool);
-	void (*tx_pkt_buf_thresh_configure)(struct sxe_hw *, u8, bool);
-	u32  (*tx_desc_ctrl_get)(struct sxe_hw *, u8);
-	void (*tx_ring_info_get)(struct sxe_hw *, u8, u32 *, u32 *);
-	void (*tx_desc_wb_thresh_clear)(struct sxe_hw *, u8);
-
-	void (*vlan_tag_strip_switch)(struct sxe_hw *, u16, bool);
-	void (*tx_vlan_tag_set)(struct sxe_hw *, u16, u16, u32);
-	void (*tx_vlan_tag_clear)(struct sxe_hw *, u32);
+	void (*tx_enable)(struct sxe_hw *hw);
+	void (*tx_multi_ring_configure)(struct sxe_hw *hw, u8 tcs, u16 pool_mask,
+			bool sriov_enable, u16 max_txq);
+	void (*tx_ring_desc_configure)(struct sxe_hw *hw, u32 desc_mem_len,
+			u64 desc_dma_addr, u8 reg_idx);
+	void (*tx_desc_thresh_set)(struct sxe_hw *hw, u8 reg_idx, u32 wb_thresh,
+			u32 host_thresh, u32 prefech_thresh);
+	void (*tx_ring_switch)(struct sxe_hw *hw, u8 reg_idx, bool is_on);
+	void (*tx_ring_switch_not_polling)(struct sxe_hw *hw, u8 reg_idx, bool is_on);
+	void (*tx_pkt_buf_thresh_configure)(struct sxe_hw *hw, u8 num_pb, bool dcb_enable);
+	u32  (*tx_desc_ctrl_get)(struct sxe_hw *hw, u8 reg_idx);
+	void (*tx_ring_info_get)(struct sxe_hw *hw, u8 idx, u32 *head, u32 *tail);
+	void (*tx_desc_wb_thresh_clear)(struct sxe_hw *hw, u8 reg_idx);
+
+	void (*vlan_tag_strip_switch)(struct sxe_hw *hw, u16 reg_index, bool is_enable);
+	void (*tx_vlan_tag_set)(struct sxe_hw *hw, u16 vid, u16 qos, u32 vf);
+	void (*tx_vlan_tag_clear)(struct sxe_hw *hw, u32 vf);
 	void (*tx_tph_update)(struct sxe_hw *hw, u8 ring_idx, u8 cpu);
 
 	void (*tph_switch)(struct sxe_hw *hw, bool is_enable);
 
 	void  (*dcb_rx_bw_alloc_configure)(struct sxe_hw *hw,
-				      u16 *refill,
-				      u16 *max,
-				      u8 *bwg_id,
-				      u8 *prio_type,
-				      u8 *prio_tc,
-				      u8 max_priority);
+					  u16 *refill,
+					  u16 *max,
+					  u8 *bwg_id,
+					  u8 *prio_type,
+					  u8 *prio_tc,
+					  u8 max_priority);
 	void  (*dcb_tx_desc_bw_alloc_configure)(struct sxe_hw *hw,
 					   u16 *refill,
 					   u16 *max,
@@ -766,7 +784,8 @@  struct sxe_dma_info {
 struct sxe_sec_operations {
 	void (*ipsec_rx_ip_store)(struct sxe_hw *hw, __be32 *ip_addr, u8 ip_len, u8 ip_idx);
 	void (*ipsec_rx_spi_store)(struct sxe_hw *hw, __be32 spi, u8 ip_idx, u16 idx);
-	void (*ipsec_rx_key_store)(struct sxe_hw *hw, u32 *key,  u8 key_len, u32 salt, u32 mode, u16 idx);
+	void (*ipsec_rx_key_store)(struct sxe_hw *hw, u32 *key,  u8 key_len,
+			u32 salt, u32 mode, u16 idx);
 	void (*ipsec_tx_key_store)(struct sxe_hw *hw, u32 *key,  u8 key_len, u32 salt, u16 idx);
 	void (*ipsec_sec_data_stop)(struct sxe_hw *hw, bool is_linkup);
 	void (*ipsec_engine_start)(struct sxe_hw *hw, bool is_linkup);
@@ -780,12 +799,12 @@  struct sxe_sec_info {
 };
 
 struct sxe_stat_operations {
-	void (*stats_clear)(struct sxe_hw *);
-	void (*stats_get)(struct sxe_hw *, struct sxe_mac_stats *);
+	void (*stats_clear)(struct sxe_hw *hw);
+	void (*stats_get)(struct sxe_hw *hw, struct sxe_mac_stats *st);
 
 	u32 (*tx_packets_num_get)(struct sxe_hw *hw);
 	u32 (*unsecurity_packets_num_get)(struct sxe_hw *hw);
-	u32  (*mac_stats_dump)(struct sxe_hw *, u32 *, u32);
+	u32  (*mac_stats_dump)(struct sxe_hw *hw, u32 *regs_buff, u32 buf_size);
 	u32  (*tx_dbu_to_mac_stats)(struct sxe_hw *hw);
 };
 
@@ -807,20 +826,20 @@  struct sxe_mbx_operations {
 };
 
 struct sxe_mbx_stats {
-	u32 send_msgs; 
-	u32 rcv_msgs;  
+	u32 send_msgs;
+	u32 rcv_msgs;
 
-	u32 reqs;      
-	u32 acks;      
-	u32 rsts;      
+	u32 reqs;
+	u32 acks;
+	u32 rsts;
 };
 
 struct sxe_mbx_info {
-	const struct sxe_mbx_operations *ops; 
-	struct sxe_mbx_stats stats; 
-	u32 retry;    
-	u32 interval; 
-	u32 msg_len; 
+	const struct sxe_mbx_operations *ops;
+	struct sxe_mbx_stats stats;
+	u32 retry;
+	u32 interval;
+	u32 msg_len;
 };
 
 struct sxe_pcie_operations {
@@ -828,7 +847,7 @@  struct sxe_pcie_operations {
 };
 
 struct sxe_pcie_info {
-	const struct sxe_pcie_operations *ops; 
+	const struct sxe_pcie_operations *ops;
 };
 
 enum sxe_hw_state {
@@ -845,40 +864,41 @@  enum sxe_fc_mode {
 };
 
 struct sxe_fc_info {
-	u32 high_water[MAX_TRAFFIC_CLASS]; 
-	u32 low_water[MAX_TRAFFIC_CLASS]; 
-	u16 pause_time; 
-	bool strict_ieee; 
-	bool disable_fc_autoneg; 
-	u16 send_xon; 
-	enum sxe_fc_mode current_mode; 
-	enum sxe_fc_mode requested_mode; 
+	u32 high_water[MAX_TRAFFIC_CLASS];
+	u32 low_water[MAX_TRAFFIC_CLASS];
+	u16 pause_time;
+	bool strict_ieee;
+	bool disable_fc_autoneg;
+	u16 send_xon;
+	enum sxe_fc_mode current_mode;
+	enum sxe_fc_mode requested_mode;
 };
 
 struct sxe_fc_nego_mode {
-	u32 adv_sym; 
-	u32 adv_asm; 
-	u32 lp_sym;  
-	u32 lp_asm;  
+	u32 adv_sym;
+	u32 adv_asm;
+	u32 lp_sym;
+	u32 lp_asm;
 
 };
 
 struct sxe_hdc_operations {
-	s32 (*pf_lock_get)(struct sxe_hw *, u32);
-	void (*pf_lock_release)(struct sxe_hw *, u32);
-	bool (*is_fw_over_set)(struct sxe_hw *);
-	u32 (*fw_ack_header_rcv)(struct sxe_hw *);
-	void (*packet_send_done)(struct sxe_hw *);
-	void (*packet_header_send)(struct sxe_hw *, u32);
-	void (*packet_data_dword_send)(struct sxe_hw *, u16, u32);
-	u32  (*packet_data_dword_rcv)(struct sxe_hw *, u16);
-	u32 (*fw_status_get)(struct sxe_hw *);
-	void (*drv_status_set)(struct sxe_hw *, u32);
-	u32 (*irq_event_get)(struct sxe_hw *);
-	void (*irq_event_clear)(struct sxe_hw *, u32);
-	void (*fw_ov_clear)(struct sxe_hw *);
-	u32 (*channel_state_get)(struct sxe_hw *);
-	void (*resource_clean)(struct sxe_hw *);
+	s32 (*pf_lock_get)(struct sxe_hw *hw, u32 trylock);
+	void (*pf_lock_release)(struct sxe_hw *hw, u32 retry_cnt);
+	bool (*is_fw_over_set)(struct sxe_hw *hw);
+	u32 (*fw_ack_header_rcv)(struct sxe_hw *hw);
+	void (*packet_send_done)(struct sxe_hw *hw);
+	void (*packet_header_send)(struct sxe_hw *hw, u32 value);
+	void (*packet_data_dword_send)(struct sxe_hw *hw,
+									u16 dword_index, u32 value);
+	u32  (*packet_data_dword_rcv)(struct sxe_hw *hw, u16 dword_index);
+	u32 (*fw_status_get)(struct sxe_hw *hw);
+	void (*drv_status_set)(struct sxe_hw *hw, u32 value);
+	u32 (*irq_event_get)(struct sxe_hw *hw);
+	void (*irq_event_clear)(struct sxe_hw *hw, u32 event);
+	void (*fw_ov_clear)(struct sxe_hw *hw);
+	u32 (*channel_state_get)(struct sxe_hw *hw);
+	void (*resource_clean)(struct sxe_hw *hw);
 };
 
 struct sxe_hdc_info {
@@ -901,29 +921,29 @@  struct sxe_phy_reg_info {
 };
 
 struct sxe_hw {
-	u8 __iomem *reg_base_addr;            
+	u8 __iomem *reg_base_addr;
 
 	void *adapter;
 	void *priv;
-	unsigned long state;   
+	unsigned long state;
 	void (*fault_handle)(void *priv);
 	u32 (*reg_read)(const volatile void *reg);
 	void (*reg_write)(u32 value, volatile void *reg);
 
-	struct sxe_hw_setup  setup;           
-	struct sxe_irq_info  irq;             
-	struct sxe_mac_info  mac;             
-	struct sxe_filter_info filter;        
-	struct sxe_dbu_info  dbu;             
-	struct sxe_dma_info  dma;             
-	struct sxe_sec_info  sec;             
-	struct sxe_stat_info stat;            
+	struct sxe_hw_setup  setup;
+	struct sxe_irq_info  irq;
+	struct sxe_mac_info  mac;
+	struct sxe_filter_info filter;
+	struct sxe_dbu_info  dbu;
+	struct sxe_dma_info  dma;
+	struct sxe_sec_info  sec;
+	struct sxe_stat_info stat;
 	struct sxe_fc_info   fc;
 
-	struct sxe_mbx_info mbx;              
-	struct sxe_pcie_info pcie;            
-	struct sxe_hdc_info  hdc;             
-	struct sxe_phy_reg_info phy;          
+	struct sxe_mbx_info mbx;
+	struct sxe_pcie_info pcie;
+	struct sxe_hdc_info  hdc;
+	struct sxe_phy_reg_info phy;
 };
 
 u16 sxe_mac_reg_num_get(void);
@@ -951,7 +971,6 @@  static inline void sxe_hw_fault_handle_init(struct sxe_hw *hw,
 	hw->priv = priv;
 	hw->fault_handle = handle;
 
-	return;
 }
 
 static inline void sxe_hw_reg_handle_init(struct sxe_hw *hw,
@@ -961,10 +980,11 @@  static inline void sxe_hw_reg_handle_init(struct sxe_hw *hw,
 	hw->reg_read  = read;
 	hw->reg_write = write;
 
-	return;
 }
 
-#ifdef SXE_DPDK 
+#ifdef SXE_DPDK
+
+void sxe_hw_crc_strip_config(struct sxe_hw *hw, bool keep_crc);
 
 void sxe_hw_stats_seq_clean(struct sxe_hw *hw, struct sxe_mac_stats *stats);
 
@@ -1117,12 +1137,12 @@  void sxe_hw_rss_field_set(struct sxe_hw *hw, u32 rss_field);
 
 void sxe_hw_rss_redir_tbl_set_all(struct sxe_hw *hw, u8 *redir_tbl);
 
-u32 sxe_hw_rss_redir_tbl_get_by_idx(struct sxe_hw *hw, u16);
+u32 sxe_hw_rss_redir_tbl_get_by_idx(struct sxe_hw *hw, u16 reg_idx);
 
 void sxe_hw_rss_redir_tbl_set_by_idx(struct sxe_hw *hw,
 						u16 reg_idx, u32 value);
 
-void sxe_hw_rx_dma_ctrl_init(struct sxe_hw *hw, bool crc_strip_on);
+void sxe_hw_rx_dma_ctrl_init(struct sxe_hw *hw);
 
 void sxe_hw_mac_max_frame_set(struct sxe_hw *hw, u32 max_frame);
 
@@ -1291,12 +1311,12 @@  void sxe_hw_dcb_tc_stats_configure(struct sxe_hw *hw,
 					u8 tc_count, bool vmdq_active);
 
 void sxe_hw_dcb_rx_bw_alloc_configure(struct sxe_hw *hw,
-				      u16 *refill,
-				      u16 *max,
-				      u8 *bwg_id,
-				      u8 *prio_type,
-				      u8 *prio_tc,
-				      u8 max_priority);
+					  u16 *refill,
+					  u16 *max,
+					  u8 *bwg_id,
+					  u8 *prio_type,
+					  u8 *prio_tc,
+					  u8 max_priority);
 
 void sxe_hw_dcb_tx_desc_bw_alloc_configure(struct sxe_hw *hw,
 					   u16 *refill,
@@ -1411,12 +1431,12 @@  s32 sxe_hw_vlvf_slot_find(struct sxe_hw *hw, u32 vlan, bool vlvf_bypass);
 
 u32 sxe_hw_vlan_pool_filter_read(struct sxe_hw *hw, u16 reg_index);
 
-void sxe_hw_mirror_vlan_set(struct sxe_hw *hw, u8 idx,u32 lsb, u32 msb);
+void sxe_hw_mirror_vlan_set(struct sxe_hw *hw, u8 idx, u32 lsb, u32 msb);
 
-void sxe_hw_mirror_virtual_pool_set(struct sxe_hw *hw, u8 idx,u32 lsb, u32 msb);
+void sxe_hw_mirror_virtual_pool_set(struct sxe_hw *hw, u8 idx, u32 lsb, u32 msb);
 
 void sxe_hw_mirror_ctl_set(struct sxe_hw *hw, u8 rule_id,
-				    u8 mirror_type, u8 dst_pool, bool on);
+					u8 mirror_type, u8 dst_pool, bool on);
 
 void sxe_hw_mirror_rule_clear(struct sxe_hw *hw, u8 rule_id);
 
@@ -1470,7 +1490,7 @@  void sxe_hw_syn_filter_add(struct sxe_hw *hw, u16 queue, u8 priority);
 void sxe_hw_syn_filter_del(struct sxe_hw *hw);
 
 void sxe_hw_rss_key_set_all(struct sxe_hw *hw, u32 *rss_key);
-#endif 
+#endif
 
 void sxe_hw_fnav_enable(struct sxe_hw *hw, u32 fnavctrl);
 
@@ -1493,7 +1513,7 @@  void sxe_hw_rss_redir_tbl_reg_write(struct sxe_hw *hw,
 u32 sxe_hw_fnav_port_mask_get(__be16 src_port_mask, __be16 dst_port_mask);
 
 s32 sxe_hw_fnav_specific_rule_mask_set(struct sxe_hw *hw,
-				    union sxe_fnav_rule_info *input_mask);
+					union sxe_fnav_rule_info *input_mask);
 
 s32 sxe_hw_vlan_filter_configure(struct sxe_hw *hw,
 					u32 vid, u32 pool,
@@ -1501,5 +1521,5 @@  s32 sxe_hw_vlan_filter_configure(struct sxe_hw *hw,
 
 void sxe_hw_ptp_systime_init(struct sxe_hw *hw);
 
-#endif 
+#endif
 #endif
diff --git a/drivers/net/sxe/base/sxe_logs.h b/drivers/net/sxe/base/sxe_logs.h
index 510d7aae5c..81088c2fc8 100644
--- a/drivers/net/sxe/base/sxe_logs.h
+++ b/drivers/net/sxe/base/sxe_logs.h
@@ -11,9 +11,9 @@ 
 
 #include "sxe_types.h"
 
-#define LOG_FILE_NAME_LEN     256
-#define LOG_FILE_PATH         "/var/log/"
-#define LOG_FILE_PREFIX       "sxepmd.log"
+#define LOG_FILE_NAME_LEN	 256
+#define LOG_FILE_PATH		 "/var/log/"
+#define LOG_FILE_PREFIX	   "sxepmd.log"
 
 extern s32 sxe_log_init;
 extern s32 sxe_log_rx;
@@ -36,9 +36,9 @@  extern s32 sxe_log_hw;
 		gettimeofday(&tv, NULL); \
 		td = localtime(&tv.tv_sec); \
 		strftime(log_time, sizeof(log_time), "%Y-%m-%d-%H:%M:%S", td); \
-	} while(0)
+	} while (0)
 
-#define filename_printf(x) strrchr((x),'/')?strrchr((x),'/')+1:(x)
+#define filename_printf(x) (strrchr((x), '/')?strrchr((x), '/')+1:(x))
 
 #ifdef SXE_DPDK_DEBUG
 #define PMD_LOG_DEBUG(logtype, fmt, ...) \
@@ -50,7 +50,7 @@  extern s32 sxe_log_hw;
 			"DEBUG", log_time, pthread_self(), \
 			filename_printf(__FILE__), __LINE__, \
 			__func__, ##__VA_ARGS__); \
-	} while(0)
+	} while (0)
 
 #define PMD_LOG_INFO(logtype, fmt, ...) \
 	do { \
@@ -61,7 +61,7 @@  extern s32 sxe_log_hw;
 			"INFO", log_time, pthread_self(), \
 			filename_printf(__FILE__), __LINE__, \
 			__func__, ##__VA_ARGS__); \
-	} while(0)
+	} while (0)
 
 #define PMD_LOG_NOTICE(logtype, fmt, ...) \
 	do { \
@@ -72,7 +72,7 @@  extern s32 sxe_log_hw;
 			"NOTICE", log_time, pthread_self(), \
 			filename_printf(__FILE__), __LINE__, \
 			__func__, ##__VA_ARGS__); \
-	} while(0)
+	} while (0)
 
 #define PMD_LOG_WARN(logtype, fmt, ...) \
 	do { \
@@ -83,7 +83,7 @@  extern s32 sxe_log_hw;
 			"WARN", log_time, pthread_self(), \
 			filename_printf(__FILE__), __LINE__, \
 			__func__, ##__VA_ARGS__); \
-	} while(0)
+	} while (0)
 
 #define PMD_LOG_ERR(logtype, fmt, ...) \
 	do { \
@@ -94,7 +94,7 @@  extern s32 sxe_log_hw;
 			"ERR", log_time, pthread_self(), \
 			filename_printf(__FILE__), __LINE__, \
 			__func__, ##__VA_ARGS__); \
-	} while(0)
+	} while (0)
 
 #define PMD_LOG_CRIT(logtype, fmt, ...) \
 	do { \
@@ -105,7 +105,7 @@  extern s32 sxe_log_hw;
 			"CRIT", log_time, pthread_self(), \
 			filename_printf(__FILE__), __LINE__, \
 			__func__, ##__VA_ARGS__); \
-	} while(0)
+	} while (0)
 
 #define PMD_LOG_ALERT(logtype, fmt, ...) \
 	do { \
@@ -116,7 +116,7 @@  extern s32 sxe_log_hw;
 			"ALERT", log_time, pthread_self(), \
 			filename_printf(__FILE__), __LINE__, \
 			__func__, ##__VA_ARGS__); \
-	} while(0)
+	} while (0)
 
 #define PMD_LOG_EMERG(logtype, fmt, ...) \
 	do { \
@@ -127,56 +127,40 @@  extern s32 sxe_log_hw;
 			"EMERG", log_time, pthread_self(), \
 			filename_printf(__FILE__), __LINE__, \
 			__func__, ##__VA_ARGS__); \
-	} while(0)
+	} while (0)
 
 #else
 #define PMD_LOG_DEBUG(logtype, fmt, ...) \
-	do { \
 		rte_log(RTE_LOG_DEBUG, logtype, "%s(): " \
-			fmt "\n", __func__, ##__VA_ARGS__); \
-	} while(0)
+			fmt "\n", __func__, ##__VA_ARGS__)
 
 #define PMD_LOG_INFO(logtype, fmt, ...) \
-	do { \
 		rte_log(RTE_LOG_INFO, logtype, "%s(): " \
-			fmt "\n", __func__, ##__VA_ARGS__); \
-	} while(0)
+			fmt "\n", __func__, ##__VA_ARGS__)
 
 #define PMD_LOG_NOTICE(logtype, fmt, ...) \
-	do { \
 		rte_log(RTE_LOG_NOTICE, logtype, "%s(): " \
-			fmt "\n", __func__, ##__VA_ARGS__); \
-	} while(0)
+			fmt "\n", __func__, ##__VA_ARGS__)
 
 #define PMD_LOG_WARN(logtype, fmt, ...) \
-	do { \
 		rte_log(RTE_LOG_WARNING, logtype, "%s(): " \
-			fmt "\n", __func__, ##__VA_ARGS__); \
-	} while(0)
+			fmt "\n", __func__, ##__VA_ARGS__)
 
 #define PMD_LOG_ERR(logtype, fmt, ...) \
-	do { \
 		rte_log(RTE_LOG_ERR, logtype, "%s(): " \
-			fmt "\n", __func__, ##__VA_ARGS__); \
-	} while(0)
+			fmt "\n", __func__, ##__VA_ARGS__)
 
 #define PMD_LOG_CRIT(logtype, fmt, ...) \
-	do { \
 		rte_log(RTE_LOG_CRIT, logtype, "%s(): " \
-			fmt "\n", __func__, ##__VA_ARGS__); \
-	} while(0)
+			fmt "\n", __func__, ##__VA_ARGS__)
 
 #define PMD_LOG_ALERT(logtype, fmt, ...) \
-	do { \
 		rte_log(RTE_LOG_ALERT, logtype, "%s(): " \
-			fmt "\n", __func__, ##__VA_ARGS__); \
-	} while(0)
+			fmt "\n", __func__, ##__VA_ARGS__)
 
 #define PMD_LOG_EMERG(logtype, fmt, ...) \
-	do { \
 		rte_log(RTE_LOG_EMERG, logtype, "%s(): " \
-			fmt "\n", __func__, ##__VA_ARGS__); \
-	} while(0)
+			fmt "\n", __func__, ##__VA_ARGS__)
 
 #endif
 
@@ -184,54 +168,38 @@  extern s32 sxe_log_hw;
 
 #ifdef SXE_DPDK_DEBUG
 #define LOG_DEBUG(fmt, ...) \
-	do { \
-		PMD_LOG_DEBUG(DRV, fmt, ##__VA_ARGS__); \
-	   } while(0)
+		PMD_LOG_DEBUG(DRV, fmt, ##__VA_ARGS__)
 
 #define LOG_INFO(fmt, ...) \
-	do { \
-		PMD_LOG_INFO(DRV, fmt, ##__VA_ARGS__); \
-	   } while(0)
+		PMD_LOG_INFO(DRV, fmt, ##__VA_ARGS__)
 
 #define LOG_WARN(fmt, ...) \
-	do { \
-		PMD_LOG_WARN(DRV, fmt, ##__VA_ARGS__); \
-	   } while(0)
+		PMD_LOG_WARN(DRV, fmt, ##__VA_ARGS__)
 
 #define LOG_ERROR(fmt, ...) \
-	do { \
-		PMD_LOG_ERR(DRV, fmt, ##__VA_ARGS__); \
-	   } while(0)
+		PMD_LOG_ERR(DRV, fmt, ##__VA_ARGS__)
 
 #define LOG_DEBUG_BDF(fmt, ...) \
-	do { \
-		PMD_LOG_DEBUG(HW, "[%s]" fmt, adapter->name, ##__VA_ARGS__); \
-	   } while(0)
+		PMD_LOG_DEBUG(HW, "[%s]" fmt, adapter->name, ##__VA_ARGS__)
 
 #define LOG_INFO_BDF(fmt, ...) \
-	do { \
-		PMD_LOG_INFO(HW, "[%s]" fmt, adapter->name, ##__VA_ARGS__); \
-	   } while(0)
+		PMD_LOG_INFO(HW, "[%s]" fmt, adapter->name, ##__VA_ARGS__)
 
 #define LOG_WARN_BDF(fmt, ...) \
-	do { \
-		PMD_LOG_WARN(HW, "[%s]" fmt, adapter->name, ##__VA_ARGS__); \
-	   } while(0)
+		PMD_LOG_WARN(HW, "[%s]" fmt, adapter->name, ##__VA_ARGS__)
 
 #define LOG_ERROR_BDF(fmt, ...) \
-	do { \
-		PMD_LOG_ERR(HW, "[%s]" fmt, adapter->name, ##__VA_ARGS__); \
-	   } while(0)
+		PMD_LOG_ERR(HW, "[%s]" fmt, adapter->name, ##__VA_ARGS__)
 
 #else
 #define LOG_DEBUG(fmt, ...)
 #define LOG_INFO(fmt, ...)
 #define LOG_WARN(fmt, ...)
 #define LOG_ERROR(fmt, ...)
-#define LOG_DEBUG_BDF(fmt, ...) do { UNUSED(adapter); } while(0)
-#define LOG_INFO_BDF(fmt, ...)  do { UNUSED(adapter); } while(0)
-#define LOG_WARN_BDF(fmt, ...)  do { UNUSED(adapter); } while(0)
-#define LOG_ERROR_BDF(fmt, ...) do { UNUSED(adapter); } while(0)
+#define LOG_DEBUG_BDF(fmt, ...) UNUSED(adapter)
+#define LOG_INFO_BDF(fmt, ...) UNUSED(adapter)
+#define LOG_WARN_BDF(fmt, ...) UNUSED(adapter)
+#define LOG_ERROR_BDF(fmt, ...) UNUSED(adapter)
 #endif
 
 #ifdef SXE_DPDK_DEBUG
@@ -239,61 +207,61 @@  extern s32 sxe_log_hw;
 	do { \
 		UNUSED(adapter); \
 		LOG_DEBUG_BDF(fmt, ##__VA_ARGS__); \
-	} while(0)
+	} while (0)
 
 #define LOG_DEV_INFO(fmt, ...) \
 	do { \
 		UNUSED(adapter); \
 		LOG_INFO_BDF(fmt, ##__VA_ARGS__); \
-	} while(0)
+	} while (0)
 
 #define LOG_DEV_WARN(fmt, ...) \
 	do { \
 		UNUSED(adapter); \
 		LOG_WARN_BDF(fmt, ##__VA_ARGS__); \
-	} while(0)
+	} while (0)
 
 #define LOG_DEV_ERR(fmt, ...) \
 	do { \
 		UNUSED(adapter); \
 		LOG_ERROR_BDF(fmt, ##__VA_ARGS__); \
-	} while(0)
+	} while (0)
 
 #define LOG_MSG_DEBUG(msglvl, fmt, ...) \
 	do { \
 		UNUSED(adapter); \
 		LOG_DEBUG_BDF(fmt, ##__VA_ARGS__); \
-	} while(0)
+	} while (0)
 
 #define LOG_MSG_INFO(msglvl, fmt, ...) \
 	do { \
 		UNUSED(adapter); \
 		LOG_INFO_BDF(fmt, ##__VA_ARGS__); \
-	} while(0)
+	} while (0)
 
 #define LOG_MSG_WARN(msglvl, fmt, ...) \
 	do { \
 		UNUSED(adapter); \
 		LOG_WARN_BDF(fmt, ##__VA_ARGS__); \
-	} while(0)
+	} while (0)
 
 #define LOG_MSG_ERR(msglvl, fmt, ...) \
 	do { \
 		UNUSED(adapter); \
 		LOG_ERROR_BDF(fmt, ##__VA_ARGS__); \
-	} while(0)
+	} while (0)
 
 #else
-#define LOG_DEV_DEBUG(fmt, ...) do { UNUSED(adapter); } while(0)
-#define LOG_DEV_INFO(fmt, ...)  do { UNUSED(adapter); } while(0)
-#define LOG_DEV_WARN(fmt, ...)  do { UNUSED(adapter); } while(0)
-#define LOG_DEV_ERR(fmt, ...)   do { UNUSED(adapter); } while(0)
-#define LOG_MSG_DEBUG(msglvl, fmt, ...) do { UNUSED(adapter); } while(0)
-#define LOG_MSG_INFO(msglvl, fmt, ...)  do { UNUSED(adapter); } while(0)
-#define LOG_MSG_WARN(msglvl, fmt, ...)  do { UNUSED(adapter); } while(0)
-#define LOG_MSG_ERR(msglvl, fmt, ...)   do { UNUSED(adapter); } while(0)
+#define LOG_DEV_DEBUG(fmt, ...) UNUSED(adapter)
+#define LOG_DEV_INFO(fmt, ...) UNUSED(adapter)
+#define LOG_DEV_WARN(fmt, ...) UNUSED(adapter)
+#define LOG_DEV_ERR(fmt, ...) UNUSED(adapter)
+#define LOG_MSG_DEBUG(msglvl, fmt, ...) UNUSED(adapter)
+#define LOG_MSG_INFO(msglvl, fmt, ...) UNUSED(adapter)
+#define LOG_MSG_WARN(msglvl, fmt, ...) UNUSED(adapter)
+#define LOG_MSG_ERR(msglvl, fmt, ...) UNUSED(adapter)
 #endif
 
 void sxe_log_stream_init(void);
 
-#endif 
+#endif
diff --git a/drivers/net/sxe/base/sxe_offload_common.c b/drivers/net/sxe/base/sxe_offload_common.c
index a7075b4669..b8d7597b84 100644
--- a/drivers/net/sxe/base/sxe_offload_common.c
+++ b/drivers/net/sxe/base/sxe_offload_common.c
@@ -30,18 +30,17 @@  u64 __sxe_rx_port_offload_capa_get(struct rte_eth_dev *dev)
 	rx_offload_capa = RTE_ETH_RX_OFFLOAD_IPV4_CKSUM  |
 		   RTE_ETH_RX_OFFLOAD_UDP_CKSUM   |
 		   RTE_ETH_RX_OFFLOAD_TCP_CKSUM   |
-		   RTE_ETH_RX_OFFLOAD_KEEP_CRC    |
+		   RTE_ETH_RX_OFFLOAD_KEEP_CRC	|
 #ifdef DEV_RX_JUMBO_FRAME
 		   DEV_RX_OFFLOAD_JUMBO_FRAME |
 #endif
 		   RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
-		   RTE_ETH_RX_OFFLOAD_VLAN_EXTEND | 
+		   RTE_ETH_RX_OFFLOAD_VLAN_EXTEND |
 		   RTE_ETH_RX_OFFLOAD_SCATTER |
 		   RTE_ETH_RX_OFFLOAD_RSS_HASH;
 
-	if (!RTE_ETH_DEV_SRIOV(dev).active) {
+	if (!RTE_ETH_DEV_SRIOV(dev).active)
 		rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TCP_LRO;
-	}
 
 	return rx_offload_capa;
 }
@@ -57,7 +56,7 @@  u64 __sxe_tx_port_offload_capa_get(struct rte_eth_dev *dev)
 		RTE_ETH_TX_OFFLOAD_UDP_CKSUM   |
 		RTE_ETH_TX_OFFLOAD_TCP_CKSUM   |
 		RTE_ETH_TX_OFFLOAD_SCTP_CKSUM  |
-		RTE_ETH_TX_OFFLOAD_TCP_TSO     |
+		RTE_ETH_TX_OFFLOAD_TCP_TSO	 |
 		RTE_ETH_TX_OFFLOAD_MULTI_SEGS  |
 		RTE_ETH_TX_OFFLOAD_MACSEC_INSERT;
 
diff --git a/drivers/net/sxe/base/sxe_queue_common.c b/drivers/net/sxe/base/sxe_queue_common.c
index eda73c3f79..6f6ba98dbe 100644
--- a/drivers/net/sxe/base/sxe_queue_common.c
+++ b/drivers/net/sxe/base/sxe_queue_common.c
@@ -46,7 +46,6 @@  static void sxe_tx_queues_clear(struct rte_eth_dev *dev)
 		}
 	}
 
-	return;
 }
 
 static void sxe_rx_queues_clear(struct rte_eth_dev *dev, bool rx_batch_alloc_allowed)
@@ -62,7 +61,6 @@  static void sxe_rx_queues_clear(struct rte_eth_dev *dev, bool rx_batch_alloc_all
 		}
 	}
 
-	return;
 }
 
 s32 __rte_cold __sxe_rx_queue_setup(struct rx_setup *rx_setup, bool is_vf)
@@ -90,7 +88,7 @@  s32 __rte_cold __sxe_rx_queue_setup(struct rx_setup *rx_setup, bool is_vf)
 	if (desc_num % SXE_RX_DESC_RING_ALIGN != 0 ||
 			(desc_num > SXE_MAX_RING_DESC) ||
 			(desc_num < SXE_MIN_RING_DESC)) {
-		PMD_LOG_ERR(INIT, "desc_num %u error",desc_num);
+		PMD_LOG_ERR(INIT, "desc_num %u error", desc_num);
 		ret = -EINVAL;
 		goto l_end;
 	}
@@ -115,11 +113,10 @@  s32 __rte_cold __sxe_rx_queue_setup(struct rx_setup *rx_setup, bool is_vf)
 	rxq->reg_idx = (u16)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
 		queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
 	rxq->port_id = dev->data->port_id;
-	if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) {
+	if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
 		rxq->crc_len = RTE_ETHER_CRC_LEN;
-	} else {
+	else
 		rxq->crc_len = 0;
-	}
 
 	rxq->drop_en = rx_conf->rx_drop_en;
 	rxq->deferred_start = rx_conf->rx_deferred_start;
@@ -140,13 +137,12 @@  s32 __rte_cold __sxe_rx_queue_setup(struct rx_setup *rx_setup, bool is_vf)
 
 	memset(rx_mz->addr, 0, SXE_RX_RING_SIZE);
 
-	if (is_vf) {
+	if (is_vf)
 		rxq->rdt_reg_addr = (volatile u32 *)(rx_setup->reg_base_addr +
 			SXE_VFRDT(rxq->reg_idx));
-	} else {
+	else
 		rxq->rdt_reg_addr = (volatile u32 *)(rx_setup->reg_base_addr +
 			SXE_RDT(rxq->reg_idx));
-	}
 
 	rxq->base_addr = rx_mz->iova;
 
@@ -160,9 +156,8 @@  s32 __rte_cold __sxe_rx_queue_setup(struct rx_setup *rx_setup, bool is_vf)
 	}
 
 	len = desc_num;
-	if (*rx_setup->rx_batch_alloc_allowed) {
+	if (*rx_setup->rx_batch_alloc_allowed)
 		len += RTE_PMD_SXE_MAX_RX_BURST;
-	}
 
 	rxq->buffer_ring = rte_zmalloc_socket("rxq->sw_ring",
 					  sizeof(struct sxe_rx_buffer) * len,
@@ -186,21 +181,21 @@  s32 __rte_cold __sxe_rx_queue_setup(struct rx_setup *rx_setup, bool is_vf)
 	}
 
 	PMD_LOG_DEBUG(INIT, "buffer_ring=%p sc_buffer_ring=%p desc_ring=%p "
-			    "dma_addr=0x%"SXE_PRIX64,
-		     rxq->buffer_ring, rxq->sc_buffer_ring, rxq->desc_ring,
-		     rxq->base_addr);
+				"dma_addr=0x%"SXE_PRIX64,
+			 rxq->buffer_ring, rxq->sc_buffer_ring, rxq->desc_ring,
+			 rxq->base_addr);
 
 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD
 	if (!rte_is_power_of_2(desc_num)) {
 		PMD_LOG_DEBUG(INIT, "queue[%d] doesn't meet Vector Rx "
-				    "preconditions - canceling the feature for "
-				    "the whole port[%d]",
-			     rxq->queue_id, rxq->port_id);
-		if (is_vf) {
+					"preconditions - canceling the feature for "
+					"the whole port[%d]",
+				 rxq->queue_id, rxq->port_id);
+		if (is_vf)
 			vf_adapter->rx_vec_allowed = false;
-		} else {
+		else
 			pf_adapter->rx_vec_allowed = false;
-		}
+
 	} else {
 		sxe_rxq_vec_setup(rxq);
 	}
@@ -245,29 +240,29 @@  int __rte_cold __sxe_tx_queue_setup(struct tx_setup *tx_setup, bool is_vf)
 		goto l_end;
 	}
 
-	txq->ops               = sxe_tx_default_ops_get();
-	txq->ring_depth        = ring_depth;
-	txq->queue_idx         = tx_queue_id;
-	txq->port_id           = dev->data->port_id;
-	txq->pthresh           = tx_conf->tx_thresh.pthresh;
-	txq->hthresh           = tx_conf->tx_thresh.hthresh;
-	txq->wthresh           = tx_conf->tx_thresh.wthresh;
-	txq->rs_thresh         = rs_thresh;
-	txq->free_thresh       = free_thresh;
+	txq->ops			   = sxe_tx_default_ops_get();
+	txq->ring_depth		= ring_depth;
+	txq->queue_idx		 = tx_queue_id;
+	txq->port_id		   = dev->data->port_id;
+	txq->pthresh		   = tx_conf->tx_thresh.pthresh;
+	txq->hthresh		   = tx_conf->tx_thresh.hthresh;
+	txq->wthresh		   = tx_conf->tx_thresh.wthresh;
+	txq->rs_thresh		 = rs_thresh;
+	txq->free_thresh	   = free_thresh;
 	txq->tx_deferred_start = tx_conf->tx_deferred_start;
-	txq->reg_idx           = (u16)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
+	txq->reg_idx		   = (u16)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
 		tx_queue_id : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + tx_queue_id);
-	txq->offloads          = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
+	txq->offloads		  = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 
-	if (is_vf) {
-		txq->tdt_reg_addr = (volatile u32 *)(tx_setup->reg_base_addr + SXE_VFTDT(txq->reg_idx));
-	} else {
-		txq->tdt_reg_addr = (u32 *)(tx_setup->reg_base_addr + SXE_TDT(txq->reg_idx));
-	}
+	if (is_vf)
+		txq->tdt_reg_addr = (volatile u32 *)(tx_setup->reg_base_addr +
+								SXE_VFTDT(txq->reg_idx));
+	else
+		txq->tdt_reg_addr = (u32 *)(tx_setup->reg_base_addr +
+								SXE_TDT(txq->reg_idx));
 
 	PMD_LOG_INFO(INIT, "buffer_ring=%p desc_ring=%p dma_addr=0x%"PRIx64,
-		     txq->buffer_ring, txq->desc_ring,
-		     (long unsigned int)txq->base_addr);
+			 txq->buffer_ring, txq->desc_ring, (u64)txq->base_addr);
 	sxe_tx_function_set(dev, txq);
 
 	txq->ops->init(txq);
@@ -294,7 +289,6 @@  void __sxe_rx_queue_info_get(struct rte_eth_dev *dev, u16 queue_id,
 	qinfo->conf.rx_deferred_start = rxq->deferred_start;
 	qinfo->conf.offloads = rxq->offloads;
 
-	return;
 }
 
 void __sxe_tx_queue_info_get(struct rte_eth_dev *dev, u16 queue_id,
@@ -313,23 +307,22 @@  void __sxe_tx_queue_info_get(struct rte_eth_dev *dev, u16 queue_id,
 	q_info->conf.offloads = txq->offloads;
 	q_info->conf.tx_deferred_start = txq->tx_deferred_start;
 
-	return;
 }
 
 s32 __sxe_tx_done_cleanup(void *tx_queue, u32 free_cnt)
 {
 	int ret;
 	struct sxe_tx_queue *txq = (struct sxe_tx_queue *)tx_queue;
-	if (txq->offloads == 0 && \
+	if (txq->offloads == 0 &&
 		txq->rs_thresh >= RTE_PMD_SXE_MAX_TX_BURST) {
 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD
 		if (txq->rs_thresh <= RTE_SXE_MAX_TX_FREE_BUF_SZ &&
 #ifndef DPDK_19_11_6
-		    rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128 &&
+			rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128 &&
 #endif
-		    (rte_eal_process_type() != RTE_PROC_PRIMARY ||
-		    txq->buffer_ring_vec != NULL)) {
-		    ret = sxe_tx_done_cleanup_vec(txq, free_cnt);
+			(rte_eal_process_type() != RTE_PROC_PRIMARY ||
+			txq->buffer_ring_vec != NULL)) {
+			ret = sxe_tx_done_cleanup_vec(txq, free_cnt);
 		} else{
 			ret = sxe_tx_done_cleanup_simple(txq, free_cnt);
 		}
@@ -357,7 +350,7 @@  s32 __rte_cold __sxe_rx_queue_mbufs_alloc(struct sxe_rx_queue *rxq)
 
 		if (mbuf == NULL) {
 			PMD_LOG_ERR(DRV, "rx mbuf alloc failed queue_id=%u",
-					(unsigned) rxq->queue_id);
+					(u16)rxq->queue_id);
 			ret = -ENOMEM;
 			goto l_end;
 		}
@@ -386,7 +379,6 @@  void __rte_cold __sxe_rx_queue_free(struct sxe_rx_queue *rxq)
 		rte_memzone_free(rxq->mz);
 		rte_free(rxq);
 	}
-	return;
 }
 
 void __rte_cold __sxe_tx_queue_free(struct sxe_tx_queue *txq)
@@ -398,7 +390,6 @@  void __rte_cold __sxe_tx_queue_free(struct sxe_tx_queue *txq)
 		rte_free(txq);
 	}
 
-	return;
 }
 
 void __rte_cold __sxe_txrx_queues_clear(struct rte_eth_dev *dev, bool rx_batch_alloc_allowed)
@@ -409,12 +400,11 @@  void __rte_cold __sxe_txrx_queues_clear(struct rte_eth_dev *dev, bool rx_batch_a
 
 	sxe_rx_queues_clear(dev, rx_batch_alloc_allowed);
 
-	return;
 }
 
 void __sxe_queues_free(struct rte_eth_dev *dev)
 {
-	unsigned i;
+	unsigned int i;
 
 	PMD_INIT_FUNC_TRACE();
 
@@ -430,10 +420,10 @@  void __sxe_queues_free(struct rte_eth_dev *dev)
 	}
 	dev->data->nb_tx_queues = 0;
 
-	return;
 }
 
-void __sxe_secondary_proc_init(struct rte_eth_dev *eth_dev, bool rx_batch_alloc_allowed, bool *rx_vec_allowed)
+void __sxe_secondary_proc_init(struct rte_eth_dev *eth_dev,
+	bool rx_batch_alloc_allowed, bool *rx_vec_allowed)
 {
 	struct sxe_tx_queue *txq;
 	if (eth_dev->data->tx_queues) {
@@ -441,10 +431,9 @@  void __sxe_secondary_proc_init(struct rte_eth_dev *eth_dev, bool rx_batch_alloc_
 		sxe_tx_function_set(eth_dev, txq);
 	} else {
 		PMD_LOG_NOTICE(INIT, "No TX queues configured yet. "
-			     "Using default TX function.");
+				 "Using default TX function.");
 	}
 
 	sxe_rx_function_set(eth_dev, rx_batch_alloc_allowed, rx_vec_allowed);
-	return;
 }
 
diff --git a/drivers/net/sxe/base/sxe_queue_common.h b/drivers/net/sxe/base/sxe_queue_common.h
index a38113b643..40867449db 100644
--- a/drivers/net/sxe/base/sxe_queue_common.h
+++ b/drivers/net/sxe/base/sxe_queue_common.h
@@ -15,9 +15,9 @@ 
 #define RTE_PMD_SXE_MAX_RX_BURST 32
 
 enum sxe_ctxt_num {
-	SXE_CTXT_DESC_0    = 0, 
-	SXE_CTXT_DESC_1    = 1, 
-	SXE_CTXT_DESC_NUM  = 2, 
+	SXE_CTXT_DESC_0	= 0,
+	SXE_CTXT_DESC_1	= 1,
+	SXE_CTXT_DESC_NUM  = 2,
 };
 
 struct rx_setup {
@@ -42,7 +42,7 @@  struct tx_setup {
 
 union sxe_tx_data_desc {
 	struct {
-		__le64 buffer_addr; 
+		__le64 buffer_addr;
 		__le32 cmd_type_len;
 		__le32 olinfo_status;
 	} read;
@@ -63,142 +63,142 @@  struct sxe_rx_queue_stats {
 
 union sxe_rx_data_desc {
 	struct {
-		__le64 pkt_addr; 
-		__le64 hdr_addr; 
+		__le64 pkt_addr;
+		__le64 hdr_addr;
 	} read;
 	struct {
 		struct {
 			union {
 				__le32 data;
 				struct {
-					__le16 pkt_info; 
-					__le16 hdr_info; 
+					__le16 pkt_info;
+					__le16 hdr_info;
 				} hs_rss;
 			} lo_dword;
 			union {
-				__le32 rss; 
+				__le32 rss;
 				struct {
-					__le16 ip_id; 
-					__le16 csum; 
+					__le16 ip_id;
+					__le16 csum;
 				} csum_ip;
 			} hi_dword;
 		} lower;
 		struct {
-			__le32 status_error; 
-			__le16 length; 
-			__le16 vlan; 
+			__le32 status_error;
+			__le16 length;
+			__le16 vlan;
 		} upper;
 	} wb;
- };
+};
 
 struct sxe_tx_buffer {
-	struct rte_mbuf *mbuf; 
-	u16 next_id;             
-	u16 last_id;             
+	struct rte_mbuf *mbuf;
+	u16 next_id;
+	u16 last_id;
 };
 
 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD
 struct sxe_tx_buffer_vec {
-	struct rte_mbuf *mbuf; 
+	struct rte_mbuf *mbuf;
 };
 #endif
 
 union sxe_tx_offload {
 	u64 data[2];
 	struct {
-		u64 l2_len:7;     
-		u64 l3_len:9;     
-		u64 l4_len:8;     
-		u64 tso_segsz:16; 
-		u64 vlan_tci:16;  
-
-		u64 outer_l3_len:8; 
-		u64 outer_l2_len:8; 
+		u64 l2_len:7;
+		u64 l3_len:9;
+		u64 l4_len:8;
+		u64 tso_segsz:16;
+		u64 vlan_tci:16;
+
+		u64 outer_l3_len:8;
+		u64 outer_l2_len:8;
 	};
 };
 
 struct sxe_ctxt_info {
-	u64 flags;  
+	u64 flags;
 	union sxe_tx_offload tx_offload;
 	union sxe_tx_offload tx_offload_mask;
 };
 
 struct sxe_tx_queue {
 	volatile union sxe_tx_data_desc *desc_ring;
-	u64             base_addr;          
+	u64			 base_addr;
 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD
 	union {
-		struct sxe_tx_buffer *buffer_ring;          
-		struct sxe_tx_buffer_vec *buffer_ring_vec;  
+		struct sxe_tx_buffer *buffer_ring;
+		struct sxe_tx_buffer_vec *buffer_ring_vec;
 	};
 #else
-	struct sxe_tx_buffer *buffer_ring;	
+	struct sxe_tx_buffer *buffer_ring;
 #endif
-	volatile u32   *tdt_reg_addr;       
-	u16            ring_depth;          
-	u16            next_to_use;         
-	u16            free_thresh;         
-
-	u16            rs_thresh;
-
-	u16            desc_used_num;
-	u16            next_to_clean;  
-	u16            desc_free_num;   
-	u16            next_dd;        
-	u16            next_rs;        
-	u16            queue_idx;      
-	u16            reg_idx;        
-	u16            port_id;        
-	u8             pthresh;        
-	u8             hthresh;        
-
-	u8             wthresh;
-	u64            offloads;       
-	u32            ctx_curr;       
-	struct sxe_ctxt_info ctx_cache[SXE_CTXT_DESC_NUM]; 
-	const struct sxe_txq_ops *ops; 
-	u8     tx_deferred_start;      
+	volatile u32   *tdt_reg_addr;
+	u16			ring_depth;
+	u16			next_to_use;
+	u16			free_thresh;
+
+	u16			rs_thresh;
+
+	u16			desc_used_num;
+	u16			next_to_clean;
+	u16			desc_free_num;
+	u16			next_dd;
+	u16			next_rs;
+	u16			queue_idx;
+	u16			reg_idx;
+	u16			port_id;
+	u8			 pthresh;
+	u8			 hthresh;
+
+	u8			 wthresh;
+	u64			offloads;
+	u32			ctx_curr;
+	struct sxe_ctxt_info ctx_cache[SXE_CTXT_DESC_NUM];
+	const struct sxe_txq_ops *ops;
+	u8	 tx_deferred_start;
 	const struct rte_memzone *mz;
 };
 
 struct sxe_rx_queue {
-	struct rte_mempool  *mb_pool;   
-	volatile union sxe_rx_data_desc *desc_ring; 
-	u64  base_addr;                 
-	volatile u32   *rdt_reg_addr;   
-	struct sxe_rx_buffer *buffer_ring; 
-	struct sxe_rx_buffer *sc_buffer_ring; 
+	struct rte_mempool  *mb_pool;
+	volatile union sxe_rx_data_desc *desc_ring;
+	u64  base_addr;
+	volatile u32   *rdt_reg_addr;
+	struct sxe_rx_buffer *buffer_ring;
+	struct sxe_rx_buffer *sc_buffer_ring;
 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD
-	struct rte_mbuf *pkt_first_seg; 
-	struct rte_mbuf *pkt_last_seg;  
-	u64    mbuf_init_value;		
-	u8     is_using_sse;		
+	struct rte_mbuf *pkt_first_seg;
+	struct rte_mbuf *pkt_last_seg;
+	u64	mbuf_init_value;
+	u8	 is_using_sse;
 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM)
-	u16    realloc_num; 		
-	u16    realloc_start;		
+	u16	realloc_num;
+	u16	realloc_start;
 #endif
 #endif
-	u16    ring_depth;           
-	u16    processing_idx;     
-	u16    hold_num;            
-	u16    completed_pkts_num;     
-	u16    next_ret_pkg;         
-	u16    batch_alloc_trigger;  
-
-	u16    batch_alloc_size;
-	u16    queue_id;            
-	u16    reg_idx;              
-	u16    pkt_type_mask;        
-	u16    port_id;              
-	u8     crc_len;              
-	u8     drop_en;              
-	u8     deferred_start;       
-	u64    vlan_flags;           
-	u64    offloads;             
-	struct rte_mbuf fake_mbuf;   
+	u16	ring_depth;
+	u16	processing_idx;
+	u16	hold_num;
+	u16	completed_pkts_num;
+	u16	next_ret_pkg;
+	u16	batch_alloc_trigger;
+
+	u16	batch_alloc_size;
+	u16	queue_id;
+	u16	reg_idx;
+	u16	pkt_type_mask;
+	u16	port_id;
+	u8	 crc_len;
+	u8	 drop_en;
+	u8	 deferred_start;
+	u64	vlan_flags;
+	u64	offloads;
+	struct rte_mbuf fake_mbuf;
 	struct rte_mbuf *completed_ring[RTE_PMD_SXE_MAX_RX_BURST * 2];
 	const struct rte_memzone *mz;
-	struct sxe_rx_queue_stats rx_stats;  
+	struct sxe_rx_queue_stats rx_stats;
 };
 
 struct sxe_txq_ops {
@@ -231,6 +231,7 @@  void __rte_cold __sxe_txrx_queues_clear(struct rte_eth_dev *dev, bool rx_batch_a
 
 void __sxe_queues_free(struct rte_eth_dev *dev);
 
-void __sxe_secondary_proc_init(struct rte_eth_dev *eth_dev, bool rx_batch_alloc_allowed, bool *rx_vec_allowed);
+void __sxe_secondary_proc_init(struct rte_eth_dev *eth_dev,
+	bool rx_batch_alloc_allowed, bool *rx_vec_allowed);
 
 #endif
diff --git a/drivers/net/sxe/base/sxe_rx_common.c b/drivers/net/sxe/base/sxe_rx_common.c
index 4472058a29..b6ca690ec8 100644
--- a/drivers/net/sxe/base/sxe_rx_common.c
+++ b/drivers/net/sxe/base/sxe_rx_common.c
@@ -39,23 +39,23 @@  static inline void sxe_rx_resource_prefetch(u16 next_idx,
 		rte_sxe_prefetch(&buf_ring[next_idx]);
 	}
 
-	return;
 }
 
-void __rte_cold __sxe_rx_function_set(struct rte_eth_dev *dev, bool rx_batch_alloc_allowed, bool *rx_vec_allowed)
+void __rte_cold __sxe_rx_function_set(struct rte_eth_dev *dev,
+	bool rx_batch_alloc_allowed, bool *rx_vec_allowed)
 {
 
 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD
 	u16  i, is_using_sse;
 
 	if (sxe_rx_vec_condition_check(dev) ||
-	    !rx_batch_alloc_allowed 
+		!rx_batch_alloc_allowed
 #ifndef DPDK_19_11_6
 		|| rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128
 #endif
 		) {
 		PMD_LOG_DEBUG(INIT, "Port[%d] doesn't meet Vector Rx "
-				    "preconditions", dev->data->port_id);
+					"preconditions", dev->data->port_id);
 		*rx_vec_allowed = false;
 	}
 #else
@@ -76,24 +76,31 @@  void __rte_cold __sxe_rx_function_set(struct rte_eth_dev *dev, bool rx_batch_all
 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD
 		if (*rx_vec_allowed) {
 			PMD_LOG_DEBUG(INIT, "Using Vector Scattered Rx "
-					    "callback (port=%d).",
-				     dev->data->port_id);
+						"callback (port=%d).",
+					 dev->data->port_id);
 
 			dev->rx_pkt_burst = sxe_scattered_pkts_vec_recv;
-		} else
+
 #endif
+
+#if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD
+
+		} else if (rx_batch_alloc_allowed) {
+#else
 		if (rx_batch_alloc_allowed) {
+#endif
+
 			PMD_LOG_DEBUG(INIT, "Using a Scattered with bulk "
 					   "allocation callback (port=%d).",
-				     dev->data->port_id);
+					 dev->data->port_id);
 
 			dev->rx_pkt_burst = sxe_batch_alloc_lro_pkts_recv;
 		} else {
 			PMD_LOG_DEBUG(INIT, "Using Regular (non-vector, "
-					    "single allocation) "
-					    "Scattered Rx callback "
-					    "(port=%d).",
-				     dev->data->port_id);
+						"single allocation) "
+						"Scattered Rx callback "
+						"(port=%d).",
+					 dev->data->port_id);
 
 			dev->rx_pkt_burst = sxe_single_alloc_lro_pkts_recv;
 		}
@@ -101,17 +108,17 @@  void __rte_cold __sxe_rx_function_set(struct rte_eth_dev *dev, bool rx_batch_all
 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD
 	else if (*rx_vec_allowed) {
 		PMD_LOG_DEBUG(INIT, "Vector rx enabled, please make sure RX "
-				    "burst size no less than %d (port=%d).",
-			     SXE_DESCS_PER_LOOP,
-			     dev->data->port_id);
+					"burst size no less than %d (port=%d).",
+				 SXE_DESCS_PER_LOOP,
+				 dev->data->port_id);
 
 		dev->rx_pkt_burst = sxe_pkts_vec_recv;
 	}
 #endif
 	else if (rx_batch_alloc_allowed) {
 		PMD_LOG_DEBUG(INIT, "Rx Burst Bulk Alloc Preconditions are "
-				    "satisfied. Rx Burst Bulk Alloc function "
-				    "will be used on port=%d.",
+					"satisfied. Rx Burst Bulk Alloc function "
+					"will be used on port=%d.",
 				dev->data->port_id);
 
 		dev->rx_pkt_burst = sxe_batch_alloc_pkts_recv;
@@ -136,7 +143,6 @@  void __rte_cold __sxe_rx_function_set(struct rte_eth_dev *dev, bool rx_batch_all
 	}
 #endif
 
-	return;
 }
 
 #if defined DPDK_20_11_5 || defined DPDK_19_11_6
@@ -156,9 +162,8 @@  s32 __sxe_rx_descriptor_done(void *rx_queue, u16 offset)
 	}
 
 	index = rxq->processing_idx + offset;
-	if (index >= rxq->ring_depth) {
+	if (index >= rxq->ring_depth)
 		index -= rxq->ring_depth;
-	}
 
 	desc = &rxq->desc_ring[index];
 	is_done = !!(desc->wb.upper.status_error &
@@ -198,17 +203,15 @@  s32 __sxe_rx_descriptor_status(void *rx_queue, u16 offset)
 	}
 
 	desc = rxq->processing_idx + offset;
-	if (desc >= rxq->ring_depth) {
+	if (desc >= rxq->ring_depth)
 		desc -= rxq->ring_depth;
-	}
 
 	status = &rxq->desc_ring[desc].wb.upper.status_error;
-	if (*status & rte_cpu_to_le_32(SXE_RXDADV_STAT_DD)) {
+	if (*status & rte_cpu_to_le_32(SXE_RXDADV_STAT_DD))
 		ret =  RTE_ETH_RX_DESC_DONE;
-	}
 
 l_end:
-	LOG_DEBUG("rx queue[%u] get desc status=%d\n",rxq->queue_id, ret);
+	LOG_DEBUG("rx queue[%u] get desc status=%d\n", rxq->queue_id, ret);
 	return ret;
 }
 
@@ -234,23 +237,22 @@  u16 __sxe_pkts_recv(void *rx_queue, struct rte_mbuf **rx_pkts,
 	while (done_num < pkts_num) {
 		cur_desc = &desc_ring[processing_idx];
 		staterr = cur_desc->wb.upper.status_error;
-		if (!(staterr & rte_cpu_to_le_32(SXE_RXDADV_STAT_DD))) {
+		if (!(staterr & rte_cpu_to_le_32(SXE_RXDADV_STAT_DD)))
 			break;
-		}
 
 		rxd = *cur_desc;
 
 		LOG_DEBUG("port_id=%u queue_id=%u processing_idx=%u "
 			   "staterr=0x%08x pkt_len=%u",
-			   (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
-			   (unsigned) processing_idx, (unsigned) staterr,
-			   (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
+			   (unsigned int)rxq->port_id, (unsigned int) rxq->queue_id,
+			   (unsigned int)processing_idx, (unsigned int) staterr,
+			   (unsigned int)rte_le_to_cpu_16(rxd.wb.upper.length));
 
 		new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
 		if (new_mb == NULL) {
 			LOG_ERROR("RX mbuf alloc failed port_id=%u "
-				   "queue_id=%u", (unsigned) rxq->port_id,
-				   (unsigned) rxq->queue_id);
+				   "queue_id=%u", (unsigned int) rxq->port_id,
+				   (unsigned int) rxq->queue_id);
 			rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
 			break;
 		}
@@ -258,9 +260,8 @@  u16 __sxe_pkts_recv(void *rx_queue, struct rte_mbuf **rx_pkts,
 		hold_num++;
 		cur_buf = &buff_ring[processing_idx];
 		processing_idx++;
-		if (processing_idx == rxq->ring_depth) {
+		if (processing_idx == rxq->ring_depth)
 			processing_idx = 0;
-		}
 
 		sxe_rx_resource_prefetch(processing_idx, buff_ring, desc_ring);
 
@@ -293,9 +294,9 @@  u16 __sxe_pkts_recv(void *rx_queue, struct rte_mbuf **rx_pkts,
 	if (hold_num > rxq->batch_alloc_size) {
 		LOG_DEBUG("port_id=%u queue_id=%u rx_tail=%u "
 			   "num_hold=%u num_done=%u",
-			   (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
-			   (unsigned) processing_idx, (unsigned) hold_num,
-			   (unsigned) done_num);
+			   (unsigned int)rxq->port_id, (unsigned int)rxq->queue_id,
+			   (unsigned int)processing_idx, (unsigned int)hold_num,
+			   (unsigned int)done_num);
 		processing_idx = (u16)((processing_idx == 0) ?
 				(rxq->ring_depth - 1) : (processing_idx - 1));
 		SXE_PCI_REG_WC_WRITE(rxq->rdt_reg_addr, processing_idx);
@@ -308,7 +309,7 @@  u16 __sxe_pkts_recv(void *rx_queue, struct rte_mbuf **rx_pkts,
 
 const u32 *__sxe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
 {
-	const u32 * ptypes = NULL;
+	const u32 *ptypes = NULL;
 	static const u32 ptypes_arr[] = {
 		RTE_PTYPE_L2_ETHER,
 		RTE_PTYPE_L3_IPV4,
@@ -337,7 +338,7 @@  const u32 *__sxe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD
 #if defined(RTE_ARCH_X86)
 	if (dev->rx_pkt_burst == sxe_pkts_vec_recv ||
-	    dev->rx_pkt_burst == sxe_scattered_pkts_vec_recv) {
+		dev->rx_pkt_burst == sxe_scattered_pkts_vec_recv) {
 		ptypes = ptypes_arr;
 	}
 #endif
diff --git a/drivers/net/sxe/base/sxe_rx_common.h b/drivers/net/sxe/base/sxe_rx_common.h
index b7eb37f54a..93d2314968 100644
--- a/drivers/net/sxe/base/sxe_rx_common.h
+++ b/drivers/net/sxe/base/sxe_rx_common.h
@@ -7,7 +7,8 @@ 
 
 #include "sxe_dpdk_version.h"
 
-void __rte_cold __sxe_rx_function_set(struct rte_eth_dev *dev, bool rx_batch_alloc_allowed, bool *rx_vec_allowed);
+void __rte_cold __sxe_rx_function_set(struct rte_eth_dev *dev,
+	bool rx_batch_alloc_allowed, bool *rx_vec_allowed);
 
 #if defined DPDK_20_11_5 || defined DPDK_19_11_6
 s32 __sxe_rx_descriptor_done(void *rx_queue, u16 offset);
diff --git a/drivers/net/sxe/base/sxe_tx_common.c b/drivers/net/sxe/base/sxe_tx_common.c
index a47f90109a..e74556866f 100644
--- a/drivers/net/sxe/base/sxe_tx_common.c
+++ b/drivers/net/sxe/base/sxe_tx_common.c
@@ -33,15 +33,13 @@  int __sxe_tx_descriptor_status(void *tx_queue, u16 offset)
 	desc_idx = ((desc_idx + txq->rs_thresh - 1) / txq->rs_thresh) * txq->rs_thresh;
 	if (desc_idx >= txq->ring_depth) {
 		desc_idx -= txq->ring_depth;
-		if (desc_idx >= txq->ring_depth) {
+		if (desc_idx >= txq->ring_depth)
 			desc_idx -= txq->ring_depth;
-		}
 	}
 
 	status = &txq->desc_ring[desc_idx].wb.status;
-	if (*status & rte_cpu_to_le_32(SXE_TX_DESC_STAT_DD)) {
+	if (*status & rte_cpu_to_le_32(SXE_TX_DESC_STAT_DD))
 		ret = RTE_ETH_TX_DESC_DONE;
-	}
 
 l_end:
 	return ret;
diff --git a/drivers/net/sxe/base/sxe_types.h b/drivers/net/sxe/base/sxe_types.h
index 966ee230b3..a36a3cfbf6 100644
--- a/drivers/net/sxe/base/sxe_types.h
+++ b/drivers/net/sxe/base/sxe_types.h
@@ -18,7 +18,7 @@ 
 typedef uint8_t		u8;
 typedef uint16_t	u16;
 typedef uint32_t	u32;
-typedef uint64_t	u64; 
+typedef uint64_t	u64;
 
 typedef char		s8;
 typedef int16_t		s16;
diff --git a/drivers/net/sxe/base/sxevf_hw.c b/drivers/net/sxe/base/sxevf_hw.c
index 75ac9dd25b..5786e28f92 100644
--- a/drivers/net/sxe/base/sxevf_hw.c
+++ b/drivers/net/sxe/base/sxevf_hw.c
@@ -1,7 +1,7 @@ 
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright (C), 2022, Linkdata Technology Co., Ltd.
  */
-#if defined (__KERNEL__) || defined (SXE_KERNEL_TEST) 
+#if defined(__KERNEL__) || defined(SXE_KERNEL_TEST)
 #include <linux/etherdevice.h>
 
 #include "sxevf_hw.h"
@@ -12,7 +12,7 @@ 
 #include "sxevf_ring.h"
 #include "sxevf.h"
 #include "sxevf_rx_proc.h"
-#else 
+#else
 #include "sxe_errno.h"
 #include "sxe_logs.h"
 #include "sxe_dpdk_version.h"
@@ -28,37 +28,33 @@  struct sxevf_adapter;
 #define DMA_BIT_MASK(n)	(((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
 #define DMA_MASK_NONE	0x0ULL
 
-#define  SXEVF_REG_READ_CNT    5
+#define  SXEVF_REG_READ_CNT	5
 
-#define SXE_REG_READ_FAIL       0xffffffffU
+#define SXE_REG_READ_FAIL	   0xffffffffU
 
-#define SXEVF_RING_WAIT_LOOP                   (100)
-#define SXEVF_MAX_RX_DESC_POLL                 (10)
+#define SXEVF_RING_WAIT_LOOP				   (100)
+#define SXEVF_MAX_RX_DESC_POLL				 (10)
 
 
-#define SXEVF_REG_READ(hw, addr)        sxevf_reg_read(hw, addr)
+#define SXEVF_REG_READ(hw, addr)		sxevf_reg_read(hw, addr)
 #define SXEVF_REG_WRITE(hw, reg, value) sxevf_reg_write(hw, reg, value)
 #define SXEVF_WRITE_FLUSH(a) sxevf_reg_read(a, SXE_VFSTATUS)
 
-#ifndef SXE_DPDK 
+#ifndef SXE_DPDK
 void sxevf_hw_fault_handle(struct sxevf_hw *hw)
 {
 	struct sxevf_adapter *adapter = hw->adapter;
 
-	if (test_bit(SXEVF_HW_FAULT, &hw->state)) {
-		goto l_ret;
-	}
+	if (test_bit(SXEVF_HW_FAULT, &hw->state))
+		return;
 
 	set_bit(SXEVF_HW_FAULT, &hw->state);
 
 	LOG_DEV_ERR("sxe nic hw fault\n");
 
-	if ((hw->fault_handle != NULL) && (hw->priv != NULL) ) {
+	if ((hw->fault_handle != NULL) && (hw->priv != NULL))
 		hw->fault_handle(hw->priv);
-	}
 
-l_ret:
-	return;
 }
 
 static void sxevf_hw_fault_check(struct sxevf_hw *hw, u32 reg)
@@ -68,32 +64,27 @@  static void sxevf_hw_fault_check(struct sxevf_hw *hw, u32 reg)
 	struct sxevf_adapter *adapter = hw->adapter;
 	u8 i;
 
-	if (reg == SXE_VFSTATUS) {
+	if (reg == SXE_VFSTATUS)
 		sxevf_hw_fault_handle(hw);
-		return;
-	}
 
 
 	for (i = 0; i < SXEVF_REG_READ_CNT; i++) {
 		value = hw->reg_read(base_addr + SXE_VFSTATUS);
 
-		if (value != SXEVF_REG_READ_FAIL) {
+		if (value != SXEVF_REG_READ_FAIL)
 			break;
-		}
 
 		mdelay(20);
 	}
 
 	LOG_INFO_BDF("retry done i:%d value:0x%x\n", i, value);
 
-	if (value == SXEVF_REG_READ_FAIL) {
+	if (value == SXEVF_REG_READ_FAIL)
 		sxevf_hw_fault_handle(hw);
-	}
 
-	return;
 }
 
-STATIC u32 sxevf_reg_read(struct sxevf_hw *hw, u32 reg)
+static u32 sxevf_reg_read(struct sxevf_hw *hw, u32 reg)
 {
 	u32 value;
 	u8  __iomem *base_addr = hw->reg_base_addr;
@@ -105,7 +96,7 @@  STATIC u32 sxevf_reg_read(struct sxevf_hw *hw, u32 reg)
 	}
 
 	value = hw->reg_read(base_addr + reg);
-	if (unlikely(SXEVF_REG_READ_FAIL == value)) {
+	if (unlikely(value == SXEVF_REG_READ_FAIL)) {
 		LOG_ERROR_BDF("reg[0x%x] read failed, value=%#x\n", reg, value);
 		sxevf_hw_fault_check(hw, reg);
 	}
@@ -114,29 +105,26 @@  STATIC u32 sxevf_reg_read(struct sxevf_hw *hw, u32 reg)
 	return value;
 }
 
-STATIC void sxevf_reg_write(struct sxevf_hw *hw, u32 reg, u32 value)
+static void sxevf_reg_write(struct sxevf_hw *hw, u32 reg, u32 value)
 {
 	u8 __iomem *base_addr = hw->reg_base_addr;
 
-	if (sxevf_is_hw_fault(hw)) {
-		goto l_ret;
-	}
+	if (sxevf_is_hw_fault(hw))
+		return;
 
 	hw->reg_write(value, base_addr + reg);
 
-l_ret:
-	return;
 }
 
-#else 
+#else
 
-STATIC u32 sxevf_reg_read(struct sxevf_hw *hw, u32 reg)
+static u32 sxevf_reg_read(struct sxevf_hw *hw, u32 reg)
 {
 	u32 i, value;
 	u8  __iomem *base_addr = hw->reg_base_addr;
 
 	value = rte_le_to_cpu_32(rte_read32(base_addr + reg));
-	if (unlikely(SXEVF_REG_READ_FAIL == value)) {
+	if (unlikely(value == SXEVF_REG_READ_FAIL)) {
 		for (i = 0; i < SXEVF_REG_READ_CNT; i++) {
 			LOG_ERROR("reg[0x%x] read failed, value=%#x\n",
 							reg, value);
@@ -154,13 +142,12 @@  STATIC u32 sxevf_reg_read(struct sxevf_hw *hw, u32 reg)
 	return value;
 }
 
-STATIC void sxevf_reg_write(struct sxevf_hw *hw, u32 reg, u32 value)
+static void sxevf_reg_write(struct sxevf_hw *hw, u32 reg, u32 value)
 {
 	u8 __iomem *base_addr = hw->reg_base_addr;
 
 	rte_write32((rte_cpu_to_le_32(value)), (base_addr + reg));
 
-	return;
 }
 #endif
 
@@ -190,7 +177,6 @@  void sxevf_hw_stop(struct sxevf_hw *hw)
 		}
 	}
 
-	return;
 }
 
 void sxevf_msg_write(struct sxevf_hw *hw, u8 index, u32 msg)
@@ -201,7 +187,6 @@  void sxevf_msg_write(struct sxevf_hw *hw, u8 index, u32 msg)
 
 	LOG_DEBUG_BDF("index:%u write mbx mem:0x%x.\n", index, msg);
 
-	return;
 }
 
 u32 sxevf_msg_read(struct sxevf_hw *hw, u8 index)
@@ -222,21 +207,18 @@  u32 sxevf_mailbox_read(struct sxevf_hw *hw)
 void sxevf_mailbox_write(struct sxevf_hw *hw, u32 value)
 {
 	SXEVF_REG_WRITE(hw, SXE_VFMAILBOX, value);
-	return;
 }
 
 void sxevf_pf_req_irq_trigger(struct sxevf_hw *hw)
 {
 	SXEVF_REG_WRITE(hw, SXE_VFMAILBOX, SXE_VFMAILBOX_REQ);
 
-	return;
 }
 
 void sxevf_pf_ack_irq_trigger(struct sxevf_hw *hw)
 {
 	SXEVF_REG_WRITE(hw, SXE_VFMAILBOX, SXE_VFMAILBOX_ACK);
 
-	return;
 }
 
 void sxevf_event_irq_map(struct sxevf_hw *hw, u16 vector)
@@ -252,14 +234,12 @@  void sxevf_event_irq_map(struct sxevf_hw *hw, u16 vector)
 
 	SXEVF_REG_WRITE(hw, SXE_VFIVAR_MISC, ivar);
 
-	return;
 }
 
 void sxevf_specific_irq_enable(struct sxevf_hw *hw, u32 value)
 {
 	SXEVF_REG_WRITE(hw, SXE_VFEIMS, value);
 
-	return;
 }
 
 void sxevf_irq_enable(struct sxevf_hw *hw, u32 mask)
@@ -267,7 +247,6 @@  void sxevf_irq_enable(struct sxevf_hw *hw, u32 mask)
 	SXEVF_REG_WRITE(hw, SXE_VFEIAM, mask);
 	SXEVF_REG_WRITE(hw, SXE_VFEIMS, mask);
 
-	return;
 }
 
 void sxevf_irq_disable(struct sxevf_hw *hw)
@@ -277,7 +256,6 @@  void sxevf_irq_disable(struct sxevf_hw *hw)
 
 	SXEVF_WRITE_FLUSH(hw);
 
-	return;
 }
 
 void sxevf_hw_ring_irq_map(struct sxevf_hw *hw, bool is_tx, u16 hw_ring_idx, u16 vector)
@@ -295,7 +273,6 @@  void sxevf_hw_ring_irq_map(struct sxevf_hw *hw, bool is_tx, u16 hw_ring_idx, u16
 
 	SXEVF_REG_WRITE(hw, SXE_VFIVAR(hw_ring_idx >> 1), ivar);
 
-	return;
 }
 
 void sxevf_ring_irq_interval_set(struct sxevf_hw *hw, u16 irq_idx, u32 interval)
@@ -306,40 +283,36 @@  void sxevf_ring_irq_interval_set(struct sxevf_hw *hw, u16 irq_idx, u32 interval)
 
 	SXEVF_REG_WRITE(hw, SXE_VFEITR(irq_idx), eitr);
 
-	return;
 }
 
 static void sxevf_event_irq_interval_set(struct sxevf_hw *hw, u16 irq_idx, u32 value)
 {
 	SXEVF_REG_WRITE(hw, SXE_VFEITR(irq_idx), value);
 
-	return;
 }
 
 static void sxevf_pending_irq_clear(struct sxevf_hw *hw)
 {
 	SXEVF_REG_READ(hw, SXE_VFEICR);
 
-	return;
 }
 
 static void sxevf_ring_irq_trigger(struct sxevf_hw *hw, u64 eics)
 {
 	SXEVF_REG_WRITE(hw, SXE_VFEICS, eics);
 
-	return;
 }
 
 static const struct sxevf_irq_operations sxevf_irq_ops = {
 	.ring_irq_interval_set   = sxevf_ring_irq_interval_set,
 	.event_irq_interval_set  = sxevf_event_irq_interval_set,
-	.ring_irq_map         = sxevf_hw_ring_irq_map,
-	.event_irq_map           = sxevf_event_irq_map,
-	.pending_irq_clear       = sxevf_pending_irq_clear,
-	.ring_irq_trigger        = sxevf_ring_irq_trigger,
-	.specific_irq_enable     = sxevf_specific_irq_enable,
-	.irq_enable              = sxevf_irq_enable,
-	.irq_disable             = sxevf_irq_disable,
+	.ring_irq_map		 = sxevf_hw_ring_irq_map,
+	.event_irq_map		   = sxevf_event_irq_map,
+	.pending_irq_clear	   = sxevf_pending_irq_clear,
+	.ring_irq_trigger		= sxevf_ring_irq_trigger,
+	.specific_irq_enable	 = sxevf_specific_irq_enable,
+	.irq_enable			  = sxevf_irq_enable,
+	.irq_disable			 = sxevf_irq_disable,
 };
 
 void sxevf_hw_reset(struct sxevf_hw *hw)
@@ -347,10 +320,9 @@  void sxevf_hw_reset(struct sxevf_hw *hw)
 	SXEVF_REG_WRITE(hw, SXE_VFCTRL, SXE_VFCTRL_RST);
 	SXEVF_WRITE_FLUSH(hw);
 
-	return;
 }
 
-STATIC bool sxevf_hw_rst_done(struct sxevf_hw *hw)
+static bool sxevf_hw_rst_done(struct sxevf_hw *hw)
 {
 	return !(SXEVF_REG_READ(hw, SXE_VFCTRL) & SXE_VFCTRL_RST);
 }
@@ -374,9 +346,8 @@  static u32 sxevf_reg_dump(struct sxevf_hw *hw, u32 *regs_buff, u32 buf_size)
 	u32 i;
 	u32 regs_num = buf_size / sizeof(u32);
 
-	for (i = 0; i < regs_num; i++) {
+	for (i = 0; i < regs_num; i++)
 		regs_buff[i] = SXEVF_REG_READ(hw, dump_regs[i]);
-	}
 
 	return i;
 }
@@ -476,7 +447,7 @@  static s32 sxevf_reg_set_and_check(struct sxevf_hw *hw, int reg,
 	return ret;
 }
 
-STATIC s32 sxevf_regs_test(struct sxevf_hw *hw)
+static s32 sxevf_regs_test(struct sxevf_hw *hw)
 {
 	u32 i;
 	s32 ret = 0;
@@ -521,9 +492,8 @@  STATIC s32 sxevf_regs_test(struct sxevf_hw *hw)
 				break;
 			}
 
-			if (ret) {
+			if (ret)
 				goto l_end;
-			}
 
 		}
 		test++;
@@ -545,14 +515,13 @@  static const struct sxevf_setup_operations sxevf_setup_ops = {
 static void sxevf_tx_ring_desc_configure(struct sxevf_hw *hw, u32 desc_mem_len,
 				u64 desc_dma_addr, u8 reg_idx)
 {
-	SXEVF_REG_WRITE(hw, SXEVF_TDBAL(reg_idx), (desc_dma_addr & \
+	SXEVF_REG_WRITE(hw, SXEVF_TDBAL(reg_idx), (desc_dma_addr &
 						DMA_BIT_MASK(32)));
 	SXEVF_REG_WRITE(hw, SXEVF_TDBAH(reg_idx), (desc_dma_addr >> 32));
 	SXEVF_REG_WRITE(hw, SXEVF_TDLEN(reg_idx), desc_mem_len);
 	SXEVF_REG_WRITE(hw, SXEVF_TDH(reg_idx), 0);
 	SXEVF_REG_WRITE(hw, SXEVF_TDT(reg_idx), 0);
 
-	return;
 }
 
 static void sxevf_tx_writeback_off(struct sxevf_hw *hw, u8 reg_idx)
@@ -560,7 +529,6 @@  static void sxevf_tx_writeback_off(struct sxevf_hw *hw, u8 reg_idx)
 	SXEVF_REG_WRITE(hw, SXEVF_TDWBAH(reg_idx), 0);
 	SXEVF_REG_WRITE(hw, SXEVF_TDWBAL(reg_idx), 0);
 
-	return;
 }
 
 static void sxevf_tx_desc_thresh_set(
@@ -578,7 +546,6 @@  static void sxevf_tx_desc_thresh_set(
 
 	SXEVF_REG_WRITE(hw, SXEVF_TXDCTL(reg_idx), txdctl);
 
-	return;
 }
 
 void sxevf_tx_ring_switch(struct sxevf_hw *hw, u8 reg_idx, bool is_on)
@@ -610,7 +577,6 @@  void sxevf_tx_ring_switch(struct sxevf_hw *hw, u8 reg_idx, bool is_on)
 			  "the polling period\n", reg_idx, is_on);
 	}
 
-	return;
 }
 
 static void sxevf_rx_disable(struct sxevf_hw *hw, u8 reg_idx)
@@ -619,9 +585,8 @@  static void sxevf_rx_disable(struct sxevf_hw *hw, u8 reg_idx)
 	u32 wait_loop = SXEVF_RX_RING_POLL_MAX;
 	struct sxevf_adapter *adapter = hw->adapter;
 
-	if (!hw->reg_base_addr) {
-		goto l_end;
-	}
+	if (!hw->reg_base_addr)
+		return;
 
 	rxdctl = SXEVF_REG_READ(hw, SXE_VFRXDCTL(reg_idx));
 	rxdctl &= ~SXE_VFRXDCTL_ENABLE;
@@ -637,8 +602,6 @@  static void sxevf_rx_disable(struct sxevf_hw *hw, u8 reg_idx)
 				reg_idx);
 	}
 
-l_end:
-	return;
 }
 
 void sxevf_rx_ring_switch(struct sxevf_hw *hw, u8 reg_idx, bool is_on)
@@ -673,7 +636,6 @@  void sxevf_rx_ring_switch(struct sxevf_hw *hw, u8 reg_idx, bool is_on)
 			  "the polling period\n", reg_idx, is_on);
 	}
 
-	return;
 }
 
 void sxevf_rx_ring_desc_configure(struct sxevf_hw *hw, u32 desc_mem_len,
@@ -689,7 +651,6 @@  void sxevf_rx_ring_desc_configure(struct sxevf_hw *hw, u32 desc_mem_len,
 	SXEVF_REG_WRITE(hw, SXE_VFRDH(reg_idx), 0);
 	SXEVF_REG_WRITE(hw, SXE_VFRDT(reg_idx), 0);
 
-	return;
 }
 
 void sxevf_rx_rcv_ctl_configure(struct sxevf_hw *hw, u8 reg_idx,
@@ -697,9 +658,8 @@  void sxevf_rx_rcv_ctl_configure(struct sxevf_hw *hw, u8 reg_idx,
 {
 	u32 srrctl = 0;
 
-	if (drop_en) {
+	if (drop_en)
 		srrctl = SXEVF_SRRCTL_DROP_EN;
-	}
 
 	srrctl |= ((header_buf_len << SXEVF_SRRCTL_BSIZEHDRSIZE_SHIFT) &
 			SXEVF_SRRCTL_BSIZEHDR_MASK);
@@ -708,7 +668,6 @@  void sxevf_rx_rcv_ctl_configure(struct sxevf_hw *hw, u8 reg_idx,
 
 	SXEVF_REG_WRITE(hw, SXE_VFSRRCTL(reg_idx), srrctl);
 
-	return;
 }
 
 static void sxevf_tx_ring_info_get(struct sxevf_hw *hw,
@@ -717,48 +676,47 @@  static void sxevf_tx_ring_info_get(struct sxevf_hw *hw,
 	*head = SXEVF_REG_READ(hw, SXE_VFTDH(idx));
 	*tail = SXEVF_REG_READ(hw, SXE_VFTDT(idx));
 
-	return;
 }
 
 static const struct sxevf_dma_operations sxevf_dma_ops = {
 	.tx_ring_desc_configure  = sxevf_tx_ring_desc_configure,
-	.tx_writeback_off      = sxevf_tx_writeback_off,
-	.tx_desc_thresh_set    = sxevf_tx_desc_thresh_set,
-	.tx_ring_switch        = sxevf_tx_ring_switch,
-	.tx_ring_info_get      = sxevf_tx_ring_info_get,
-
-	.rx_disable          = sxevf_rx_disable,
-	.rx_ring_switch      = sxevf_rx_ring_switch,
-	.rx_ring_desc_configure= sxevf_rx_ring_desc_configure,
+	.tx_writeback_off	  = sxevf_tx_writeback_off,
+	.tx_desc_thresh_set	= sxevf_tx_desc_thresh_set,
+	.tx_ring_switch		= sxevf_tx_ring_switch,
+	.tx_ring_info_get	  = sxevf_tx_ring_info_get,
+
+	.rx_disable		  = sxevf_rx_disable,
+	.rx_ring_switch	  = sxevf_rx_ring_switch,
+	.rx_ring_desc_configure = sxevf_rx_ring_desc_configure,
 	.rx_rcv_ctl_configure  = sxevf_rx_rcv_ctl_configure,
 };
 
 #ifdef SXE_DPDK
-#define SXEVF_32BIT_COUNTER_UPDATE(reg, last, cur)                          \
-	{																\
-		u32 latest = SXEVF_REG_READ(hw, reg);				\
-		cur += (latest - last) & UINT_MAX;						\
-		last = latest;											\
-	}
-	
-#define SXEVF_36BIT_COUNTER_UPDATE(lsb, msb, last, cur)                \
-	{																 \
-		u64 new_lsb = SXEVF_REG_READ(hw, lsb);					 \
-		u64 new_msb = SXEVF_REG_READ(hw, msb);					 \
-		u64 latest = ((new_msb << 32) | new_lsb);				 \
+#define SXEVF_32BIT_COUNTER_UPDATE(reg, last, cur) \
+	{ \
+		u32 latest = SXEVF_REG_READ(hw, reg); \
+		cur += (latest - last) & UINT_MAX; \
+		last = latest; \
+	}
+
+#define SXEVF_36BIT_COUNTER_UPDATE(lsb, msb, last, cur) \
+	{ \
+		u64 new_lsb = SXEVF_REG_READ(hw, lsb); \
+		u64 new_msb = SXEVF_REG_READ(hw, msb); \
+		u64 latest = ((new_msb << 32) | new_lsb); \
 		cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
-		last = latest;											 \
+		last = latest; \
 	}
 
 #else
 #define SXEVF_32BIT_COUNTER_UPDATE(reg, last_counter, counter)	\
-	{							\
-		u32 current_counter = SXEVF_REG_READ(hw, reg);	\
-		if (current_counter < last_counter)		\
-			counter += 0x100000000LL;		\
-		last_counter = current_counter;			\
-		counter &= 0xFFFFFFFF00000000LL;		\
-		counter |= current_counter;			\
+	{ \
+		u32 current_counter = SXEVF_REG_READ(hw, reg); \
+		if (current_counter < last_counter) \
+			counter += 0x100000000LL; \
+		last_counter = current_counter; \
+		counter &= 0xFFFFFFFF00000000LL; \
+		counter |= current_counter; \
 	}
 
 #define SXEVF_36BIT_COUNTER_UPDATE(reg_lsb, reg_msb, last_counter, counter) \
@@ -791,7 +749,6 @@  void sxevf_packet_stats_get(struct sxevf_hw *hw,
 	SXEVF_32BIT_COUNTER_UPDATE(SXEVF_VFMPRC, stats->last_vfmprc,
 				stats->vfmprc);
 
-	return;
 }
 
 void sxevf_stats_init_value_get(struct sxevf_hw *hw,
@@ -805,7 +762,6 @@  void sxevf_stats_init_value_get(struct sxevf_hw *hw,
 	stats->last_vfgotc |= (((u64)(SXEVF_REG_READ(hw, SXE_VFGOTC_MSB))) << 32);
 	stats->last_vfmprc = SXEVF_REG_READ(hw, SXE_VFMPRC);
 
-	return;
 }
 static const struct sxevf_stat_operations sxevf_stat_ops = {
 	.packet_stats_get	= sxevf_packet_stats_get,
@@ -816,13 +772,11 @@  static void sxevf_rx_max_used_ring_set(struct sxevf_hw *hw, u16 max_rx_ring)
 {
 	u32 rqpl = 0;
 
-	if (max_rx_ring > 1) {
+	if (max_rx_ring > 1)
 		rqpl |= BIT(29);
-	}
 
 	SXEVF_REG_WRITE(hw, SXE_VFPSRTYPE, rqpl);
 
-	return;
 }
 
 static const struct sxevf_dbu_operations sxevf_dbu_ops = {
@@ -844,23 +798,22 @@  static const struct sxevf_mbx_operations sxevf_mbx_ops = {
 void sxevf_hw_ops_init(struct sxevf_hw *hw)
 {
 	hw->setup.ops   = &sxevf_setup_ops;
-	hw->irq.ops     = &sxevf_irq_ops;
-	hw->mbx.ops     = &sxevf_mbx_ops;
-	hw->dma.ops     = &sxevf_dma_ops;
-	hw->stat.ops    = &sxevf_stat_ops;
-	hw->dbu.ops     = &sxevf_dbu_ops;
+	hw->irq.ops	 = &sxevf_irq_ops;
+	hw->mbx.ops	 = &sxevf_mbx_ops;
+	hw->dma.ops	 = &sxevf_dma_ops;
+	hw->stat.ops	= &sxevf_stat_ops;
+	hw->dbu.ops	 = &sxevf_dbu_ops;
 
-	return;
 }
 
-#ifdef SXE_DPDK 
+#ifdef SXE_DPDK
 
-#define SXEVF_RSS_FIELD_MASK        0xffff0000
-#define SXEVF_MRQC_RSSEN            0x00000001 
+#define SXEVF_RSS_FIELD_MASK		0xffff0000
+#define SXEVF_MRQC_RSSEN			0x00000001
 
-#define SXEVF_RSS_KEY_SIZE                (40)  
-#define SXEVF_MAX_RSS_KEY_ENTRIES	  (10)  
-#define SXEVF_MAX_RETA_ENTRIES            (128) 
+#define SXEVF_RSS_KEY_SIZE				(40)
+#define SXEVF_MAX_RSS_KEY_ENTRIES	  (10)
+#define SXEVF_MAX_RETA_ENTRIES			(128)
 
 void sxevf_rxtx_reg_init(struct sxevf_hw *hw)
 {
@@ -886,7 +839,6 @@  void sxevf_rxtx_reg_init(struct sxevf_hw *hw)
 
 	SXEVF_WRITE_FLUSH(hw);
 
-	return;
 }
 
 u32 sxevf_irq_cause_get(struct sxevf_hw *hw)
@@ -898,21 +850,19 @@  void sxevf_tx_desc_configure(struct sxevf_hw *hw, u32 desc_mem_len,
 				u64 desc_dma_addr, u8 reg_idx)
 {
 
-	SXEVF_REG_WRITE(hw, SXEVF_TDBAL(reg_idx), (desc_dma_addr & \
+	SXEVF_REG_WRITE(hw, SXEVF_TDBAL(reg_idx), (desc_dma_addr &
 						DMA_BIT_MASK(32)));
 	SXEVF_REG_WRITE(hw, SXEVF_TDBAH(reg_idx), (desc_dma_addr >> 32));
 	SXEVF_REG_WRITE(hw, SXEVF_TDLEN(reg_idx), desc_mem_len);
 	SXEVF_REG_WRITE(hw, SXEVF_TDH(reg_idx), 0);
 	SXEVF_REG_WRITE(hw, SXEVF_TDT(reg_idx), 0);
 
-	return;
 }
 
 void sxevf_rss_bit_num_set(struct sxevf_hw *hw, u32 value)
 {
 	SXEVF_REG_WRITE(hw, SXE_VFPSRTYPE, value);
 
-	return;
 }
 
 void sxevf_hw_vlan_tag_strip_switch(struct sxevf_hw *hw,
@@ -922,15 +872,13 @@  void sxevf_hw_vlan_tag_strip_switch(struct sxevf_hw *hw,
 
 	vlnctrl = SXEVF_REG_READ(hw, SXE_VFRXDCTL(reg_index));
 
-	if (is_enable) {
+	if (is_enable)
 		vlnctrl |= SXEVF_RXDCTL_VME;
-	} else {
+	else
 		vlnctrl &= ~SXEVF_RXDCTL_VME;
-	}
 
 	SXEVF_REG_WRITE(hw, SXE_VFRXDCTL(reg_index), vlnctrl);
 
-	return;
 }
 
 void sxevf_tx_queue_thresh_set(struct sxevf_hw *hw, u8 reg_idx,
@@ -944,14 +892,12 @@  void sxevf_tx_queue_thresh_set(struct sxevf_hw *hw, u8 reg_idx,
 
 	SXEVF_REG_WRITE(hw, SXEVF_TXDCTL(reg_idx), txdctl);
 
-	return;
 }
 
 void sxevf_rx_desc_tail_set(struct sxevf_hw *hw, u8 reg_idx, u32 value)
 {
 	SXEVF_REG_WRITE(hw, SXE_VFRDT(reg_idx), value);
 
-	return;
 }
 
 u32 sxevf_hw_rss_redir_tbl_get(struct sxevf_hw *hw, u16 reg_idx)
@@ -963,18 +909,16 @@  void sxevf_hw_rss_redir_tbl_set(struct sxevf_hw *hw,
 						u16 reg_idx, u32 value)
 {
 	SXEVF_REG_WRITE(hw, SXE_VFRETA(reg_idx >> 2), value);
-	return;
 }
 
 u32 sxevf_hw_rss_key_get(struct sxevf_hw *hw, u8 reg_idx)
 {
 	u32 rss_key;
 
-	if (reg_idx >= SXEVF_MAX_RSS_KEY_ENTRIES) {
+	if (reg_idx >= SXEVF_MAX_RSS_KEY_ENTRIES)
 		rss_key = 0;
-	} else {
+	else
 		rss_key = SXEVF_REG_READ(hw, SXE_VFRSSRK(reg_idx));
-	}
 
 	return rss_key;
 }
@@ -989,9 +933,8 @@  bool sxevf_hw_is_rss_enabled(struct sxevf_hw *hw)
 {
 	bool rss_enable = false;
 	u32 mrqc = SXEVF_REG_READ(hw, SXE_VFMRQC);
-	if (mrqc & SXEVF_MRQC_RSSEN) {
+	if (mrqc & SXEVF_MRQC_RSSEN)
 		rss_enable = true;
-	}
 
 	return rss_enable;
 }
@@ -1000,25 +943,21 @@  void sxevf_hw_rss_key_set_all(struct sxevf_hw *hw, u32 *rss_key)
 {
 	u32 i;
 
-	for (i = 0; i < SXEVF_MAX_RSS_KEY_ENTRIES; i++) {
+	for (i = 0; i < SXEVF_MAX_RSS_KEY_ENTRIES; i++)
 		SXEVF_REG_WRITE(hw, SXE_VFRSSRK(i), rss_key[i]);
-	}
 
-	return;
 }
 
 void sxevf_hw_rss_cap_switch(struct sxevf_hw *hw, bool is_on)
 {
 	u32 mrqc = SXEVF_REG_READ(hw, SXE_VFMRQC);
-	if (is_on) {
+	if (is_on)
 		mrqc |= SXEVF_MRQC_RSSEN;
-	} else {
+	else
 		mrqc &= ~SXEVF_MRQC_RSSEN;
-	}
 
 	SXEVF_REG_WRITE(hw, SXE_VFMRQC, mrqc);
 
-	return;
 }
 
 void sxevf_hw_rss_field_set(struct sxevf_hw *hw, u32 rss_field)
@@ -1029,7 +968,6 @@  void sxevf_hw_rss_field_set(struct sxevf_hw *hw, u32 rss_field)
 	mrqc |= rss_field;
 	SXEVF_REG_WRITE(hw, SXE_VFMRQC, mrqc);
 
-	return;
 }
 
 u32 sxevf_hw_regs_group_read(struct sxevf_hw *hw,
@@ -1044,7 +982,7 @@  u32 sxevf_hw_regs_group_read(struct sxevf_hw *hw,
 			reg_buf[count + j] = SXEVF_REG_READ(hw,
 					regs[i].addr + j * regs[i].stride);
 			LOG_INFO("regs= %s, regs_addr=%x, regs_value=%04x\n",
-				regs[i].name , regs[i].addr, reg_buf[count + j]);
+				regs[i].name, regs[i].addr, reg_buf[count + j]);
 		}
 
 		i++;
diff --git a/drivers/net/sxe/base/sxevf_hw.h b/drivers/net/sxe/base/sxevf_hw.h
index 67d711d5b8..1530a3949f 100644
--- a/drivers/net/sxe/base/sxevf_hw.h
+++ b/drivers/net/sxe/base/sxevf_hw.h
@@ -5,7 +5,7 @@ 
 #ifndef __SXEVF_HW_H__
 #define __SXEVF_HW_H__
 
-#if defined (__KERNEL__) || defined (SXE_KERNEL_TEST)
+#if defined(__KERNEL__) || defined(SXE_KERNEL_TEST)
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/if_ether.h>
@@ -18,7 +18,7 @@ 
 
 #include "sxevf_regs.h"
 
-#if defined (__KERNEL__) || defined (SXE_KERNEL_TEST)
+#if defined(__KERNEL__) || defined(SXE_KERNEL_TEST)
 #define SXE_PRIU64  "llu"
 #define SXE_PRIX64  "llx"
 #define SXE_PRID64  "lld"
@@ -28,30 +28,30 @@ 
 #define SXE_PRID64  PRId64
 #endif
 
-#define SXEVF_TXRX_RING_NUM_MAX           8  
-#define SXEVF_MAX_TXRX_DESC_POLL          (10)
+#define SXEVF_TXRX_RING_NUM_MAX		   8
+#define SXEVF_MAX_TXRX_DESC_POLL		  (10)
 #define SXEVF_TX_DESC_PREFETCH_THRESH_32  (32)
-#define SXEVF_TX_DESC_HOST_THRESH_1       (1)
+#define SXEVF_TX_DESC_HOST_THRESH_1	   (1)
 #define SXEVF_TX_DESC_WRITEBACK_THRESH_8  (8)
-#define SXEVF_TXDCTL_HTHRESH_SHIFT        (8)
-#define SXEVF_TXDCTL_WTHRESH_SHIFT        (16)
+#define SXEVF_TXDCTL_HTHRESH_SHIFT		(8)
+#define SXEVF_TXDCTL_WTHRESH_SHIFT		(16)
 
-#define SXEVF_TXDCTL_THRESH_MASK          (0x7F)
+#define SXEVF_TXDCTL_THRESH_MASK		  (0x7F)
 
-#define SXEVF_RX_RING_POLL_MAX           (10)
+#define SXEVF_RX_RING_POLL_MAX		   (10)
 
-#define SXEVF_MAC_HDR_LEN_MAX           (127)
-#define SXEVF_NETWORK_HDR_LEN_MAX       (511)
+#define SXEVF_MAC_HDR_LEN_MAX		   (127)
+#define SXEVF_NETWORK_HDR_LEN_MAX	   (511)
 
-#define SXEVF_LINK_SPEED_UNKNOWN        0
+#define SXEVF_LINK_SPEED_UNKNOWN		0
 #define SXEVF_LINK_SPEED_1GB_FULL	0x0020
 #define SXEVF_LINK_SPEED_10GB_FULL	0x0080
 #define SXEVF_LINK_SPEED_100_FULL	0x0008
 
-#define SXEVF_VFT_TBL_SIZE           (128)   
-#define SXEVF_HW_TXRX_RING_NUM_MAX   (128)   
+#define SXEVF_VFT_TBL_SIZE		   (128)
+#define SXEVF_HW_TXRX_RING_NUM_MAX   (128)
 
-#define SXEVF_VLAN_TAG_SIZE          (4)
+#define SXEVF_VLAN_TAG_SIZE		  (4)
 
 #define SXEVF_HW_UC_ENTRY_NUM_MAX   128
 
@@ -65,7 +65,7 @@  enum {
 	SXEVF_DIAG_TEST_PASSED			= 0,
 	SXEVF_DIAG_TEST_BLOCKED			= 1,
 	SXEVF_DIAG_REG_PATTERN_TEST_ERR		= 2,
-	SXEVF_DIAG_CHECK_REG_TEST_ERR           = 3,
+	SXEVF_DIAG_CHECK_REG_TEST_ERR		   = 3,
 };
 
 struct sxevf_hw;
@@ -83,11 +83,11 @@  struct sxevf_hw_stats {
 	u64 last_vfgotc;
 	u64 last_vfmprc;
 
-	u64 vfgprc;      
-	u64 vfgptc;      
-	u64 vfgorc;      
-	u64 vfgotc;      
-	u64 vfmprc;      
+	u64 vfgprc;
+	u64 vfgptc;
+	u64 vfgorc;
+	u64 vfgotc;
+	u64 vfmprc;
 
 	u64 saved_reset_vfgprc;
 	u64 saved_reset_vfgptc;
@@ -100,12 +100,12 @@  void sxevf_hw_ops_init(struct sxevf_hw *hw);
 
 
 struct sxevf_setup_operations {
-	void (*reset)(struct sxevf_hw *);
+	void (*reset)(struct sxevf_hw *hw);
 	void (*hw_stop)(struct sxevf_hw *hw);
 	s32  (*regs_test)(struct sxevf_hw *hw);
 	u32  (*link_state_get)(struct sxevf_hw *hw);
 	u32  (*regs_dump)(struct sxevf_hw *hw, u32 *regs_buff, u32 buf_size);
-	bool (*reset_done)(struct sxevf_hw *);
+	bool (*reset_done)(struct sxevf_hw *hw);
 };
 
 struct sxevf_hw_setup {
@@ -115,12 +115,12 @@  struct sxevf_hw_setup {
 struct sxevf_irq_operations {
 	void (*pending_irq_clear)(struct sxevf_hw *hw);
 	void (*ring_irq_interval_set)(struct sxevf_hw *hw, u16 irq_idx, u32 interval);
-	void (*event_irq_interval_set)(struct sxevf_hw * hw, u16 irq_idx, u32 value);
+	void (*event_irq_interval_set)(struct sxevf_hw *hw, u16 irq_idx, u32 value);
 	void (*ring_irq_map)(struct sxevf_hw *hw, bool is_tx, u16 hw_ring_idx, u16 irq_idx);
 	void (*event_irq_map)(struct sxevf_hw *hw, u16 irq_idx);
 	void (*ring_irq_trigger)(struct sxevf_hw *hw, u64 eics);
-	void (*irq_enable)(struct sxevf_hw * hw, u32 mask);
-	void (*specific_irq_enable)(struct sxevf_hw * hw, u32 value);
+	void (*irq_enable)(struct sxevf_hw *hw, u32 mask);
+	void (*specific_irq_enable)(struct sxevf_hw *hw, u32 value);
 	void (*irq_disable)(struct sxevf_hw *hw);
 	void (*irq_off)(struct sxevf_hw *hw);
 };
@@ -142,37 +142,40 @@  struct sxevf_mbx_operations {
 };
 
 struct sxevf_mbx_stats {
-	u32 send_msgs; 
-	u32 rcv_msgs;  
+	u32 send_msgs;
+	u32 rcv_msgs;
 
-	u32 reqs;      
-	u32 acks;      
-	u32 rsts;      
+	u32 reqs;
+	u32 acks;
+	u32 rsts;
 };
 
 struct sxevf_mbx_info {
-	const struct sxevf_mbx_operations *ops; 
-
-	struct sxevf_mbx_stats stats; 
-	u32 msg_len;  
-	u32 retry;    
-	u32 interval; 
-	u32 reg_value; 
-	u32 api_version; 
+	const struct sxevf_mbx_operations *ops;
+
+	struct sxevf_mbx_stats stats;
+	u32 msg_len;
+	u32 retry;
+	u32 interval;
+	u32 reg_value;
+	u32 api_version;
 };
 
 struct sxevf_dma_operations {
-	void (* tx_ring_desc_configure)(struct sxevf_hw *, u32, u64, u8);
-	void (* tx_writeback_off)(struct sxevf_hw *, u8);
-	void (* tx_desc_thresh_set)(struct sxevf_hw *, u8, u32, u32, u32);
-	void (* tx_ring_switch)(struct sxevf_hw *, u8, bool);
-	void (* tx_desc_wb_flush)(struct sxevf_hw *, u8);
-	void (* tx_ring_info_get)(struct sxevf_hw *hw, u8 reg_idx,
+	void (*tx_ring_desc_configure)(struct sxevf_hw *hw, u32 desc_mem_len,
+				u64 desc_dma_addr, u8 reg_idx);
+	void (*tx_writeback_off)(struct sxevf_hw *hw, u8 reg_idx);
+	void (*tx_desc_thresh_set)(struct sxevf_hw *hw, u8 reg_idx,
+				u32 wb_thresh, u32 host_thresh, u32 prefech_thresh);
+	void (*tx_ring_switch)(struct sxevf_hw *hw, u8 reg_idx, bool is_on);
+	void (*tx_desc_wb_flush)(struct sxevf_hw *hw, u8 val);
+	void (*tx_ring_info_get)(struct sxevf_hw *hw, u8 reg_idx,
 					u32 *head, u32 *tail);
-	void (* rx_disable)(struct sxevf_hw *, u8);
-	void (* rx_ring_switch)(struct sxevf_hw *, u8, bool);
-	void (* rx_ring_desc_configure)(struct sxevf_hw *, u32, u64, u8);
-	void (* rx_rcv_ctl_configure)(struct sxevf_hw *hw, u8 reg_idx,
+	void (*rx_disable)(struct sxevf_hw *hw, u8 reg_idx);
+	void (*rx_ring_switch)(struct sxevf_hw *hw, u8 reg_idx, bool is_on);
+	void (*rx_ring_desc_configure)(struct sxevf_hw *hw, u32 desc_mem_len,
+				u64 desc_dma_addr, u8 reg_idx);
+	void (*rx_rcv_ctl_configure)(struct sxevf_hw *hw, u8 reg_idx,
 				   u32 header_buf_len, u32 pkg_buf_len, bool drop_en);
 };
 
@@ -181,8 +184,8 @@  struct sxevf_dma_info {
 };
 
 struct sxevf_stat_operations {
-	void (*packet_stats_get)(struct sxevf_hw *,
-			struct sxevf_hw_stats *);
+	void (*packet_stats_get)(struct sxevf_hw *hw,
+			struct sxevf_hw_stats *stats);
 	void (*stats_init_value_get)(struct sxevf_hw *hw,
 				struct sxevf_hw_stats *stats);
 };
@@ -192,7 +195,7 @@  struct sxevf_stat_info {
 };
 
 struct sxevf_dbu_operations {
-	void (*rx_max_used_ring_set)(struct sxevf_hw *, u16);
+	void (*rx_max_used_ring_set)(struct sxevf_hw *hw, u16 max_rx_ring);
 
 };
 
@@ -206,30 +209,30 @@  enum sxevf_hw_state {
 };
 
 struct sxevf_hw {
-	u8 __iomem *reg_base_addr;      
+	u8 __iomem *reg_base_addr;
 	void *adapter;
 
 	void *priv;
-	unsigned long state;   
+	unsigned long state;
 	void (*fault_handle)(void *priv);
 	u32 (*reg_read)(const volatile void *reg);
 	void (*reg_write)(u32 value, volatile void *reg);
-	s32	board_type;		
+	s32	board_type;
 
-	struct sxevf_hw_setup   setup;   
-	struct sxevf_irq_info   irq;     
-	struct sxevf_mbx_info   mbx;     
+	struct sxevf_hw_setup   setup;
+	struct sxevf_irq_info   irq;
+	struct sxevf_mbx_info   mbx;
 
-	struct sxevf_dma_info    dma;    
-	struct sxevf_stat_info   stat;   
-	struct sxevf_dbu_info    dbu;
+	struct sxevf_dma_info	dma;
+	struct sxevf_stat_info   stat;
+	struct sxevf_dbu_info	dbu;
 };
 
 struct sxevf_reg_info {
-	u32 addr;        
-	u32 count;       
-	u32 stride;      
-	const s8 *name;  
+	u32 addr;
+	u32 count;
+	u32 stride;
+	const s8 *name;
 };
 
 u16 sxevf_reg_dump_num_get(void);
@@ -247,7 +250,6 @@  static inline void sxevf_hw_fault_handle_init(struct sxevf_hw *hw,
 	hw->priv = priv;
 	hw->fault_handle = handle;
 
-	return;
 }
 
 static inline void sxevf_hw_reg_handle_init(struct sxevf_hw *hw,
@@ -257,10 +259,9 @@  static inline void sxevf_hw_reg_handle_init(struct sxevf_hw *hw,
 	hw->reg_read  = read;
 	hw->reg_write = write;
 
-	return;
 }
 
-#ifdef SXE_DPDK 
+#ifdef SXE_DPDK
 
 void sxevf_irq_disable(struct sxevf_hw *hw);
 
@@ -347,5 +348,5 @@  u32 sxevf_hw_regs_group_read(struct sxevf_hw *hw,
 				const struct sxevf_reg_info *regs,
 				u32 *reg_buf);
 
-#endif 
+#endif
 #endif
diff --git a/drivers/net/sxe/base/sxevf_regs.h b/drivers/net/sxe/base/sxevf_regs.h
index 43486db526..50a22f559c 100644
--- a/drivers/net/sxe/base/sxevf_regs.h
+++ b/drivers/net/sxe/base/sxevf_regs.h
@@ -14,106 +14,106 @@ 
 #define SXE_VFLINKS_SPEED_1G	0x00000004
 #define SXE_VFLINKS_SPEED_100	0x00000002
 
-#define SXE_VFCTRL        0x00000
-#define SXE_VFSTATUS      0x00008
-#define SXE_VFLINKS       0x00018
-#define SXE_VFFRTIMER     0x00048
+#define SXE_VFCTRL		0x00000
+#define SXE_VFSTATUS	  0x00008
+#define SXE_VFLINKS	   0x00018
+#define SXE_VFFRTIMER	 0x00048
 #define SXE_VFRXMEMWRAP   0x03190
-#define SXE_VFEICR        0x00100
-#define SXE_VFEICS        0x00104
-#define SXE_VFEIMS        0x00108
-#define SXE_VFEIMC        0x0010C
-#define SXE_VFEIAM        0x00114
-#define SXE_VFEITR(x)     (0x00820 + (4 * (x)))
-#define SXE_VFIVAR(x)     (0x00120 + (4 * (x)))
-#define SXE_VFIVAR_MISC    0x00140
-#define SXE_VFRDBAL(x)    (0x01000 + (0x40 * (x)))
-#define SXE_VFRDBAH(x)    (0x01004 + (0x40 * (x)))
-#define SXE_VFRDLEN(x)    (0x01008 + (0x40 * (x)))
-#define SXE_VFRDH(x)      (0x01010 + (0x40 * (x)))
-#define SXE_VFRDT(x)      (0x01018 + (0x40 * (x)))
+#define SXE_VFEICR		0x00100
+#define SXE_VFEICS		0x00104
+#define SXE_VFEIMS		0x00108
+#define SXE_VFEIMC		0x0010C
+#define SXE_VFEIAM		0x00114
+#define SXE_VFEITR(x)	 (0x00820 + (4 * (x)))
+#define SXE_VFIVAR(x)	 (0x00120 + (4 * (x)))
+#define SXE_VFIVAR_MISC	0x00140
+#define SXE_VFRDBAL(x)	(0x01000 + (0x40 * (x)))
+#define SXE_VFRDBAH(x)	(0x01004 + (0x40 * (x)))
+#define SXE_VFRDLEN(x)	(0x01008 + (0x40 * (x)))
+#define SXE_VFRDH(x)	  (0x01010 + (0x40 * (x)))
+#define SXE_VFRDT(x)	  (0x01018 + (0x40 * (x)))
 #define SXE_VFRXDCTL(x)   (0x01028 + (0x40 * (x)))
 #define SXE_VFSRRCTL(x)   (0x01014 + (0x40 * (x)))
 #define SXE_VFLROCTL(x)   (0x0102C + (0x40 * (x)))
-#define SXE_VFPSRTYPE     0x00300
-#define SXE_VFTDBAL(x)    (0x02000 + (0x40 * (x)))
-#define SXE_VFTDBAH(x)    (0x02004 + (0x40 * (x)))
-#define SXE_VFTDLEN(x)    (0x02008 + (0x40 * (x)))
-#define SXE_VFTDH(x)      (0x02010 + (0x40 * (x)))
-#define SXE_VFTDT(x)      (0x02018 + (0x40 * (x)))
+#define SXE_VFPSRTYPE	 0x00300
+#define SXE_VFTDBAL(x)	(0x02000 + (0x40 * (x)))
+#define SXE_VFTDBAH(x)	(0x02004 + (0x40 * (x)))
+#define SXE_VFTDLEN(x)	(0x02008 + (0x40 * (x)))
+#define SXE_VFTDH(x)	  (0x02010 + (0x40 * (x)))
+#define SXE_VFTDT(x)	  (0x02018 + (0x40 * (x)))
 #define SXE_VFTXDCTL(x)   (0x02028 + (0x40 * (x)))
 #define SXE_VFTDWBAL(x)   (0x02038 + (0x40 * (x)))
 #define SXE_VFTDWBAH(x)   (0x0203C + (0x40 * (x)))
-#define SXE_VFDCA_RXCTRL(x)    (0x0100C + (0x40 * (x)))
-#define SXE_VFDCA_TXCTRL(x)    (0x0200c + (0x40 * (x)))
-#define SXE_VFGPRC        0x0101C
-#define SXE_VFGPTC        0x0201C
-#define SXE_VFGORC_LSB    0x01020
-#define SXE_VFGORC_MSB    0x01024
-#define SXE_VFGOTC_LSB    0x02020
-#define SXE_VFGOTC_MSB    0x02024
-#define SXE_VFMPRC        0x01034
-#define SXE_VFMRQC        0x3000
-#define SXE_VFRSSRK(x)    (0x3100 + ((x) * 4))
-#define SXE_VFRETA(x)     (0x3200 + ((x) * 4))
-
-#define SXEVF_VFEIMC_IRQ_MASK            (7)
-#define SXEVF_IVAR_ALLOC_VALID    (0x80)
-
-#define SXEVF_EITR_CNT_WDIS       (0x80000000)
-#define SXEVF_EITR_ITR_MASK       (0x00000FF8)
-#define SXEVF_EITR_ITR_SHIFT      (2)
-#define SXEVF_EITR_ITR_MAX        (SXEVF_EITR_ITR_MASK >> SXEVF_EITR_ITR_SHIFT)
+#define SXE_VFDCA_RXCTRL(x)	(0x0100C + (0x40 * (x)))
+#define SXE_VFDCA_TXCTRL(x)	(0x0200c + (0x40 * (x)))
+#define SXE_VFGPRC		0x0101C
+#define SXE_VFGPTC		0x0201C
+#define SXE_VFGORC_LSB	0x01020
+#define SXE_VFGORC_MSB	0x01024
+#define SXE_VFGOTC_LSB	0x02020
+#define SXE_VFGOTC_MSB	0x02024
+#define SXE_VFMPRC		0x01034
+#define SXE_VFMRQC		0x3000
+#define SXE_VFRSSRK(x)	(0x3100 + ((x) * 4))
+#define SXE_VFRETA(x)	 (0x3200 + ((x) * 4))
+
+#define SXEVF_VFEIMC_IRQ_MASK			(7)
+#define SXEVF_IVAR_ALLOC_VALID	(0x80)
+
+#define SXEVF_EITR_CNT_WDIS	   (0x80000000)
+#define SXEVF_EITR_ITR_MASK	   (0x00000FF8)
+#define SXEVF_EITR_ITR_SHIFT	  (2)
+#define SXEVF_EITR_ITR_MAX		(SXEVF_EITR_ITR_MASK >> SXEVF_EITR_ITR_SHIFT)
 
 #define SXE_VFRXDCTL_ENABLE  0x02000000
 #define SXE_VFTXDCTL_ENABLE  0x02000000
-#define SXE_VFCTRL_RST       0x04000000
-
-#define SXEVF_RXDCTL_ENABLE     0x02000000  
-#define SXEVF_RXDCTL_VME	0x40000000  
-
-#define SXEVF_PSRTYPE_RQPL_SHIFT               29 
-
-#define SXEVF_SRRCTL_DROP_EN                   0x10000000
-#define SXEVF_SRRCTL_DESCTYPE_DATA_ONEBUF      0x02000000
-#define SXEVF_SRRCTL_BSIZEPKT_SHIFT            (10)
-#define SXEVF_SRRCTL_BSIZEHDRSIZE_SHIFT        (2)
-#define SXEVF_SRRCTL_BSIZEPKT_MASK	       0x0000007F
-#define SXEVF_SRRCTL_BSIZEHDR_MASK	       0x00003F00
-
-#define SXE_VFMAILBOX       0x002FC
-#define SXE_VFMBMEM         0x00200
-
-#define SXE_VFMAILBOX_REQ     0x00000001 
-#define SXE_VFMAILBOX_ACK     0x00000002 
-#define SXE_VFMAILBOX_VFU     0x00000004 
-#define SXE_VFMAILBOX_PFU     0x00000008 
-#define SXE_VFMAILBOX_PFSTS   0x00000010 
-#define SXE_VFMAILBOX_PFACK   0x00000020 
-#define SXE_VFMAILBOX_RSTI    0x00000040 
-#define SXE_VFMAILBOX_RSTD    0x00000080 
-#define SXE_VFMAILBOX_RC_BIT  0x000000B0  
-
-#define SXEVF_TDBAL(_i)      (0x02000 + ((_i) * 0x40))
-#define SXEVF_TDBAH(_i)      (0x02004 + ((_i) * 0x40))
-#define SXEVF_TDLEN(_i)      (0x02008 + ((_i) * 0x40))
-#define SXEVF_TDH(_i)        (0x02010 + ((_i) * 0x40))
-#define SXEVF_TDT(_i)        (0x02018 + ((_i) * 0x40))
-#define SXEVF_TXDCTL(_i)     (0x02028 + ((_i) * 0x40))
-#define SXEVF_TDWBAL(_i)     (0x02038 + ((_i) * 0x40))
-#define SXEVF_TDWBAH(_i)     (0x0203C + ((_i) * 0x40))
-
-#define SXEVF_TXDCTL_SWFLSH  (0x02000000)  
-#define SXEVF_TXDCTL_ENABLE  (0x02000000) 
-
-#define SXEVF_VFGPRC          0x0101C
-#define SXEVF_VFGPTC          0x0201C
-#define SXEVF_VFGORC_LSB      0x01020
-#define SXEVF_VFGORC_MSB      0x01024
-#define SXEVF_VFGOTC_LSB      0x02020
-#define SXEVF_VFGOTC_MSB      0x02024
-#define SXEVF_VFMPRC          0x01034
-
-#define SXEVF_EICR_MASK       0x07
+#define SXE_VFCTRL_RST	   0x04000000
+
+#define SXEVF_RXDCTL_ENABLE	 0x02000000
+#define SXEVF_RXDCTL_VME	0x40000000
+
+#define SXEVF_PSRTYPE_RQPL_SHIFT			   29
+
+#define SXEVF_SRRCTL_DROP_EN				   0x10000000
+#define SXEVF_SRRCTL_DESCTYPE_DATA_ONEBUF	  0x02000000
+#define SXEVF_SRRCTL_BSIZEPKT_SHIFT			(10)
+#define SXEVF_SRRCTL_BSIZEHDRSIZE_SHIFT		(2)
+#define SXEVF_SRRCTL_BSIZEPKT_MASK		   0x0000007F
+#define SXEVF_SRRCTL_BSIZEHDR_MASK		   0x00003F00
+
+#define SXE_VFMAILBOX	   0x002FC
+#define SXE_VFMBMEM		 0x00200
+
+#define SXE_VFMAILBOX_REQ	 0x00000001
+#define SXE_VFMAILBOX_ACK	 0x00000002
+#define SXE_VFMAILBOX_VFU	 0x00000004
+#define SXE_VFMAILBOX_PFU	 0x00000008
+#define SXE_VFMAILBOX_PFSTS   0x00000010
+#define SXE_VFMAILBOX_PFACK   0x00000020
+#define SXE_VFMAILBOX_RSTI	0x00000040
+#define SXE_VFMAILBOX_RSTD	0x00000080
+#define SXE_VFMAILBOX_RC_BIT  0x000000B0
+
+#define SXEVF_TDBAL(_i)	  (0x02000 + ((_i) * 0x40))
+#define SXEVF_TDBAH(_i)	  (0x02004 + ((_i) * 0x40))
+#define SXEVF_TDLEN(_i)	  (0x02008 + ((_i) * 0x40))
+#define SXEVF_TDH(_i)		(0x02010 + ((_i) * 0x40))
+#define SXEVF_TDT(_i)		(0x02018 + ((_i) * 0x40))
+#define SXEVF_TXDCTL(_i)	 (0x02028 + ((_i) * 0x40))
+#define SXEVF_TDWBAL(_i)	 (0x02038 + ((_i) * 0x40))
+#define SXEVF_TDWBAH(_i)	 (0x0203C + ((_i) * 0x40))
+
+#define SXEVF_TXDCTL_SWFLSH  (0x02000000)
+#define SXEVF_TXDCTL_ENABLE  (0x02000000)
+
+#define SXEVF_VFGPRC		  0x0101C
+#define SXEVF_VFGPTC		  0x0201C
+#define SXEVF_VFGORC_LSB	  0x01020
+#define SXEVF_VFGORC_MSB	  0x01024
+#define SXEVF_VFGOTC_LSB	  0x02020
+#define SXEVF_VFGOTC_MSB	  0x02024
+#define SXEVF_VFMPRC		  0x01034
+
+#define SXEVF_EICR_MASK	   0x07
 
 #endif
diff --git a/drivers/net/sxe/include/drv_msg.h b/drivers/net/sxe/include/drv_msg.h
index 9f06624cc3..e441f9d371 100644
--- a/drivers/net/sxe/include/drv_msg.h
+++ b/drivers/net/sxe/include/drv_msg.h
@@ -16,7 +16,7 @@ 
 
 
 typedef struct sxe_version_resp {
-    U8 fw_version[SXE_VERSION_LEN];
-}sxe_version_resp_s;
+	U8 fw_version[SXE_VERSION_LEN];
+} sxe_version_resp_s;
 
-#endif 
+#endif
diff --git a/drivers/net/sxe/include/sxe/mgl/sxe_port.h b/drivers/net/sxe/include/sxe/mgl/sxe_port.h
index e41cb9e87b..642b9eb045 100644
--- a/drivers/net/sxe/include/sxe/mgl/sxe_port.h
+++ b/drivers/net/sxe/include/sxe/mgl/sxe_port.h
@@ -11,26 +11,27 @@  extern "C" {
 #include "mgc_types.h"
 #include "ps3_types.h"
 
-typedef enum MglPortCmdSetCode{
-    MGL_CMD_PORT_SET_BASE      = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 0),
-    MGL_CMD_PORT_SET_REG       = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 1),
-    MGL_CMD_PORT_SET_LED       = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 2),
-    MGL_CMD_SXE_SOC_HTHRESHOLD = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 3),
-    MGL_CMD_SXE_SFP_HTHRESHOLD = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 4),
-    MGL_CMD_SXE_SOC_RST        = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 5),
-    MGL_CMD_SXE_SET_MFGINFO    = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 6),
-    MGL_CMD_SXE_SET_INSIGHT    = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 7),
-    MGL_CMD_SXE_OPT_INSIGHT    = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 8),
+typedef enum MglPortCmdSetCode {
+	MGL_CMD_PORT_SET_BASE	  = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 0),
+	MGL_CMD_PORT_SET_REG	   = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 1),
+	MGL_CMD_PORT_SET_LED	   = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 2),
+	MGL_CMD_SXE_SOC_HTHRESHOLD = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 3),
+	MGL_CMD_SXE_SFP_HTHRESHOLD = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 4),
+	MGL_CMD_SXE_SOC_RST		= MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 5),
+	MGL_CMD_SXE_SET_MFGINFO	= MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 6),
+	MGL_CMD_SXE_SET_INSIGHT	= MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 7),
+	MGL_CMD_SXE_OPT_INSIGHT	= MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 8),
+	MGL_CMD_SXE_SET_LLDPSTATE  = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_SET, 9),
 } MglPortCmdSetCode_e;
 
-typedef enum MglPortCmdGetCode{
-    MGL_CMD_SXE_GET_REG        = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_GET, 0),
-    MGL_CMD_SXE_GET_SOC_INFO   = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_GET, 1),
-    MGL_CMD_SXE_LOG_EXPORT     = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_GET, 2),
-    MGL_CMD_SXE_REGS_DUMP      = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_GET, 3),
-    MGL_CMD_SXE_GET_MFGINFO    = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_GET, 4),
-    MGL_CMD_SXE_MAC_ADDR_GET   = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_GET, 5),
-    MGL_CMD_SXE_GET_INSIGHT    = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_GET, 6),
+typedef enum MglPortCmdGetCode {
+	MGL_CMD_SXE_GET_REG		= MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_GET, 0),
+	MGL_CMD_SXE_GET_SOC_INFO   = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_GET, 1),
+	MGL_CMD_SXE_LOG_EXPORT	 = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_GET, 2),
+	MGL_CMD_SXE_REGS_DUMP	  = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_GET, 3),
+	MGL_CMD_SXE_GET_MFGINFO	= MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_GET, 4),
+	MGL_CMD_SXE_MAC_ADDR_GET   = MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_GET, 5),
+	MGL_CMD_SXE_GET_INSIGHT	= MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CMD_GET, 6),
 } MglPortCmdGetCode_e;
 
 #if defined(__cplusplus)
diff --git a/drivers/net/sxe/include/sxe/sxe_cli.h b/drivers/net/sxe/include/sxe/sxe_cli.h
index 206cc48542..a03e51b08e 100644
--- a/drivers/net/sxe/include/sxe/sxe_cli.h
+++ b/drivers/net/sxe/include/sxe/sxe_cli.h
@@ -9,160 +9,165 @@ 
 #include "sxe_drv_type.h"
 #endif
 
-#define SXE_VERION_LEN                  (32)
-#define SXE_MAC_NUM                     (128)
-#define SXE_PORT_TRANSCEIVER_LEN        (32)
-#define SXE_PORT_VENDOR_LEN             (32)
-#define SXE_CHIP_TYPE_LEN               (32)
-#define SXE_VPD_SN_LEN                  (16)
-#define SXE_SOC_RST_TIME                (0x93A80)  
-#define SXE_SFP_TEMP_THRESHOLD_INTERVAL (3)        
-#define MGC_TERMLOG_INFO_MAX_LEN        (12 * 1024)
-#define SXE_REGS_DUMP_MAX_LEN           (12 * 1024)
-#define SXE_PRODUCT_NAME_LEN        (32)       
+#define SXE_VERION_LEN				  (32)
+#define SXE_MAC_NUM					 (128)
+#define SXE_PORT_TRANSCEIVER_LEN		(32)
+#define SXE_PORT_VENDOR_LEN			 (32)
+#define SXE_CHIP_TYPE_LEN			   (32)
+#define SXE_VPD_SN_LEN				  (16)
+#define SXE_SOC_RST_TIME				(0x93A80)
+#define SXE_SFP_TEMP_THRESHOLD_INTERVAL (3)
+#define MGC_TERMLOG_INFO_MAX_LEN		(12 * 1024)
+#define SXE_REGS_DUMP_MAX_LEN		   (12 * 1024)
+#define SXE_PRODUCT_NAME_LEN		(32)
 
 typedef enum sxe_led_mode {
-    SXE_IDENTIFY_LED_BLINK_ON   = 0,    
-    SXE_IDENTIFY_LED_BLINK_OFF,         
-    SXE_IDENTIFY_LED_ON,                
-    SXE_IDENTIFY_LED_OFF,               
-    SXE_IDENTIFY_LED_RESET,             
+	SXE_IDENTIFY_LED_BLINK_ON   = 0,
+	SXE_IDENTIFY_LED_BLINK_OFF,
+	SXE_IDENTIFY_LED_ON,
+	SXE_IDENTIFY_LED_OFF,
+	SXE_IDENTIFY_LED_RESET,
 } sxe_led_mode_s;
 
 typedef struct sxe_led_ctrl {
-    U32    mode;      
-    U32    duration;  
+	U32	mode;
+	U32	duration;
 
 } sxe_led_ctrl_s;
 
 typedef struct sxe_led_ctrl_resp {
-    U32    ack;       
+	U32	ack;
 } sxe_led_ctrl_resp_s;
 
 typedef enum PortLinkSpeed {
-    PORT_LINK_NO            = 0,     
-    PORT_LINK_100M          = 1,     
-    PORT_LINK_1G            = 2,     
-    PORT_LINK_10G           = 3,     
+	PORT_LINK_NO			= 0,
+	PORT_LINK_100M		  = 1,
+	PORT_LINK_1G			= 2,
+	PORT_LINK_10G		   = 3,
 } PortLinkSpeed_e;
 
 typedef struct SysSocInfo {
-    S8     fwVer[SXE_VERION_LEN];        
-    S8     optVer[SXE_VERION_LEN];       
-    U8     socStatus;                    
-    U8     pad[3];
-    S32    socTemp;                      
-    U64    chipId;                       
-    S8     chipType[SXE_CHIP_TYPE_LEN];  
-    S8     pba[SXE_VPD_SN_LEN];          
-    S8     productName[SXE_PRODUCT_NAME_LEN];   
+	S8	 fwVer[SXE_VERION_LEN];
+	S8	 optVer[SXE_VERION_LEN];
+	U8	 socStatus;
+	U8	 pad[3];
+	S32	socTemp;
+	U64	chipId;
+	S8	 chipType[SXE_CHIP_TYPE_LEN];
+	S8	 pba[SXE_VPD_SN_LEN];
+	S8	 productName[SXE_PRODUCT_NAME_LEN];
 } SysSocInfo_s;
 
 typedef struct SysPortInfo {
-    U64    mac[SXE_MAC_NUM];         
-    U8     isPortAbs;                
-    U8     linkStat;                 
-    U8     linkSpeed;                
-
-
-    U8     isSfp:1;                                     
-    U8     isGetInfo:1;                                 
-    U8     rvd:6;                                       
-    S8     opticalModTemp;                              
-    U8     pad[3];
-    S8     transceiverType[SXE_PORT_TRANSCEIVER_LEN];   
-    S8     vendorName[SXE_PORT_VENDOR_LEN];             
-    S8     vendorPn[SXE_PORT_VENDOR_LEN];               
+	U64	mac[SXE_MAC_NUM];
+	U8	 isPortAbs;
+	U8	 linkStat;
+	U8	 linkSpeed;
+
+
+	U8	 isSfp:1;
+	U8	 isGetInfo:1;
+	U8	 rvd:6;
+	S8	 opticalModTemp;
+	U8	 pad[3];
+	S8	 transceiverType[SXE_PORT_TRANSCEIVER_LEN];
+	S8	 vendorName[SXE_PORT_VENDOR_LEN];
+	S8	 vendorPn[SXE_PORT_VENDOR_LEN];
 } SysPortInfo_s;
 
 typedef struct SysInfoResp {
-    SysSocInfo_s     socInfo;        
-    SysPortInfo_s    portInfo;       
+	SysSocInfo_s	 socInfo;
+	SysPortInfo_s	portInfo;
 } SysInfoResp_s;
 
 typedef enum SfpTempTdMode {
-    SFP_TEMP_THRESHOLD_MODE_ALARM   = 0,
-    SFP_TEMP_THRESHOLD_MODE_WARN,
+	SFP_TEMP_THRESHOLD_MODE_ALARM   = 0,
+	SFP_TEMP_THRESHOLD_MODE_WARN,
 } SfpTempTdMode_e;
 
-typedef struct SfpTempTdSet{
-    U8     mode;             
-    U8     pad[3];
-    S8     hthreshold;       
-    S8     lthreshold;       
+typedef struct SfpTempTdSet {
+	U8	 mode;
+	U8	 pad[3];
+	S8	 hthreshold;
+	S8	 lthreshold;
 } SfpTempTdSet_s;
 
 typedef struct SxeLogExportResp {
-    U16    curLogLen;       
-    U8     isEnd;
-    U8     pad;
-    S32    sessionId;       
-    S8     data[0];
+	U16	curLogLen;
+	U8	 isEnd;
+	U8	 pad;
+	S32	sessionId;
+	S8	 data[0];
 } SxeLogExportResp_s;
 
 typedef enum SxeLogExportType  {
-    SXE_LOG_EXPORT_REQ    = 0,     
-    SXE_LOG_EXPORT_FIN,            
-    SXE_LOG_EXPORT_ABORT,          
+	SXE_LOG_EXPORT_REQ	= 0,
+	SXE_LOG_EXPORT_FIN,
+	SXE_LOG_EXPORT_ABORT,
 } SxeLogExportType_e;
 
 typedef struct SxeLogExportReq {
-    U8     isALLlog;       
-    U8     cmdtype;        
-    U8     isBegin;        
-    U8     pad;
-    S32    sessionId;      
-    U32    logLen;         
+	U8	 isALLlog;
+	U8	 cmdtype;
+	U8	 isBegin;
+	U8	 pad;
+	S32	sessionId;
+	U32	logLen;
 } SxeLogExportReq_s;
 
 typedef struct SocRstReq {
-    U32    time;        
+	U32	time;
 } SocRstReq_s;
 
 typedef struct RegsDumpResp {
-    U32    curdwLen;    
-    U8     data[0];
+	U32	curdwLen;
+	U8	 data[0];
 } RegsDumpResp_s;
 
 enum {
-    SXE_MFG_PART_NUMBER_LEN   = 8,
-    SXE_MFG_SERIAL_NUMBER_LEN = 16,
-    SXE_MFG_REVISION_LEN      = 4,
-    SXE_MFG_OEM_STR_LEN       = 64,
-    SXE_MFG_SXE_BOARD_ASSEMBLY_LEN  = 32,
-    SXE_MFG_SXE_BOARD_TRACE_NUM_LEN = 16,
-    SXE_MFG_SXE_MAC_ADDR_CNT        = 2,
+	SXE_MFG_PART_NUMBER_LEN   = 8,
+	SXE_MFG_SERIAL_NUMBER_LEN = 16,
+	SXE_MFG_REVISION_LEN	  = 4,
+	SXE_MFG_OEM_STR_LEN	   = 64,
+	SXE_MFG_SXE_BOARD_ASSEMBLY_LEN  = 32,
+	SXE_MFG_SXE_BOARD_TRACE_NUM_LEN = 16,
+	SXE_MFG_SXE_MAC_ADDR_CNT		= 2,
 };
 
 typedef struct sxeMfgInfo {
-    U8 partNumber[SXE_MFG_PART_NUMBER_LEN];      
-    U8 serialNumber [SXE_MFG_SERIAL_NUMBER_LEN]; 
-    U32 mfgDate;                               
-    U8 revision[SXE_MFG_REVISION_LEN];         
-    U32 reworkDate;                            
-    U8 pad[4];
-    U64 macAddr[SXE_MFG_SXE_MAC_ADDR_CNT];             
-    U8 boardTraceNum[SXE_MFG_SXE_BOARD_TRACE_NUM_LEN]; 
-    U8 boardAssembly[SXE_MFG_SXE_BOARD_ASSEMBLY_LEN];  
-    U8 extra1[SXE_MFG_OEM_STR_LEN];                    
-    U8 extra2[SXE_MFG_OEM_STR_LEN];                    
+	U8 partNumber[SXE_MFG_PART_NUMBER_LEN];
+	U8 serialNumber[SXE_MFG_SERIAL_NUMBER_LEN];
+	U32 mfgDate;
+	U8 revision[SXE_MFG_REVISION_LEN];
+	U32 reworkDate;
+	U8 pad[4];
+	U64 macAddr[SXE_MFG_SXE_MAC_ADDR_CNT];
+	U8 boardTraceNum[SXE_MFG_SXE_BOARD_TRACE_NUM_LEN];
+	U8 boardAssembly[SXE_MFG_SXE_BOARD_ASSEMBLY_LEN];
+	U8 extra1[SXE_MFG_OEM_STR_LEN];
+	U8 extra2[SXE_MFG_OEM_STR_LEN];
 } sxeMfgInfo_t;
 
+typedef struct SxeLldpInfo {
+	U8	  lldpState;
+	U8	  pad[3];
+} SxeLldpInfo_t;
+
 typedef struct RegsDumpReq {
-    U32    baseAddr;    
-    U32    dwLen;       
+	U32	baseAddr;
+	U32	dwLen;
 } RegsDumpReq_s;
 
 typedef enum sxe_pcs_mode {
-    SXE_PCS_MODE_1000BASE_KX_WO = 0, 
-    SXE_PCS_MODE_1000BASE_KX_W,      
-    SXE_PCS_MODE_SGMII,              
-    SXE_PCS_MODE_10GBASE_KR_WO,      
-    SXE_PCS_MODE_AUTO_NEGT_73,       
-    SXE_PCS_MODE_LPBK_PHY_TX2RX,     
-    SXE_PCS_MODE_LPBK_PHY_RX2TX,     
-    SXE_PCS_MODE_LPBK_PCS_RX2TX,     
-    SXE_PCS_MODE_BUTT,               
+	SXE_PCS_MODE_1000BASE_KX_WO = 0,
+	SXE_PCS_MODE_1000BASE_KX_W,
+	SXE_PCS_MODE_SGMII,
+	SXE_PCS_MODE_10GBASE_KR_WO,
+	SXE_PCS_MODE_AUTO_NEGT_73,
+	SXE_PCS_MODE_LPBK_PHY_TX2RX,
+	SXE_PCS_MODE_LPBK_PHY_RX2TX,
+	SXE_PCS_MODE_LPBK_PCS_RX2TX,
+	SXE_PCS_MODE_BUTT,
 } sxe_pcs_mode_e;
 
 typedef enum sxe_remote_fault_mode {
@@ -174,40 +179,40 @@  typedef enum sxe_remote_fault_mode {
 } sxe_remote_fault_e;
 
 typedef struct sxe_phy_cfg {
-    sxe_pcs_mode_e mode;          
-    U32 mtu;
+	sxe_pcs_mode_e mode;
+	U32 mtu;
 } sxe_pcs_cfg_s;
 
 typedef enum sxe_an_speed {
-    SXE_AN_SPEED_NO_LINK = 0,
-    SXE_AN_SPEED_100M,
-    SXE_AN_SPEED_1G,      
-    SXE_AN_SPEED_10G,     
-    SXE_AN_SPEED_UNKNOWN,
+	SXE_AN_SPEED_NO_LINK = 0,
+	SXE_AN_SPEED_100M,
+	SXE_AN_SPEED_1G,
+	SXE_AN_SPEED_10G,
+	SXE_AN_SPEED_UNKNOWN,
 } sxe_an_speed_e;
 
 typedef enum sxe_phy_pause_cap {
-    SXE_PAUSE_CAP_NO_PAUSE    = 0,   
-    SXE_PAUSE_CAP_ASYMMETRIC_PAUSE,  
-    SXE_PAUSE_CAP_SYMMETRIC_PAUSE,   
-    SXE_PAUSE_CAP_BOTH_PAUSE,        
-    SXE_PAUSE_CAP_UNKNOWN,
+	SXE_PAUSE_CAP_NO_PAUSE	= 0,
+	SXE_PAUSE_CAP_ASYMMETRIC_PAUSE,
+	SXE_PAUSE_CAP_SYMMETRIC_PAUSE,
+	SXE_PAUSE_CAP_BOTH_PAUSE,
+	SXE_PAUSE_CAP_UNKNOWN,
 } sxe_phy_pause_cap_e;
 
 typedef enum sxe_phy_duplex_type {
-    SXE_FULL_DUPLEX	= 0,	  
-    SXE_HALF_DUPLEX	= 1,	  
-    SXE_UNKNOWN_DUPLEX,
+	SXE_FULL_DUPLEX	= 0,
+	SXE_HALF_DUPLEX	= 1,
+	SXE_UNKNOWN_DUPLEX,
 } sxe_phy_duplex_type_e;
 
 typedef struct sxe_phy_an_cap {
-    sxe_remote_fault_e   remote_fault; 
-    sxe_phy_pause_cap_e  pause_cap;    
-    sxe_phy_duplex_type_e duplex_cap;  
+	sxe_remote_fault_e   remote_fault;
+	sxe_phy_pause_cap_e  pause_cap;
+	sxe_phy_duplex_type_e duplex_cap;
 } sxe_phy_an_cap_s;
 
 typedef struct sxe_an_cap {
-    sxe_phy_an_cap_s local;     
-    sxe_phy_an_cap_s peer;      
+	sxe_phy_an_cap_s local;
+	sxe_phy_an_cap_s peer;
 } sxe_an_cap_s;
 #endif
diff --git a/drivers/net/sxe/include/sxe/sxe_hdc.h b/drivers/net/sxe/include/sxe/sxe_hdc.h
index bbdc273bf9..ee69d9afb0 100644
--- a/drivers/net/sxe/include/sxe/sxe_hdc.h
+++ b/drivers/net/sxe/include/sxe/sxe_hdc.h
@@ -9,35 +9,35 @@ 
 #include "sxe_drv_type.h"
 #endif
 
-#define HDC_CACHE_TOTAL_LEN     (16 *1024)    
-#define ONE_PACKET_LEN_MAX      (1024)        
-#define DWORD_NUM               (256)         
-#define HDC_TRANS_RETRY_COUNT   (3)           
+#define HDC_CACHE_TOTAL_LEN	 (16 *1024)
+#define ONE_PACKET_LEN_MAX	  (1024)
+#define DWORD_NUM			   (256)
+#define HDC_TRANS_RETRY_COUNT   (3)
 
 
 typedef enum SxeHdcErrnoCode {
-    PKG_OK            = 0,     
-    PKG_ERR_REQ_LEN,           
-    PKG_ERR_RESP_LEN,          
-    PKG_ERR_PKG_SKIP,          
-    PKG_ERR_NODATA,            
-    PKG_ERR_PF_LK,             
-    PKG_ERR_OTHER,
+	PKG_OK			= 0,
+	PKG_ERR_REQ_LEN,
+	PKG_ERR_RESP_LEN,
+	PKG_ERR_PKG_SKIP,
+	PKG_ERR_NODATA,
+	PKG_ERR_PF_LK,
+	PKG_ERR_OTHER,
 } SxeHdcErrnoCode_e;
 
 typedef union HdcHeader {
-    struct {
-        U8 pid:4;          
-        U8 errCode:4;      
-        U8 len;            
-        U16 startPkg:1;    
-        U16 endPkg:1;      
-        U16 isRd:1;        
-        U16 msi:1;         
-        U16 totalLen:12;   
-    } head;
-    U32 dw0;
+	struct {
+		U8 pid:4;
+		U8 errCode:4;
+		U8 len;
+		U16 startPkg:1;
+		U16 endPkg:1;
+		U16 isRd:1;
+		U16 msi:1;
+		U16 totalLen:12;
+	} head;
+	U32 dw0;
 } HdcHeader_u;
 
-#endif 
+#endif
 
diff --git a/drivers/net/sxe/include/sxe/sxe_ioctl.h b/drivers/net/sxe/include/sxe/sxe_ioctl.h
index 4f39b0f92c..0a796add40 100644
--- a/drivers/net/sxe/include/sxe/sxe_ioctl.h
+++ b/drivers/net/sxe/include/sxe/sxe_ioctl.h
@@ -9,11 +9,11 @@ 
 #endif
 
 struct SxeIoctlSyncCmd {
-    U64   traceid;
-    void *inData;
-    U32   inLen;
-    void *outData;
-    U32   outLen;
+	U64   traceid;
+	void *inData;
+	U32   inLen;
+	void *outData;
+	U32   outLen;
 };
 
 #define SXE_CMD_IOCTL_SYNC_CMD _IOWR('M', 1, struct SxeIoctlSyncCmd)
diff --git a/drivers/net/sxe/include/sxe/sxe_msg.h b/drivers/net/sxe/include/sxe/sxe_msg.h
index 3db4e60ce5..cea8915aa6 100644
--- a/drivers/net/sxe/include/sxe/sxe_msg.h
+++ b/drivers/net/sxe/include/sxe/sxe_msg.h
@@ -15,125 +15,125 @@ 
 #define SXE_HDC_MSG_HDR_SIZE  sizeof(struct sxe_hdc_drv_cmd_msg)
 
 enum sxe_cmd_type {
-    SXE_CMD_TYPE_CLI,
-    SXE_CMD_TYPE_DRV,
-    SXE_CMD_TYPE_UNKOWN,
+	SXE_CMD_TYPE_CLI,
+	SXE_CMD_TYPE_DRV,
+	SXE_CMD_TYPE_UNKNOWN,
 };
 
 typedef struct sxe_hdc_cmd_hdr {
-    U8 cmd_type;       
-    U8 cmd_sub_type;   
-    U8 reserve[6];
+	U8 cmd_type;
+	U8 cmd_sub_type;
+	U8 reserve[6];
 }sxe_hdc_cmd_hdr_s;
 
 
 
 typedef enum SxeFWState {
-    SXE_FW_START_STATE_UNDEFINED    = 0x00,   
-    SXE_FW_START_STATE_INIT_BASE    = 0x10,   
-    SXE_FW_START_STATE_SCAN_DEVICE  = 0x20,   
-    SXE_FW_START_STATE_FINISHED     = 0x30,   
-    SXE_FW_START_STATE_UPGRADE      = 0x31,   
-    SXE_FW_RUNNING_STATE_ABNOMAL    = 0x40,   
-    SXE_FW_START_STATE_MASK         = 0xF0,
+	SXE_FW_START_STATE_UNDEFINED	= 0x00,
+	SXE_FW_START_STATE_INIT_BASE	= 0x10,
+	SXE_FW_START_STATE_SCAN_DEVICE  = 0x20,
+	SXE_FW_START_STATE_FINISHED	 = 0x30,
+	SXE_FW_START_STATE_UPGRADE	  = 0x31,
+	SXE_FW_RUNNING_STATE_ABNOMAL	= 0x40,
+	SXE_FW_START_STATE_MASK		 = 0xF0,
 }SxeFWState_e;
 
 typedef struct SxeFWStateInfo {
-    U8 socStatus;          
-    char statBuff[32];       
+	U8 socStatus;
+	char statBuff[32];
 } SxeFWStateInfo_s;
 
 
 typedef enum MsiEvt {
-    MSI_EVT_SOC_STATUS          = 0x1,
-    MSI_EVT_HDC_FWOV            = 0x2,
-    MSI_EVT_HDC_TIME_SYNC       = 0x4,
+	MSI_EVT_SOC_STATUS		  = 0x1,
+	MSI_EVT_HDC_FWOV			= 0x2,
+	MSI_EVT_HDC_TIME_SYNC	   = 0x4,
 
-    MSI_EVT_MAX                 = 0x80000000,
+	MSI_EVT_MAX				 = 0x80000000,
 } MsiEvt_u;
 
 
 typedef enum SxeFwHdcState {
-    SXE_FW_HDC_TRANSACTION_IDLE = 0x01,
-    SXE_FW_HDC_TRANSACTION_BUSY,
+	SXE_FW_HDC_TRANSACTION_IDLE = 0x01,
+	SXE_FW_HDC_TRANSACTION_BUSY,
 
-    SXE_FW_HDC_TRANSACTION_ERR,
+	SXE_FW_HDC_TRANSACTION_ERR,
 } SxeFwHdcState_e;
 
 enum sxe_hdc_cmd_opcode {
-    SXE_CMD_SET_WOL         = 1,
-    SXE_CMD_LED_CTRL,
-    SXE_CMD_SFP_READ,
-    SXE_CMD_SFP_WRITE,
-    SXE_CMD_TX_DIS_CTRL     = 5,
-    SXE_CMD_TINE_SYNC,
-    SXE_CMD_RATE_SELECT,
-    SXE_CMD_R0_MAC_GET,
-    SXE_CMD_LOG_EXPORT,
-    SXE_CMD_FW_VER_GET  = 10,
-    SXE_CMD_PCS_SDS_INIT,         
-    SXE_CMD_AN_SPEED_GET,         
-    SXE_CMD_AN_CAP_GET,           
-    SXE_CMD_GET_SOC_INFO,         
-    SXE_CMD_MNG_RST = 15,         
-
-    SXE_CMD_MAX,
+	SXE_CMD_SET_WOL		 = 1,
+	SXE_CMD_LED_CTRL,
+	SXE_CMD_SFP_READ,
+	SXE_CMD_SFP_WRITE,
+	SXE_CMD_TX_DIS_CTRL	 = 5,
+	SXE_CMD_TINE_SYNC,
+	SXE_CMD_RATE_SELECT,
+	SXE_CMD_R0_MAC_GET,
+	SXE_CMD_LOG_EXPORT,
+	SXE_CMD_FW_VER_GET  = 10,
+	SXE_CMD_PCS_SDS_INIT,
+	SXE_CMD_AN_SPEED_GET,
+	SXE_CMD_AN_CAP_GET,
+	SXE_CMD_GET_SOC_INFO,
+	SXE_CMD_MNG_RST = 15,
+
+	SXE_CMD_MAX,
 };
 
 enum sxe_hdc_cmd_errcode {
-    SXE_ERR_INVALID_PARAM = 1,
+	SXE_ERR_INVALID_PARAM = 1,
 };
 
 typedef struct sxe_hdc_drv_cmd_msg {
 
-    U16 opcode;
-    U16 errcode;
-    union dataLength {
-        U16 req_len;
-        U16 ack_len;
-    } length;
-    U8 reserve[8];
-    U64 traceid;
-    U8 body[0];
+	U16 opcode;
+	U16 errcode;
+	union dataLength {
+		U16 req_len;
+		U16 ack_len;
+	} length;
+	U8 reserve[8];
+	U64 traceid;
+	U8 body[0];
 } sxe_hdc_drv_cmd_msg_s;
 
 
 typedef struct sxe_sfp_rw_req {
-    U16 offset;       
-    U16 len;          
-    U8  write_data[0];
+	U16 offset;
+	U16 len;
+	U8  write_data[0];
 } sxe_sfp_rw_req_s;
 
 
 typedef struct sxe_sfp_read_resp {
-    U16 len;     
-    U8  resp[0]; 
+	U16 len;
+	U8  resp[0];
 } sxe_sfp_read_resp_s;
 
-typedef enum sxe_sfp_rate{
-    SXE_SFP_RATE_1G     = 0,
-    SXE_SFP_RATE_10G    = 1,
+typedef enum sxe_sfp_rate {
+	SXE_SFP_RATE_1G	 = 0,
+	SXE_SFP_RATE_10G	= 1,
 } sxe_sfp_rate_e;
 
 
 typedef struct sxe_sfp_rate_able {
-    sxe_sfp_rate_e rate;       
+	sxe_sfp_rate_e rate;
 } sxe_sfp_rate_able_s;
 
 
 typedef struct sxe_spp_tx_able {
-    BOOL isDisable;       
+	BOOL isDisable;
 } sxe_spp_tx_able_s;
 
 
 typedef struct sxe_default_mac_addr_resp {
-    U8  addr[SXE_MAC_ADDR_LEN]; 
+	U8  addr[SXE_MAC_ADDR_LEN];
 } sxe_default_mac_addr_resp_s;
 
 
 typedef struct sxe_mng_rst {
-    BOOL enable;       
+	BOOL enable;
 } sxe_mng_rst_s;
 
-#endif 
+#endif
 
diff --git a/drivers/net/sxe/include/sxe/sxe_regs.h b/drivers/net/sxe/include/sxe/sxe_regs.h
index 0652cd4906..aa41f5aa18 100644
--- a/drivers/net/sxe/include/sxe/sxe_regs.h
+++ b/drivers/net/sxe/include/sxe/sxe_regs.h
@@ -1,7 +1,7 @@ 
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright (C), 2022, Linkdata Technology Co., Ltd.
  */
- 
+
 #ifndef __SXE_REGS_H__
 #define __SXE_REGS_H__
 
@@ -20,9 +20,9 @@ 
 #endif
 
 
-#define SXE_CTRL	0x00000 
-#define SXE_STATUS	0x00008 
-#define SXE_CTRL_EXT	0x00018 
+#define SXE_CTRL	0x00000
+#define SXE_STATUS	0x00008
+#define SXE_CTRL_EXT	0x00018
 
 
 #define SXE_CTRL_LNK_RST	0x00000008
@@ -57,7 +57,7 @@ 
 #define SXE_FCCFG_TFCE_PRIORITY	0x00000010
 
 
-#define SXE_GCR_EXT           0x11050 
+#define SXE_GCR_EXT		   0x11050
 
 
 #define SXE_GCR_CMPL_TMOUT_MASK		0x0000F000
@@ -117,7 +117,7 @@ 
 #define SXE_EIMC_EX(i)	(0x00AB0 + (i) * 4)
 #define SXE_EIAM_EX(i)	(0x00AD0 + (i) * 4)
 #define SXE_EITR(i)	(((i) <= 23) ? (0x00820 + ((i) * 4)) : \
-                        	(0x012300 + (((i) - 24) * 4)))
+							(0x012300 + (((i) - 24) * 4)))
 
 #define SXE_SPP_PROC	0x00AD8
 #define SXE_SPP_STATE	0x00AF4
@@ -136,13 +136,13 @@ 
 
 
 #define SXE_EICS_RTX_QUEUE	SXE_EICR_RTX_QUEUE
-#define SXE_EICS_FLOW_NAV	SXE_EICR_FLOW_NAV 
-#define SXE_EICS_MAILBOX	SXE_EICR_MAILBOX  
-#define SXE_EICS_LSC		SXE_EICR_LSC      
-#define SXE_EICS_ECC		SXE_EICR_ECC      
-#define SXE_EICS_HDC		SXE_EICR_HDC      
+#define SXE_EICS_FLOW_NAV	SXE_EICR_FLOW_NAV
+#define SXE_EICS_MAILBOX	SXE_EICR_MAILBOX
+#define SXE_EICS_LSC		SXE_EICR_LSC
+#define SXE_EICS_ECC		SXE_EICR_ECC
+#define SXE_EICS_HDC		SXE_EICR_HDC
 #define SXE_EICS_TCP_TIMER	SXE_EICR_TCP_TIMER
-#define SXE_EICS_OTHER		SXE_EICR_OTHER    
+#define SXE_EICS_OTHER		SXE_EICR_OTHER
 
 
 #define SXE_EIMS_RTX_QUEUE	SXE_EICR_RTX_QUEUE
@@ -156,9 +156,9 @@ 
 #define SXE_EIMS_ENABLE_MASK	(SXE_EIMS_RTX_QUEUE | SXE_EIMS_LSC | \
 					SXE_EIMS_TCP_TIMER | SXE_EIMS_OTHER)
 
-#define SXE_EIMC_FLOW_NAV	SXE_EICR_FLOW_NAV 
-#define SXE_EIMC_LSC		SXE_EICR_LSC      
-#define SXE_EIMC_HDC		SXE_EICR_HDC      
+#define SXE_EIMC_FLOW_NAV	SXE_EICR_FLOW_NAV
+#define SXE_EIMC_LSC		SXE_EICR_LSC
+#define SXE_EIMC_HDC		SXE_EICR_HDC
 
 
 #define SXE_GPIE_SPP0_EN	0x00000001
@@ -204,7 +204,7 @@ 
 #define SXE_RXCSUM		0x05000
 #define SXE_RFCTL		0x05008
 #define SXE_FCTRL		0x05080
-#define SXE_EXVET               0x05078
+#define SXE_EXVET			   0x05078
 #define SXE_VLNCTRL		0x05088
 #define SXE_MCSTCTRL		0x05090
 #define SXE_ETQF(_i)		(0x05128 + ((_i) * 4))
@@ -218,8 +218,8 @@ 
 #define SXE_MPSAR_LOW(_i)	(0x0A600 + ((_i) * 8))
 #define SXE_MPSAR_HIGH(_i)	(0x0A604 + ((_i) * 8))
 #define SXE_PSRTYPE(_i)		(0x0EA00 + ((_i) * 4))
-#define SXE_RETA(_i)		(0x0EB00 + ((_i) * 4)) 
-#define SXE_RSSRK(_i)		(0x0EB80 + ((_i) * 4)) 
+#define SXE_RETA(_i)		(0x0EB00 + ((_i) * 4))
+#define SXE_RSSRK(_i)		(0x0EB80 + ((_i) * 4))
 #define SXE_RQTC		0x0EC70
 #define SXE_MRQC		0x0EC80
 #define SXE_IEOI		0x0F654
@@ -242,8 +242,8 @@ 
 #define SXE_LPL_DEFAULT			0x26000000
 
 
-#define SXE_RXCSUM_IPPCSE	0x00001000  
-#define SXE_RXCSUM_PCSD		0x00002000  
+#define SXE_RXCSUM_IPPCSE	0x00001000
+#define SXE_RXCSUM_PCSD		0x00002000
 
 
 #define SXE_RFCTL_LRO_DIS	0x00000020
@@ -259,14 +259,14 @@ 
 #define SXE_FCTRL_DPF		0x00002000
 
 
-#define SXE_VLNCTRL_VET		0x0000FFFF 
-#define SXE_VLNCTRL_CFI		0x10000000 
-#define SXE_VLNCTRL_CFIEN	0x20000000 
-#define SXE_VLNCTRL_VFE		0x40000000 
-#define SXE_VLNCTRL_VME		0x80000000 
+#define SXE_VLNCTRL_VET		0x0000FFFF
+#define SXE_VLNCTRL_CFI		0x10000000
+#define SXE_VLNCTRL_CFIEN	0x20000000
+#define SXE_VLNCTRL_VFE		0x40000000
+#define SXE_VLNCTRL_VME		0x80000000
 
-#define SXE_EXVET_VET_EXT_SHIFT              16
-#define SXE_EXTENDED_VLAN	             (1 << 26)
+#define SXE_EXVET_VET_EXT_SHIFT			  16
+#define SXE_EXTENDED_VLAN				 (1 << 26)
 
 
 #define SXE_MCSTCTRL_MFE	4
@@ -290,10 +290,10 @@ 
 #define SXE_ETQS_QUEUE_EN	0x80000000
 
 
-#define SXE_SYN_FILTER_ENABLE         0x00000001
-#define SXE_SYN_FILTER_QUEUE          0x000000FE
-#define SXE_SYN_FILTER_QUEUE_SHIFT    1
-#define SXE_SYN_FILTER_SYNQFP         0x80000000
+#define SXE_SYN_FILTER_ENABLE		 0x00000001
+#define SXE_SYN_FILTER_QUEUE		  0x000000FE
+#define SXE_SYN_FILTER_QUEUE_SHIFT	1
+#define SXE_SYN_FILTER_SYNQFP		 0x80000000
 
 
 #define SXE_RAH_VIND_MASK	0x003C0000
@@ -309,26 +309,26 @@ 
 #define SXE_PSRTYPE_L2HDR	0x00001000
 
 
-#define SXE_MRQC_RSSEN                 0x00000001 
-#define SXE_MRQC_MRQE_MASK                    0xF
-#define SXE_MRQC_RT8TCEN               0x00000002
-#define SXE_MRQC_RT4TCEN               0x00000003
-#define SXE_MRQC_RTRSS8TCEN            0x00000004
-#define SXE_MRQC_RTRSS4TCEN            0x00000005
-#define SXE_MRQC_VMDQEN                0x00000008
-#define SXE_MRQC_VMDQRSS32EN           0x0000000A
-#define SXE_MRQC_VMDQRSS64EN           0x0000000B
-#define SXE_MRQC_VMDQRT8TCEN           0x0000000C
-#define SXE_MRQC_VMDQRT4TCEN           0x0000000D
-#define SXE_MRQC_RSS_FIELD_MASK        0xFFFF0000
-#define SXE_MRQC_RSS_FIELD_IPV4_TCP    0x00010000
-#define SXE_MRQC_RSS_FIELD_IPV4        0x00020000
+#define SXE_MRQC_RSSEN				 0x00000001
+#define SXE_MRQC_MRQE_MASK					0xF
+#define SXE_MRQC_RT8TCEN			   0x00000002
+#define SXE_MRQC_RT4TCEN			   0x00000003
+#define SXE_MRQC_RTRSS8TCEN			0x00000004
+#define SXE_MRQC_RTRSS4TCEN			0x00000005
+#define SXE_MRQC_VMDQEN				0x00000008
+#define SXE_MRQC_VMDQRSS32EN		   0x0000000A
+#define SXE_MRQC_VMDQRSS64EN		   0x0000000B
+#define SXE_MRQC_VMDQRT8TCEN		   0x0000000C
+#define SXE_MRQC_VMDQRT4TCEN		   0x0000000D
+#define SXE_MRQC_RSS_FIELD_MASK		0xFFFF0000
+#define SXE_MRQC_RSS_FIELD_IPV4_TCP	0x00010000
+#define SXE_MRQC_RSS_FIELD_IPV4		0x00020000
 #define SXE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
-#define SXE_MRQC_RSS_FIELD_IPV6_EX     0x00080000
-#define SXE_MRQC_RSS_FIELD_IPV6        0x00100000
-#define SXE_MRQC_RSS_FIELD_IPV6_TCP    0x00200000
-#define SXE_MRQC_RSS_FIELD_IPV4_UDP    0x00400000
-#define SXE_MRQC_RSS_FIELD_IPV6_UDP    0x00800000
+#define SXE_MRQC_RSS_FIELD_IPV6_EX	 0x00080000
+#define SXE_MRQC_RSS_FIELD_IPV6		0x00100000
+#define SXE_MRQC_RSS_FIELD_IPV6_TCP	0x00200000
+#define SXE_MRQC_RSS_FIELD_IPV4_UDP	0x00400000
+#define SXE_MRQC_RSS_FIELD_IPV6_UDP	0x00800000
 #define SXE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
 
 
@@ -348,9 +348,9 @@ 
 					(0x0D028 + (((_i) - 64) * 0x40)))
 #define SXE_LROCTL(_i)		(((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
 					(0x0D02C + (((_i) - 64) * 0x40)))
-#define SXE_RDRXCTL		0x02F00  
-#define SXE_RXCTRL		0x03000 
-#define SXE_LRODBU 		0x03028  
+#define SXE_RDRXCTL		0x02F00
+#define SXE_RXCTRL		0x03000
+#define SXE_LRODBU		0x03028
 #define SXE_RXPBSIZE(_i)	(0x03C00 + ((_i) * 4))
 
 #define SXE_DRXCFG		(0x03C20)
@@ -370,9 +370,9 @@ 
 #define SXE_SRRCTL_BSIZEHDR_MASK	0x00003F00
 
 
-#define SXE_RXDCTL_ENABLE	0x02000000 
-#define SXE_RXDCTL_SWFLSH	0x04000000 
-#define SXE_RXDCTL_VME		0x40000000 
+#define SXE_RXDCTL_ENABLE	0x02000000
+#define SXE_RXDCTL_SWFLSH	0x04000000
+#define SXE_RXDCTL_VME		0x40000000
 #define SXE_RXDCTL_DESC_FIFO_AE_TH_SHIFT	8
 #define SXE_RXDCTL_PREFETCH_NUM_CFG_SHIFT	16
 
@@ -409,11 +409,11 @@ 
 #define SXE_LRODBU_LROACKDIS	0x00000080
 
 
-#define SXE_DRXCFG_GSP_ZERO    0x00000002
+#define SXE_DRXCFG_GSP_ZERO	0x00000002
 #define SXE_DRXCFG_DBURX_START 0x00000001
 
 
-#define SXE_DMATXCTL		0x04A80   
+#define SXE_DMATXCTL		0x04A80
 #define SXE_TDBAL(_i)		(0x06000 + ((_i) * 0x40))
 #define SXE_TDBAH(_i)		(0x06004 + ((_i) * 0x40))
 #define SXE_TDLEN(_i)		(0x06008 + ((_i) * 0x40))
@@ -424,25 +424,25 @@ 
 #define SXE_PVFTDWBAH(p)	(0x0603C + (0x40 * (p)))
 #define SXE_TXPBSIZE(_i)	(0x0CC00 + ((_i) * 4))
 #define SXE_TXPBTHRESH(_i)	(0x04950 + ((_i) * 4))
-#define SXE_MTQC		0x08120               
-#define SXE_TXPBFCS		0x0CE00               
-#define SXE_DTXCFG		0x0CE08               
-#define SXE_DTMPCNT		0x0CE98               
+#define SXE_MTQC		0x08120
+#define SXE_TXPBFCS		0x0CE00
+#define SXE_DTXCFG		0x0CE08
+#define SXE_DTMPCNT		0x0CE98
 
 
 #define SXE_DMATXCTL_DEFAULT		0x81000000
 
 
-#define SXE_DMATXCTL_TE		0x1       
-#define SXE_DMATXCTL_GDV	0x8       
-#define SXE_DMATXCTL_VT_SHIFT	16        
-#define SXE_DMATXCTL_VT_MASK    0xFFFF0000
+#define SXE_DMATXCTL_TE		0x1
+#define SXE_DMATXCTL_GDV	0x8
+#define SXE_DMATXCTL_VT_SHIFT	16
+#define SXE_DMATXCTL_VT_MASK	0xFFFF0000
 
 
 #define SXE_TXDCTL_HTHRESH_SHIFT 8
 #define SXE_TXDCTL_WTHRESH_SHIFT 16
-#define SXE_TXDCTL_ENABLE     0x02000000
-#define SXE_TXDCTL_SWFLSH     0x04000000
+#define SXE_TXDCTL_ENABLE	 0x02000000
+#define SXE_TXDCTL_SWFLSH	 0x04000000
 
 #define SXE_PVFTDWBAL_N(ring_per_pool, vf_idx, vf_ring_idx) \
 		SXE_PVFTDWBAL((ring_per_pool) * (vf_idx) + vf_ring_idx)
@@ -470,7 +470,7 @@ 
 #define SXE_TFCS_PB_MASK	0xff
 
 
-#define SXE_DTXCFG_DBUTX_START	0x00000001   
+#define SXE_DTXCFG_DBUTX_START	0x00000001
 #define SXE_DTXCFG_DBUTX_BUF_ALFUL_CFG	0x20
 
 
@@ -494,7 +494,7 @@ 
 
 
 #define SXE_RTRPT4C_MCL_SHIFT	12
-#define SXE_RTRPT4C_BWG_SHIFT	9 
+#define SXE_RTRPT4C_BWG_SHIFT	9
 #define SXE_RTRPT4C_GSP		0x40000000
 #define SXE_RTRPT4C_LSP		0x80000000
 
@@ -537,40 +537,40 @@ 
 #define SXE_RTTPCS_ARBDIS	0x00000040
 #define SXE_RTTPCS_TPRM		0x00000100
 #define SXE_RTTPCS_ARBD_SHIFT	22
-#define SXE_RTTPCS_ARBD_DCB	0x4       
+#define SXE_RTTPCS_ARBD_DCB	0x4
 
 
 #define SXE_RTTPT2C_MCL_SHIFT 12
 #define SXE_RTTPT2C_BWG_SHIFT 9
-#define SXE_RTTPT2C_GSP       0x40000000
-#define SXE_RTTPT2C_LSP       0x80000000
+#define SXE_RTTPT2C_GSP	   0x40000000
+#define SXE_RTTPT2C_LSP	   0x80000000
 
 
 #define SXE_TPH_CTRL		0x11074
-#define SXE_TPH_TXCTRL(_i)      (0x0600C + ((_i) * 0x40))
+#define SXE_TPH_TXCTRL(_i)	  (0x0600C + ((_i) * 0x40))
 #define SXE_TPH_RXCTRL(_i)	(((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
 				 (0x0D00C + (((_i) - 64) * 0x40)))
 
 
 #define SXE_TPH_CTRL_ENABLE		0x00000000
 #define SXE_TPH_CTRL_DISABLE		0x00000001
-#define SXE_TPH_CTRL_MODE_CB1		0x00      
-#define SXE_TPH_CTRL_MODE_CB2		0x02      
+#define SXE_TPH_CTRL_MODE_CB1		0x00
+#define SXE_TPH_CTRL_MODE_CB2		0x02
 
 
-#define SXE_TPH_RXCTRL_DESC_TPH_EN	BIT(5) 
-#define SXE_TPH_RXCTRL_HEAD_TPH_EN	BIT(6) 
-#define SXE_TPH_RXCTRL_DATA_TPH_EN	BIT(7) 
-#define SXE_TPH_RXCTRL_DESC_RRO_EN	BIT(9) 
+#define SXE_TPH_RXCTRL_DESC_TPH_EN	BIT(5)
+#define SXE_TPH_RXCTRL_HEAD_TPH_EN	BIT(6)
+#define SXE_TPH_RXCTRL_DATA_TPH_EN	BIT(7)
+#define SXE_TPH_RXCTRL_DESC_RRO_EN	BIT(9)
 #define SXE_TPH_RXCTRL_DATA_WRO_EN	BIT(13)
 #define SXE_TPH_RXCTRL_HEAD_WRO_EN	BIT(15)
-#define SXE_TPH_RXCTRL_CPUID_SHIFT	24     
+#define SXE_TPH_RXCTRL_CPUID_SHIFT	24
 
-#define SXE_TPH_TXCTRL_DESC_TPH_EN	BIT(5) 
-#define SXE_TPH_TXCTRL_DESC_RRO_EN	BIT(9) 
+#define SXE_TPH_TXCTRL_DESC_TPH_EN	BIT(5)
+#define SXE_TPH_TXCTRL_DESC_RRO_EN	BIT(9)
 #define SXE_TPH_TXCTRL_DESC_WRO_EN	BIT(11)
 #define SXE_TPH_TXCTRL_DATA_RRO_EN	BIT(13)
-#define SXE_TPH_TXCTRL_CPUID_SHIFT	24     
+#define SXE_TPH_TXCTRL_CPUID_SHIFT	24
 
 
 #define SXE_SECTXCTRL		0x08800
@@ -579,18 +579,18 @@ 
 #define SXE_SECTXMINIFG		0x08810
 #define SXE_SECRXCTRL		0x08D00
 #define SXE_SECRXSTAT		0x08D04
-#define SXE_LSECTXCTRL            0x08A04
-#define SXE_LSECTXSCL             0x08A08
-#define SXE_LSECTXSCH             0x08A0C
-#define SXE_LSECTXSA              0x08A10
-#define SXE_LSECTXPN(_n)          (0x08A14 + (4 * (_n)))
-#define SXE_LSECTXKEY(_n, _m)     (0x08A1C + ((0x10 * (_n)) + (4 * (_m))))
-#define SXE_LSECRXCTRL            0x08B04
-#define SXE_LSECRXSCL             0x08B08
-#define SXE_LSECRXSCH             0x08B0C
-#define SXE_LSECRXSA(_i)          (0x08B10 + (4 * (_i)))
-#define SXE_LSECRXPN(_i)          (0x08B18 + (4 * (_i)))
-#define SXE_LSECRXKEY(_n, _m)     (0x08B20 + ((0x10 * (_n)) + (4 * (_m))))  
+#define SXE_LSECTXCTRL			0x08A04
+#define SXE_LSECTXSCL			 0x08A08
+#define SXE_LSECTXSCH			 0x08A0C
+#define SXE_LSECTXSA			  0x08A10
+#define SXE_LSECTXPN(_n)		  (0x08A14 + (4 * (_n)))
+#define SXE_LSECTXKEY(_n, _m)	 (0x08A1C + ((0x10 * (_n)) + (4 * (_m))))
+#define SXE_LSECRXCTRL			0x08B04
+#define SXE_LSECRXSCL			 0x08B08
+#define SXE_LSECRXSCH			 0x08B0C
+#define SXE_LSECRXSA(_i)		  (0x08B10 + (4 * (_i)))
+#define SXE_LSECRXPN(_i)		  (0x08B18 + (4 * (_i)))
+#define SXE_LSECRXKEY(_n, _m)	 (0x08B20 + ((0x10 * (_n)) + (4 * (_m))))
 
 
 #define SXE_SECTXCTRL_SECTX_DIS		0x00000001
@@ -605,7 +605,7 @@ 
 
 #define SXE_SECRXCTRL_SECRX_DIS		0x00000001
 #define SXE_SECRXCTRL_RX_DIS		0x00000002
-#define SXE_SECRXCTRL_RP              0x00000080
+#define SXE_SECRXCTRL_RP			  0x00000080
 
 
 #define SXE_SECRXSTAT_SECRX_RDY		0x00000001
@@ -614,41 +614,41 @@ 
 
 #define SXE_SECTX_DCB_ENABLE_MASK	0x00001F00
 
-#define SXE_LSECTXCTRL_EN_MASK        0x00000003
-#define SXE_LSECTXCTRL_EN_SHIFT       0
-#define SXE_LSECTXCTRL_ES             0x00000010
-#define SXE_LSECTXCTRL_AISCI          0x00000020
+#define SXE_LSECTXCTRL_EN_MASK		0x00000003
+#define SXE_LSECTXCTRL_EN_SHIFT	   0
+#define SXE_LSECTXCTRL_ES			 0x00000010
+#define SXE_LSECTXCTRL_AISCI		  0x00000020
 #define SXE_LSECTXCTRL_PNTHRSH_MASK   0xFFFFFF00
 #define SXE_LSECTXCTRL_PNTHRSH_SHIFT  8
-#define SXE_LSECTXCTRL_RSV_MASK       0x000000D8
+#define SXE_LSECTXCTRL_RSV_MASK	   0x000000D8
 
-#define SXE_LSECRXCTRL_EN_MASK        0x0000000C
-#define SXE_LSECRXCTRL_EN_SHIFT       2
-#define SXE_LSECRXCTRL_DROP_EN        0x00000010
+#define SXE_LSECRXCTRL_EN_MASK		0x0000000C
+#define SXE_LSECRXCTRL_EN_SHIFT	   2
+#define SXE_LSECRXCTRL_DROP_EN		0x00000010
 #define SXE_LSECRXCTRL_DROP_EN_SHIFT  4
-#define SXE_LSECRXCTRL_PLSH           0x00000040
-#define SXE_LSECRXCTRL_PLSH_SHIFT     6
-#define SXE_LSECRXCTRL_RP             0x00000080
-#define SXE_LSECRXCTRL_RP_SHIFT       7
-#define SXE_LSECRXCTRL_RSV_MASK       0xFFFFFF33
-
-#define SXE_LSECTXSA_AN0_MASK         0x00000003
-#define SXE_LSECTXSA_AN0_SHIFT        0
-#define SXE_LSECTXSA_AN1_MASK         0x0000000C
-#define SXE_LSECTXSA_AN1_SHIFT        2
-#define SXE_LSECTXSA_SELSA            0x00000010
-#define SXE_LSECTXSA_SELSA_SHIFT      4
-#define SXE_LSECTXSA_ACTSA            0x00000020
-
-#define SXE_LSECRXSA_AN_MASK          0x00000003
-#define SXE_LSECRXSA_AN_SHIFT         0
-#define SXE_LSECRXSA_SAV              0x00000004
-#define SXE_LSECRXSA_SAV_SHIFT        2
-#define SXE_LSECRXSA_RETIRED          0x00000010
-#define SXE_LSECRXSA_RETIRED_SHIFT    4
-
-#define SXE_LSECRXSCH_PI_MASK         0xFFFF0000
-#define SXE_LSECRXSCH_PI_SHIFT        16
+#define SXE_LSECRXCTRL_PLSH		   0x00000040
+#define SXE_LSECRXCTRL_PLSH_SHIFT	 6
+#define SXE_LSECRXCTRL_RP			 0x00000080
+#define SXE_LSECRXCTRL_RP_SHIFT	   7
+#define SXE_LSECRXCTRL_RSV_MASK	   0xFFFFFF33
+
+#define SXE_LSECTXSA_AN0_MASK		 0x00000003
+#define SXE_LSECTXSA_AN0_SHIFT		0
+#define SXE_LSECTXSA_AN1_MASK		 0x0000000C
+#define SXE_LSECTXSA_AN1_SHIFT		2
+#define SXE_LSECTXSA_SELSA			0x00000010
+#define SXE_LSECTXSA_SELSA_SHIFT	  4
+#define SXE_LSECTXSA_ACTSA			0x00000020
+
+#define SXE_LSECRXSA_AN_MASK		  0x00000003
+#define SXE_LSECRXSA_AN_SHIFT		 0
+#define SXE_LSECRXSA_SAV			  0x00000004
+#define SXE_LSECRXSA_SAV_SHIFT		2
+#define SXE_LSECRXSA_RETIRED		  0x00000010
+#define SXE_LSECRXSA_RETIRED_SHIFT	4
+
+#define SXE_LSECRXSCH_PI_MASK		 0xFFFF0000
+#define SXE_LSECRXSCH_PI_SHIFT		16
 
 #define SXE_LSECTXCTRL_DISABLE	0x0
 #define SXE_LSECTXCTRL_AUTH		0x1
@@ -658,7 +658,7 @@ 
 #define SXE_LSECRXCTRL_CHECK		0x1
 #define SXE_LSECRXCTRL_STRICT		0x2
 #define SXE_LSECRXCTRL_DROP		0x3
-#define SXE_SECTXCTRL_STORE_FORWARD_ENABLE    0x4
+#define SXE_SECTXCTRL_STORE_FORWARD_ENABLE	0x4
 
 
 
@@ -757,34 +757,34 @@ 
 #define SXE_PXOFFRXCNT(_i)	(0x04160 + ((_i) * 4))
 
 #define SXE_EPC_GPRC		0x050E0
-#define SXE_RXDGPC              0x02F50
-#define SXE_RXDGBCL             0x02F54
-#define SXE_RXDGBCH             0x02F58
-#define SXE_RXDDGPC             0x02F5C
-#define SXE_RXDDGBCL            0x02F60
-#define SXE_RXDDGBCH            0x02F64
-#define SXE_RXLPBKGPC           0x02F68
-#define SXE_RXLPBKGBCL          0x02F6C
-#define SXE_RXLPBKGBCH          0x02F70
-#define SXE_RXDLPBKGPC          0x02F74
-#define SXE_RXDLPBKGBCL         0x02F78
-#define SXE_RXDLPBKGBCH         0x02F7C
-
-#define SXE_RXTPCIN             0x02F88
-#define SXE_RXTPCOUT            0x02F8C
-#define SXE_RXPRDDC             0x02F9C
+#define SXE_RXDGPC			  0x02F50
+#define SXE_RXDGBCL			 0x02F54
+#define SXE_RXDGBCH			 0x02F58
+#define SXE_RXDDGPC			 0x02F5C
+#define SXE_RXDDGBCL			0x02F60
+#define SXE_RXDDGBCH			0x02F64
+#define SXE_RXLPBKGPC		   0x02F68
+#define SXE_RXLPBKGBCL		  0x02F6C
+#define SXE_RXLPBKGBCH		  0x02F70
+#define SXE_RXDLPBKGPC		  0x02F74
+#define SXE_RXDLPBKGBCL		 0x02F78
+#define SXE_RXDLPBKGBCH		 0x02F7C
+
+#define SXE_RXTPCIN			 0x02F88
+#define SXE_RXTPCOUT			0x02F8C
+#define SXE_RXPRDDC			 0x02F9C
 
 #define SXE_TXDGPC		0x087A0
-#define SXE_TXDGBCL             0x087A4
-#define SXE_TXDGBCH             0x087A8
-#define SXE_TXSWERR             0x087B0
-#define SXE_TXSWITCH            0x087B4
-#define SXE_TXREPEAT            0x087B8
-#define SXE_TXDESCERR           0x087BC
+#define SXE_TXDGBCL			 0x087A4
+#define SXE_TXDGBCH			 0x087A8
+#define SXE_TXSWERR			 0x087B0
+#define SXE_TXSWITCH			0x087B4
+#define SXE_TXREPEAT			0x087B8
+#define SXE_TXDESCERR		   0x087BC
 #define SXE_MNGPRC		0x040B4
 #define SXE_MNGPDC		0x040B8
-#define SXE_RQSMR(_i)		(0x02300 + ((_i) * 4))   
-#define SXE_TQSM(_i)		(0x08600 + ((_i) * 4))   
+#define SXE_RQSMR(_i)		(0x02300 + ((_i) * 4))
+#define SXE_TQSM(_i)		(0x08600 + ((_i) * 4))
 #define SXE_QPRC(_i)		(0x01030 + ((_i) * 0x40))
 #define SXE_QBRC_L(_i)		(0x01034 + ((_i) * 0x40))
 #define SXE_QBRC_H(_i)		(0x01038 + ((_i) * 0x40))
@@ -792,9 +792,9 @@ 
 
 #define SXE_QPRDC(_i)		(0x01430 + ((_i) * 0x40))
 #define SXE_QPTC(_i)		(0x08680 + ((_i) * 0x4))
-#define SXE_QBTC_L(_i)		(0x08700 + ((_i) * 0x8)) 
-#define SXE_QBTC_H(_i)		(0x08704 + ((_i) * 0x8)) 
-#define SXE_SSVPC		0x08780                  
+#define SXE_QBTC_L(_i)		(0x08700 + ((_i) * 0x8))
+#define SXE_QBTC_H(_i)		(0x08704 + ((_i) * 0x8))
+#define SXE_SSVPC		0x08780
 #define SXE_MNGPTC		0x0CF90
 #define SXE_MPC(_i)		(0x03FA0 + ((_i) * 4))
 
@@ -808,91 +808,91 @@ 
 
 
 
-#define SXE_WUC                       0x05800
-#define SXE_WUFC                      0x05808
-#define SXE_WUS                       0x05810
-#define SXE_IP6AT(_i)                 (0x05880 + ((_i) * 4))   
+#define SXE_WUC					   0x05800
+#define SXE_WUFC					  0x05808
+#define SXE_WUS					   0x05810
+#define SXE_IP6AT(_i)				 (0x05880 + ((_i) * 4))
 
 
-#define SXE_IP6AT_CNT                 4
+#define SXE_IP6AT_CNT				 4
 
 
-#define SXE_WUC_PME_EN                0x00000002
-#define SXE_WUC_PME_STATUS            0x00000004
-#define SXE_WUC_WKEN                  0x00000010
-#define SXE_WUC_APME                  0x00000020
+#define SXE_WUC_PME_EN				0x00000002
+#define SXE_WUC_PME_STATUS			0x00000004
+#define SXE_WUC_WKEN				  0x00000010
+#define SXE_WUC_APME				  0x00000020
 
 
-#define SXE_WUFC_LNKC                 0x00000001
-#define SXE_WUFC_MAG                  0x00000002
-#define SXE_WUFC_EX                   0x00000004
-#define SXE_WUFC_MC                   0x00000008
-#define SXE_WUFC_BC                   0x00000010
-#define SXE_WUFC_ARP                  0x00000020
-#define SXE_WUFC_IPV4                 0x00000040
-#define SXE_WUFC_IPV6                 0x00000080
-#define SXE_WUFC_MNG                  0x00000100
+#define SXE_WUFC_LNKC				 0x00000001
+#define SXE_WUFC_MAG				  0x00000002
+#define SXE_WUFC_EX				   0x00000004
+#define SXE_WUFC_MC				   0x00000008
+#define SXE_WUFC_BC				   0x00000010
+#define SXE_WUFC_ARP				  0x00000020
+#define SXE_WUFC_IPV4				 0x00000040
+#define SXE_WUFC_IPV6				 0x00000080
+#define SXE_WUFC_MNG				  0x00000100
 
 
 
 
-#define SXE_TSCTRL              0x14800
-#define SXE_TSES                0x14804
-#define SXE_TSYNCTXCTL          0x14810
-#define SXE_TSYNCRXCTL          0x14820
-#define SXE_RXSTMPL             0x14824
-#define SXE_RXSTMPH             0x14828
-#define SXE_SYSTIML             0x14840
-#define SXE_SYSTIMM             0x14844
-#define SXE_SYSTIMH             0x14848
-#define SXE_TIMADJL             0x14850
-#define SXE_TIMADJH             0x14854
-#define SXE_TIMINC              0x14860
+#define SXE_TSCTRL			  0x14800
+#define SXE_TSES				0x14804
+#define SXE_TSYNCTXCTL		  0x14810
+#define SXE_TSYNCRXCTL		  0x14820
+#define SXE_RXSTMPL			 0x14824
+#define SXE_RXSTMPH			 0x14828
+#define SXE_SYSTIML			 0x14840
+#define SXE_SYSTIMM			 0x14844
+#define SXE_SYSTIMH			 0x14848
+#define SXE_TIMADJL			 0x14850
+#define SXE_TIMADJH			 0x14854
+#define SXE_TIMINC			  0x14860
 
 
-#define SXE_TSYNCTXCTL_TXTT     0x0001
-#define SXE_TSYNCTXCTL_TEN      0x0010
+#define SXE_TSYNCTXCTL_TXTT	 0x0001
+#define SXE_TSYNCTXCTL_TEN	  0x0010
 
 
-#define SXE_TSYNCRXCTL_RXTT     0x0001
-#define SXE_TSYNCRXCTL_REN      0x0010
+#define SXE_TSYNCRXCTL_RXTT	 0x0001
+#define SXE_TSYNCRXCTL_REN	  0x0010
 
 
-#define SXE_TSCTRL_TSSEL        0x00001
-#define SXE_TSCTRL_TSEN         0x00002
-#define SXE_TSCTRL_VER_2        0x00010
-#define SXE_TSCTRL_ONESTEP      0x00100
-#define SXE_TSCTRL_CSEN         0x01000
-#define SXE_TSCTRL_PTYP_ALL     0x00C00
+#define SXE_TSCTRL_TSSEL		0x00001
+#define SXE_TSCTRL_TSEN		 0x00002
+#define SXE_TSCTRL_VER_2		0x00010
+#define SXE_TSCTRL_ONESTEP	  0x00100
+#define SXE_TSCTRL_CSEN		 0x01000
+#define SXE_TSCTRL_PTYP_ALL	 0x00C00
 #define SXE_TSCTRL_L4_UNICAST   0x08000
 
 
-#define SXE_TSES_TXES                   0x00200
-#define SXE_TSES_RXES                   0x00800
-#define SXE_TSES_TXES_V1_SYNC           0x00000
-#define SXE_TSES_TXES_V1_DELAY_REQ      0x00100
-#define SXE_TSES_TXES_V1_ALL            0x00200
-#define SXE_TSES_RXES_V1_SYNC           0x00000
-#define SXE_TSES_RXES_V1_DELAY_REQ      0x00400
-#define SXE_TSES_RXES_V1_ALL            0x00800
-#define SXE_TSES_TXES_V2_ALL            0x00200
-#define SXE_TSES_RXES_V2_ALL            0x00800
+#define SXE_TSES_TXES				   0x00200
+#define SXE_TSES_RXES				   0x00800
+#define SXE_TSES_TXES_V1_SYNC		   0x00000
+#define SXE_TSES_TXES_V1_DELAY_REQ	  0x00100
+#define SXE_TSES_TXES_V1_ALL			0x00200
+#define SXE_TSES_RXES_V1_SYNC		   0x00000
+#define SXE_TSES_RXES_V1_DELAY_REQ	  0x00400
+#define SXE_TSES_RXES_V1_ALL			0x00800
+#define SXE_TSES_TXES_V2_ALL			0x00200
+#define SXE_TSES_RXES_V2_ALL			0x00800
 
-#define SXE_IV_SNS              0
-#define SXE_IV_NS               8
-#define SXE_INCPD               0
-#define SXE_BASE_INCVAL         8
+#define SXE_IV_SNS			  0
+#define SXE_IV_NS			   8
+#define SXE_INCPD			   0
+#define SXE_BASE_INCVAL		 8
 
 
 #define SXE_VT_CTL		0x051B0
 #define SXE_PFMAILBOX(_i)	(0x04B00 + (4 * (_i)))
 
 #define SXE_PFMBICR(_i)		(0x00710 + (4 * (_i)))
-#define SXE_VFLRE(i)		((i & 1)? 0x001C0 : 0x00600)
+#define SXE_VFLRE(i)		((i & 1) ? 0x001C0 : 0x00600)
 #define SXE_VFLREC(i)		(0x00700 + (i * 4))
 #define SXE_VFRE(_i)		(0x051E0 + ((_i) * 4))
 #define SXE_VFTE(_i)		(0x08110 + ((_i) * 4))
-#define SXE_QDE			(0x02F04)             
+#define SXE_QDE			(0x02F04)
 #define SXE_SPOOF(_i)		(0x08200 + (_i) * 4)
 #define SXE_PFDTXGSWC		0x08220
 #define SXE_VMVIR(_i)		(0x08000 + ((_i) * 4))
@@ -900,7 +900,7 @@ 
 #define SXE_VLVF(_i)		(0x0F100 + ((_i) * 4))
 #define SXE_VLVFB(_i)		(0x0F200 + ((_i) * 4))
 #define SXE_MRCTL(_i)		(0x0F600 + ((_i) * 4))
-#define SXE_VMRVLAN(_i)	        (0x0F610 + ((_i) * 4))
+#define SXE_VMRVLAN(_i)			(0x0F610 + ((_i) * 4))
 #define SXE_VMRVM(_i)		(0x0F630 + ((_i) * 4))
 #define SXE_VMECM(_i)		(0x08790 + ((_i) * 4))
 #define SXE_PFMBMEM(_i)		(0x13000 + (64 * (_i)))
@@ -932,23 +932,23 @@ 
 
 
 #define SXE_VT_CTL_DIS_DEFPL  0x20000000
-#define SXE_VT_CTL_REPLEN     0x40000000
-#define SXE_VT_CTL_VT_ENABLE  0x00000001 
+#define SXE_VT_CTL_REPLEN	 0x40000000
+#define SXE_VT_CTL_VT_ENABLE  0x00000001
 #define SXE_VT_CTL_POOL_SHIFT 7
 #define SXE_VT_CTL_POOL_MASK  (0x3F << SXE_VT_CTL_POOL_SHIFT)
 
 
-#define SXE_PFMAILBOX_STS         0x00000001
-#define SXE_PFMAILBOX_ACK         0x00000002
-#define SXE_PFMAILBOX_VFU         0x00000004
-#define SXE_PFMAILBOX_PFU         0x00000008
-#define SXE_PFMAILBOX_RVFU        0x00000010
+#define SXE_PFMAILBOX_STS		 0x00000001
+#define SXE_PFMAILBOX_ACK		 0x00000002
+#define SXE_PFMAILBOX_VFU		 0x00000004
+#define SXE_PFMAILBOX_PFU		 0x00000008
+#define SXE_PFMAILBOX_RVFU		0x00000010
 
 
-#define SXE_PFMBICR_VFREQ         0x00000001
-#define SXE_PFMBICR_VFACK         0x00010000
-#define SXE_PFMBICR_VFREQ_MASK    0x0000FFFF
-#define SXE_PFMBICR_VFACK_MASK    0xFFFF0000
+#define SXE_PFMBICR_VFREQ		 0x00000001
+#define SXE_PFMBICR_VFACK		 0x00010000
+#define SXE_PFMBICR_VFREQ_MASK	0x0000FFFF
+#define SXE_PFMBICR_VFACK_MASK	0xFFFF0000
 
 
 #define SXE_QDE_ENABLE		(0x00000001)
@@ -962,7 +962,7 @@ 
 #define SXE_SPOOF_VLAN_SHIFT  (8)
 
 
-#define SXE_PFDTXGSWC_VT_LBEN	0x1 
+#define SXE_PFDTXGSWC_VT_LBEN	0x1
 
 
 #define SXE_VMVIR_VLANA_DEFAULT 0x40000000
@@ -978,51 +978,51 @@ 
 #define SXE_VMOLR_MPE		0x10000000
 
 
-#define SXE_VLVF_VIEN         0x80000000 
-#define SXE_VLVF_ENTRIES      64
+#define SXE_VLVF_VIEN		 0x80000000
+#define SXE_VLVF_ENTRIES	  64
 #define SXE_VLVF_VLANID_MASK  0x00000FFF
 
 
-#define SXE_HDC_HOST_BASE       0x16000
-#define SXE_HDC_SW_LK           (SXE_HDC_HOST_BASE + 0x00)
-#define SXE_HDC_PF_LK           (SXE_HDC_HOST_BASE + 0x04)
-#define SXE_HDC_SW_OV           (SXE_HDC_HOST_BASE + 0x08)
-#define SXE_HDC_FW_OV           (SXE_HDC_HOST_BASE + 0x0C)
-#define SXE_HDC_PACKET_HEAD0    (SXE_HDC_HOST_BASE + 0x10)
+#define SXE_HDC_HOST_BASE	   0x16000
+#define SXE_HDC_SW_LK		   (SXE_HDC_HOST_BASE + 0x00)
+#define SXE_HDC_PF_LK		   (SXE_HDC_HOST_BASE + 0x04)
+#define SXE_HDC_SW_OV		   (SXE_HDC_HOST_BASE + 0x08)
+#define SXE_HDC_FW_OV		   (SXE_HDC_HOST_BASE + 0x0C)
+#define SXE_HDC_PACKET_HEAD0	(SXE_HDC_HOST_BASE + 0x10)
 
-#define SXE_HDC_PACKET_DATA0    (SXE_HDC_HOST_BASE + 0x20)
+#define SXE_HDC_PACKET_DATA0	(SXE_HDC_HOST_BASE + 0x20)
 
 
 #define SXE_HDC_MSI_STATUS_REG  0x17000
-#define SXE_FW_STATUS_REG       0x17004
-#define SXE_DRV_STATUS_REG      0x17008
-#define SXE_FW_HDC_STATE_REG    0x1700C
-#define SXE_R0_MAC_ADDR_RAL     0x17010
-#define SXE_R0_MAC_ADDR_RAH     0x17014
+#define SXE_FW_STATUS_REG	   0x17004
+#define SXE_DRV_STATUS_REG	  0x17008
+#define SXE_FW_HDC_STATE_REG	0x1700C
+#define SXE_R0_MAC_ADDR_RAL	 0x17010
+#define SXE_R0_MAC_ADDR_RAH	 0x17014
 #define SXE_CRC_STRIP_REG		0x17018
 
 
-#define SXE_HDC_SW_LK_BIT       0x0001
-#define SXE_HDC_PF_LK_BIT       0x0003
-#define SXE_HDC_SW_OV_BIT       0x0001
-#define SXE_HDC_FW_OV_BIT       0x0001
+#define SXE_HDC_SW_LK_BIT	   0x0001
+#define SXE_HDC_PF_LK_BIT	   0x0003
+#define SXE_HDC_SW_OV_BIT	   0x0001
+#define SXE_HDC_FW_OV_BIT	   0x0001
 #define SXE_HDC_RELEASE_SW_LK   0x0000
 
-#define SXE_HDC_LEN_TO_REG(n)        (n - 1)
-#define SXE_HDC_LEN_FROM_REG(n)      (n + 1)
+#define SXE_HDC_LEN_TO_REG(n)		(n - 1)
+#define SXE_HDC_LEN_FROM_REG(n)	  (n + 1)
 
 
-#define SXE_RX_PKT_BUF_SIZE_SHIFT    10
-#define SXE_TX_PKT_BUF_SIZE_SHIFT    10
+#define SXE_RX_PKT_BUF_SIZE_SHIFT	10
+#define SXE_TX_PKT_BUF_SIZE_SHIFT	10
 
-#define SXE_RXIDX_TBL_SHIFT           1
-#define SXE_RXTXIDX_IPS_EN            0x00000001
-#define SXE_RXTXIDX_IDX_SHIFT         3
-#define SXE_RXTXIDX_READ              0x40000000
-#define SXE_RXTXIDX_WRITE             0x80000000
+#define SXE_RXIDX_TBL_SHIFT		   1
+#define SXE_RXTXIDX_IPS_EN			0x00000001
+#define SXE_RXTXIDX_IDX_SHIFT		 3
+#define SXE_RXTXIDX_READ			  0x40000000
+#define SXE_RXTXIDX_WRITE			 0x80000000
 
 
-#define SXE_KEEP_CRC_EN		      0x00000001
+#define SXE_KEEP_CRC_EN			  0x00000001
 
 
 #define SXE_VMD_CTL			0x0581C
@@ -1032,208 +1032,208 @@ 
 #define SXE_VMD_CTL_POOL_FILTER		0x00000002
 
 
-#define SXE_FLCTRL                    0x14300
-#define SXE_PFCTOP                    0x14304
-#define SXE_FCTTV0                    0x14310
-#define SXE_FCTTV(_i)                (SXE_FCTTV0 + ((_i) * 4))
-#define SXE_FCRTV                     0x14320
-#define SXE_TFCS                      0x14324
+#define SXE_FLCTRL					0x14300
+#define SXE_PFCTOP					0x14304
+#define SXE_FCTTV0					0x14310
+#define SXE_FCTTV(_i)				(SXE_FCTTV0 + ((_i) * 4))
+#define SXE_FCRTV					 0x14320
+#define SXE_TFCS					  0x14324
 
 
-#define SXE_FCTRL_TFCE_MASK           0x0018
-#define SXE_FCTRL_TFCE_LFC_EN         0x0008
-#define SXE_FCTRL_TFCE_PFC_EN         0x0010
-#define SXE_FCTRL_TFCE_DPF_EN         0x0020
-#define SXE_FCTRL_RFCE_MASK           0x0300
-#define SXE_FCTRL_RFCE_LFC_EN         0x0100
-#define SXE_FCTRL_RFCE_PFC_EN         0x0200
+#define SXE_FCTRL_TFCE_MASK		   0x0018
+#define SXE_FCTRL_TFCE_LFC_EN		 0x0008
+#define SXE_FCTRL_TFCE_PFC_EN		 0x0010
+#define SXE_FCTRL_TFCE_DPF_EN		 0x0020
+#define SXE_FCTRL_RFCE_MASK		   0x0300
+#define SXE_FCTRL_RFCE_LFC_EN		 0x0100
+#define SXE_FCTRL_RFCE_PFC_EN		 0x0200
 
-#define SXE_FCTRL_TFCE_FCEN_MASK      0x00FF0000
-#define SXE_FCTRL_TFCE_XONE_MASK      0xFF000000
+#define SXE_FCTRL_TFCE_FCEN_MASK	  0x00FF0000
+#define SXE_FCTRL_TFCE_XONE_MASK	  0xFF000000
 
 
-#define SXE_PFCTOP_FCT               0x8808
-#define SXE_PFCTOP_FCOP_MASK         0xFFFF0000
-#define SXE_PFCTOP_FCOP_PFC          0x01010000
-#define SXE_PFCTOP_FCOP_LFC          0x00010000
+#define SXE_PFCTOP_FCT			   0x8808
+#define SXE_PFCTOP_FCOP_MASK		 0xFFFF0000
+#define SXE_PFCTOP_FCOP_PFC		  0x01010000
+#define SXE_PFCTOP_FCOP_LFC		  0x00010000
 
 
-#define SXE_COMCTRL                   0x14400
-#define SXE_PCCTRL                    0x14404
-#define SXE_LPBKCTRL                  0x1440C
-#define SXE_MAXFS                     0x14410
-#define SXE_SACONH                    0x14420
-#define SXE_SACONL                    0x14424
-#define SXE_VLANCTRL                  0x14430
-#define SXE_VLANID                    0x14434
-#define SXE_LINKS                     0x14454
-#define SXE_FPGA_SDS_STS	      0x14704
-#define SXE_MSCA                      0x14500
-#define SXE_MSCD                      0x14504
+#define SXE_COMCTRL				   0x14400
+#define SXE_PCCTRL					0x14404
+#define SXE_LPBKCTRL				  0x1440C
+#define SXE_MAXFS					 0x14410
+#define SXE_SACONH					0x14420
+#define SXE_SACONL					0x14424
+#define SXE_VLANCTRL				  0x14430
+#define SXE_VLANID					0x14434
+#define SXE_LINKS					 0x14454
+#define SXE_FPGA_SDS_STS		  0x14704
+#define SXE_MSCA					  0x14500
+#define SXE_MSCD					  0x14504
 
-#define SXE_HLREG0                    0x04240
-#define SXE_MFLCN                     0x04294
-#define SXE_MACC                      0x04330
+#define SXE_HLREG0					0x04240
+#define SXE_MFLCN					 0x04294
+#define SXE_MACC					  0x04330
 
-#define SXE_PCS1GLSTA                 0x0420C
-#define SXE_MFLCN                     0x04294
-#define SXE_PCS1GANA                  0x04850
-#define SXE_PCS1GANLP                 0x04854
+#define SXE_PCS1GLSTA				 0x0420C
+#define SXE_MFLCN					 0x04294
+#define SXE_PCS1GANA				  0x04850
+#define SXE_PCS1GANLP				 0x04854
 
 
-#define SXE_LPBKCTRL_EN               0x00000001
+#define SXE_LPBKCTRL_EN			   0x00000001
 
 
-#define SXE_MAC_ADDR_SACONH_SHIFT     32
-#define SXE_MAC_ADDR_SACONL_MASK      0xFFFFFFFF
+#define SXE_MAC_ADDR_SACONH_SHIFT	 32
+#define SXE_MAC_ADDR_SACONL_MASK	  0xFFFFFFFF
 
 
-#define SXE_PCS1GLSTA_AN_COMPLETE     0x10000
-#define SXE_PCS1GLSTA_AN_PAGE_RX      0x20000
-#define SXE_PCS1GLSTA_AN_TIMED_OUT    0x40000
+#define SXE_PCS1GLSTA_AN_COMPLETE	 0x10000
+#define SXE_PCS1GLSTA_AN_PAGE_RX	  0x20000
+#define SXE_PCS1GLSTA_AN_TIMED_OUT	0x40000
 #define SXE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
-#define SXE_PCS1GLSTA_AN_ERROR_RWS    0x100000
-
-#define SXE_PCS1GANA_SYM_PAUSE        0x100
-#define SXE_PCS1GANA_ASM_PAUSE        0x80 
-
-
-#define SXE_LKSTS_PCS_LKSTS_UP        0x00000001
-#define SXE_LINK_UP_TIME              90
-#define SXE_AUTO_NEG_TIME             45
-
-
-#define SXE_MSCA_NP_ADDR_MASK      0x0000FFFF
-#define SXE_MSCA_NP_ADDR_SHIFT     0
-#define SXE_MSCA_DEV_TYPE_MASK     0x001F0000
-#define SXE_MSCA_DEV_TYPE_SHIFT    16        
-#define SXE_MSCA_PHY_ADDR_MASK     0x03E00000
-#define SXE_MSCA_PHY_ADDR_SHIFT    21        
-#define SXE_MSCA_OP_CODE_MASK      0x0C000000
-#define SXE_MSCA_OP_CODE_SHIFT     26        
-#define SXE_MSCA_ADDR_CYCLE        0x00000000
-#define SXE_MSCA_WRITE             0x04000000
-#define SXE_MSCA_READ              0x0C000000
-#define SXE_MSCA_READ_AUTOINC      0x08000000
-#define SXE_MSCA_ST_CODE_MASK      0x30000000
-#define SXE_MSCA_ST_CODE_SHIFT     28        
-#define SXE_MSCA_NEW_PROTOCOL      0x00000000
-#define SXE_MSCA_OLD_PROTOCOL      0x10000000
-#define SXE_MSCA_BYPASSRA_C45      0x40000000
+#define SXE_PCS1GLSTA_AN_ERROR_RWS	0x100000
+
+#define SXE_PCS1GANA_SYM_PAUSE		0x100
+#define SXE_PCS1GANA_ASM_PAUSE		0x80
+
+
+#define SXE_LKSTS_PCS_LKSTS_UP		0x00000001
+#define SXE_LINK_UP_TIME			  90
+#define SXE_AUTO_NEG_TIME			 45
+
+
+#define SXE_MSCA_NP_ADDR_MASK	  0x0000FFFF
+#define SXE_MSCA_NP_ADDR_SHIFT	 0
+#define SXE_MSCA_DEV_TYPE_MASK	 0x001F0000
+#define SXE_MSCA_DEV_TYPE_SHIFT	16
+#define SXE_MSCA_PHY_ADDR_MASK	 0x03E00000
+#define SXE_MSCA_PHY_ADDR_SHIFT	21
+#define SXE_MSCA_OP_CODE_MASK	  0x0C000000
+#define SXE_MSCA_OP_CODE_SHIFT	 26
+#define SXE_MSCA_ADDR_CYCLE		0x00000000
+#define SXE_MSCA_WRITE			 0x04000000
+#define SXE_MSCA_READ			  0x0C000000
+#define SXE_MSCA_READ_AUTOINC	  0x08000000
+#define SXE_MSCA_ST_CODE_MASK	  0x30000000
+#define SXE_MSCA_ST_CODE_SHIFT	 28
+#define SXE_MSCA_NEW_PROTOCOL	  0x00000000
+#define SXE_MSCA_OLD_PROTOCOL	  0x10000000
+#define SXE_MSCA_BYPASSRA_C45	  0x40000000
 #define SXE_MSCA_MDI_CMD_ON_PROG   0x80000000
 
 
-#define MDIO_MSCD_RDATA_LEN        16
-#define MDIO_MSCD_RDATA_SHIFT      16
-
-
-#define SXE_CRCERRS                   0x14A04
-#define SXE_ERRBC                     0x14A10
-#define SXE_RLEC                      0x14A14
-#define SXE_PRC64                     0x14A18
-#define SXE_PRC127                    0x14A1C
-#define SXE_PRC255                    0x14A20
-#define SXE_PRC511                    0x14A24
-#define SXE_PRC1023                   0x14A28
-#define SXE_PRC1522                   0x14A2C
-#define SXE_BPRC                      0x14A30
-#define SXE_MPRC                      0x14A34
-#define SXE_GPRC                      0x14A38
-#define SXE_GORCL                     0x14A3C
-#define SXE_GORCH                     0x14A40
-#define SXE_RUC                       0x14A44
-#define SXE_RFC                       0x14A48
-#define SXE_ROC                       0x14A4C
-#define SXE_RJC                       0x14A50
-#define SXE_TORL                      0x14A54
-#define SXE_TORH                      0x14A58
-#define SXE_TPR                       0x14A5C
-#define SXE_PRCPF(_i)                 (0x14A60 + ((_i) * 4))
-#define SXE_GPTC                      0x14B00
-#define SXE_GOTCL                     0x14B04
-#define SXE_GOTCH                     0x14B08
-#define SXE_TPT                       0x14B0C
-#define SXE_PTC64                     0x14B10
-#define SXE_PTC127                    0x14B14
-#define SXE_PTC255                    0x14B18
-#define SXE_PTC511                    0x14B1C
-#define SXE_PTC1023                   0x14B20
-#define SXE_PTC1522                   0x14B24
-#define SXE_MPTC                      0x14B28
-#define SXE_BPTC                      0x14B2C
-#define SXE_PFCT(_i)                  (0x14B30 + ((_i) * 4))
-
-#define SXE_MACCFG                    0x0CE04
-#define SXE_MACCFG_PAD_EN             0x00000001
-
-
-#define SXE_COMCTRL_TXEN	      0x0001        
-#define SXE_COMCTRL_RXEN	      0x0002        
-#define SXE_COMCTRL_EDSEL	      0x0004        
-#define SXE_COMCTRL_SPEED_1G	      0x0200        
-#define SXE_COMCTRL_SPEED_10G	      0x0300        
-
-
-#define SXE_PCCTRL_TXCE		      0x0001        
-#define SXE_PCCTRL_RXCE		      0x0002        
-#define SXE_PCCTRL_PEN		      0x0100        
-#define SXE_PCCTRL_PCSC_ALL	      0x30000       
-
-
-#define SXE_MAXFS_TFSEL		      0x0001        
-#define SXE_MAXFS_RFSEL		      0x0002        
-#define SXE_MAXFS_MFS_MASK	      0xFFFF0000    
-#define SXE_MAXFS_MFS		      0x40000000    
-#define