diff mbox series

[v1,7/9] common/iavf: add RefSync support

Message ID 20240910101224.497044-8-soumyadeep.hore@intel.com (mailing list archive)
State Accepted
Delegated to: Bruce Richardson
Headers
Series Update IAVF Base Driver |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Hore, Soumyadeep Sept. 10, 2024, 10:12 a.m. UTC 
From: Julian Grajkowski <julianx.grajkowski@intel.com>

Update virtchnl to reflect RefSync implementation.
Reading and modifying DPLL input pin configuration, including
Esync/RefSync option, is possible on VM using sysfs. The request
is passed from the VM via virtchnl message to the host driver
and results in an admin command being sent to FW. Before the
change only Esync enable/disable option was supported and it
used bit 6, but this change introduces support for RefSync option,
so there are now 3 possible values - Esync disabled (0), Esync
enabled (1) and RefSync enabled (2). The change updates description
of relevant virtchnl messages, but leaves the previous description
of bit 6 for backward compatibility, so that when RefSync is not
supported this bit may still be used for Esync enable/disable only.

Signed-off-by: Julian Grajkowski <julianx.grajkowski@intel.com>
Signed-off-by: Soumyadeep Hore <soumyadeep.hore@intel.com>
---
 drivers/common/iavf/virtchnl.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)
diff mbox series

Patch

diff --git a/drivers/common/iavf/virtchnl.h b/drivers/common/iavf/virtchnl.h
index ae6770adaf..2d88b83932 100644
--- a/drivers/common/iavf/virtchnl.h
+++ b/drivers/common/iavf/virtchnl.h
@@ -2320,6 +2320,12 @@  struct virtchnl_synce_get_input_pin_cfg {
 	u8 flags2;
 #define VIRTCHNL_GET_CGU_IN_CFG_FLG2_INPUT_EN		BIT(5)
 #define VIRTCHNL_GET_CGU_IN_CFG_FLG2_ESYNC_EN		BIT(6)
+#define VIRTCHNL_GET_CGU_IN_CFG_FLG2_ESYNC_REFSYNC_EN_SHIFT	6
+#define VIRTHCNL_GET_CGU_IN_CFG_FLG2_ESYNC_REFSYNC_EN \
+	MAKEMASK(0x3, VIRTCHNL_GET_CGU_IN_CFG_FLG2_ESYNC_REFSYNC_EN_SHIFT)
+#define VIRTCHNL_GET_CGU_IN_CFG_ESYNC_DIS			0
+#define VIRTCHNL_GET_CGU_IN_CFG_ESYNC_EN			1
+#define VIRTCHNL_GET_CGU_IN_CFG_REFSYNC_EN			2
 	u8 rsvd[3];
 };
 
@@ -2335,6 +2341,12 @@  struct virtchnl_synce_set_input_pin_cfg {
 	u8 flags2;
 #define VIRTCHNL_SET_CGU_IN_CFG_FLG2_INPUT_EN		BIT(5)
 #define VIRTCHNL_SET_CGU_IN_CFG_FLG2_ESYNC_EN		BIT(6)
+#define VIRTCHNL_SET_CGU_IN_CFG_FLG2_ESYNC_REFSYNC_EN_SHIFT	6
+#define VIRTCHNL_SET_CGU_IN_CFG_FLG2_ESYNC_REFSYNC_EN \
+	MAKEMASK(0x3, ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_REFSYNC_EN_SHIFT)
+#define VIRTCHNL_SET_CGU_IN_CFG_ESYNC_DIS			0
+#define VIRTCHNL_SET_CGU_IN_CFG_ESYNC_EN			1
+#define VIRTCHNL_SET_CGU_IN_CFG_REFSYNC_EN			2
 	u8 rsvd[5];
 };