@@ -6,12 +6,11 @@
#define _DLB2_EVDEV_LOG_H_
extern int eventdev_dlb2_log_level;
-#define RTE_LOGTYPE_EVENTDEV_DLB2_LOG_LEVEL eventdev_dlb2_log_level
+#define RTE_LOGTYPE_EVENTDEV_DLB2 eventdev_dlb2_log_level
/* Dynamic logging */
#define DLB2_LOG_IMPL(level, fmt, args...) \
- rte_log(RTE_LOG_ ## level, eventdev_dlb2_log_level, "%s" fmt "\n", \
- __func__, ##args)
+ RTE_LOG(level, EVENTDEV_DLB2, "%s" fmt "\n", __func__, ##args)
#define DLB2_LOG_INFO(fmt, args...) \
DLB2_LOG_IMPL(INFO, fmt, ## args)
@@ -21,6 +20,6 @@ extern int eventdev_dlb2_log_level;
/* remove debug logs at compile time unless actually debugging */
#define DLB2_LOG_DBG(fmt, args...) \
- RTE_LOG_DP(DEBUG, EVENTDEV_DLB2_LOG_LEVEL, fmt, ## args)
+ RTE_LOG_DP(DEBUG, EVENTDEV_DLB2, fmt, ## args)
#endif /* _DLB2_EVDEV_LOG_H_ */
@@ -41,13 +41,13 @@
/* Map to PMDs logging interface */
#define DLB2_ERR(dev, fmt, args...) \
- DLB2_LOG_ERR(fmt, ## args)
+ RTE_LOG(ERR, EVENTDEV_DLB2, "%s" fmt, __func__, ## args)
#define DLB2_INFO(dev, fmt, args...) \
- DLB2_LOG_INFO(fmt, ## args)
+ RTE_LOG(INFO, EVENTDEV_DLB2, "%s" fmt, __func__, ## args)
#define DLB2_DEBUG(dev, fmt, args...) \
- DLB2_LOG_DBG(fmt, ## args)
+ RTE_LOG_DP(DEBUG, EVENTDEV_DLB2, fmt, ## args)
/**
* os_udelay() - busy-wait for a number of microseconds
@@ -139,6 +139,16 @@ static inline void os_fence_hcw(struct dlb2_hw *hw, u64 *pp_addr)
DLB2_ERR(dlb2, __VA_ARGS__); \
} while (0)
+/**
+ * DLB2_HW_INFO() - log an error message
+ * @dlb2: dlb2_hw handle for a particular device.
+ * @...: variable string args.
+ */
+#define DLB2_HW_INFO(dlb2, ...) do { \
+ RTE_SET_USED(dlb2); \
+ DLB2_INFO(dlb2, __VA_ARGS__); \
+} while (0)
+
/**
* DLB2_HW_DBG() - log an info message
* @dlb2: dlb2_hw handle for a particular device.
@@ -841,7 +841,7 @@ dlb2_get_pp_allocation(struct dlb2_hw *hw, int cpu, int port_type)
dlb2_dev->enqueue_four = dlb2_movdir64b;
- DLB2_LOG_INFO(" for %s: cpu core used in pp profiling: %d\n",
+ DLB2_HW_INFO(hw, " for %s: cpu core used in pp profiling: %d\n",
is_ldb ? "LDB" : "DIR", cpu);
memset(cos_cycles, 0, num_sort * sizeof(struct dlb2_pp_thread_data));
@@ -854,7 +854,7 @@ dlb2_get_pp_allocation(struct dlb2_hw *hw, int cpu, int port_type)
err = rte_thread_attr_init(&th_attr);
if (err != 0) {
- DLB2_LOG_ERR(": thread attribute failed! err=%d", err);
+ DLB2_HW_ERR(hw, ": thread attribute failed! err=%d\n", err);
return;
}
CPU_SET(cpu, &th_attr.cpuset);
@@ -862,7 +862,7 @@ dlb2_get_pp_allocation(struct dlb2_hw *hw, int cpu, int port_type)
err = rte_thread_create(&thread, &th_attr,
&dlb2_pp_profile_func, &dlb2_thread_data[i]);
if (err) {
- DLB2_LOG_ERR(": thread creation failed! err=%d", err);
+ DLB2_HW_ERR(hw, ": thread creation failed! err=%d\n", err);
return;
}
@@ -871,7 +871,7 @@ dlb2_get_pp_allocation(struct dlb2_hw *hw, int cpu, int port_type)
err = rte_thread_join(thread, NULL);
if (err) {
- DLB2_LOG_ERR(": thread join failed! err=%d", err);
+ DLB2_HW_ERR(hw, ": thread join failed! err=%d\n", err);
return;
}
@@ -911,7 +911,7 @@ dlb2_get_pp_allocation(struct dlb2_hw *hw, int cpu, int port_type)
for (i = 0; i < num_ports; i++) {
port_allocations[i] = dlb2_thread_data[i].pp;
- DLB2_LOG_INFO(": pp %d cycles %d", port_allocations[i],
+ DLB2_HW_INFO(hw, ": pp %d cycles %d\n", port_allocations[i],
dlb2_thread_data[i].cycles);
}
@@ -929,7 +929,7 @@ dlb2_resource_probe(struct dlb2_hw *hw, const void *probe_args)
}
if (mask && rte_eal_parse_coremask(mask, cores)) {
- DLB2_LOG_ERR(": Invalid producer coremask=%s", mask);
+ DLB2_HW_ERR(hw, ": Invalid producer coremask=%s\n", mask);
return -1;
}
@@ -956,7 +956,7 @@ dlb2_resource_probe(struct dlb2_hw *hw, const void *probe_args)
break;
}
} else if (is_pcore) {
- DLB2_LOG_ERR("Producer coremask(%s) must be a subset of EAL coremask",
+ DLB2_HW_ERR(hw, "Producer coremask(%s) must be a subset of EAL coremask\n",
mask);
return -1;
}
@@ -4599,7 +4599,7 @@ dlb2_verify_create_ldb_port_args(struct dlb2_hw *hw,
return -EINVAL;
}
- DLB2_LOG_INFO(": LDB: cos=%d port:%d\n", id, port->id.phys_id);
+ DLB2_HW_INFO(hw, ": LDB: cos=%d port:%d\n", id, port->id.phys_id);
/* Check cache-line alignment */
if ((cq_dma_base & 0x3F) != 0) {
@@ -4826,7 +4826,7 @@ dlb2_verify_create_dir_port_args(struct dlb2_hw *hw,
resp->status = DLB2_ST_DIR_PORTS_UNAVAILABLE;
return -EINVAL;
}
- DLB2_LOG_INFO(": DIR: port:%d is_producer=%d\n",
+ DLB2_HW_INFO(hw, ": DIR: port:%d is_producer=%d\n",
pq->id.phys_id, args->is_producer);
}