From: Vanshika Shukla <vanshika.shukla@nxp.com>
This patch adds PTP one-step timestamping support.
dpni_set_single_step_cfg() MC API is utilized with offset provided
to insert correction time on frame.
Signed-off-by: Vanshika Shukla <vanshika.shukla@nxp.com>
---
drivers/net/dpaa2/dpaa2_ethdev.c | 61 +++++++++++++++++++++++++++++++
drivers/net/dpaa2/dpaa2_ethdev.h | 3 ++
drivers/net/dpaa2/rte_pmd_dpaa2.h | 10 +++++
drivers/net/dpaa2/version.map | 3 ++
4 files changed, 77 insertions(+)
@@ -548,6 +548,9 @@ dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
int tx_l4_csum_offload = false;
int ret, tc_index;
uint32_t max_rx_pktlen;
+#if defined(RTE_LIBRTE_IEEE1588)
+ uint16_t ptp_correction_offset;
+#endif
PMD_INIT_FUNC_TRACE();
@@ -632,6 +635,11 @@ dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
dpaa2_enable_ts[dev->data->port_id] = true;
}
+#if defined(RTE_LIBRTE_IEEE1588)
+ /* By default setting ptp correction offset for Ethernet SYNC packets */
+ ptp_correction_offset = RTE_ETHER_HDR_LEN + 8;
+ rte_pmd_dpaa2_set_one_step_ts(dev->data->port_id, ptp_correction_offset, 0);
+#endif
if (tx_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)
tx_l3_csum_offload = true;
@@ -2867,6 +2875,59 @@ int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev)
return dev->device->driver == &rte_dpaa2_pmd.driver;
}
+#if defined(RTE_LIBRTE_IEEE1588)
+int
+rte_pmd_dpaa2_get_one_step_ts(uint16_t port_id, bool mc_query)
+{
+ struct rte_eth_dev *dev = &rte_eth_devices[port_id];
+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
+ struct fsl_mc_io *dpni = priv->eth_dev->process_private;
+ struct dpni_single_step_cfg ptp_cfg;
+ int err;
+
+ if (!mc_query)
+ return priv->ptp_correction_offset;
+
+ err = dpni_get_single_step_cfg(dpni, CMD_PRI_LOW, priv->token, &ptp_cfg);
+ if (err) {
+ DPAA2_PMD_ERR("Failed to retrieve onestep configuration");
+ return err;
+ }
+
+ if (!ptp_cfg.ptp_onestep_reg_base) {
+ DPAA2_PMD_ERR("1588 onestep reg not available");
+ return -1;
+ }
+
+ priv->ptp_correction_offset = ptp_cfg.offset;
+
+ return priv->ptp_correction_offset;
+}
+
+int
+rte_pmd_dpaa2_set_one_step_ts(uint16_t port_id, uint16_t offset, uint8_t ch_update)
+{
+ struct rte_eth_dev *dev = &rte_eth_devices[port_id];
+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
+ struct fsl_mc_io *dpni = dev->process_private;
+ struct dpni_single_step_cfg cfg;
+ int err;
+
+ cfg.en = 1;
+ cfg.ch_update = ch_update;
+ cfg.offset = offset;
+ cfg.peer_delay = 0;
+
+ err = dpni_set_single_step_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
+ if (err)
+ return err;
+
+ priv->ptp_correction_offset = offset;
+
+ return 0;
+}
+#endif
+
static int dpaa2_tx_sg_pool_init(void)
{
char name[RTE_MEMZONE_NAMESIZE];
@@ -230,6 +230,9 @@ struct dpaa2_dev_priv {
rte_spinlock_t lpbk_qp_lock;
uint8_t channel_inuse;
+ /* Stores correction offset for one step timestamping */
+ uint16_t ptp_correction_offset;
+
LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */
LIST_HEAD(nodes, dpaa2_tm_node) nodes;
LIST_HEAD(shaper_profiles, dpaa2_tm_shaper_profile) shaper_profiles;
@@ -102,4 +102,14 @@ rte_pmd_dpaa2_thread_init(void);
__rte_experimental
uint32_t
rte_pmd_dpaa2_get_tlu_hash(uint8_t *key, int size);
+
+#if defined(RTE_LIBRTE_IEEE1588)
+__rte_experimental
+int
+rte_pmd_dpaa2_set_one_step_ts(uint16_t port_id, uint16_t offset, uint8_t ch_update);
+
+__rte_experimental
+int
+rte_pmd_dpaa2_get_one_step_ts(uint16_t port_id, bool mc_query);
+#endif
#endif /* _RTE_PMD_DPAA2_H */
@@ -16,6 +16,9 @@ EXPERIMENTAL {
rte_pmd_dpaa2_thread_init;
# added in 21.11
rte_pmd_dpaa2_get_tlu_hash;
+ # added in 24.11
+ rte_pmd_dpaa2_set_one_step_ts;
+ rte_pmd_dpaa2_get_one_step_ts;
};
INTERNAL {