From patchwork Fri Oct 4 17:53:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sriharsha Basavapatna X-Patchwork-Id: 145205 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1CD3145ABA; Sat, 5 Oct 2024 10:01:50 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CF297432E6; Sat, 5 Oct 2024 10:01:49 +0200 (CEST) Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) by mails.dpdk.org (Postfix) with ESMTP id 4A53742F2F for ; Fri, 4 Oct 2024 19:45:35 +0200 (CEST) Received: by mail-pf1-f174.google.com with SMTP id d2e1a72fcca58-718d91eef2eso1766735b3a.1 for ; Fri, 04 Oct 2024 10:45:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1728063934; x=1728668734; darn=dpdk.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7Cv3FsyeGrBOgi03PHgjjNG1/KCzAHP21ApzusOBHnI=; b=V9vkfK5iwZWmARIwbpWCV8PbmzuR+hoNd7+qk6wwR275x1oMqxam2cc3s55iLCiEBi kATwAsX2z0YTsCjRiTKujxXC58Qo0vim1h5WQfdFr156mSKH95k+JfvXNGvXlss1ByqN /84aRP1mdSHNMmtgHWUACWCam+Uz39Q0Ksuvk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728063934; x=1728668734; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7Cv3FsyeGrBOgi03PHgjjNG1/KCzAHP21ApzusOBHnI=; b=YONZct2rUF5A7T2LoHnA9p05MbEQo2dFHOaBiGEWw8a4qBAJ9sk0yYYZ4e0b+WqQIG jZaKSykqCPoFtHCddVt/OWvIyaJAW8ZewVjrUE2smE8NdBf6N9Fd2ZEOD6MQYHZE8GpY 45Qy6oc7otywwN3+s5Ir0amta3J56tUEgi4mfx5oYv/SDYJWQuB9abINhs9yp21gG5xC SbnwjGXw6kEZlu7SDRKCqUSIRU++4/5u6KNJM5VqSH8+eVrEC96pFsWFcjYaX2gPCpt3 7QZ1ljwT5q03BXF8aUUOfTbfDLGEGM5PrbsbTUv1Rq9o0vOh45gYPvTO24AtOZuTLbjQ viSw== X-Gm-Message-State: AOJu0YxBLQC2oOcNGD636HrUbgDwWB0XQje8Jbbt7wt5ZiaV6XipMw0x iZTutsF8jGa+VgTXEBjTapOphn9lBouaD10nXjux2LeQQ9obdvZiSyT6fkXk62AyniQI3zxMACc 3xnsbr648WsNDZLWOJgg5/NqI0ITkPFzoHNXURpD9bRUgpnAnPVxzghTAcC5BQaLExcTTbT6KvT OLeMtinf91Q2I/SmYyTDyLpR1uzM51XEAsEoLml6oDkw== X-Google-Smtp-Source: AGHT+IHEfUoDnmCVuxh5qWshEtoJBGXfeKuhloaXxag/o+SkRcstQrPmrz8zPvbmEVb7iH+IrP4LNw== X-Received: by 2002:a05:6a00:1307:b0:707:fa61:1c6a with SMTP id d2e1a72fcca58-71de234c099mr5739556b3a.10.1728063928781; Fri, 04 Oct 2024 10:45:28 -0700 (PDT) Received: from dhcp-10-123-154-23.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71df0cd0b5bsm128103b3a.53.2024.10.04.10.45.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2024 10:45:27 -0700 (PDT) From: Sriharsha Basavapatna To: dev@dpdk.org Cc: Farah Smith , Jay Ding , Peter Spreadborough , Sriharsha Basavapatna , Shahaji Bhosle , Ajit Khaparde Subject: [PATCH v4 11/47] net/bnxt: tfc: support tf-core for Thor2 Date: Fri, 4 Oct 2024 23:23:02 +0530 Message-Id: <20241004175338.3156160-12-sriharsha.basavapatna@broadcom.com> X-Mailer: git-send-email 2.39.0.189.g4dbebc36b0 In-Reply-To: <20241004175338.3156160-1-sriharsha.basavapatna@broadcom.com> References: <20241004175338.3156160-1-sriharsha.basavapatna@broadcom.com> MIME-Version: 1.0 X-Mailman-Approved-At: Sat, 05 Oct 2024 10:01:45 +0200 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Farah Smith This patch introduces tf-core (tfc) functionality for Thor2 chips. The new code is added under ~/tf_core/v3/ and ~/hcapi/cfa_v3/. There are some dependent changes needed in some of the core bnxt pmd files. Those also have been updated accordingly. TruFlow(TF) is the software library that exposes CFA HW resources to upper layer protocols or applications. This patch series implements the tfc library as a part of bnxt_en driver so that upper layer APIs such as flow add can access the hardware. The tfc is designed to expose the CFA HW tables to the TF ULP via a set of TF APIs. The TF APIs are the gateway to the CFA HW resources. Most API calls will result in a call to the TF FW to carry out the actual HW programming. The APIs support Thor2. As a first step, the tfc object is opened during which memory is allocated and initialized to manage memory associated with table scopes and store the session. Table scopes are used to manage host memory used for EM (exact match) lookups and actions. Sessions are created by the application and other hardware resources can be allocated associated with the session or associated with a function. HCAPI (hardware control APIs) consist of APIs supporting MPC (midpath control) messages sent to the CFA to access table scope memory. Additional table scope management tools Table scope instance manager (TIM) and Table scope pool manager (TPM) reside within HCAPI to support VFs requiring table scope memory. The HWRMs are implemented in tfc_msg.c and they are grouped as shown below: Session management: HWRM_TFC_SESSION_ID_ALLOC HWRM_TFC_SESSION_FID_ADD HWRM_TFC_SESSION_FID_REM Table Scope management: HWRM_TFC_TBL_SCOPE_QCAPS HWRM_TFC_TBL_SCOPE_ID_ALLOC HWRM_TFC_TBL_SCOPE_CONFIG HWRM_TFC_TBL_SCOPE_DECONFIG HWRM_TFC_TBL_SCOPE_FID_ADD HWRM_TFC_TBL_SCOPE_FID_REM HWRM_TFC_TBL_SCOPE_POOL_ALLOC HWRM_TFC_TBL_SCOPE_POOL_FREE HWRM_TFC_TBL_SCOPE_CONFIG_GET HW/Table Management: HWRM_TFC_IDENT_ALLOC HWRM_TFC_IDENT_FREE HWRM_TFC_IDX_TBL_ALLOC HWRM_TFC_IDX_TBL_ALLOC_SET HWRM_TFC_IDX_TBL_SET HWRM_TFC_IDX_TBL_GET HWRM_TFC_IDX_TBL_FREE HWRM_TFC_GLOBAL_ID_ALLOC HWRM_TFC_TCAM_SET HWRM_TFC_TCAM_GET HWRM_TFC_TCAM_ALLOC HWRM_TFC_TCAM_ALLOC_SET HWRM_TFC_TCAM_FREE HWRM_TFC_IF_TBL_SET HWRM_TFC_IF_TBL_GET HWRM_TFC_RESC_USAGE_QUERY This patch also includes the required header files to support these APIs, listed below. TF-Core APIs: tfc.h TF HWRM messages: tfc_msg.h, tfc_vf2pf_msg.h TF Object: tfo.h TF Table Scope: tfc_em.h, tfc_action_handle.h, tfc_flow_handle.h, tfc_cpm.h, cfa_tim.h, cfa_tim_priv.h, cfa_tpm.h, cfa_tpm_priv.h TF general support: tfc_debug.h tfc_priv.h tfc_util.h CFA HW files: cfa_bld_defs.h, cfa_resource_types.h, cfa_bld_p70_defs.h, cfa_bld_p70_field_ids.h, cfa_bld_p70_fkb_keycodes.h cfa_bld_p70_mpc.h, cfa_p70.h cfa_p70_hw.h cfa_p70_mpc_structs.h, cfa_p70_mpc_structs.h, cfa_bld_mpc_field_ids.h, cfa_bld.h, cfa_bld_mpcops.h Signed-off-by: Farah Smith Signed-off-by: Jay Ding Signed-off-by: Peter Spreadborough Signed-off-by: Sriharsha Basavapatna Reviewed-by: Shahaji Bhosle Reviewed-by: Ajit Khaparde --- drivers/net/bnxt/bnxt.h | 3 + drivers/net/bnxt/bnxt_cpr.h | 24 +- drivers/net/bnxt/bnxt_hwrm.c | 83 +- drivers/net/bnxt/bnxt_hwrm.h | 9 + drivers/net/bnxt/bnxt_mpc.c | 828 + drivers/net/bnxt/bnxt_mpc.h | 117 + drivers/net/bnxt/bnxt_ring.c | 19 +- drivers/net/bnxt/bnxt_ring.h | 54 +- drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h | 15 +- drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h | 576 +- drivers/net/bnxt/hcapi/cfa_v3/CMakeLists.txt | 92 + .../bnxt/hcapi/cfa_v3/bld/host/cfa_bld_mpc.c | 42 + .../hcapi/cfa_v3/bld/include/cfa_bld_defs.h | 578 + .../hcapi/cfa_v3/bld/include/host/cfa_bld.h | 524 + .../cfa_v3/bld/include/host/cfa_bld_devops.h | 297 + .../bld/include/host/cfa_bld_field_ids.h | 1542 + .../bld/include/host/cfa_bld_mpc_field_ids.h | 1286 + .../cfa_v3/bld/include/host/cfa_bld_mpcops.h | 598 + .../cfa_v3/bld/include/p70/cfa_bld_p70_defs.h | 543 + .../bld/include/p70/cfa_bld_p70_field_ids.h | 1542 + .../cfa_v3/bld/include/p70/cfa_bld_p70_mpc.h | 548 + .../hcapi/cfa_v3/bld/include/p70/cfa_p70.h | 164 + .../hcapi/cfa_v3/bld/include/p70/cfa_p70_hw.h | 4286 ++ .../bld/include/p70/cfa_p70_mpc_structs.h | 1496 + .../hcapi/cfa_v3/bld/p70/cfa_bld_p70_mpc.c | 927 + .../cfa_v3/bld/p70/cfa_bld_p70_mpc_defs.h | 51 + .../p70/host/cfa_bld_p70_host_mpc_wrapper.c | 1127 + .../p70/host/cfa_bld_p70_host_mpc_wrapper.h | 83 + .../cfa_v3/bld/p70/host/cfa_bld_p70_mpcops.c | 56 + .../cfa_v3/bld/p70/host/cfa_bld_p70_mpcops.h | 22 + .../bld/p70/host/cfa_p70_mpc_field_ids.h | 1177 + .../bld/p70/host/cfa_p70_mpc_field_mapping.h | 775 + .../bnxt/hcapi/cfa_v3/include/cfa_resources.h | 185 + .../net/bnxt/hcapi/cfa_v3/include/cfa_trace.h | 273 + .../net/bnxt/hcapi/cfa_v3/include/cfa_types.h | 122 + .../net/bnxt/hcapi/cfa_v3/include/cfa_util.h | 44 + .../include/platform/dpdk/cfa_debug_defs.h | 52 + .../net/bnxt/hcapi/cfa_v3/include/sys_util.h | 101 + drivers/net/bnxt/hcapi/cfa_v3/meson.build | 36 + .../net/bnxt/hcapi/cfa_v3/mm/CMakeLists.txt | 42 + drivers/net/bnxt/hcapi/cfa_v3/mm/cfa_mm.c | 624 + .../net/bnxt/hcapi/cfa_v3/mm/cfa_mm_priv.h | 92 + .../net/bnxt/hcapi/cfa_v3/mm/include/cfa_mm.h | 173 + .../net/bnxt/hcapi/cfa_v3/tim/CMakeLists.txt | 43 + drivers/net/bnxt/hcapi/cfa_v3/tim/cfa_tim.c | 124 + .../net/bnxt/hcapi/cfa_v3/tim/cfa_tim_priv.h | 85 + .../bnxt/hcapi/cfa_v3/tim/include/cfa_tim.h | 133 + .../net/bnxt/hcapi/cfa_v3/tpm/CMakeLists.txt | 44 + drivers/net/bnxt/hcapi/cfa_v3/tpm/cfa_tpm.c | 273 + .../net/bnxt/hcapi/cfa_v3/tpm/cfa_tpm_priv.h | 47 + .../bnxt/hcapi/cfa_v3/tpm/include/cfa_tpm.h | 215 + drivers/net/bnxt/hsi_struct_def_dpdk.h | 54800 +++++++++------- drivers/net/bnxt/meson.build | 5 +- drivers/net/bnxt/tf_core/v3/meson.build | 34 + drivers/net/bnxt/tf_core/v3/tfc.h | 1527 + drivers/net/bnxt/tf_core/v3/tfc_act.c | 843 + .../net/bnxt/tf_core/v3/tfc_action_handle.h | 68 + drivers/net/bnxt/tf_core/v3/tfc_cpm.c | 439 + drivers/net/bnxt/tf_core/v3/tfc_cpm.h | 214 + drivers/net/bnxt/tf_core/v3/tfc_debug.h | 28 + drivers/net/bnxt/tf_core/v3/tfc_em.c | 1053 + drivers/net/bnxt/tf_core/v3/tfc_em.h | 174 + drivers/net/bnxt/tf_core/v3/tfc_flow_handle.h | 81 + drivers/net/bnxt/tf_core/v3/tfc_global_id.c | 58 + drivers/net/bnxt/tf_core/v3/tfc_ident.c | 83 + drivers/net/bnxt/tf_core/v3/tfc_idx_tbl.c | 328 + drivers/net/bnxt/tf_core/v3/tfc_if_tbl.c | 133 + drivers/net/bnxt/tf_core/v3/tfc_init.c | 69 + drivers/net/bnxt/tf_core/v3/tfc_mpc_table.c | 1211 + drivers/net/bnxt/tf_core/v3/tfc_msg.c | 1202 + drivers/net/bnxt/tf_core/v3/tfc_msg.h | 164 + drivers/net/bnxt/tf_core/v3/tfc_priv.c | 124 + drivers/net/bnxt/tf_core/v3/tfc_priv.h | 78 + drivers/net/bnxt/tf_core/v3/tfc_resources.c | 99 + drivers/net/bnxt/tf_core/v3/tfc_resources.h | 15 + drivers/net/bnxt/tf_core/v3/tfc_session.c | 155 + drivers/net/bnxt/tf_core/v3/tfc_tbl_scope.c | 2069 + drivers/net/bnxt/tf_core/v3/tfc_tcam.c | 299 + drivers/net/bnxt/tf_core/v3/tfc_util.c | 230 + drivers/net/bnxt/tf_core/v3/tfc_util.h | 123 + drivers/net/bnxt/tf_core/v3/tfc_vf2pf_msg.c | 360 + drivers/net/bnxt/tf_core/v3/tfc_vf2pf_msg.h | 220 + drivers/net/bnxt/tf_core/v3/tfo.c | 575 + drivers/net/bnxt/tf_core/v3/tfo.h | 429 + drivers/net/bnxt/tf_ulp/bnxt_ulp_tfc.h | 74 + 85 files changed, 65295 insertions(+), 24261 deletions(-) create mode 100644 drivers/net/bnxt/bnxt_mpc.c create mode 100644 drivers/net/bnxt/bnxt_mpc.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/CMakeLists.txt create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/host/cfa_bld_mpc.c create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/cfa_bld_defs.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_devops.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_field_ids.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_mpc_field_ids.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_mpcops.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_defs.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_field_ids.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_mpc.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70_hw.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70_mpc_structs.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/p70/cfa_bld_p70_mpc.c create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/p70/cfa_bld_p70_mpc_defs.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_host_mpc_wrapper.c create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_host_mpc_wrapper.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_mpcops.c create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_mpcops.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_p70_mpc_field_ids.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_p70_mpc_field_mapping.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/include/cfa_resources.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/include/cfa_trace.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/include/cfa_types.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/include/cfa_util.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/include/platform/dpdk/cfa_debug_defs.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/include/sys_util.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/meson.build create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/mm/CMakeLists.txt create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/mm/cfa_mm.c create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/mm/cfa_mm_priv.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/mm/include/cfa_mm.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/tim/CMakeLists.txt create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/tim/cfa_tim.c create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/tim/cfa_tim_priv.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/tim/include/cfa_tim.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/tpm/CMakeLists.txt create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/tpm/cfa_tpm.c create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/tpm/cfa_tpm_priv.h create mode 100644 drivers/net/bnxt/hcapi/cfa_v3/tpm/include/cfa_tpm.h create mode 100644 drivers/net/bnxt/tf_core/v3/meson.build create mode 100644 drivers/net/bnxt/tf_core/v3/tfc.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_act.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_action_handle.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_cpm.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_cpm.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_debug.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_em.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_em.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_flow_handle.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_global_id.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_ident.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_idx_tbl.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_if_tbl.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_init.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_mpc_table.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_msg.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_msg.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_priv.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_priv.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_resources.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_resources.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_session.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_tbl_scope.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_tcam.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_util.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_util.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_vf2pf_msg.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfc_vf2pf_msg.h create mode 100644 drivers/net/bnxt/tf_core/v3/tfo.c create mode 100644 drivers/net/bnxt/tf_core/v3/tfo.h create mode 100644 drivers/net/bnxt/tf_ulp/bnxt_ulp_tfc.h diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index aaa7ea00cc..00123e51ac 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -24,8 +24,10 @@ #include "bnxt_util.h" #include "tf_core.h" +#include "tfc.h" #include "bnxt_ulp.h" #include "bnxt_tf_common.h" +#include "bnxt_mpc.h" #include "bnxt_vnic.h" /* Vendor ID */ @@ -1034,6 +1036,7 @@ struct bnxt { struct bnxt_ring_stats_ext *prev_tx_ring_stats_ext; struct bnxt_vnic_queue_db vnic_queue_db; + struct bnxt_mpc *mpc; #define BNXT_MAX_MC_ADDRS ((bp)->max_mcast_addr) struct rte_ether_addr *mcast_addr_list; rte_iova_t mc_list_dma_addr; diff --git a/drivers/net/bnxt/bnxt_cpr.h b/drivers/net/bnxt/bnxt_cpr.h index 43f06fdc92..d97e0befd5 100644 --- a/drivers/net/bnxt/bnxt_cpr.h +++ b/drivers/net/bnxt/bnxt_cpr.h @@ -8,6 +8,7 @@ #include #include +#include #include "hsi_struct_def_dpdk.h" struct bnxt_db_info; @@ -15,6 +16,10 @@ struct bnxt_db_info; #define CMP_TYPE(cmp) \ (((struct cmpl_base *)cmp)->type & CMPL_BASE_TYPE_MASK) +#define CMPL_VALID(cmp, v) \ + (!!(rte_le_to_cpu_32(((struct cmpl_base *)(cmp))->info3_v) & \ + CMPL_BASE_V) == !(v)) + /* Get completion length from completion type, in 16-byte units. */ #define CMP_LEN(cmp_type) (((cmp_type) & 1) + 1) @@ -28,6 +33,14 @@ struct bnxt_db_info; #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) +#define NEXT_CMPL(cpr, idx, v, inc) do { \ + (idx) += (inc); \ + if (unlikely((idx) >= (cpr)->cp_ring_struct->ring_size)) { \ + (v) = !(v); \ + (idx) = 0; \ + } \ +} while (0) + #define B_CP_DB_REARM(cpr, raw_cons) \ rte_write32((DB_CP_REARM_FLAGS | \ DB_RING_IDX(&((cpr)->cp_db), raw_cons)), \ @@ -74,6 +87,8 @@ struct bnxt_cp_ring_info { uint32_t hw_stats_ctx_id; struct bnxt_ring *cp_ring_struct; + bool valid; + uint32_t epoch; }; #define RX_CMP_L2_ERRORS \ @@ -104,10 +119,13 @@ bool bnxt_is_recovery_enabled(struct bnxt *bp); bool bnxt_is_primary_func(struct bnxt *bp); void bnxt_stop_rxtx(struct rte_eth_dev *eth_dev); +#if (RTE_VERSION_NUM(21, 8, 0, 0) < RTE_VERSION) +void bnxt_start_rxtx(struct rte_eth_dev *eth_dev); +#endif /** * Check validity of a completion ring entry. If the entry is valid, include a - * C11 rte_memory_order_acquire fence to ensure that subsequent loads of fields in the + * C11 __ATOMIC_ACQUIRE fence to ensure that subsequent loads of fields in the * completion are not hoisted by the compiler or by the CPU to come before the * loading of the "valid" field. * @@ -124,13 +142,13 @@ void bnxt_stop_rxtx(struct rte_eth_dev *eth_dev); static __rte_always_inline bool bnxt_cpr_cmp_valid(const void *cmpl, uint32_t raw_cons, uint32_t ring_size) { - const struct cmpl_base *c = cmpl; + const struct cmpl_base *c = (const struct cmpl_base *)cmpl; bool expected, valid; expected = !(raw_cons & ring_size); valid = !!(rte_le_to_cpu_32(c->info3_v) & CMPL_BASE_V); if (valid == expected) { - rte_atomic_thread_fence(rte_memory_order_acquire); + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); return true; } return false; diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index fc142672f6..4e62dbbcca 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -2370,7 +2370,7 @@ int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) return rc; } -static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) +int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) { int rc; struct hwrm_stat_ctx_free_input req = {.req_type = 0 }; @@ -7449,6 +7449,49 @@ int bnxt_hwrm_config_host_mtu(struct bnxt *bp) return rc; } +int bnxt_hwrm_func_cfg_mpc(struct bnxt *bp, uint8_t mpc_chnls_msk, bool enable) +{ + struct hwrm_func_cfg_input req = {0}; + struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr; + int rc; + uint16_t mpc_chnls = 0; + + HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB); + req.fid = rte_cpu_to_le_16(0xffff); + req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS); + if (enable) { + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_TCE)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE; + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_RCE)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE; + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_TE_CFA)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE; + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_RE_CFA)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE; + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_PRIMATE)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE; + } else { + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_TCE)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE; + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_RCE)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE; + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_TE_CFA)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE; + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_RE_CFA)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE; + if (mpc_chnls_msk & (1 << BNXT_MPC_CHNL_PRIMATE)) + mpc_chnls |= HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE; + } + req.mpc_chnls = rte_cpu_to_le_16(mpc_chnls); + + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); + + HWRM_CHECK_RESULT(); + HWRM_UNLOCK(); + + return rc; +} + int bnxt_vnic_rss_clear_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic) { @@ -7471,3 +7514,41 @@ bnxt_vnic_rss_clear_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic) return rc; } + +int bnxt_hwrm_tf_oem_cmd(struct bnxt *bp, + uint32_t *in, + uint16_t in_len, + uint32_t *out, + uint16_t out_len) +{ + struct hwrm_oem_cmd_output *resp = bp->hwrm_cmd_resp_addr; + struct hwrm_oem_cmd_input req = {0}; + int rc = 0; + + if (!BNXT_VF(bp)) { + PMD_DRV_LOG(DEBUG, "Not a VF. Command not supported\n"); + return -ENOTSUP; + } + + HWRM_PREP(&req, HWRM_OEM_CMD, BNXT_USE_CHIMP_MB); + + req.oem_id = rte_cpu_to_le_32(0x14e4); + req.naming_authority = + HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_PCI_SIG; + req.message_family = + HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_TRUFLOW; + memcpy(req.oem_data, in, in_len); + + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); + + HWRM_CHECK_RESULT(); + if (resp->oem_id == 0x14e4 && + resp->naming_authority == + HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_PCI_SIG && + resp->message_family == + HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_TRUFLOW) + memcpy(out, resp->oem_data, out_len); + HWRM_UNLOCK(); + + return rc; +} diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h index 19fb35f223..ec639bdbce 100644 --- a/drivers/net/bnxt/bnxt_hwrm.h +++ b/drivers/net/bnxt/bnxt_hwrm.h @@ -367,6 +367,10 @@ int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr); void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index); int bnxt_alloc_hwrm_tx_ring(struct bnxt *bp, int queue_index); int bnxt_hwrm_config_host_mtu(struct bnxt *bp); +int bnxt_hwrm_func_cfg_mpc(struct bnxt *bp, + uint8_t mpc_chnls_msk, + bool enable); +int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr); int bnxt_vnic_rss_clear_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic); int bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic); int bnxt_hwrm_func_backing_store_qcaps_v2(struct bnxt *bp); @@ -375,4 +379,9 @@ int bnxt_hwrm_func_backing_store_cfg_v2(struct bnxt *bp, int bnxt_hwrm_func_backing_store_types_count(struct bnxt *bp); int bnxt_hwrm_func_backing_store_ctx_alloc(struct bnxt *bp, uint16_t types); int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp); +int bnxt_hwrm_tf_oem_cmd(struct bnxt *bp, + uint32_t *in, + uint16_t in_len, + uint32_t *out, + uint16_t out_len); #endif diff --git a/drivers/net/bnxt/bnxt_mpc.c b/drivers/net/bnxt/bnxt_mpc.c new file mode 100644 index 0000000000..5d1353184c --- /dev/null +++ b/drivers/net/bnxt/bnxt_mpc.c @@ -0,0 +1,828 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014-2020 Broadcom + * All rights reserved. + */ + +#include +#include +#include + +#include "bnxt.h" +#include "bnxt_ring.h" +#include "bnxt_mpc.h" +#include "bnxt_hwrm.h" +#include "hsi_struct_def_dpdk.h" + +/*#define MPC_DEBUG 1*/ + +#define BNXT_MPC_BP_SIZE 16 + +static int bnxt_mpc_chnls_enable(struct bnxt *bp) +{ + struct bnxt_mpc *mpc = bp->mpc; + uint8_t mpc_chnl_msk = 0; + int i, rc; + + if (!mpc) + return -EINVAL; + + for (i = 0; i < BNXT_MPC_CHNL_MAX; i++) { + if (!(mpc->mpc_chnls_cap & (1 << i))) + continue; + mpc_chnl_msk |= (1 << i); + } + mpc->mpc_chnls_en = mpc_chnl_msk; + + if (!BNXT_PF(bp)) + return 0; + + rc = bnxt_hwrm_func_cfg_mpc(bp, mpc_chnl_msk, true); + if (rc != 0) { + mpc->mpc_chnls_en = 0; + PMD_DRV_LOG(ERR, "MPC chnls enabling failed rc:%d\n", rc); + } + + return rc; +} + +static int bnxt_mpc_chnls_disable(struct bnxt *bp) +{ + struct bnxt_mpc *mpc = bp->mpc; + uint8_t mpc_chnl_msk = 0; + int i, rc; + + if (!mpc) + return -EINVAL; + mpc->mpc_chnls_en = 0; + + if (!BNXT_PF(bp)) + return 0; + + for (i = 0; i < BNXT_MPC_CHNL_MAX; i++) { + if (!(mpc->mpc_chnls_en & (1 << i))) + continue; + mpc_chnl_msk |= (1 << i); + } + rc = bnxt_hwrm_func_cfg_mpc(bp, mpc_chnl_msk, false); + if (rc != 0) + PMD_DRV_LOG(ERR, "MPC chnls disabling failed rc:%d\n", rc); + + return rc; +} + +static void bnxt_mpc_queue_release_mbufs(struct bnxt_mpc_txq *mpc_queue) +{ + struct bnxt_sw_mpc_bd *sw_ring; + uint16_t i; + + if (!mpc_queue) + return; + + sw_ring = mpc_queue->mpc_ring->mpc_buf_ring; + if (!sw_ring) + return; + + for (i = 0; i < mpc_queue->mpc_ring->mpc_ring_struct->ring_size; i++) { + if (sw_ring[i].mpc_mbuf) { + rte_free(sw_ring[i].mpc_mbuf); + sw_ring[i].mpc_mbuf = NULL; + } + } +} + +static void bnxt_mpc_queue_release_one(struct bnxt_mpc_txq *mpc_queue) +{ + if (!mpc_queue) + return; + + if (is_bnxt_in_error(mpc_queue->bp)) + return; + /* Free MPC ring HW descriptors */ + bnxt_mpc_queue_release_mbufs(mpc_queue); + bnxt_free_ring(mpc_queue->mpc_ring->mpc_ring_struct); + /* Free MPC completion ring HW descriptors */ + bnxt_free_ring(mpc_queue->cp_ring->cp_ring_struct); + + rte_memzone_free(mpc_queue->mz); + mpc_queue->mz = NULL; + + rte_free(mpc_queue->free); + rte_free(mpc_queue); +} + +static void bnxt_mpc_ring_free_one(struct bnxt_mpc_txq *mpc_queue) +{ + struct bnxt_cp_ring_info *cpr; + struct bnxt_mpc_ring_info *mpr; + struct bnxt_ring *ring; + + if (!mpc_queue) + return; + + if (is_bnxt_in_error(mpc_queue->bp)) + return; + + mpr = mpc_queue->mpc_ring; + ring = mpr->mpc_ring_struct; + if (ring->fw_ring_id == INVALID_HW_RING_ID) + return; + + cpr = mpc_queue->cp_ring; + bnxt_hwrm_ring_free(mpc_queue->bp, ring, + HWRM_RING_FREE_INPUT_RING_TYPE_TX, + cpr->cp_ring_struct->fw_ring_id); + ring->fw_ring_id = INVALID_HW_RING_ID; + memset(mpr->mpc_desc_ring, 0, + mpr->mpc_ring_struct->ring_size * sizeof(*mpr->mpc_desc_ring)); + memset(mpr->mpc_buf_ring, 0, + mpr->mpc_ring_struct->ring_size * sizeof(*mpr->mpc_buf_ring)); + mpr->raw_prod = 0; + mpr->raw_cons = 0; + + bnxt_free_cp_ring(mpc_queue->bp, cpr); + bnxt_hwrm_stat_ctx_free(mpc_queue->bp, cpr); +} + +int bnxt_mpc_close(struct bnxt *bp) +{ + int i, rc = 0; + struct bnxt_mpc_txq *mpc_queue; + struct bnxt_mpc *mpc; + + rc = is_bnxt_in_error(bp); + if (rc) + return rc; + + if (!bp->mpc) + return 0; + + mpc = bp->mpc; + /* free the MPC TX ring for each channel. */ + for (i = 0 ; i < BNXT_MPC_CHNL_MAX; i++) { + if (!(mpc->mpc_chnls_en & (1 << i))) + continue; + mpc_queue = mpc->mpc_txq[i]; + if (!mpc_queue) + continue; + bnxt_mpc_ring_free_one(mpc_queue); + bnxt_mpc_queue_release_one(mpc_queue); + mpc->mpc_txq[i] = NULL; + } + + rc = bnxt_mpc_chnls_disable(bp); + if (rc) + PMD_DRV_LOG(ERR, "MPC channels disable failed rc:%d\n", rc); + + return rc; +} + +static int bnxt_init_mpc_ring_struct(struct bnxt_mpc_txq *mpc_queue, + unsigned int socket_id) +{ + struct bnxt_cp_ring_info *cpr; + struct bnxt_mpc_ring_info *mpr; + struct bnxt_ring *ring; + int rc = 0; + + mpr = rte_zmalloc_socket("bnxt_mpc_ring", + sizeof(struct bnxt_mpc_ring_info), + RTE_CACHE_LINE_SIZE, socket_id); + if (mpr == NULL) + return -ENOMEM; + mpc_queue->mpc_ring = mpr; + + ring = rte_zmalloc_socket("bnxt_mpc_ring_struct", + sizeof(struct bnxt_ring), + RTE_CACHE_LINE_SIZE, socket_id); + if (ring == NULL) { + PMD_DRV_LOG(ERR, "MPC ring struct alloc failed rc:%d\n", rc); + rc = -ENOMEM; + goto bnxt_init_mpc_ring_struct_err; + } + + mpr->mpc_ring_struct = ring; + ring->ring_size = rte_align32pow2(mpc_queue->nb_mpc_desc); + ring->ring_mask = ring->ring_size - 1; + ring->bd = (void *)mpr->mpc_desc_ring; + ring->bd_dma = mpr->mpc_desc_mapping; + ring->vmem_size = ring->ring_size * sizeof(struct bnxt_sw_mpc_bd); + ring->vmem = (void **)&mpr->mpc_buf_ring; + ring->fw_ring_id = INVALID_HW_RING_ID; + + cpr = rte_zmalloc_socket("bnxt_mpc_ring", + sizeof(struct bnxt_cp_ring_info), + RTE_CACHE_LINE_SIZE, socket_id); + if (cpr == NULL) { + PMD_DRV_LOG(ERR, "MPC cp ring alloc failed rc:%d\n", rc); + rc = -ENOMEM; + goto bnxt_init_mpc_ring_struct_err1; + } + mpc_queue->cp_ring = cpr; + + ring = rte_zmalloc_socket("bnxt_mpc_ring_struct", + sizeof(struct bnxt_ring), + RTE_CACHE_LINE_SIZE, socket_id); + if (ring == NULL) { + PMD_DRV_LOG(ERR, "MPC cp ring struct alloc failed rc:%d\n", rc); + rc = -ENOMEM; + goto bnxt_init_mpc_ring_struct_err2; + } + cpr->cp_ring_struct = ring; + ring->ring_size = mpr->mpc_ring_struct->ring_size; + ring->ring_mask = ring->ring_size - 1; + ring->bd = (void *)cpr->cp_desc_ring; + ring->bd_dma = cpr->cp_desc_mapping; + ring->vmem_size = 0; + ring->vmem = NULL; + ring->fw_ring_id = INVALID_HW_RING_ID; + + return 0; + +bnxt_init_mpc_ring_struct_err2: + rte_free(cpr); +bnxt_init_mpc_ring_struct_err1: + rte_free(ring); +bnxt_init_mpc_ring_struct_err: + rte_free(mpr); + mpc_queue->mpc_ring = NULL; + return rc; +} + +/* + * For a MPC queue, allocates a completion ring with vmem and bd ring, + * stats mem, a TX ring with vmem and bd ring. + * + * Order in the allocation is: + * stats - Always non-zero length + * cp vmem - Always zero-length, supported for the bnxt_ring abstraction + * tx vmem - Only non-zero length + * cp bd ring - Always non-zero length + * tx bd ring - Only non-zero length + */ + +static int bnxt_alloc_mpc_rings(struct bnxt_mpc_txq *mpc_queue, + const char *suffix) +{ + struct bnxt_ring *cp_ring; + struct bnxt_cp_ring_info *cp_ring_info; + struct bnxt_mpc_ring_info *mpc_ring_info; + struct bnxt_ring *ring; + struct rte_pci_device *pdev; + const struct rte_memzone *mz = NULL; + char mz_name[RTE_MEMZONE_NAMESIZE]; + rte_iova_t mz_phys_addr; + + if (!mpc_queue) + return -EINVAL; + + pdev = mpc_queue->bp->pdev; + mpc_ring_info = mpc_queue->mpc_ring; + cp_ring = mpc_queue->cp_ring->cp_ring_struct; + cp_ring_info = mpc_queue->cp_ring; + + int stats_len = BNXT_HWRM_CTX_GET_SIZE(mpc_queue->bp); + stats_len = RTE_CACHE_LINE_ROUNDUP(stats_len); + stats_len = RTE_ALIGN(stats_len, 128); + + int cp_vmem_start = stats_len; + int cp_vmem_len = RTE_CACHE_LINE_ROUNDUP(cp_ring->vmem_size); + cp_vmem_len = RTE_ALIGN(cp_vmem_len, 128); + + int nq_vmem_len = RTE_CACHE_LINE_ROUNDUP(cp_ring->vmem_size); + nq_vmem_len = RTE_ALIGN(nq_vmem_len, 128); + + int nq_vmem_start = cp_vmem_start + cp_vmem_len; + + int mpc_vmem_start = nq_vmem_start + nq_vmem_len; + int mpc_vmem_len = + RTE_CACHE_LINE_ROUNDUP(mpc_ring_info->mpc_ring_struct->vmem_size); + mpc_vmem_len = RTE_ALIGN(mpc_vmem_len, 128); + + int cp_ring_start = mpc_vmem_start + mpc_vmem_len; + cp_ring_start = RTE_ALIGN(cp_ring_start, 4096); + + int cp_ring_len = RTE_CACHE_LINE_ROUNDUP(cp_ring->ring_size * + sizeof(struct cmpl_base)); + cp_ring_len = RTE_ALIGN(cp_ring_len, 128); + + int mpc_ring_start = cp_ring_start + cp_ring_len; + mpc_ring_start = RTE_ALIGN(mpc_ring_start, 4096); + int mpc_ring_len = + RTE_CACHE_LINE_ROUNDUP(mpc_ring_info->mpc_ring_struct->ring_size * + sizeof(struct tx_bd_mp_cmd)); + mpc_ring_len = RTE_ALIGN(mpc_ring_len, 4096); + + int total_alloc_len = mpc_ring_start + mpc_ring_len; + snprintf(mz_name, RTE_MEMZONE_NAMESIZE, + "bnxt_" PCI_PRI_FMT "-%04x_%s", pdev->addr.domain, + pdev->addr.bus, pdev->addr.devid, pdev->addr.function, + mpc_queue->chnl_id, suffix); + mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; + mz = rte_memzone_lookup(mz_name); + if (!mz) { + mz = rte_memzone_reserve_aligned(mz_name, total_alloc_len, + SOCKET_ID_ANY, + RTE_MEMZONE_2MB | + RTE_MEMZONE_SIZE_HINT_ONLY | + RTE_MEMZONE_IOVA_CONTIG, + getpagesize()); + if (mz == NULL || !mz->addr) + return -ENOMEM; + } + memset(mz->addr, 0, mz->len); + mz_phys_addr = mz->iova; + + mpc_queue->mz = mz; + ring = mpc_ring_info->mpc_ring_struct; + + ring->bd = ((char *)mz->addr + mpc_ring_start); + mpc_ring_info->mpc_desc_ring = (struct tx_bd_mp_cmd *)ring->bd; + ring->bd_dma = mz_phys_addr + mpc_ring_start; + mpc_ring_info->mpc_desc_mapping = ring->bd_dma; + ring->mem_zone = (const void *)mz; + + if (ring->vmem_size) { + ring->vmem = (void **)((char *)mz->addr + mpc_vmem_start); + mpc_ring_info->mpc_buf_ring = + (struct bnxt_sw_mpc_bd *)ring->vmem; + } + + cp_ring->bd = ((char *)mz->addr + cp_ring_start); + cp_ring->bd_dma = mz_phys_addr + cp_ring_start; + cp_ring_info->cp_desc_ring = cp_ring->bd; + cp_ring_info->cp_desc_mapping = cp_ring->bd_dma; + cp_ring->mem_zone = (const void *)mz; + + if (cp_ring->vmem_size) + *cp_ring->vmem = (char *)mz->addr + stats_len; + + cp_ring_info->hw_stats = mz->addr; + cp_ring_info->hw_stats_map = mz_phys_addr; + cp_ring_info->hw_stats_ctx_id = HWRM_NA_SIGNATURE; + + return 0; +} + +static void bnxt_init_one_mpc_ring(struct bnxt_mpc_txq *mpc_queue) +{ + struct bnxt_mpc_ring_info *mpr = mpc_queue->mpc_ring; + struct bnxt_cp_ring_info *cpr = mpc_queue->cp_ring; + struct bnxt_ring *ring = mpr->mpc_ring_struct; + + mpc_queue->wake_thresh = ring->ring_size / 2; + ring->fw_ring_id = INVALID_HW_RING_ID; + mpr->epoch = 0; + cpr->epoch = 0; +} + +static uint16_t get_mpc_ring_logical_id(uint8_t mpc_cap, + enum bnxt_mpc_chnl chnl_id, + uint16_t offset) +{ + unsigned int i; + uint8_t logical_id = 0; + + for (i = 0; i < BNXT_MPC_CHNL_MAX; i++) { + if (!(mpc_cap & (1 << i))) + continue; + + if (i == chnl_id) + return (logical_id + offset); + + logical_id++; + } + + return INVALID_HW_RING_ID; +} + +static int bnxt_mpc_queue_setup_one(struct bnxt *bp, enum bnxt_mpc_chnl chnl_id, + uint16_t nb_desc, unsigned int socket_id) +{ + int rc = 0; + struct bnxt_mpc *mpc; + struct bnxt_mpc_txq *mpc_queue; + + if (!bp || !bp->mpc) + return 0; + + mpc = bp->mpc; + mpc_queue = rte_zmalloc_socket("bnxt_mpc_queue", + sizeof(struct bnxt_mpc_txq), + RTE_CACHE_LINE_SIZE, socket_id); + if (!mpc_queue) { + PMD_DRV_LOG(ERR, "bnxt_mpc_queue allocation failed!"); + return -ENOMEM; + } + + mpc_queue->free = + rte_zmalloc_socket(NULL, + sizeof(struct bnxt_mpc_mbuf *) * nb_desc, + RTE_CACHE_LINE_SIZE, socket_id); + if (!mpc_queue->free) { + PMD_DRV_LOG(ERR, "allocation of mpc mbuf free array failed!"); + rc = -ENOMEM; + goto bnxt_mpc_queue_setup_one_err; + } + mpc_queue->bp = bp; + mpc_queue->nb_mpc_desc = nb_desc; + /* TBD: hardcoded to 1 for now and should be tuned later for perf */ + mpc_queue->free_thresh = BNXT_MPC_DESC_THRESH; + + rc = bnxt_init_mpc_ring_struct(mpc_queue, socket_id); + if (rc) + goto bnxt_mpc_queue_setup_one_err1; + + mpc_queue->chnl_id = chnl_id; + + /* allocate MPC TX ring hardware descriptors */ + rc = bnxt_alloc_mpc_rings(mpc_queue, "mpc"); + if (rc) { + PMD_DRV_LOG(ERR, "ring_dma_zone_reserve for mpc_ring failed!"); + rc = -ENOMEM; + goto bnxt_mpc_queue_setup_one_err1; + } + bnxt_init_one_mpc_ring(mpc_queue); + mpc_queue->queue_idx = get_mpc_ring_logical_id(bp->mpc->mpc_chnls_cap, + chnl_id, + bp->tx_cp_nr_rings); + mpc_queue->started = true; + mpc->mpc_txq[chnl_id] = mpc_queue; + + return 0; + +bnxt_mpc_queue_setup_one_err1: + rte_free(mpc_queue->free); +bnxt_mpc_queue_setup_one_err: + rte_free(mpc_queue); + return rc; +} + +static int bnxt_mpc_ring_alloc_one(struct bnxt *bp, enum bnxt_mpc_chnl chnl_id) +{ + int rc = 0; + struct bnxt_mpc_txq *mpc_queue; + struct bnxt_cp_ring_info *cpr; + struct bnxt_ring *cp_ring; + struct bnxt_mpc_ring_info *mpr; + struct bnxt_ring *ring; + struct bnxt_coal coal; + uint32_t map_index; + + if (!bp || !bp->mpc) + return 0; + + mpc_queue = bp->mpc->mpc_txq[chnl_id]; + if (!mpc_queue) + return -EINVAL; + + bnxt_init_dflt_coal(&coal); + cpr = mpc_queue->cp_ring; + cp_ring = cpr->cp_ring_struct; + map_index = mpc_queue->queue_idx; + + rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr); + if (rc) { + PMD_DRV_LOG(ERR, "mpc ring %d stats alloc failed rc:%d!\n", + chnl_id, rc); + return rc; + } + rc = bnxt_alloc_cmpl_ring(bp, map_index, cpr); + if (rc) { + PMD_DRV_LOG(ERR, "mpc ring %d cmpl ring alloc failed rc:%d!\n", + chnl_id, rc); + goto bnxt_mpc_ring_alloc_one_err; + } + mpr = mpc_queue->mpc_ring; + ring = mpr->mpc_ring_struct; + map_index = BNXT_MPC_MAP_INDEX(chnl_id, mpc_queue->queue_idx); + + rc = bnxt_hwrm_ring_alloc(bp, + ring, + HWRM_RING_ALLOC_INPUT_RING_TYPE_TX, + map_index, + cpr->hw_stats_ctx_id, + cp_ring->fw_ring_id, + MPC_HW_COS_ID); + if (rc) { + PMD_DRV_LOG(ERR, "mpc ring %d tx ring alloc failed rc:%d!\n", + chnl_id, rc); + goto bnxt_mpc_ring_alloc_one_err1; + } + + bnxt_set_db(bp, &mpr->db, HWRM_RING_ALLOC_INPUT_RING_TYPE_TX, chnl_id, + ring->fw_ring_id, ring->ring_mask); + + bnxt_hwrm_set_ring_coal(bp, &coal, cp_ring->fw_ring_id); + + return rc; + +bnxt_mpc_ring_alloc_one_err1: + bnxt_free_cp_ring(bp, cpr); +bnxt_mpc_ring_alloc_one_err: + bnxt_hwrm_stat_ctx_free(bp, cpr); + return rc; +} + +int bnxt_mpc_open(struct bnxt *bp) +{ + int rc = 0; + enum bnxt_mpc_chnl i; + struct bnxt_mpc *mpc; + unsigned int socket_id; + + rc = is_bnxt_in_error(bp); + if (rc) + return rc; + + if (!bp->mpc) + return 0; + + /* enable the MPC channels first */ + rc = bnxt_mpc_chnls_enable(bp); + if (rc) { + PMD_DRV_LOG(ERR, "MPC channels enable failed rc:%d\n", rc); + return rc; + } + socket_id = rte_lcore_to_socket_id(rte_get_main_lcore()); + mpc = bp->mpc; + + /* Limit to MPC TE_CFA and RE_CFA */ + mpc->mpc_chnls_cap &= (1 << HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA) | + (1 << HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA); + + /* allocate one MPC TX ring for each channel. */ + for (i = 0; i < BNXT_MPC_CHNL_MAX; i++) { + if (!(mpc->mpc_chnls_cap & (1 << i))) + continue; + rc = bnxt_mpc_queue_setup_one(bp, i, BNXT_MPC_NB_DESC, socket_id); + if (rc) { + PMD_DRV_LOG(ERR, "MPC queue %d setup failed rc:%d\n", + i, rc); + goto bnxt_mpc_open_err; + } + rc = bnxt_mpc_ring_alloc_one(bp, i); + if (rc) { + PMD_DRV_LOG(ERR, "MPC ring %d alloc failed rc:%d\n", + i, rc); + goto bnxt_mpc_open_err; + } + } + + return rc; + +bnxt_mpc_open_err: + bnxt_mpc_close(bp); + return rc; +} + +int bnxt_mpc_cmd_cmpl(struct bnxt_mpc_txq *mpc_queue, struct bnxt_mpc_mbuf *out_msg) +{ + struct bnxt_cp_ring_info *cpr = mpc_queue->cp_ring; + uint32_t raw_cons = cpr->cp_raw_cons; + uint32_t cons; + struct cmpl_base *mpc_cmpl; + uint32_t nb_mpc_cmds = 0; + struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring; + struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct; + uint32_t ring_mask = cp_ring_struct->ring_mask; + uint32_t idx = raw_cons; + uint32_t num_bds; + bool is_long = + (out_msg->cmp_type == CMPL_BASE_TYPE_MID_PATH_LONG ? true : false); + + do { + cons = RING_CMPL(ring_mask, raw_cons); +#ifdef MPC_DEBUG + printf("raw_cons:%d cons:%d\n", raw_cons, cons); +#endif + mpc_cmpl = &cpr->cp_desc_ring[cons]; + + rte_prefetch_non_temporal(&cp_desc_ring[(cons + 2) & + ring_mask]); + + if (!CMPL_VALID(mpc_cmpl, cpr->valid)) { + break; + } else if (is_long) { + uint32_t cons_tmp = cons + 1; + uint32_t valid; + struct cmpl_base *tmp_mpc_cmpl = &cp_desc_ring[cons_tmp & ring_mask]; + + if ((cons_tmp & ring_mask) < (cons & ring_mask)) + valid = !cpr->valid; + else + valid = cpr->valid; + + if (!CMPL_VALID(tmp_mpc_cmpl, valid)) + break; + } + + NEXT_CMPL(cpr, + cons, + cpr->valid, + (is_long ? 2 : 1)); + + rte_prefetch0(&cp_desc_ring[cons]); + + if (likely(CMP_TYPE(mpc_cmpl) == out_msg->cmp_type)) { + nb_mpc_cmds++; + idx = raw_cons; + raw_cons = cons; + break; + } else { + RTE_LOG_DP(DEBUG, BNXT, "Unhandled CMP type %02x\n", + CMP_TYPE(mpc_cmpl)); + } +#ifdef MPC_DEBUG + printf("info2:0x%08x nb_mpc_cmds:%d\n", mpc_cmpl->info2, nb_mpc_cmds); +#endif + raw_cons = cons; + } while (nb_mpc_cmds < ring_mask); + + if (nb_mpc_cmds) { + memcpy(out_msg->msg_data, + &cpr->cp_desc_ring[idx], + BNXT_MPC_BP_SIZE); + + if (is_long) { + uint32_t tidx = idx + 1; + + if (tidx >= BNXT_MPC_NB_DESC) + tidx = 0; + + memcpy(out_msg->msg_data + BNXT_MPC_BP_SIZE, + &cpr->cp_desc_ring[tidx], + BNXT_MPC_BP_SIZE); + } + +#ifdef MPC_DEBUG + printf("cp_raw_cons:%d\n", cpr->cp_raw_cons); +#endif + if (is_long) + num_bds = 2; + else + num_bds = 1; + + cpr->cp_raw_cons = idx + num_bds; + + /* Handle the wrap */ + if (cpr->cp_raw_cons >= BNXT_MPC_NB_DESC) { +#ifdef MPC_DEBUG + printf("Completion queue epoch flip from: %d to %d\n", + cpr->epoch, + (cpr->epoch == 0 ? 1 : 0)); +#endif + cpr->epoch = (cpr->epoch == 0 ? 1 : 0); + cpr->cp_raw_cons -= BNXT_MPC_NB_DESC; + } + + bnxt_db_mpc_cq(cpr); + } + + return nb_mpc_cmds; +} + +#ifdef MPC_DEBUG +void dump_bd(uint8_t *bd, uint32_t num_bd) +{ + int j; + int i; + + for (j = 0; j < num_bd; j++) { + printf("%d: ", j); + for (i = 0; i < BNXT_MPC_BP_SIZE; i++) { + printf("%02x", *bd); + bd++; + } + + printf("\n"); + } + printf("\n"); +} +#endif + +static uint16_t bnxt_mpc_xmit(struct bnxt_mpc_mbuf *mpc_cmd, + struct bnxt_mpc_txq *mpc_queue, + uint32_t *opaque) +{ + struct bnxt_mpc_ring_info *mpr = mpc_queue->mpc_ring; + struct bnxt_ring *ring = mpr->mpc_ring_struct; + unsigned short nr_bds = 0; + uint16_t prod; + struct bnxt_sw_mpc_bd *mpc_buf; + struct tx_bd_mp_cmd *mpc_bd; + uint8_t *msg_buf; + int i; + + if (unlikely(is_bnxt_in_error(mpc_queue->bp))) + return -EIO; + + nr_bds = (mpc_cmd->msg_size + sizeof(struct tx_bd_mp_cmd) - 1) + / sizeof(struct tx_bd_mp_cmd) + 1; + + prod = RING_IDX(ring, mpr->raw_prod); +#ifdef MPC_DEBUG + printf("tx raw prod:%d prod:%d\n", mpr->raw_prod, prod); +#endif + mpc_buf = &mpr->mpc_buf_ring[prod]; + mpc_buf->mpc_mbuf = mpc_cmd; + mpc_buf->nr_bds = nr_bds; + + mpc_bd = &mpr->mpc_desc_ring[prod]; + memset(mpc_bd, 0, sizeof(struct tx_bd_mp_cmd)); + mpc_bd->opaque = *opaque; + mpc_bd->flags_type = nr_bds << TX_BD_MP_CMD_FLAGS_BD_CNT_SFT; + mpc_bd->flags_type |= TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD; + mpc_bd->len = mpc_cmd->msg_size; + + /* copy the messages to the subsequent inline bds */ + for (i = 0; i < nr_bds - 1; i++) { + mpr->raw_prod = RING_NEXT(mpr->raw_prod) % BNXT_MPC_NB_DESC; + prod = RING_IDX(ring, mpr->raw_prod); +#ifdef MPC_DEUBG + printf("tx raw prod:%d prod:%d\n", mpr->raw_prod, prod); +#endif + mpc_bd = &mpr->mpc_desc_ring[prod]; + msg_buf = mpc_cmd->msg_data + i * sizeof(struct tx_bd_mp_cmd); + memcpy(mpc_bd, msg_buf, sizeof(struct tx_bd_mp_cmd)); + } + + mpr->raw_prod = RING_NEXT(mpr->raw_prod) % BNXT_MPC_NB_DESC; +#ifdef MPC_DEBUG + printf("tx raw prod:%d prod:%d\n", mpr->raw_prod, prod); +#endif + return 0; +} + +int bnxt_mpc_send(struct bnxt *bp, + struct bnxt_mpc_mbuf *in_msg, + struct bnxt_mpc_mbuf *out_msg, + uint32_t *opaque, + bool batch) +{ + int rc; + struct bnxt_mpc_txq *mpc_queue = bp->mpc->mpc_txq[in_msg->chnl_id]; + int retry = BNXT_MPC_RX_RETRY; + uint32_t pi = 0; + + if (out_msg->cmp_type != CMPL_BASE_TYPE_MID_PATH_SHORT && + out_msg->cmp_type != CMPL_BASE_TYPE_MID_PATH_LONG) + return -1; + +#ifdef MPC_DEBUG + if (mpc_queue == NULL || mpc_queue->mpc_ring == NULL) + return -1; +#endif + + /* + * Save the producer index so that if wrapping occurs + * it can be detected. + */ + pi = mpc_queue->mpc_ring->raw_prod; + rc = bnxt_mpc_xmit(in_msg, mpc_queue, opaque); + + if (unlikely(rc)) + return -1; +#ifdef MPC_DEBUG + printf("raw_prod:%d pi:%d\n", mpc_queue->mpc_ring->raw_prod, pi); +#endif + /* + * If the producer index wraps then toggle the epoch. + */ + if (mpc_queue->mpc_ring->raw_prod < pi) { +#ifdef MPC_DEBUG + printf("Tx queue epoch flip from: %d to %d\n", + mpc_queue->mpc_ring->epoch, + (mpc_queue->mpc_ring->epoch == 0 ? 1 : 0)); +#endif + mpc_queue->mpc_ring->epoch = (mpc_queue->mpc_ring->epoch == 0 ? 1 : 0); + } + +#ifdef MPC_DEBUG + dump_bd(&mpc_queue->mpc_ring->mpc_desc_ring[pi], 4); +#endif + /* + * Ring the Tx doorbell. + */ + bnxt_db_mpc_write(&mpc_queue->mpc_ring->db, + mpc_queue->mpc_ring->raw_prod, + mpc_queue->mpc_ring->epoch); + + if (batch) + return 0; + + /* Wait for response */ + do { + rte_delay_us_block(BNXT_MPC_RX_US_DELAY); + + rc = bnxt_mpc_cmd_cmpl(mpc_queue, out_msg); + + if (rc == 1) + return 0; +#ifdef MPC_DEBUG + printf("Received zero or more than one completion:%d\n", rc); +#endif + retry--; + } while (retry); + + return -1; +} diff --git a/drivers/net/bnxt/bnxt_mpc.h b/drivers/net/bnxt/bnxt_mpc.h new file mode 100644 index 0000000000..cfbb461e9c --- /dev/null +++ b/drivers/net/bnxt/bnxt_mpc.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014-2020 Broadcom + * All rights reserved. + */ + +#ifndef _BNXT_MPC_H_ +#define _BNXT_MPC_H_ + +#include +#include +#include + +/* MPC Batch support */ +extern bool bnxt_tfc_mpc_batch; +extern uint8_t bnxt_mpc_batch_count; + +#define BNXT_MPC_RX_RETRY 100000 + +#define BNXT_MPC_NB_DESC 128 +#define BNXT_MPC_DESC_THRESH 3 +#define BNXT_MPC_CHNL_SHIFT 16 +#define BNXT_MPC_QIDX_MSK 0xFFFF +#define BNXT_MPC_CHNL(x) ((x) >> BNXT_MPC_CHNL_SHIFT) +#define BNXT_MPC_QIDX(x) ((x) & BNXT_MPC_QIDX_MSK) +#define BNXT_MPC_MAP_INDEX(x, y) (((x) << BNXT_MPC_CHNL_SHIFT) | (y)) + +#define BNXT_MPC_CHNLS_SUPPORTED 2 /* Limit to MPC TE_CFA and RE_CFA */ + +/* BNXT_MPC_RINGS_SUPPORTED set to 1 TE_CFA and 1 1 RE_CFA types. + * Can be set upto tx_nr_rings * BNXT_MPC_CHNLS_SUPPORTED if needed. + */ +#define BNXT_MPC_RINGS_SUPPORTED (1 * BNXT_MPC_CHNLS_SUPPORTED) + +/* Defines the number of msgs there are in an MPC msg completion event. + * Used to pass an opaque value into the MPC msg xmit function. The + * completion processing uses this value to ring the doorbell correctly to + * signal "completion event processing complete" to the hardware. + */ +#define BNXT_MPC_COMP_MSG_COUNT 1 + +/* Defines the uS delay prior to processing an MPC completion */ +#define BNXT_MPC_RX_US_DELAY 1 + +enum bnxt_mpc_chnl { + BNXT_MPC_CHNL_TCE = 0, + BNXT_MPC_CHNL_RCE = 1, + BNXT_MPC_CHNL_TE_CFA = 2, + BNXT_MPC_CHNL_RE_CFA = 3, + BNXT_MPC_CHNL_PRIMATE = 4, + BNXT_MPC_CHNL_MAX = 5, +}; + +struct bnxt_sw_mpc_bd { + struct bnxt_mpc_mbuf *mpc_mbuf; /* mpc mbuf associated with mpc bd */ + unsigned short nr_bds; +}; + +struct bnxt_mpc_ring_info { + uint16_t raw_prod; + uint16_t raw_cons; + struct bnxt_db_info db; + + struct tx_bd_mp_cmd *mpc_desc_ring; + struct bnxt_sw_mpc_bd *mpc_buf_ring; + + rte_iova_t mpc_desc_mapping; + + uint32_t dev_state; + + struct bnxt_ring *mpc_ring_struct; + uint32_t epoch; +}; + +struct bnxt_mpc_mbuf { + enum bnxt_mpc_chnl chnl_id; + uint8_t cmp_type; + uint8_t *msg_data; + /* MPC msg size in bytes, must be multiple of 16Bytes */ + uint16_t msg_size; +}; + +struct bnxt_mpc_txq { + enum bnxt_mpc_chnl chnl_id; + uint32_t queue_idx; + uint16_t nb_mpc_desc; /* number of MPC descriptors */ + uint16_t free_thresh;/* minimum mpc cmds before freeing */ + int wake_thresh; + uint8_t started; /* MPC queue is started */ + + struct bnxt *bp; + struct bnxt_mpc_ring_info *mpc_ring; + unsigned int cp_nr_rings; + struct bnxt_cp_ring_info *cp_ring; + const struct rte_memzone *mz; + struct bnxt_mpc_mbuf **free; + + void (*cmpl_handler_cb)(struct bnxt_mpc_txq *mpc_queue, + uint32_t nb_mpc_cmds); +}; + +struct bnxt_mpc { + uint8_t mpc_chnls_cap; + uint8_t mpc_chnls_en; + struct bnxt_mpc_txq *mpc_txq[BNXT_MPC_CHNL_MAX]; +}; + +int bnxt_mpc_open(struct bnxt *bp); +int bnxt_mpc_close(struct bnxt *bp); +int bnxt_mpc_send(struct bnxt *bp, + struct bnxt_mpc_mbuf *in_msg, + struct bnxt_mpc_mbuf *out_msg, + uint32_t *opaque, + bool batch); +int bnxt_mpc_cmd_cmpl(struct bnxt_mpc_txq *mpc_queue, struct bnxt_mpc_mbuf *out_msg); +int bnxt_mpc_poll_cmd_cmpls(struct bnxt_mpc_txq *mpc_queue); + +#endif diff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c index 9e512321d9..c4a5877ccc 100644 --- a/drivers/net/bnxt/bnxt_ring.c +++ b/drivers/net/bnxt/bnxt_ring.c @@ -57,6 +57,7 @@ int bnxt_alloc_ring_grps(struct bnxt *bp) /* P5 does not support ring groups. * But we will use the array to save RSS context IDs. */ + /* TODO Revisit for Thor 2 */ if (BNXT_CHIP_P5_P7(bp)) { bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5; } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) { @@ -329,7 +330,7 @@ int bnxt_alloc_rings(struct bnxt *bp, unsigned int socket_id, uint16_t qidx, return 0; } -static void bnxt_init_dflt_coal(struct bnxt_coal *coal) +void bnxt_init_dflt_coal(struct bnxt_coal *coal) { /* Tick values in micro seconds. * 1 coal_buf x bufs_per_record = 1 completion record. @@ -347,12 +348,12 @@ static void bnxt_init_dflt_coal(struct bnxt_coal *coal) coal->cmpl_aggr_dma_tmr_during_int = BNXT_CMPL_AGGR_DMA_TMR_DURING_INT; } -static void bnxt_set_db(struct bnxt *bp, - struct bnxt_db_info *db, - uint32_t ring_type, - uint32_t map_idx, - uint32_t fid, - uint32_t ring_mask) +void bnxt_set_db(struct bnxt *bp, + struct bnxt_db_info *db, + uint32_t ring_type, + uint32_t map_idx, + uint32_t fid, + uint32_t ring_mask) { if (BNXT_CHIP_P5_P7(bp)) { int db_offset = DB_PF_OFFSET; @@ -400,8 +401,8 @@ static void bnxt_set_db(struct bnxt *bp, db->db_ring_mask = ring_mask; } -static int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index, - struct bnxt_cp_ring_info *cpr) +int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index, + struct bnxt_cp_ring_info *cpr) { struct bnxt_ring *cp_ring = cpr->cp_ring_struct; uint32_t nq_ring_id = HWRM_NA_SIGNATURE; diff --git a/drivers/net/bnxt/bnxt_ring.h b/drivers/net/bnxt/bnxt_ring.h index b33fb75284..be0a560ead 100644 --- a/drivers/net/bnxt/bnxt_ring.h +++ b/drivers/net/bnxt/bnxt_ring.h @@ -37,7 +37,8 @@ #define MAX_CP_DESC_CNT (16 * 1024) #define INVALID_HW_RING_ID ((uint16_t)-1) -#define INVALID_STATS_CTX_ID ((uint16_t)-1) +#define INVALID_STATS_CTX_ID ((uint16_t)-1) +#define MPC_HW_COS_ID ((uint16_t)-2) struct bnxt_ring { void *bd; @@ -80,6 +81,15 @@ void bnxt_free_async_cp_ring(struct bnxt *bp); int bnxt_alloc_async_ring_struct(struct bnxt *bp); int bnxt_alloc_rxtx_nq_ring(struct bnxt *bp); void bnxt_free_rxtx_nq_ring(struct bnxt *bp); +void bnxt_init_dflt_coal(struct bnxt_coal *coal); +int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index, + struct bnxt_cp_ring_info *cpr); +void bnxt_set_db(struct bnxt *bp, + struct bnxt_db_info *db, + uint32_t ring_type, + uint32_t map_idx, + uint32_t fid, + uint32_t ring_mask); static inline void bnxt_db_write(struct bnxt_db_info *db, uint32_t idx) { @@ -98,6 +108,27 @@ static inline void bnxt_db_write(struct bnxt_db_info *db, uint32_t idx) } } +static inline void bnxt_db_mpc_write(struct bnxt_db_info *db, uint32_t idx, uint32_t epoch) +{ + uint32_t db_idx = DB_RING_IDX(db, idx); + void *doorbell = db->doorbell; + + if (likely(db->db_64)) { + uint64_t key_idx = db->db_key64 | db_idx | + (epoch << 24); +#ifdef RING_DEBUG + printf("DB: 0x%08x:%08x\n", + (uint32_t)((key_idx >> 32) & 0xFFFFFFFF), + (uint32_t)(key_idx & 0xFFFFFFFF)); +#endif + rte_write64_relaxed(key_idx, doorbell); + } else { + uint32_t key_idx = db->db_key32 | db_idx; + + rte_write32_relaxed(key_idx, doorbell); + } +} + /* Ring an NQ doorbell and disable interrupts for the ring. */ static inline void bnxt_db_nq(struct bnxt_cp_ring_info *cpr) { @@ -143,4 +174,25 @@ static inline void bnxt_db_cq(struct bnxt_cp_ring_info *cpr) B_CP_DIS_DB(cpr, cp_raw_cons); } } + +static inline void bnxt_db_mpc_cq(struct bnxt_cp_ring_info *cpr) +{ + struct bnxt_db_info *db = &cpr->cp_db; + uint32_t idx = DB_RING_IDX(&cpr->cp_db, cpr->cp_raw_cons); + + if (likely(db->db_64)) { + uint64_t key_idx = db->db_key64 | idx | + (cpr->epoch << 24); + void *doorbell = db->doorbell; + + rte_compiler_barrier(); + rte_write64_relaxed(key_idx, doorbell); + } else { + uint32_t cp_raw_cons = cpr->cp_raw_cons; + + rte_compiler_barrier(); + B_CP_DIS_DB(cpr, cp_raw_cons); + } +} + #endif diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h index f9190fcd89..fd83e4881d 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h @@ -3,6 +3,10 @@ * All rights reserved. */ +/*! + * \file + * \brief Exported functions for CFA HW programming + */ #ifndef _HCAPI_CFA_H_ #define _HCAPI_CFA_H_ @@ -104,18 +108,7 @@ struct hcapi_cfa_devops { extern const size_t CFA_RM_HANDLE_DATA_SIZE; -#if SUPPORT_CFA_HW_ALL -extern const struct hcapi_cfa_devops cfa_p4_devops; -extern const struct hcapi_cfa_devops cfa_p58_devops; - -#elif defined(SUPPORT_CFA_HW_P4) && SUPPORT_CFA_HW_P4 extern const struct hcapi_cfa_devops cfa_p4_devops; -uint64_t hcapi_cfa_p4_key_hash(uint64_t *key_data, uint16_t bitlen); -/* SUPPORT_CFA_HW_P4 */ -#elif defined(SUPPORT_CFA_HW_P58) && SUPPORT_CFA_HW_P58 extern const struct hcapi_cfa_devops cfa_p58_devops; -uint64_t hcapi_cfa_p58_key_hash(uint64_t *key_data, uint16_t bitlen); -/* SUPPORT_CFA_HW_P58 */ -#endif #endif /* HCAPI_CFA_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h index 16a31598d6..7d19bf3847 100644 --- a/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h +++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h @@ -1,12 +1,8 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2021 Broadcom + * Copyright(c) 2019-2023 Broadcom * All rights reserved. */ -/*! - * \file - * \brief Exported functions for CFA HW programming - */ #ifndef _HCAPI_CFA_DEFS_H_ #define _HCAPI_CFA_DEFS_H_ @@ -23,34 +19,24 @@ #define CFA_BITS_PER_BYTE (8) #define CFA_BITS_PER_WORD (sizeof(uint32_t) * CFA_BITS_PER_BYTE) #define __CFA_ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask)) +#ifndef CFA_ALIGN #define CFA_ALIGN(x, a) __CFA_ALIGN_MASK((x), (a) - 1) +#endif #define CFA_ALIGN_256(x) CFA_ALIGN(x, 256) #define CFA_ALIGN_128(x) CFA_ALIGN(x, 128) #define CFA_ALIGN_32(x) CFA_ALIGN(x, 32) -#define NUM_WORDS_ALIGN_32BIT(x) (CFA_ALIGN_32(x) / CFA_BITS_PER_WORD) -#define NUM_WORDS_ALIGN_128BIT(x) (CFA_ALIGN_128(x) / CFA_BITS_PER_WORD) -#define NUM_WORDS_ALIGN_256BIT(x) (CFA_ALIGN_256(x) / CFA_BITS_PER_WORD) - /* TODO: redefine according to chip variant */ #define CFA_GLOBAL_CFG_DATA_SZ (100) -#ifndef SUPPORT_CFA_HW_P4 -#define SUPPORT_CFA_HW_P4 (0) -#endif - -#ifndef SUPPORT_CFA_HW_P45 -#define SUPPORT_CFA_HW_P45 (0) -#endif - -#ifndef SUPPORT_CFA_HW_P58 -#define SUPPORT_CFA_HW_P58 (0) -#endif - -#if SUPPORT_CFA_HW_ALL #include "hcapi_cfa_p4.h" #include "hcapi_cfa_p58.h" -#endif /* SUPPORT_CFA_HW_ALL */ + +#define CFA_PROF_L2CTXT_TCAM_MAX_FIELD_CNT CFA_P58_PROF_L2_CTXT_TCAM_MAX_FLD +#define CFA_PROF_L2CTXT_REMAP_MAX_FIELD_CNT CFA_P58_PROF_L2_CTXT_RMP_DR_MAX_FLD +#define CFA_PROF_MAX_KEY_CFG_SZ sizeof(struct cfa_p58_prof_key_cfg) +#define CFA_KEY_MAX_FIELD_CNT 0 +#define CFA_ACT_MAX_TEMPLATE_SZ 0 /* * Hashing defines @@ -61,6 +47,7 @@ #define ucrc32(ch, crc) (crc32tbl[((crc) ^ (ch)) & 0xff] ^ ((crc) >> 8)) #define crc32(x, y) crc32i(~0, x, y) + /** * CFA HW version definition */ @@ -68,7 +55,8 @@ enum hcapi_cfa_ver { HCAPI_CFA_P40 = 0, /**< CFA phase 4.0 */ HCAPI_CFA_P45 = 1, /**< CFA phase 4.5 */ HCAPI_CFA_P58 = 2, /**< CFA phase 5.8 */ - HCAPI_CFA_PMAX = 3 + HCAPI_CFA_P59 = 3, /**< CFA phase 5.9 */ + HCAPI_CFA_PMAX = 4 }; /** @@ -100,7 +88,7 @@ enum hcapi_cfa_hwops { * operation is also undo the add operation * performed by the HCAPI_CFA_HWOPS_ADD op. */ - HCAPI_CFA_HWOPS_EVICT, /*< This operation is used to evict entries from + HCAPI_CFA_HWOPS_EVICT, /*< This operation is used to edit entries from * CFA cache memories. This operation is only * applicable to tables that use CFA caches. */ @@ -116,6 +104,44 @@ enum hcapi_cfa_key_ctrlops { HCAPI_CFA_KEY_CTRLOPS_MAX }; +/** + * CFA HW field structure definition + */ +struct hcapi_cfa_field { + /** [in] Starting bit position pf the HW field within a HW table + * entry. + */ + uint16_t bitpos; + /** [in] Number of bits for the HW field. */ + uint16_t bitlen; +}; + +/** + * CFA HW table entry layout structure definition + */ +struct hcapi_cfa_layout { + /** [out] Bit order of layout */ + bool is_msb_order; + /** [out] Size in bits of entry */ + uint32_t total_sz_in_bits; + /** [out] data pointer of the HW layout fields array */ + struct hcapi_cfa_field *field_array; + /** [out] number of HW field entries in the HW layout field array */ + uint32_t array_sz; + /** [out] layout_id - layout id associated with the layout */ + uint16_t layout_id; +}; + +/** + * CFA HW data object definition + */ +struct hcapi_cfa_data_obj { + /** [in] HW field identifier. Used as an index to a HW table layout */ + uint16_t field_id; + /** [in] Value of the HW field */ + uint64_t val; +}; + /** * CFA HW definition */ @@ -294,6 +320,91 @@ struct hcapi_cfa_key_loc { uint32_t mem_idx; }; +/** + * CFA HW layout table definition + */ +struct hcapi_cfa_layout_tbl { + /** [out] data pointer to an array of fix formatted layouts supported. + * The index to the array is the CFA HW table ID + */ + const struct hcapi_cfa_layout *tbl; + /** [out] number of fix formatted layouts in the layout array */ + uint16_t num_layouts; +}; + +/** + * Key template consists of key fields that can be enabled/disabled + * individually. + */ +struct hcapi_cfa_key_template { + /** [in] key field enable field array, set 1 to the correspeonding + * field enable to make a field valid + */ + uint8_t field_en[CFA_KEY_MAX_FIELD_CNT]; + /** [in] Identify if the key template is for TCAM. If false, the + * key template is for EM. This field is mandantory for device that + * only support fix key formats. + */ + bool is_wc_tcam_key; + /** [in] Identify if the key template will be use for IPv6 Keys. + * + */ + bool is_ipv6_key; +}; + +/** + * key layout consist of field array, key bitlen, key ID, and other meta data + * pertain to a key + */ +struct hcapi_cfa_key_layout { + /** [out] key layout data */ + struct hcapi_cfa_layout *layout; + /** [out] actual key size in number of bits */ + uint16_t bitlen; + /** [out] key identifier and this field is only valid for device + * that supports fix key formats + */ + uint16_t id; + /** [out] Identified the key layout is WC TCAM key */ + bool is_wc_tcam_key; + /** [out] Identify if the key template will be use for IPv6 Keys. + * + */ + bool is_ipv6_key; + /** [out] total slices size, valid for WC TCAM key only. It can be + * used by the user to determine the total size of WC TCAM key slices + * in bytes. + */ + uint16_t slices_size; +}; + +/** + * key layout memory contents + */ +struct hcapi_cfa_key_layout_contents { + /** key layouts */ + struct hcapi_cfa_key_layout key_layout; + + /** layout */ + struct hcapi_cfa_layout layout; + + /** fields */ + struct hcapi_cfa_field field_array[CFA_KEY_MAX_FIELD_CNT]; +}; + +/** + * Action template consists of action fields that can be enabled/disabled + * individually. + */ +struct hcapi_cfa_action_template { + /** [in] CFA version for the action template */ + enum hcapi_cfa_ver hw_ver; + /** [in] action field enable field array, set 1 to the correspeonding + * field enable to make a field valid + */ + uint8_t data[CFA_ACT_MAX_TEMPLATE_SZ]; +}; + /** * Action record info */ @@ -332,6 +443,421 @@ struct hcapi_cfa_action_obj { struct hcapi_cfa_action_layout *layout; }; +/** + * action layout consist of field array, action wordlen and action format ID + */ +struct hcapi_cfa_action_layout { + /** [in] action identifier */ + uint16_t id; + /** [out] action layout data */ + struct hcapi_cfa_layout *layout; + /** [out] actual action record size in number of bits */ + uint16_t bitlen; +}; + +/** + * CFA backing store type definition + */ +enum hcapi_cfa_bs_type { + HCAPI_CFA_BS_TYPE_LKUP, /**< EM LKUP backing store type */ + HCAPI_CFA_BS_TYPE_ACT, /**< Action backing store type */ + HCAPI_CFA_BS_TYPE_MAX +}; + +/** + * CFA backing store configuration data object + */ +struct hcapi_cfa_bs_cfg { + enum hcapi_cfa_bs_type type; + uint16_t tbl_scope; + struct hcapi_cfa_bs_db *bs_db; +}; + +/** + * CFA backing store data base object + */ +struct hcapi_cfa_bs_db { + /** [in] memory manager database signature */ + uint32_t signature; +#define HCAPI_CFA_BS_SIGNATURE 0xCFA0B300 + /** [in] memory manager database base pointer (VA) */ + void *mgmt_db; + /** [in] memory manager database size in bytes */ + uint32_t mgmt_db_sz; + /** [in] Backing store memory pool base pointer + * (VA – backed by IOVA which is DMA accessible)) + */ + void *bs_ptr; + /** [in] bs_offset - byte offset to the section of the + * backing store memory managed by the backing store + * memory manager. + * For EM backing store, this is the starting byte + * offset to the EM record memory. + * For Action backing store, this offset is 0. + */ + uint32_t offset; + /** [in] backing store memory pool size in bytes + */ + uint32_t bs_sz; +}; + +/** + * \defgroup CFA_HCAPI_PUT_API + * HCAPI used for writing to the hardware + * @{ + */ + +/** + * This API provides the functionality to program a specified value to a + * HW field based on the provided programming layout. + * + * @param[in,out] obj_data + * A data pointer to a CFA HW key/mask data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_id + * ID of the HW field to be programmed + * + * @param[in] val + * Value of the HW field to be programmed + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_put_field(uint64_t *data_buf, + const struct hcapi_cfa_layout *layout, + uint16_t field_id, uint64_t val); + +/** + * This API provides the functionality to program an array of field values + * with corresponding field IDs to a number of profiler sub-block fields + * based on the fixed profiler sub-block hardware programming layout. + * + * @param[in, out] obj_data + * A pointer to a CFA profiler key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_tbl + * A pointer to an array that consists of the object field + * ID/value pairs + * + * @param[in] field_tbl_sz + * Number of entries in the table + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_put_fields(uint64_t *obj_data, + const struct hcapi_cfa_layout *layout, + struct hcapi_cfa_data_obj *field_tbl, + uint16_t field_tbl_sz); +/** + * This API provides the functionality to program an array of field values + * with corresponding field IDs to a number of profiler sub-block fields + * based on the fixed profiler sub-block hardware programming layout. This + * API will swap the n byte blocks before programming the field array. + * + * @param[in, out] obj_data + * A pointer to a CFA profiler key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_tbl + * A pointer to an array that consists of the object field + * ID/value pairs + * + * @param[in] field_tbl_sz + * Number of entries in the table + * + * @param[in] data_size + * size of the data in bytes + * + * @param[in] n + * block size in bytes + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_put_fields_swap(uint64_t *obj_data, + const struct hcapi_cfa_layout *layout, + struct hcapi_cfa_data_obj *field_tbl, + uint16_t field_tbl_sz, uint16_t data_size, + uint16_t n); +/** + * This API provides the functionality to write a value to a + * field within the bit position and bit length of a HW data + * object based on a provided programming layout. + * + * @param[in, out] act_obj + * A pointer of the action object to be initialized + * + * @param[in] layout + * A pointer of the programming layout + * + * @param field_id + * [in] Identifier of the HW field + * + * @param[in] bitpos_adj + * Bit position adjustment value + * + * @param[in] bitlen_adj + * Bit length adjustment value + * + * @param[in] val + * HW field value to be programmed + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_put_field_rel(uint64_t *obj_data, + const struct hcapi_cfa_layout *layout, + uint16_t field_id, int16_t bitpos_adj, + int16_t bitlen_adj, uint64_t val); + +/*@}*/ + +/** + * \defgroup CFA_HCAPI_GET_API + * HCAPI used for writing to the hardware + * @{ + */ + +/** + * This API provides the functionality to get the word length of + * a layout object. + * + * @param[in] layout + * A pointer of the HW layout + * + * @return + * Word length of the layout object + */ +uint16_t hcapi_cfa_get_wordlen(const struct hcapi_cfa_layout *layout); + +/** + * The API provides the functionality to get bit offset and bit + * length information of a field from a programming layout. + * + * @param[in] layout + * A pointer of the action layout + * + * @param[out] slice + * A pointer to the action offset info data structure + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_get_slice(const struct hcapi_cfa_layout *layout, + uint16_t field_id, struct hcapi_cfa_field *slice); + +/** + * This API provides the functionality to read the value of a + * CFA HW field from CFA HW data object based on the hardware + * programming layout. + * + * @param[in] obj_data + * A pointer to a CFA HW key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_id + * ID of the HW field to be programmed + * + * @param[out] val + * Value of the HW field + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_get_field(uint64_t *obj_data, + const struct hcapi_cfa_layout *layout, + uint16_t field_id, uint64_t *val); + +/** + * This API provides the functionality to read 128-bit value of + * a CFA HW field from CFA HW data object based on the hardware + * programming layout. + * + * @param[in] obj_data + * A pointer to a CFA HW key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_id + * ID of the HW field to be programmed + * + * @param[out] val_msb + * Msb value of the HW field + * + * @param[out] val_lsb + * Lsb value of the HW field + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_get128_field(uint64_t *obj_data, + const struct hcapi_cfa_layout *layout, + uint16_t field_id, uint64_t *val_msb, + uint64_t *val_lsb); + +/** + * This API provides the functionality to read a number of + * HW fields from a CFA HW data object based on the hardware + * programming layout. + * + * @param[in] obj_data + * A pointer to a CFA profiler key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in, out] field_tbl + * A pointer to an array that consists of the object field + * ID/value pairs + * + * @param[in] field_tbl_sz + * Number of entries in the table + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_get_fields(uint64_t *obj_data, + const struct hcapi_cfa_layout *layout, + struct hcapi_cfa_data_obj *field_tbl, + uint16_t field_tbl_sz); + +/** + * This API provides the functionality to read a number of + * HW fields from a CFA HW data object based on the hardware + * programming layout.This API will swap the n byte blocks before + * retrieving the field array. + * + * @param[in] obj_data + * A pointer to a CFA profiler key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in, out] field_tbl + * A pointer to an array that consists of the object field + * ID/value pairs + * + * @param[in] field_tbl_sz + * Number of entries in the table + * + * @param[in] data_size + * size of the data in bytes + * + * @param[in] n + * block size in bytes + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_get_fields_swap(uint64_t *obj_data, + const struct hcapi_cfa_layout *layout, + struct hcapi_cfa_data_obj *field_tbl, + uint16_t field_tbl_sz, uint16_t data_size, + uint16_t n); + +/** + * Get a value to a specific location relative to a HW field + * + * This API provides the functionality to read HW field from + * a section of a HW data object identified by the bit position + * and bit length from a given programming layout in order to avoid + * reading the entire HW data object. + * + * @param[in] obj_data + * A pointer of the data object to read from + * + * @param[in] layout + * A pointer of the programming layout + * + * @param[in] field_id + * Identifier of the HW field + * + * @param[in] bitpos_adj + * Bit position adjustment value + * + * @param[in] bitlen_adj + * Bit length adjustment value + * + * @param[out] val + * Value of the HW field + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_get_field_rel(uint64_t *obj_data, + const struct hcapi_cfa_layout *layout, + uint16_t field_id, int16_t bitpos_adj, + int16_t bitlen_adj, uint64_t *val); + +/** + * Get the length of the layout in words + * + * @param[in] layout + * A pointer to the layout to determine the number of words + * required + * + * @return + * number of words needed for the given layout + */ +uint16_t cfa_hw_get_wordlen(const struct hcapi_cfa_layout *layout); + +/** + * This function is used to initialize a layout_contents structure + * + * The struct hcapi_cfa_key_layout is complex as there are three + * layers of abstraction. Each of those layer need to be properly + * initialized. + * + * @param[in] contents + * A pointer of the layout contents to initialize + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_init_key_contents(struct hcapi_cfa_key_layout_contents *contents); + +/** + * This function is used to validate a key template + * + * The struct hcapi_cfa_key_template is complex as there are three + * layers of abstraction. Each of those layer need to be properly + * validated. + * + * @param[in] key_template + * A pointer of the key template contents to validate + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_is_valid_key_template(struct hcapi_cfa_key_template *key_template); + +/** + * This function is used to validate a key layout + * + * The struct hcapi_cfa_key_layout is complex as there are three + * layers of abstraction. Each of those layer need to be properly + * validated. + * + * @param[in] key_layout + * A pointer of the key layout contents to validate + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int hcapi_cfa_is_valid_key_layout(struct hcapi_cfa_key_layout *key_layout); + /** * This function is used to hash E/EM keys * diff --git a/drivers/net/bnxt/hcapi/cfa_v3/CMakeLists.txt b/drivers/net/bnxt/hcapi/cfa_v3/CMakeLists.txt new file mode 100644 index 0000000000..a6b6103c99 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/CMakeLists.txt @@ -0,0 +1,92 @@ +# +# Copyright(c) 2019-2021 Broadcom Limited, all rights reserved +# Contains proprietary and confidential information. +# +# This source file is the property of Broadcom Limited, and +# may not be copied or distributed in any isomorphic form without +# the prior written consent of Broadcom Limited. +# + +# Needed for compilation with chip-specific regdef.h +add_definitions(-DFIRMWARE_VIEW=1) + +# Platform specific defines +if (cfa_p70) + add_definitions(-DSUPPORT_CFA_HW_P70=1) + set(PXX_FOLDER p70) + set (tsm_needed 1) + set (mm_needed 1) +endif () + +if (cfa_p80) + add_definitions(-DSUPPORT_CFA_HW_P80=1) + set(PXX_FOLDER p80) + set (tcm_needed 1) +endif () + +# Reset Doc dir variables +set(CFA_API_DOC_DIRS "" CACHE INTERNAL "") +set(CFA_DESIGN_DOC_DIRS "" CACHE INTERNAL "") +set(CFA_UT_DOC_DIRS "" CACHE INTERNAL "") + +# Include sub directories + +if (idm_needed) + add_subdirectory(idm) + set(idm_libs cfa-idm-lib cfa-idm-lib-ut) +endif () + +if (tbm_needed) + add_subdirectory(tbm) + set(tbm_libs cfa-tbm-lib cfa-tbm-lib-ut) +endif () + +if (gim_needed) + add_subdirectory(gim) + set(gim_libs cfa-gim-lib cfa-gim-lib-ut) +endif () + +if (mm_needed) + add_subdirectory(mm) + set(mm_libs cfa-mm-lib cfa-mm-lib-ut) +endif () + +if (tsm_needed) + add_subdirectory(tpm) + add_subdirectory(tim) + set(cfa-tim-lib cfa-tim-lib-ut cfa-tpm-lib cfa-tpm-lib-ut) +endif () + +if (tcm_needed) + add_subdirectory(tcm) + set(tcm_libs cfa-tcm-lib cfa-tcm-lib-ut) +endif () + +if (rdm_needed) + add_subdirectory(rdm) + set(rdm_libs cfa-rdm-lib cfa-rdm-lib-ut) +endif () + +# Update Doxygen dirs for api documentation +#set(CFA_API_DOC_DIRS ${CFA_API_DOC_DIRS} +# ${CMAKE_CURRENT_SOURCE_DIR}/include +# CACHE INTERNAL "") + +# Update Doxygen dirs for design documentation +#set(CFA_DESIGN_DOC_DIRS ${CFA_DESIGN_DOC_DIRS} +# ${CMAKE_CURRENT_SOURCE_DIR}/include +# CACHE INTERNAL "") + +# Include docs +#if (DOXYGEN_FOUND) +# add_subdirectory(docs) +# add_custom_target(cfa-v3-docs +# DEPENDS hcapi-cfa-api-docs +# hcapi-cfa-design-docs +# hcapi-cfa-ut-docs +# ) +#endif (DOXYGEN_FOUND) + +add_custom_target(cfa-v3-libs + ALL + DEPENDS ${tpm_libs} ${tim_libs} ${mm_libs}) diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/host/cfa_bld_mpc.c b/drivers/net/bnxt/hcapi/cfa_v3/bld/host/cfa_bld_mpc.c new file mode 100644 index 0000000000..e84341b52f --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/host/cfa_bld_mpc.c @@ -0,0 +1,42 @@ +/**************************************************************************** + * Copyright(c) 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_mpc.c + * + * @brief CFA Builder MPC binding api + */ + +#include +#include "cfa_bld.h" +#include "host/cfa_bld_mpcops.h" + +#if SUPPORT_CFA_HW_P70 +#include "cfa_bld_p70_mpcops.h" +#endif + +int cfa_bld_mpc_bind(enum cfa_ver hw_ver, struct cfa_bld_mpcinfo *mpcinfo) +{ + if (!mpcinfo) + return -EINVAL; + + switch (hw_ver) { + case CFA_P40: + case CFA_P45: + case CFA_P58: + case CFA_P59: + return -ENOTSUP; + case CFA_P70: +#if SUPPORT_CFA_HW_P70 + return cfa_bld_p70_mpc_bind(hw_ver, mpcinfo); +#else + return -ENOTSUP; +#endif + default: + return -EINVAL; + } +} diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/cfa_bld_defs.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/cfa_bld_defs.h new file mode 100644 index 0000000000..8acd770589 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/cfa_bld_defs.h @@ -0,0 +1,578 @@ +/**************************************************************************** + * Copyright(c) 2021 - 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_defs.h + * + * @brief CFA Builder library structure definitions and API + */ + +#ifndef _CFA_BLD_DEFS_H_ +#define _CFA_BLD_DEFS_H_ + +#include +#include + +#include "cfa_resources.h" +#include "cfa_types.h" + +/** + * @addtogroup CFA_BLD CFA Builder Library + * \ingroup CFA_V3 + * The CFA builder library is a set of APIs provided the following services: + * + * 1. Provide users generic put service to convert software programming data + * into a hardware data bit stream according to a HW layout representation, + * or generic get service to extract value of a field or values of a number + * of fields from the raw hardware data bit stream according to a HW layout. + * + * - A software programming data is represented in {field_idx, val} + * structure. + * - A HW layout is represented with array of CFA field structures with + * {bitpos, bitlen} and identified by a layout id corresponding to a CFA + * HW table. + * - A HW data bit stream are bits that is formatted according to a HW + * layout representation. + * + * 2. Provide EM/WC key and action related service APIs to compile layout, + * init, and manipulate key and action data objects. + * + * 3. Provide CFA mid-path message building APIs. (TBD) + * + * The CFA builder library is designed to run in the primate firmware and also + * as part of the following host base diagnostic software. + * - Lcdiag + * - Truflow CLI + * - coredump decorder + * + * @{ + */ + +/** @name CFA Builder Common Definition + * CFA builder common structures and enumerations + */ + +/**@{*/ +/** + * CFA HW KEY CONTROL OPCODE definition + */ +enum cfa_key_ctrlops { + CFA_KEY_CTRLOPS_INSERT, /**< insert WC control bits */ + CFA_KEY_CTRLOPS_STRIP, /**< strip WC control bits */ + CFA_KEY_CTRLOPS_SWAP, /**< swap EM cache lines */ + CFA_KEY_CTRLOPS_MAX +}; + +/** + * CFA HW field structure definition + */ +struct cfa_field { + /** [in] Starting bit position pf the HW field within a HW table + * entry. + */ + uint16_t bitpos; + /** [in] Number of bits for the HW field. */ + uint16_t bitlen; +}; + +/** + * CFA HW table entry layout structure definition + */ +struct cfa_layout { + /** [out] Bit order of layout + * if swap_order_bitpos is non-zero, the bit order of the layout + * will be swapped after this bit. swap_order_bitpos must be a + * multiple of 64. This is currently only used for inlined action + * records where the AR is lsb and the following inlined actions + * must be msb. + */ + bool is_msb_order; + /** [out] Reverse is_msb_order after this bit if non-zero */ + uint16_t swap_order_bitpos; + /** [out] Size in bits of entry */ + uint32_t total_sz_in_bits; + /** [in/out] data pointer of the HW layout fields array */ + struct cfa_field *field_array; + /** [out] number of HW field entries in the HW layout field array */ + uint32_t array_sz; + /** [out] layout_id - layout id associated with the layout */ + uint16_t layout_id; +}; + +/** + * CFA HW data object definition + */ +struct cfa_data_obj { + /** [in] HW field identifier. Used as an index to a HW table layout */ + uint16_t field_id; + /** [in] Value of the HW field */ + uint64_t val; +}; + +/** + * CFA HW key buffer definition + */ +struct cfa_key_obj { + /** [in] pointer to the key data buffer */ + uint32_t *data; + /** [in] buffer len in bytes */ + uint32_t data_len_bytes; + /** [out] Data length in bits + * When cfa_key_obj is passed as an output parameter, the updated + * key length (if the key length changes) is returned in this field by the + * key processing api (e.g cfa_bld_key_transform) + * When cfa_key_obj is passed as an input parameter, this field is unused + * and need not be initialized by the caller. + */ + uint32_t data_len_bits; + /** [in] Pointer to the key layout */ + struct cfa_key_layout *layout; +}; + +/** + * CFA HW layout table definition + */ +struct cfa_layout_tbl { + /** [out] data pointer to an array of fix formatted layouts supported. + * The index to the array is either the CFA resource subtype or + * remap table ID + */ + const struct cfa_layout *layouts; + /** [out] number of fix formatted layouts in the layout array */ + uint16_t num_layouts; +}; + +/** + * key layout consist of field array, key bitlen, key ID, and other meta data + * pertain to a key + */ +struct cfa_key_layout { + /** [in/out] key layout data */ + struct cfa_layout *layout; + /** [out] actual key size in number of bits */ + uint16_t bitlen; + /** [out] key identifier and this field is only valid for device + * that supports fix key formats + */ + uint16_t id; + /** [out] Identified the key layout is WC TCAM key */ + bool is_wc_tcam_key; + /** [out] Identify if the key template will be use for IPv6 Keys. + * + * Note: This is important for Thor2 as the field length for the FlowId + * is dependent on the L3 flow type. For Thor2 for IPv4 Keys, the Flow + * Id field is 16 bits, for all other types (IPv6, ARP, PTP, EAP, RoCE, + * FCoE, UPAR), the Flow Id field length is 20 bits. + */ + bool is_ipv6_key; + /** [out] total number of slices, valid for WC TCAM key only. It can be + * used by the user to pass in the num_slices to write to the hardware. + */ + uint16_t num_slices; +}; + +/** + * CFA HW key table definition + * + * Applicable to EEM and on-chip EM table only. + */ +struct cfa_key_tbl { + /** [in] For EEM, this is the KEY0 base mem pointer. For off-chip EM, + * this is the base mem pointer of the key table. + */ + uint8_t *base0; + /** [in] total size of the key table in bytes. For EEM, this size is + * same for both KEY0 and KEY1 table. + */ + uint32_t size; + /** [in] number of key buckets, applicable for newer chips */ + uint32_t num_buckets; + /** [in] For EEM, this is KEY1 base mem pointer. Fo on-chip EM, + * this is the key record memory base pointer within the key table, + * applicable for newer chip + */ + uint8_t *base1; + /** [in] Optional - If the table is managed by a Backing Store + * database, then this object can be use to configure the EM Key. + */ + struct cfa_bs_db *bs_db; + /** [in] Page size for EEM tables */ + uint32_t page_size; +}; + +/** + * CFA HW key data definition + */ +struct cfa_key_data { + /** [in] For on-chip key table, it is the offset in unit of smallest + * key. For off-chip key table, it is the byte offset relative + * to the key record memory base and adjusted for page and entry size. + */ + uint32_t offset; + /** [in] HW key data buffer pointer */ + uint8_t *data; + /** [in] size of the key in bytes */ + uint16_t size; + /** [in] optional table scope ID */ + uint8_t tbl_scope; + /** [in] the fid owner of the key */ + uint64_t metadata; + /** [in] stored with the bucket which can be used to by + * the caller to retreved later via the GET HW OP. + */ +}; + +/** + * CFA HW key location definition + */ +struct cfa_key_loc { + /** [out] on-chip EM bucket offset or off-chip EM bucket mem pointer */ + uint64_t bucket_mem_ptr; + /** [out] off-chip EM key offset mem pointer */ + uint64_t mem_ptr; + /** [out] index within the array of the EM buckets */ + uint32_t bucket_mem_idx; + /** [out] index within the EM bucket */ + uint8_t bucket_idx; + /** [out] index within the EM records */ + uint32_t mem_idx; +}; + +/** + * Action record info + */ +struct cfa_action_addr { + /** [in] action SRAM block ID for on-chip action records or table + * scope of the action backing store + */ + uint16_t blk_id; + /** [in] ar_id or cache line aligned address offset for the action + * record + */ + uint32_t offset; +}; + +/** + * Action object definition + */ +struct cfa_action_obj { + /** [in] pointer to the action data buffer */ + uint64_t *data; + /** [in] buffer len in bytes */ + uint32_t len; + /** [in] pointer to the action layout */ + struct cfa_action_layout *layout; +}; + +/** + * action layout consist of field array, action wordlen and action format ID + */ +struct cfa_action_layout { + /** [in] action identifier */ + uint16_t id; + /** [out] action layout data */ + struct cfa_layout *layout; + /** [out] actual action record size in number of bits */ + uint16_t bitlen; +}; + +/**@}*/ + +/** @name CFA Builder PUT_FIELD APIs + * CFA Manager apis used for generating hw layout specific data objects that + * can be programmed to the hardware + */ + +/**@{*/ +/** + * @brief This API provides the functionality to program a specified value to a + * HW field based on the provided programming layout. + * + * @param[in,out] data_buf + * A data pointer to a CFA HW key/mask data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_id + * ID of the HW field to be programmed + * + * @param[in] val + * Value of the HW field to be programmed + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_put_field(uint64_t *data_buf, const struct cfa_layout *layout, + uint16_t field_id, uint64_t val); + +/** + * @brief This API provides the functionality to program an array of field + * values with corresponding field IDs to a number of profiler sub-block fields + * based on the fixed profiler sub-block hardware programming layout. + * + * @param[in, out] obj_data + * A pointer to a CFA profiler key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_tbl + * A pointer to an array that consists of the object field + * ID/value pairs + * + * @param[in] field_tbl_sz + * Number of entries in the table + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_put_fields(uint64_t *obj_data, const struct cfa_layout *layout, + struct cfa_data_obj *field_tbl, uint16_t field_tbl_sz); + +/** + * @brief This API provides the functionality to program an array of field + * values with corresponding field IDs to a number of profiler sub-block fields + * based on the fixed profiler sub-block hardware programming layout. This + * API will swap the n byte blocks before programming the field array. + * + * @param[in, out] obj_data + * A pointer to a CFA profiler key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_tbl + * A pointer to an array that consists of the object field + * ID/value pairs + * + * @param[in] field_tbl_sz + * Number of entries in the table + * + * @param[in] data_size + * size of the data in bytes + * + * @param[in] n + * block size in bytes + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_put_fields_swap(uint64_t *obj_data, const struct cfa_layout *layout, + struct cfa_data_obj *field_tbl, uint16_t field_tbl_sz, + uint16_t data_size, uint16_t n); + +/** + * @brief This API provides the functionality to write a value to a + * field within the bit position and bit length of a HW data + * object based on a provided programming layout. + * + * @param[in, out] obj_data + * A pointer of the action object to be initialized + * + * @param[in] layout + * A pointer of the programming layout + * + * @param field_id + * [in] Identifier of the HW field + * + * @param[in] bitpos_adj + * Bit position adjustment value + * + * @param[in] bitlen_adj + * Bit length adjustment value + * + * @param[in] val + * HW field value to be programmed + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_put_field_rel(uint64_t *obj_data, const struct cfa_layout *layout, + uint16_t field_id, int16_t bitpos_adj, int16_t bitlen_adj, + uint64_t val); + +/**@}*/ + +/** @name CFA Builder GET_FIELD APIs + * CFA Manager apis used for extract hw layout specific fields from CFA HW + * data objects + */ + +/**@{*/ +/** + * @brief The API provides the functionality to get bit offset and bit + * length information of a field from a programming layout. + * + * @param[in] layout + * A pointer of the action layout + * + * @param[in] field_id + * The field for which to retrieve the slice + * + * @param[out] slice + * A pointer to the action offset info data structure + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_get_slice(const struct cfa_layout *layout, uint16_t field_id, + struct cfa_field *slice); + +/** + * @brief This API provides the functionality to read the value of a + * CFA HW field from CFA HW data object based on the hardware + * programming layout. + * + * @param[in] obj_data + * A pointer to a CFA HW key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_id + * ID of the HW field to be programmed + * + * @param[out] val + * Value of the HW field + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_get_field(uint64_t *obj_data, const struct cfa_layout *layout, + uint16_t field_id, uint64_t *val); + +/** + * @brief This API provides the functionality to read 128-bit value of + * a CFA HW field from CFA HW data object based on the hardware + * programming layout. + * + * @param[in] obj_data + * A pointer to a CFA HW key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in] field_id + * ID of the HW field to be programmed + * + * @param[out] val_msb + * Msb value of the HW field + * + * @param[out] val_lsb + * Lsb value of the HW field + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_get128_field(uint64_t *obj_data, const struct cfa_layout *layout, + uint16_t field_id, uint64_t *val_msb, uint64_t *val_lsb); + +/** + * @brief This API provides the functionality to read a number of + * HW fields from a CFA HW data object based on the hardware + * programming layout. + * + * @param[in] obj_data + * A pointer to a CFA profiler key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in, out] field_tbl + * A pointer to an array that consists of the object field + * ID/value pairs + * + * @param[in] field_tbl_sz + * Number of entries in the table + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_get_fields(uint64_t *obj_data, const struct cfa_layout *layout, + struct cfa_data_obj *field_tbl, uint16_t field_tbl_sz); + +/** + * @brief This API provides the functionality to read a number of + * HW fields from a CFA HW data object based on the hardware + * programming layout.This API will swap the n byte blocks before + * retrieving the field array. + * + * @param[in] obj_data + * A pointer to a CFA profiler key/mask object data + * + * @param[in] layout + * A pointer to CFA HW programming layout + * + * @param[in, out] field_tbl + * A pointer to an array that consists of the object field + * ID/value pairs + * + * @param[in] field_tbl_sz + * Number of entries in the table + * + * @param[in] data_size + * size of the data in bytes + * + * @param[in] n + * block size in bytes + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_get_fields_swap(uint64_t *obj_data, const struct cfa_layout *layout, + struct cfa_data_obj *field_tbl, uint16_t field_tbl_sz, + uint16_t data_size, uint16_t n); + +/** + * @brief Get a value to a specific location relative to a HW field + * This API provides the functionality to read HW field from + * a section of a HW data object identified by the bit position + * and bit length from a given programming layout in order to avoid + * reading the entire HW data object. + * + * @param[in] obj_data + * A pointer of the data object to read from + * + * @param[in] layout + * A pointer of the programming layout + * + * @param[in] field_id + * Identifier of the HW field + * + * @param[in] bitpos_adj + * Bit position adjustment value + * + * @param[in] bitlen_adj + * Bit length adjustment value + * + * @param[out] val + * Value of the HW field + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_get_field_rel(uint64_t *obj_data, const struct cfa_layout *layout, + uint16_t field_id, int16_t bitpos_adj, int16_t bitlen_adj, + uint64_t *val); + +/** + * @brief Get the length of the layout in words + * + * @param[in] layout + * A pointer to the layout to determine the number of words + * required + * + * @return + * number of words needed for the given layout + */ +uint16_t cfa_get_wordlen(const struct cfa_layout *layout); + +/**@}*/ + +/**@}*/ +#endif /* _CFA_BLD_DEFS_H_*/ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld.h new file mode 100644 index 0000000000..ce16d10e5b --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld.h @@ -0,0 +1,524 @@ +/**************************************************************************** + * Copyright(c) 2021 - 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld.h + * + * @brief CFA HW independent Builder library public api header + */ + +#ifndef _CFA_BLD_H_ +#define _CFA_BLD_H_ + +#include "sys_util.h" +#include "cfa_bld_defs.h" +#include "cfa_bld_field_ids.h" + +/** + * @addtogroup CFA_BLD CFA Builder Library + * \ingroup CFA_V3 + * @{ + */ + +/** + * Maximum key array size + */ +#define CFA_V3_KEY_MAX_FIELD_CNT \ + MAX((uint16_t)CFA_BLD_EM_KEY_LAYOUT_MAX_FLD, \ + (uint16_t)CFA_BLD_WC_TCAM_FKB_MAX_FLD) +#define CFA_V3_ACT_MAX_TEMPLATE_SZ sizeof(struct cfa_bld_action_template) + +/** @name CFA Builder Templates + * CFA builder action and key templates definition and enumerations + */ + +/**@{*/ +enum action_type { + /** Select this type to build an Full Action Record Object + */ + CFA_BLD_ACT_OBJ_TYPE_FULL_ACT, + /** Select this type to build an Compact Action Record Object + */ + CFA_BLD_ACT_OBJ_TYPE_COMPACT_ACT, + /** Select this type to build an MCG Action Record Object + */ + CFA_BLD_ACT_OBJ_TYPE_MCG_ACT, + /** Select this type to build Standalone Modify Action Record Object */ + CFA_BLD_ACT_OBJ_TYPE_MODIFY, + /** Select this type to build Standalone Stat Action Record Object */ + CFA_BLD_ACT_OBJ_TYPE_STAT, + /** Select this type to build Standalone Source Action Record Object */ + CFA_BLD_ACT_OBJ_TYPE_SRC_PROP, + /** Select this type to build Standalone Encap Action Record Object */ + CFA_BLD_ACT_OBJ_TYPE_ENCAP, +}; + +enum stat_op { + /** Set to statistic to ingress to CFA + */ + CFA_BLD_STAT_OP_INGRESS = 0, + /** Set to statistic to egress from CFA + */ + CFA_BLD_STAT_OP_EGRESS = 1, +}; + +enum stat_type { + /** Set to statistic to Foward packet count(64b)/Foward byte + * count(64b) + */ + CFA_BLD_STAT_COUNTER_SIZE_16B = 0, + /** Set to statistic to Forward packet count(64b)/Forward byte + * count(64b)/ TCP Flags(16b)/Timestamp(32b) + */ + CFA_BLD_STAT_COUNTER_SIZE_24B = 1, + /** Set to statistic to Forward packet count(64b)/Forward byte + * count(64b)/Meter(drop or red) packet count(64b)/Meter(drop + * or red) byte count(64b) + */ + CFA_BLD_STAT_COUNTER_SIZE_32B = 2, + /** Set to statistic to Forward packet count(64b)/Forward byte + * count(64b)/Meter(drop or red) packet count(38b)/Meter(drop + * or red) byte count(42b)/TCP Flags(16b)/Timestamp(32b) + */ + CFA_BLD_STAT_COUNTER_SIZE_32B_ALL = 3, +}; + +enum encap_vtag { + CFA_BLD_ACT_ENCAP_VTAGS_PUSH_0 = 0, + CFA_BLD_ACT_ENCAP_VTAGS_PUSH_1, + CFA_BLD_ACT_ENCAP_VTAGS_PUSH_2 +}; + +enum encap_l3 { + /** Set to disable any L3 encapsulation + * processing, default + */ + CFA_BLD_ACT_ENCAP_L3_NONE = 0, + /** Set to enable L3 IPv4 encapsulation + */ + CFA_BLD_ACT_ENCAP_L3_IPV4 = 4, + /** Set to enable L3 IPv6 encapsulation + */ + CFA_BLD_ACT_ENCAP_L3_IPV6 = 5, + /** Set to enable L3 MPLS 8847 encapsulation + */ + CFA_BLD_ACT_ENCAP_L3_MPLS_8847 = 6, + /** Set to enable L3 MPLS 8848 encapsulation + */ + CFA_BLD_ACT_ENCAP_L3_MPLS_8848 = 7 +}; + +enum encap_tunnel { + /** Set to disable Tunnel header encapsulation + * processing, default + */ + CFA_BLD_ACT_ENCAP_TNL_NONE = 0, + /** Set to enable Tunnel Generic Full header + * encapsulation + */ + CFA_BLD_ACT_ENCAP_TNL_GENERIC_FULL, + /** Set to enable VXLAN header encapsulation + */ + CFA_BLD_ACT_ENCAP_TNL_VXLAN, + /** Set to enable NGE (VXLAN2) header encapsulation + */ + CFA_BLD_ACT_ENCAP_TNL_NGE, + /** Set to enable NVGRE header encapsulation + */ + CFA_BLD_ACT_ENCAP_TNL_NVGRE, + /** Set to enable GRE header encapsulation + */ + CFA_BLD_ACT_ENCAP_TNL_GRE, + /** Set to enable Generic header after Tunnel + * L4 encapsulation + */ + CFA_BLD_ACT_ENCAP_TNL_GENERIC_AFTER_TL4, + /** Set to enable Generic header after Tunnel + * encapsulation + */ + CFA_BLD_ACT_ENCAP_TNL_GENERIC_AFTER_TNL +}; + +enum source_rec_type { + /** Set to Source MAC Address + */ + CFA_BLD_SOURCE_MAC = 0, + /** Set to Source MAC and IPv4 Addresses + */ + CFA_BLD_SOURCE_MAC_IPV4 = 1, + /** Set to Source MAC and IPv6 Addresses + */ + CFA_BLD_SOURCE_MAC_IPV6 = 2, +}; + +/** + * From CFA phase 7.0 onwards, setting the modify vector bit + * 'ACT_MODIFY_TUNNEL_MODIFY' requires corresponding data fields to be + * set. This enum defines the parameters that determine the + * layout of this associated data fields. This structure + * is not used for versions older than CFA Phase 7.0 and setting + * the 'ACT_MODIFY_TUNNEL_MODIFY' bit will just delete the internal tunnel + */ +enum tunnel_modify_mode { + /* No change to tunnel protocol */ + CFA_BLD_ACT_MOD_TNL_NO_PROTO_CHANGE = 0, + /* 8-bit tunnel protocol change */ + CFA_BLD_ACT_MOD_TNL_8B_PROTO_CHANGE = 1, + /* 16-bit tunnel protocol change */ + CFA_BLD_ACT_MOD_TNL_16B_PROTO_CHANGE = 2, + CFA_BLD_ACT_MOD_TNL_MAX +}; + +/** + * Action object template structure + * + * Template structure presents data fields that are necessary to know + * at the beginning of Action Builder (AB) processing. Like before the + * AB compilation. One such example could be a template that is + * flexible in size (Encap Record) and the presence of these fields + * allows for determining the template size as well as where the + * fields are located in the record. + * + * The template may also present fields that are not made visible to + * the caller by way of the action fields. + * + * Template fields also allow for additional checking on user visible + * fields. One such example could be the encap pointer behavior on a + * CFA_BLD_ACT_OBJ_TYPE_ACT or CFA_BLD_ACT_OBJ_TYPE_ACT_SRAM. + */ +struct cfa_bld_action_template { + /** Action Object type + * + * Controls the type of the Action Template + */ + enum action_type obj_type; + + /** Action Control + * + * Controls the internals of the Action Template + * + * act is valid when: + * ((obj_type == CFA_BLD_ACT_OBJ_TYPE_FULL_ACT) + * || + * (obj_type == CFA_BLD_ACT_OBJ_TYPE_COMPACT_ACT)) + * + * Specifies whether each action is to be in-line or not. + */ + struct { + /** Set to true to enable statistics + */ + uint8_t stat_enable; + /** Set to true to enable statistics to be inlined + */ + uint8_t stat_inline; + /** Set to true to enable statistics 1 + */ + uint8_t stat1_enable; + /** Set to true to enable statistics 1 to be inlined + */ + uint8_t stat1_inline; + /** Set to true to enable encapsulation + */ + uint8_t encap_enable; + /** Set to true to enable encapsulation to be inlined + */ + uint8_t encap_inline; + /** Set to true to align the encap record to cache + * line + */ + uint8_t encap_align; + /** Set to true to source + */ + uint8_t source_enable; + /** Set to true to enable source to be inlined + */ + uint8_t source_inline; + /** Set to true to enable modfication + */ + uint8_t mod_enable; + /** Set to true to enable modify to be inlined + */ + uint8_t mod_inline; + /** Set to true to enable subsequent MCGs + */ + uint8_t mcg_subseq_enable; + } act; + + /** Statistic Control + * Controls the type of statistic the template is describing + * + * stat is valid when: + * ((obj_type == CFA_BLD_ACT_OBJ_TYPE_FULL_ACT) || + * (obj_type == CFA_BLD_ACT_OBJ_TYPE_COMPACT_ACT)) && + * act.stat_enable || act.stat_inline) + */ + struct { + enum stat_op op; + enum stat_type type; + } stat; + + /** Encap Control + * Controls the type of encapsulation the template is + * describing + * + * encap is valid when: + * ((obj_type == CFA_BLD_ACT_OBJ_TYPE_FULL_ACT) || + * (obj_type == CFA_BLD_ACT_OBJ_TYPE_COMPACT_ACT) && + * act.encap_enable || act.encap_inline) + */ + struct { + /** Set to true to enable L2 capability in the + * template + */ + uint8_t l2_enable; + /** vtag controls the Encap Vector - VTAG Encoding, 4 bits + * + *
    + *
  • CFA_BLD_ACT_ENCAP_VTAGS_PUSH_0, default, no VLAN + * Tags applied + *
  • CFA_BLD_ACT_ENCAP_VTAGS_PUSH_1, adds capability to + * set 1 VLAN Tag. Action Template compile adds + * the following field to the action object + * TF_ER_VLAN1 + *
  • CFA_BLD_ACT_ENCAP_VTAGS_PUSH_2, adds capability to + * set 2 VLAN Tags. Action Template compile adds + * the following fields to the action object + * TF_ER_VLAN1 and TF_ER_VLAN2 + *
+ */ + enum encap_vtag vtag; + + /* + * The remaining fields are NOT supported when + * direction is RX and ((obj_type == + * CFA_BLD_ACT_OBJ_TYPE_ACT) && act.encap_enable). + * cfa_bld_devops.act_compile_layout will perform the + * checking and skip remaining fields. + */ + /** L3 Encap controls the Encap Vector - L3 Encoding, + * 3 bits. Defines the type of L3 Encapsulation the + * template is describing. + *
    + *
  • CFA_BLD_ACT_ENCAP_L3_NONE, default, no L3 + * Encapsulation processing. + *
  • CFA_BLD_ACT_ENCAP_L3_IPV4, enables L3 IPv4 + * Encapsulation. + *
  • CFA_BLD_ACT_ENCAP_L3_IPV6, enables L3 IPv6 + * Encapsulation. + *
  • CFA_BLD_ACT_ENCAP_L3_MPLS_8847, enables L3 MPLS + * 8847 Encapsulation. + *
  • CFA_BLD_ACT_ENCAP_L3_MPLS_8848, enables L3 MPLS + * 8848 Encapsulation. + *
+ */ + enum encap_l3 l3; + +#define CFA_BLD_ACT_ENCAP_MAX_MPLS_LABELS 8 + /** 1-8 labels, valid when + * (l3 == CFA_BLD_ACT_ENCAP_L3_MPLS_8847) || + * (l3 == CFA_BLD_ACT_ENCAP_L3_MPLS_8848) + * + * MAX number of MPLS Labels 8. + */ + uint8_t l3_num_mpls_labels; + + /** Set to true to enable L4 capability in the + * template. + * + * true adds TF_EN_UDP_SRC_PORT and + * TF_EN_UDP_DST_PORT to the template. + */ + uint8_t l4_enable; + + /** Tunnel Encap controls the Encap Vector - Tunnel + * Encap, 3 bits. Defines the type of Tunnel + * encapsulation the template is describing + *
    + *
  • CFA_BLD_ACT_ENCAP_TNL_NONE, default, no Tunnel + * Encapsulation processing. + *
  • CFA_BLD_ACT_ENCAP_TNL_GENERIC_FULL + *
  • CFA_BLD_ACT_ENCAP_TNL_VXLAN. NOTE: Expects + * l4_enable set to true; + *
  • CFA_BLD_ACT_ENCAP_TNL_NGE. NOTE: Expects l4_enable + * set to true; + *
  • CFA_BLD_ACT_ENCAP_TNL_NVGRE. NOTE: only valid if + * l4_enable set to false. + *
  • CFA_BLD_ACT_ENCAP_TNL_GRE.NOTE: only valid if + * l4_enable set to false. + *
  • CFA_BLD_ACT_ENCAP_TNL_GENERIC_AFTER_TL4 + *
  • CFA_BLD_ACT_ENCAP_TNL_GENERIC_AFTER_TNL + *
+ */ + enum encap_tunnel tnl; + +#define CFA_BLD_ACT_ENCAP_MAX_TUNNEL_GENERIC_SIZE 128 + /** Number of bytes of generic tunnel header, + * valid when + * (tnl == CFA_BLD_ACT_ENCAP_TNL_GENERIC_FULL) || + * (tnl == CFA_BLD_ACT_ENCAP_TNL_GENERIC_AFTER_TL4) || + * (tnl == CFA_BLD_ACT_ENCAP_TNL_GENERIC_AFTER_TNL) + */ + uint8_t tnl_generic_size; + +#define CFA_BLD_ACT_ENCAP_MAX_OPLEN 15 + /** Number of 32b words of nge options, + * valid when + * (tnl == CFA_BLD_ACT_ENCAP_TNL_NGE) + */ + uint8_t tnl_nge_op_len; + + /** Set to true to enable SPDNIC tunnel + * template, + * valid when + * (tnl == CFA_BLD_ACT_ENCAP_TNL_GENERIC_FULL) + */ + uint8_t spdnic_enable; + + /** SPDNIC flags field, + * valid when + * (tnl == CFA_BLD_ACT_ENCAP_TNL_GENERIC_FULL) + */ + uint8_t tnl_spdnic_flags; + + /** Set to true to enable MAC/VLAN/IP/TNL overrides in the + * template + */ + bool encap_override; + /* Currently not planned */ + /* Custom Header */ + /* uint8_t custom_enable; */ + } encap; + + /** Modify Control + * + * Controls the type of the Modify Action the template is + * describing + * + * modify is valid when: + * ((obj_type == CFA_BLD_ACT_OBJ_TYPE_FULL_ACT) || + * (obj_type == CFA_BLD_ACT_OBJ_TYPE_COMPACT_ACT) && + * act.modify_enable || act.modify_inline) + */ +/** Set to enable Modify of Metadata + */ +#define CFA_BLD_ACT_MODIFY_META 0x1 +/** Set to enable Delete of Outer VLAN + */ +#define CFA_BLD_ACT_MODIFY_DEL_OVLAN 0x2 +/** Set to enable Delete of Inner VLAN + */ +#define CFA_BLD_ACT_MODIFY_DEL_IVLAN 0x4 +/** Set to enable Replace or Add of Outer VLAN + */ +#define CFA_BLD_ACT_MODIFY_REPL_ADD_OVLAN 0x8 +/** Set to enable Replace or Add of Inner VLAN + */ +#define CFA_BLD_ACT_MODIFY_REPL_ADD_IVLAN 0x10 +/** Set to enable Modify of TTL + */ +#define CFA_BLD_ACT_MODIFY_TTL_UPDATE 0x20 +/** Set to enable delete of INT Tunnel + */ +#define CFA_BLD_ACT_MODIFY_DEL_INT_TNL 0x40 +/** For phase 7.0 this bit can be used to modify the tunnel + * protocol in addition to deleting internal or outer tunnel + */ +#define CFA_BLD_ACT_MODIFY_TUNNEL_MODIFY CFA_BLD_ACT_MODIFY_DEL_INT_TNL +/** Set to enable Modify of Field + */ +#define CFA_BLD_ACT_MODIFY_FIELD 0x80 +/** Set to enable Modify of Destination MAC + */ +#define CFA_BLD_ACT_MODIFY_DMAC 0x100 +/** Set to enable Modify of Source MAC + */ +#define CFA_BLD_ACT_MODIFY_SMAC 0x200 +/** Set to enable Modify of Source IPv6 Address + */ +#define CFA_BLD_ACT_MODIFY_SRC_IPV6 0x400 +/** Set to enable Modify of Destination IPv6 Address + */ +#define CFA_BLD_ACT_MODIFY_DST_IPV6 0x800 +/** Set to enable Modify of Source IPv4 Address + */ +#define CFA_BLD_ACT_MODIFY_SRC_IPV4 0x1000 +/** Set to enable Modify of Destination IPv4 Address + */ +#define CFA_BLD_ACT_MODIFY_DST_IPV4 0x2000 +/** Set to enable Modify of L4 Source Port + */ +#define CFA_BLD_ACT_MODIFY_SRC_PORT 0x4000 +/** Set to enable Modify of L4 Destination Port + */ +#define CFA_BLD_ACT_MODIFY_DST_PORT 0x8000 + uint16_t modify; + +/** Set to enable Modify of KID + */ +#define CFA_BLD_ACT_MODIFY_FIELD_KID 0x1 + + /* Valid for phase 7.0 or higher */ + uint16_t field_modify; + + /* Valid for phase 7.0 or higher */ + enum tunnel_modify_mode tnl_mod_mode; + + /** Source Control + * + * Controls the type of the Source Action the template is + * describing + * + * source is valid when: + * ((obj_type == CFA_BLD_ACT_OBJ_TYPE_FULL_ACT) || + * (obj_type == CFA_BLD_ACT_OBJ_TYPE_COMPACT_ACT) && + * act.source_enable || act.source_inline) + */ + enum source_rec_type source; +}; + +/** + * Key template consists of key fields that can be enabled/disabled + * individually. + */ +struct cfa_key_template { + /** [in] Identify if the key template is for TCAM. If false, the + * key template is for EM. This field is mandantory for device that + * only support fix key formats. + */ + bool is_wc_tcam_key; + /** [in] Identify if the key template will be use for IPv6 Keys. + * + * Note: This is important for THOR2 as the field length for the FlowId + * is dependent on the L3 flow type. For THOR2 for IPv4 Keys, the Flow + * Id field is 16 bits, for all other types (IPv6, ARP, PTP, EAP, RoCE, + * FCoE, UPAR), the Flow Id field length is 20 bits. + */ + bool is_ipv6_key; + /** [in] key field enable field array, set 1 to the corresponding + * field enable to make a field valid + */ + uint8_t field_en[CFA_V3_KEY_MAX_FIELD_CNT]; +}; + +/** + * Action template consists of action fields that can be enabled/disabled + * individually. + */ +struct cfa_action_template { + /** [in] CFA version for the action template */ + enum cfa_ver hw_ver; + /** [in] action field enable field array, set 1 to the corresponding + * field enable to make a field valid + */ + uint8_t data[CFA_V3_ACT_MAX_TEMPLATE_SZ]; +}; + +/**@}*/ + +/**@}*/ + +#endif /* _CFA_BLD_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_devops.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_devops.h new file mode 100644 index 0000000000..64b5fc6b56 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_devops.h @@ -0,0 +1,297 @@ +/**************************************************************************** + * Copyright(c) 2021 - 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_devops.h + * + * @brief CFA Builder devops interface for host applications + */ + +#ifndef _CFA_BLD_DEVOPS_H_ +#define _CFA_BLD_DEVOPS_H_ + +#include + +#include "cfa_bld.h" +#include "cfa_bld_defs.h" + +struct cfa_bld_devops; + +/** + * @addtogroup CFA_BLD CFA Builder Library + * \ingroup CFA_V3 + * @{ + */ + +/** + * CFA device information + */ +struct cfa_bld_devinfo { + /** [out] CFA Builder operations function pointer table */ + const struct cfa_bld_devops *devops; +}; + +/** + * @name CFA_BLD CFA Builder Host Device OPS API + * CFA builder host specific API used by host CFA application to bind + * to different CFA devices and access device by using device OPS. + */ + +/**@{*/ +/** CFA bind builder API + * + * This API retrieves the CFA global device configuration. This API should be + * called first before doing any operations to CFA through API. The returned + * global device information should be referenced throughout the lifetime of + * the CFA application. + * + * @param[in] hw_ver + * hardware version of the CFA + * + * @param[out] dev_info + * CFA global device information + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_bld_bind(enum cfa_ver hw_ver, struct cfa_bld_devinfo *dev_info); + +/** CFA device specific function hooks structure + * + * The following device hooks can be defined; unless noted otherwise, they are + * optional and can be filled with a null pointer. The pupose of these hooks + * to support CFA device operations for different device variants. + */ +struct cfa_bld_devops { + /** Get CFA layout for hw fix format tables + * + * This API takes returns the CFA layout for a given resource type + * resource subtype and CFA direction. + * + * @param[in] rtype + * CFA HW resource type. Valid values are CFA_RTYPE_XXX + * + * @param[in] rsubtype + * CFA HW resource sub type for the given resource type 'rtype' + * Valid values are CFA_RSUBTYPE_XXX_YYY, where XXX is the resource + * type + * + * @param[in] dir + * CFA direction. RX/TX. Note that the returned layout is different + * for RX and TX, only for VEB and VSPT tables. For all tables, the + * layout is the same for both directions. + * + * @param[out] layout + * Pointer to the table layout to be returned + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + * @note example usage: To get L2 context TCAM table, use + * struct cfa_layout *l2ctxt_tcam_layout; + * devops->cfa_bld_get_table_layout(CFA_RTYPE_TCAM, + * CFA_RSUBTYPE_TCAM_L2CTX, + * CFA_TX, + * &l2ctxt_tcam_layout); + */ + int (*cfa_bld_get_table_layout)(enum cfa_resource_type rtype, + uint8_t rsubtype, enum cfa_dir dir, + struct cfa_layout **layout); + + /** Get CFA layout for HW remap tables + * + * This API takes returns the CFA remap layout for a given tcam + * resource sub type, remap type and CFA direction. + * + * @param[in] st + * CFA TCAM table sub types. Valid values are CFA_RSUBTYPE_TCAM_XXX + * + * @param[in] rmp_tt + * CFA Remap table type. See enum cfa_remap_tbl_type + * + * @param[in] dir + * CFA direction. RX/TX. + * + * @param[out] layout + * Pointer to the remap table layout to be returned + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + * @note example usage: To get Profiler TCAM Remap bypass table, use + * struct cfa_layout *prof_tcam_rmp_byp_layout; + * devops->cfa_bld_get_remap_table_layout(CFA_RSUBTYPE_TCAM_PROF_TCAM, + * CFA_REMAP_TBL_TYPE_BYPASS, + * CFA_TX, + * &prof_tcam_rmp_byp_layout); + */ + int (*cfa_bld_get_remap_table_layout)(enum cfa_resource_subtype_tcam st, + enum cfa_remap_tbl_type rmp_tt, + enum cfa_dir dir, + struct cfa_layout **layout); + + /** build key layout + * + * This API takes the user provided key template as input and + * compiles it into a key layout supported by the hardware. + * It is intended that an application will only compile a + * key layout once for the provided key template and then + * reference the key layout throughout the lifetime of that + * key template. + * + * @param[in] key_template + * A pointer to the key template + * + * @param[in,out] layout + * A pointer of the key layout + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ + int (*cfa_bld_key_compile_layout)(struct cfa_key_template *t, + struct cfa_key_layout *l); + + /** Print formatted key object + * + * This API prints in human readable form the data in a key + * object based upon the key layout provided. It also provides the + * option to provide a raw byte output. + * + * @param[in] stream + * Generally set to stdout (stderr possible) + * + * @param[in] key_obj + * A pointer to the key_obj to be displayed + * + * @param[in] key_layout + * A pointer to the key_layout indicating the key format + * + * @param[in] decode + * If set, decode the fields, if clear provide raw byte output. + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ + int (*cfa_bld_key_print_obj)(FILE *stream, struct cfa_key_obj *key_obj, + struct cfa_key_layout *key_layout, + bool decode); + + /** Transform key data with device specific control information + * + * This API inserts or strips device specific control information + * to/from a key object. + * + * @param[in] op + * specify key transform operations. + * + * @param[in] key_obj + * A pointer of the key object to be transformed + * + * @param[out] key_obj_out + * A pointer of the transformed key data object + * The updated bitlen for the transformed key is returned + * in the data_len_bits field of this object. + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ + int (*cfa_bld_key_transform)(enum cfa_key_ctrlops op, + struct cfa_key_obj *key_obj, + struct cfa_key_obj *key_obj_out); + + /** build action layout + * + * This API takes the user provided action template as input and + * compiles it into an action layout supported by the hardware. + * It is intended that an application will only compile an + * action layout once for the provided action template and then + * reference the action layout throughout the lifetime of that + * action template. + * + * @param[in] act_template + * A pointer to the action template + * + * @param[in,out] layout + * A pointer of the action layout + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ + int (*cfa_bld_act_compile_layout)(struct cfa_action_template *t, + struct cfa_action_layout *l); + + /** initialize action private fields + * + * This API provides the functionality to zero out the action + * object data fields and set pre-initialized private fields + * based on the layout. Any action object must be initialized + * using this API before any put and get APIs can be executed + * for an action object. + * + * @param[in,out] act_obj + * A pointer of the action object to be initialized + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ + int (*cfa_bld_action_init_obj)(struct cfa_action_obj *act_obj); + + /** compute inline action object pointers/offsets + * + * This API provides the functionality to compute and set + * pointers/offset to the inlined actions in an action record. + * This API is applicable only to the action object type that + * support inline actions. + * + * @param[in,out] act_obj + * A pointer of the action object to be initialized + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ + int (*cfa_bld_action_compute_ptr)(struct cfa_action_obj *obj); + + /** Print action object + * + * This API presents the action object in human readable + * format. + * + * + * @param[in] stream + * Generally set to stdout (stderr possible) + * + * @param[in,out] act_obj + * A pointer of the action object to be displayed + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ + int (*cfa_bld_action_print_obj)(FILE *stream, + struct cfa_action_obj *obj, + bool decode); + + /** Print field object + * + * This API prints out the raw field output + * + * @param[in] fld_obj + * A pointer fld_obj to be displayed + * + * @param[in] fld_layout + * A pointer to the cfa_layout indicating the field format + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ + int (*cfa_bld_fld_print_obj)(uint64_t *fld_obj, + struct cfa_layout *layout); +}; + +/**@}*/ + +/**@}*/ +#endif /* _CFA_BLD_DEVOPS_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_field_ids.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_field_ids.h new file mode 100644 index 0000000000..1860aa2e3e --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_field_ids.h @@ -0,0 +1,1542 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_field_ids.h + * + * @brief Enumerations definitions for CFA HW table fields, Action record + * fields and Lookup Key (EM/WC-TCAM) fields. + * + * This file is independent of the CFA HW version and defines the + * superset of the enumeration values for table, action and EM/WC-TCAM + * bit fields. This file is meant for use by host applications that + * support multiple devices with different CFA Hw versions. + * + * These enum definitions should be updated whenever any of the + * definitions in the auto-generated header 'cfa_bld_pxx_field_ids.h' + * file gets any new enum values. + */ + +#ifndef _CFA_BLD_FIELD_IDS_H_ +#define _CFA_BLD_FIELD_IDS_H_ + +/** + * Lookup Field Range Check Range Memory Fields: + */ +enum cfa_bld_lkup_frc_profile_flds { + CFA_BLD_LKUP_FRC_PROFILE_FIELD_SEL_1_FLD = 0, + CFA_BLD_LKUP_FRC_PROFILE_RANGE_CHECK_1_FLD = 1, + CFA_BLD_LKUP_FRC_PROFILE_FIELD_SEL_0_FLD = 2, + CFA_BLD_LKUP_FRC_PROFILE_RANGE_CHECK_0_FLD = 3, + CFA_BLD_LKUP_FRC_PROFILE_MAX_FLD +}; + +/** + * Lookup Connection Tracking State Memory Fields: + */ +enum cfa_bld_lkup_ct_state_flds { + CFA_BLD_LKUP_CT_STATE_NOTIFY_FLD = 0, + CFA_BLD_LKUP_CT_STATE_NOTIFY_STATE_FLD = 1, + CFA_BLD_LKUP_CT_STATE_ACTION_FLD = 2, + CFA_BLD_LKUP_CT_STATE_TIMER_SELECT_FLD = 3, + CFA_BLD_LKUP_CT_STATE_TIMER_PRELOAD_FLD = 4, + CFA_BLD_LKUP_CT_STATE_MAX_FLD +}; + +/** + * Lookup Connection Tracking State Machine Rule Memory Fields: + */ +enum cfa_bld_lkup_ct_rule_flds { + CFA_BLD_LKUP_CT_RULE_VALID_FLD = 0, + CFA_BLD_LKUP_CT_RULE_MASK_FLD = 1, + CFA_BLD_LKUP_CT_RULE_PKT_NOT_BG_FLD = 2, + CFA_BLD_LKUP_CT_RULE_STATE_FLD = 3, + CFA_BLD_LKUP_CT_RULE_TCP_FLAGS_FLD = 4, + CFA_BLD_LKUP_CT_RULE_PROT_IS_TCP_FLD = 5, + CFA_BLD_LKUP_CT_RULE_MSB_UPDT_FLD = 6, + CFA_BLD_LKUP_CT_RULE_FLAGS_FAILED_FLD = 7, + CFA_BLD_LKUP_CT_RULE_WIN_FAILED_FLD = 8, + CFA_BLD_LKUP_CT_RULE_MAX_FLD +}; + +/** + * Lookup Connection Tracking State Machine Rule Record Memory Fields: + */ +enum cfa_bld_lkup_ct_rule_record_flds { + CFA_BLD_LKUP_CT_RULE_RECORD_ACTION_FLD = 0, + CFA_BLD_LKUP_CT_RULE_RECORD_NEXT_STATE_FLD = 1, + CFA_BLD_LKUP_CT_RULE_RECORD_SEND_FLD = 2, + CFA_BLD_LKUP_CT_RULE_RECORD_MAX_FLD +}; + +/** + * VEB Destination Bitmap Remap Table. Fields: + */ +enum cfa_bld_act_veb_rmp_flds { + CFA_BLD_ACT_VEB_RMP_MODE_FLD = 0, + CFA_BLD_ACT_VEB_RMP_ENABLE_FLD = 1, + CFA_BLD_ACT_VEB_RMP_BITMAP_FLD = 2, + CFA_BLD_ACT_VEB_RMP_MAX_FLD +}; + +/** + * Lookup Field Range Check Range Memory Fields: + */ +enum cfa_bld_lkup_frc_range_flds { + CFA_BLD_LKUP_FRC_RANGE_RANGE_LO_FLD = 0, + CFA_BLD_LKUP_FRC_RANGE_RANGE_HI_FLD = 1, + CFA_BLD_LKUP_FRC_RANGE_MAX_FLD +}; + +/** + * L2 Context TCAM. Fields: + */ +enum cfa_bld_prof_l2_ctxt_tcam_flds { + CFA_BLD_PROF_L2_CTXT_TCAM_VALID_FLD = 0, + CFA_BLD_PROF_L2_CTXT_TCAM_SPARE_FLD = 1, + CFA_BLD_PROF_L2_CTXT_TCAM_MPASS_CNT_FLD = 2, + CFA_BLD_PROF_L2_CTXT_TCAM_RCYC_FLD = 3, + CFA_BLD_PROF_L2_CTXT_TCAM_LOOPBACK_FLD = 4, + CFA_BLD_PROF_L2_CTXT_TCAM_SPIF_FLD = 5, + CFA_BLD_PROF_L2_CTXT_TCAM_PARIF_FLD = 6, + CFA_BLD_PROF_L2_CTXT_TCAM_SVIF_FLD = 7, + CFA_BLD_PROF_L2_CTXT_TCAM_METADATA_FLD = 8, + CFA_BLD_PROF_L2_CTXT_TCAM_L2_FUNC_FLD = 9, + CFA_BLD_PROF_L2_CTXT_TCAM_ROCE_FLD = 10, + CFA_BLD_PROF_L2_CTXT_TCAM_PURE_LLC_FLD = 11, + CFA_BLD_PROF_L2_CTXT_TCAM_OT_HDR_TYPE_FLD = 12, + CFA_BLD_PROF_L2_CTXT_TCAM_T_HDR_TYPE_FLD = 13, + CFA_BLD_PROF_L2_CTXT_TCAM_ID_CTXT_FLD = 14, + CFA_BLD_PROF_L2_CTXT_TCAM_MAC0_FLD = 15, + CFA_BLD_PROF_L2_CTXT_TCAM_MAC1_FLD = 16, + CFA_BLD_PROF_L2_CTXT_TCAM_VTAG_PRESENT_FLD = 17, + CFA_BLD_PROF_L2_CTXT_TCAM_TWO_VTAGS_FLD = 18, + CFA_BLD_PROF_L2_CTXT_TCAM_OVLAN_VID_FLD = 19, + CFA_BLD_PROF_L2_CTXT_TCAM_OVLAN_TPID_SEL_FLD = 20, + CFA_BLD_PROF_L2_CTXT_TCAM_IVLAN_VID_FLD = 21, + CFA_BLD_PROF_L2_CTXT_TCAM_IVLAN_TPID_SEL_FLD = 22, + CFA_BLD_PROF_L2_CTXT_TCAM_ETYPE_FLD = 23, + CFA_BLD_PROF_L2_CTXT_TCAM_MAX_FLD +}; + +/** + * Profiler Profile Lookup TCAM Fields: + */ +enum cfa_bld_prof_profile_tcam_flds { + CFA_BLD_PROF_PROFILE_TCAM_VALID_FLD = 0, + CFA_BLD_PROF_PROFILE_TCAM_SPARE_FLD = 1, + CFA_BLD_PROF_PROFILE_TCAM_LOOPBACK_FLD = 2, + CFA_BLD_PROF_PROFILE_TCAM_PKT_TYPE_FLD = 3, + CFA_BLD_PROF_PROFILE_TCAM_RCYC_FLD = 4, + CFA_BLD_PROF_PROFILE_TCAM_METADATA_FLD = 5, + CFA_BLD_PROF_PROFILE_TCAM_AGG_ERROR_FLD = 6, + CFA_BLD_PROF_PROFILE_TCAM_L2_FUNC_FLD = 7, + CFA_BLD_PROF_PROFILE_TCAM_PROF_FUNC_FLD = 8, + CFA_BLD_PROF_PROFILE_TCAM_HREC_NEXT_FLD = 9, + CFA_BLD_PROF_PROFILE_TCAM_INT_HDR_TYPE_FLD = 10, + CFA_BLD_PROF_PROFILE_TCAM_INT_HDR_GROUP_FLD = 11, + CFA_BLD_PROF_PROFILE_TCAM_INT_IFA_TAIL_FLD = 12, + CFA_BLD_PROF_PROFILE_TCAM_OTL2_HDR_VALID_FLD = 13, + CFA_BLD_PROF_PROFILE_TCAM_OTL2_HDR_TYPE_FLD = 14, + CFA_BLD_PROF_PROFILE_TCAM_OTL2_UC_MC_BC_FLD = 15, + CFA_BLD_PROF_PROFILE_TCAM_OTL2_VTAG_PRESENT_FLD = 16, + CFA_BLD_PROF_PROFILE_TCAM_OTL2_TWO_VTAGS_FLD = 17, + CFA_BLD_PROF_PROFILE_TCAM_OTL3_HDR_VALID_FLD = 18, + CFA_BLD_PROF_PROFILE_TCAM_OTL3_HDR_ERROR_FLD = 19, + CFA_BLD_PROF_PROFILE_TCAM_OTL3_HDR_TYPE_FLD = 20, + CFA_BLD_PROF_PROFILE_TCAM_OTL3_HDR_ISIP_FLD = 21, + CFA_BLD_PROF_PROFILE_TCAM_OTL4_HDR_VALID_FLD = 22, + CFA_BLD_PROF_PROFILE_TCAM_OTL4_HDR_ERROR_FLD = 23, + CFA_BLD_PROF_PROFILE_TCAM_OTL4_HDR_TYPE_FLD = 24, + CFA_BLD_PROF_PROFILE_TCAM_OTL4_HDR_IS_UDP_TCP_FLD = 25, + CFA_BLD_PROF_PROFILE_TCAM_OT_HDR_VALID_FLD = 26, + CFA_BLD_PROF_PROFILE_TCAM_OT_HDR_ERROR_FLD = 27, + CFA_BLD_PROF_PROFILE_TCAM_OT_HDR_TYPE_FLD = 28, + CFA_BLD_PROF_PROFILE_TCAM_OT_HDR_FLAGS_FLD = 29, + CFA_BLD_PROF_PROFILE_TCAM_TL2_HDR_VALID_FLD = 30, + CFA_BLD_PROF_PROFILE_TCAM_TL2_HDR_TYPE_FLD = 31, + CFA_BLD_PROF_PROFILE_TCAM_TL2_UC_MC_BC_FLD = 32, + CFA_BLD_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_FLD = 33, + CFA_BLD_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_FLD = 34, + CFA_BLD_PROF_PROFILE_TCAM_TL3_HDR_VALID_FLD = 35, + CFA_BLD_PROF_PROFILE_TCAM_TL3_HDR_ERROR_FLD = 36, + CFA_BLD_PROF_PROFILE_TCAM_TL3_HDR_TYPE_FLD = 37, + CFA_BLD_PROF_PROFILE_TCAM_TL3_HDR_ISIP_FLD = 38, + CFA_BLD_PROF_PROFILE_TCAM_TL4_HDR_VALID_FLD = 39, + CFA_BLD_PROF_PROFILE_TCAM_TL4_HDR_ERROR_FLD = 40, + CFA_BLD_PROF_PROFILE_TCAM_TL4_HDR_TYPE_FLD = 41, + CFA_BLD_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_FLD = 42, + CFA_BLD_PROF_PROFILE_TCAM_TUN_HDR_VALID_FLD = 43, + CFA_BLD_PROF_PROFILE_TCAM_TUN_HDR_ERROR_FLD = 44, + CFA_BLD_PROF_PROFILE_TCAM_TUN_HDR_TYPE_FLD = 45, + CFA_BLD_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_FLD = 46, + CFA_BLD_PROF_PROFILE_TCAM_L2_HDR_VALID_FLD = 47, + CFA_BLD_PROF_PROFILE_TCAM_L2_HDR_ERROR_FLD = 48, + CFA_BLD_PROF_PROFILE_TCAM_L2_HDR_TYPE_FLD = 49, + CFA_BLD_PROF_PROFILE_TCAM_L2_UC_MC_BC_FLD = 50, + CFA_BLD_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_FLD = 51, + CFA_BLD_PROF_PROFILE_TCAM_L2_TWO_VTAGS_FLD = 52, + CFA_BLD_PROF_PROFILE_TCAM_L3_HDR_VALID_FLD = 53, + CFA_BLD_PROF_PROFILE_TCAM_L3_HDR_ERROR_FLD = 54, + CFA_BLD_PROF_PROFILE_TCAM_L3_HDR_TYPE_FLD = 55, + CFA_BLD_PROF_PROFILE_TCAM_L3_HDR_ISIP_FLD = 56, + CFA_BLD_PROF_PROFILE_TCAM_L3_PROT_FLD = 57, + CFA_BLD_PROF_PROFILE_TCAM_L4_HDR_VALID_FLD = 58, + CFA_BLD_PROF_PROFILE_TCAM_L4_HDR_ERROR_FLD = 59, + CFA_BLD_PROF_PROFILE_TCAM_L4_HDR_TYPE_FLD = 60, + CFA_BLD_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_FLD = 61, + CFA_BLD_PROF_PROFILE_TCAM_L4_HDR_SUBTYPE_FLD = 62, + CFA_BLD_PROF_PROFILE_TCAM_L4_HDR_FLAGS_FLD = 63, + CFA_BLD_PROF_PROFILE_TCAM_L4_DCN_PRESENT_FLD = 64, + CFA_BLD_PROF_PROFILE_TCAM_MAX_FLD +}; + +/** + * Action VEB TCAM. TX Fields (VEB Remap Mode): + */ +enum cfa_bld_act_veb_tcam_tx_flds { + CFA_BLD_ACT_VEB_TCAM_TX_VALID_FLD = 0, + CFA_BLD_ACT_VEB_TCAM_TX_PARIF_IN_FLD = 1, + CFA_BLD_ACT_VEB_TCAM_TX_NUM_VTAGS_FLD = 2, + CFA_BLD_ACT_VEB_TCAM_TX_DMAC_FLD = 3, + CFA_BLD_ACT_VEB_TCAM_TX_OVID_FLD = 4, + CFA_BLD_ACT_VEB_TCAM_TX_IVID_FLD = 5, + CFA_BLD_ACT_VEB_TCAM_TX_MAX_FLD +}; + +/** + * RX Fields (Source Knockout Mode): + */ +enum cfa_bld_act_veb_tcam_rx_flds { + CFA_BLD_ACT_VEB_TCAM_RX_VALID_FLD = 0, + CFA_BLD_ACT_VEB_TCAM_RX_SPARE_FLD = 1, + CFA_BLD_ACT_VEB_TCAM_RX_PADDING_FLD = 2, + CFA_BLD_ACT_VEB_TCAM_RX_UNICAST_FLD = 3, + CFA_BLD_ACT_VEB_TCAM_RX_MULTICAST_FLD = 4, + CFA_BLD_ACT_VEB_TCAM_RX_BROADCAST_FLD = 5, + CFA_BLD_ACT_VEB_TCAM_RX_PFID_FLD = 6, + CFA_BLD_ACT_VEB_TCAM_RX_VFID_FLD = 7, + CFA_BLD_ACT_VEB_TCAM_RX_SMAC_FLD = 8, + CFA_BLD_ACT_VEB_TCAM_RX_MAX_FLD +}; + +/** + * Action Feature Chaining TCAM. + */ +enum cfa_bld_act_fc_tcam_flds { + CFA_BLD_ACT_FC_TCAM_FC_VALID_FLD = 0, + CFA_BLD_ACT_FC_TCAM_FC_RSVD_FLD = 1, + CFA_BLD_ACT_FC_TCAM_FC_METADATA_FLD = 2, + CFA_BLD_ACT_FC_TCAM_MAX_FLD +}; + +/** + * Feature Chaining TCAM Remap Table Fields: + */ +enum cfa_bld_act_fc_rmp_dr_flds { + CFA_BLD_ACT_FC_RMP_DR_METADATA_FLD = 0, + CFA_BLD_ACT_FC_RMP_DR_METAMASK_FLD = 1, + CFA_BLD_ACT_FC_RMP_DR_L2_FUNC_FLD = 2, + CFA_BLD_ACT_FC_RMP_DR_RSVD_FLD = 3, + CFA_BLD_ACT_FC_RMP_DR_MAX_FLD +}; + +/** + * Profile Input Lookup Table Memory Fields: + */ +enum cfa_bld_prof_ilt_dr_flds { + CFA_BLD_PROF_ILT_DR_ILT_META_EN_FLD = 0, + CFA_BLD_PROF_ILT_DR_META_PROF_FLD = 1, + CFA_BLD_PROF_ILT_DR_METADATA_FLD = 2, + CFA_BLD_PROF_ILT_DR_PARIF_FLD = 3, + CFA_BLD_PROF_ILT_DR_L2_FUNC_FLD = 4, + CFA_BLD_PROF_ILT_DR_EN_BD_META_FLD = 5, + CFA_BLD_PROF_ILT_DR_EN_BD_ACTION_FLD = 6, + CFA_BLD_PROF_ILT_DR_EN_ILT_DEST_FLD = 7, + CFA_BLD_PROF_ILT_DR_ILT_FWD_OP_FLD = 8, + CFA_BLD_PROF_ILT_DR_ILT_ACT_HINT_FLD = 9, + CFA_BLD_PROF_ILT_DR_ILT_SCOPE_FLD = 10, + CFA_BLD_PROF_ILT_DR_ILT_ACT_REC_PTR_FLD = 11, + CFA_BLD_PROF_ILT_DR_ILT_DESTINATION_FLD = 12, + CFA_BLD_PROF_ILT_DR_MAX_FLD +}; + +/** + * Profile Lookup TCAM Remap Table Fields: + */ +enum cfa_bld_prof_profile_rmp_dr_flds { + CFA_BLD_PROF_PROFILE_RMP_DR_PL_BYP_LKUP_EN_FLD = 0, + CFA_BLD_PROF_PROFILE_RMP_DR_EM_SEARCH_EN_FLD = 1, + CFA_BLD_PROF_PROFILE_RMP_DR_EM_PROFILE_ID_FLD = 2, + CFA_BLD_PROF_PROFILE_RMP_DR_EM_KEY_ID_FLD = 3, + CFA_BLD_PROF_PROFILE_RMP_DR_EM_SCOPE_FLD = 4, + CFA_BLD_PROF_PROFILE_RMP_DR_TCAM_SEARCH_EN_FLD = 5, + CFA_BLD_PROF_PROFILE_RMP_DR_TCAM_PROFILE_ID_FLD = 6, + CFA_BLD_PROF_PROFILE_RMP_DR_TCAM_KEY_ID_FLD = 7, + CFA_BLD_PROF_PROFILE_RMP_DR_TCAM_SCOPE_FLD = 8, + CFA_BLD_PROF_PROFILE_RMP_DR_MAX_FLD +}; + +/** + * PROF_PROFILE_RMP_DR_BYP + */ +enum cfa_bld_prof_profile_rmp_dr_byp_flds { + CFA_BLD_PROF_PROFILE_RMP_DR_BYP_PL_BYP_LKUP_EN_FLD = 0, + CFA_BLD_PROF_PROFILE_RMP_DR_BYP_RESERVED_FLD = 1, + CFA_BLD_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_FLD = 2, + CFA_BLD_PROF_PROFILE_RMP_DR_BYP_PL_ACT_HINT_FLD = 3, + CFA_BLD_PROF_PROFILE_RMP_DR_BYP_PL_SCOPE_FLD = 4, + CFA_BLD_PROF_PROFILE_RMP_DR_BYP_PL_ACT_REC_PTR_FLD = 5, + CFA_BLD_PROF_PROFILE_RMP_DR_BYP_MAX_FLD +}; + +/** + * VNIC-SVIF Properties Table Fields: TX SVIF Properties Table + */ +enum cfa_bld_act_vspt_dr_tx_flds { + CFA_BLD_ACT_VSPT_DR_TX_TPID_AS_CTL_FLD = 0, + CFA_BLD_ACT_VSPT_DR_TX_ALWD_TPID_FLD = 1, + CFA_BLD_ACT_VSPT_DR_TX_DFLT_TPID_FLD = 2, + CFA_BLD_ACT_VSPT_DR_TX_PRI_AS_CTL_FLD = 3, + CFA_BLD_ACT_VSPT_DR_TX_ALWD_PRI_FLD = 4, + CFA_BLD_ACT_VSPT_DR_TX_DFLT_PRI_FLD = 5, + CFA_BLD_ACT_VSPT_DR_TX_MIR_FLD = 6, + CFA_BLD_ACT_VSPT_DR_TX_MAX_FLD +}; + +/** + * RX VNIC Properties Table + */ +enum cfa_bld_act_vspt_dr_rx_flds { + CFA_BLD_ACT_VSPT_DR_RX_RSVD_FLD = 0, + CFA_BLD_ACT_VSPT_DR_RX_METAFMT_FLD = 1, + CFA_BLD_ACT_VSPT_DR_RX_FID_FLD = 2, + CFA_BLD_ACT_VSPT_DR_RX_MIR_FLD = 3, + CFA_BLD_ACT_VSPT_DR_RX_MAX_FLD +}; + +/** + * LAG ID Balance Table Fields: + */ +enum cfa_bld_act_lbt_dr_flds { + CFA_BLD_ACT_LBT_DR_DST_BMP_FLD = 0, + CFA_BLD_ACT_LBT_DR_MAX_FLD +}; + +/** + * L2 Context Lookup Remap Table Fields: + */ +enum cfa_bld_prof_l2_ctxt_rmp_dr_flds { + CFA_BLD_PROF_L2_CTXT_RMP_DR_PRSV_PARIF_FLD = 0, + CFA_BLD_PROF_L2_CTXT_RMP_DR_PARIF_FLD = 1, + CFA_BLD_PROF_L2_CTXT_RMP_DR_PRSV_L2IP_CTXT_FLD = 2, + CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_CTXT_FLD = 3, + CFA_BLD_PROF_L2_CTXT_RMP_DR_PRSV_PROF_FUNC_FLD = 4, + CFA_BLD_PROF_L2_CTXT_RMP_DR_PROF_FUNC_FLD = 5, + CFA_BLD_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_FLD = 6, + CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_META_ENB_FLD = 7, + CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_META_FLD = 8, + CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_ACT_ENB_FLD = 9, + CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_ACT_DATA_FLD = 10, + CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_RFS_ENB_FLD = 11, + CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_RFS_DATA_FLD = 12, + CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_DEST_ENB_FLD = 13, + CFA_BLD_PROF_L2_CTXT_RMP_DR_L2IP_DEST_DATA_FLD = 14, + CFA_BLD_PROF_L2_CTXT_RMP_DR_MAX_FLD +}; + +/** + * Multi Field Register. + */ +enum cfa_bld_act_fc_tcam_result_flds { + CFA_BLD_ACT_FC_TCAM_RESULT_SEARCH_RESULT_FLD = 0, + CFA_BLD_ACT_FC_TCAM_RESULT_UNUSED_0_FLD = 1, + CFA_BLD_ACT_FC_TCAM_RESULT_SEARCH_HIT_FLD = 2, + CFA_BLD_ACT_FC_TCAM_RESULT_MAX_FLD +}; + +/** + * Multi Field Register. + */ +enum cfa_bld_act_mirror_flds { + CFA_BLD_ACT_MIRROR_UNUSED_0_FLD = 0, + CFA_BLD_ACT_MIRROR_RELATIVE_FLD = 1, + CFA_BLD_ACT_MIRROR_HINT_FLD = 2, + CFA_BLD_ACT_MIRROR_SAMP_FLD = 3, + CFA_BLD_ACT_MIRROR_TRUNC_FLD = 4, + CFA_BLD_ACT_MIRROR_IGN_DROP_FLD = 5, + CFA_BLD_ACT_MIRROR_MODE_FLD = 6, + CFA_BLD_ACT_MIRROR_COND_FLD = 7, + CFA_BLD_ACT_MIRROR_AR_PTR_FLD = 8, + CFA_BLD_ACT_MIRROR_SAMP_CFG_FLD = 9, + CFA_BLD_ACT_MIRROR_MAX_FLD +}; + +/** + * WC LREC Lookup Record + */ +enum cfa_bld_wc_lrec_flds { + CFA_BLD_WC_LREC_METADATA_FLD = 0, + CFA_BLD_WC_LREC_META_PROF_FLD = 1, + CFA_BLD_WC_LREC_PROF_FUNC_FLD = 2, + CFA_BLD_WC_LREC_RECYCLE_DEST_FLD = 3, + CFA_BLD_WC_LREC_FC_PTR_FLD = 4, + CFA_BLD_WC_LREC_FC_TYPE_FLD = 5, + CFA_BLD_WC_LREC_FC_OP_FLD = 6, + CFA_BLD_WC_LREC_PATHS_M1_FLD = 7, + CFA_BLD_WC_LREC_ACT_REC_SIZE_FLD = 8, + CFA_BLD_WC_LREC_RING_TABLE_IDX_FLD = 9, + CFA_BLD_WC_LREC_DESTINATION_FLD = 10, + CFA_BLD_WC_LREC_ACT_REC_PTR_FLD = 11, + CFA_BLD_WC_LREC_ACT_HINT_FLD = 12, + CFA_BLD_WC_LREC_STRENGTH_FLD = 13, + CFA_BLD_WC_LREC_OPCODE_FLD = 14, + CFA_BLD_WC_LREC_EPOCH1_FLD = 15, + CFA_BLD_WC_LREC_EPOCH0_FLD = 16, + CFA_BLD_WC_LREC_REC_SIZE_FLD = 17, + CFA_BLD_WC_LREC_VALID_FLD = 18, + CFA_BLD_WC_LREC_MAX_FLD +}; + +/** + * EM LREC Lookup Record + */ +enum cfa_bld_em_lrec_flds { + CFA_BLD_EM_LREC_RANGE_IDX_FLD = 0, + CFA_BLD_EM_LREC_RANGE_PROFILE_FLD = 1, + CFA_BLD_EM_LREC_CREC_TIMER_VALUE_FLD = 2, + CFA_BLD_EM_LREC_CREC_STATE_FLD = 3, + CFA_BLD_EM_LREC_CREC_TCP_MSB_OPP_INIT_FLD = 4, + CFA_BLD_EM_LREC_CREC_TCP_MSB_OPP_FLD = 5, + CFA_BLD_EM_LREC_CREC_TCP_MSB_LOC_FLD = 6, + CFA_BLD_EM_LREC_CREC_TCP_WIN_FLD = 7, + CFA_BLD_EM_LREC_CREC_TCP_UPDT_EN_FLD = 8, + CFA_BLD_EM_LREC_CREC_TCP_DIR_FLD = 9, + CFA_BLD_EM_LREC_METADATA_FLD = 10, + CFA_BLD_EM_LREC_PROF_FUNC_FLD = 11, + CFA_BLD_EM_LREC_META_PROF_FLD = 12, + CFA_BLD_EM_LREC_RECYCLE_DEST_FLD = 13, + CFA_BLD_EM_LREC_FC_PTR_FLD = 14, + CFA_BLD_EM_LREC_FC_TYPE_FLD = 15, + CFA_BLD_EM_LREC_FC_OP_FLD = 16, + CFA_BLD_EM_LREC_PATHS_M1_FLD = 17, + CFA_BLD_EM_LREC_ACT_REC_SIZE_FLD = 18, + CFA_BLD_EM_LREC_RING_TABLE_IDX_FLD = 19, + CFA_BLD_EM_LREC_DESTINATION_FLD = 20, + CFA_BLD_EM_LREC_ACT_REC_PTR_FLD = 21, + CFA_BLD_EM_LREC_ACT_HINT_FLD = 22, + CFA_BLD_EM_LREC_STRENGTH_FLD = 23, + CFA_BLD_EM_LREC_OPCODE_FLD = 24, + CFA_BLD_EM_LREC_EPOCH1_FLD = 25, + CFA_BLD_EM_LREC_EPOCH0_FLD = 26, + CFA_BLD_EM_LREC_REC_SIZE_FLD = 27, + CFA_BLD_EM_LREC_VALID_FLD = 28, + CFA_BLD_EM_LREC_MAX_FLD +}; + +/** + * EM Lookup Bucket Format + */ +enum cfa_bld_em_bucket_flds { + CFA_BLD_EM_BUCKET_BIN0_ENTRY_FLD = 0, + CFA_BLD_EM_BUCKET_BIN0_HASH_MSBS_FLD = 1, + CFA_BLD_EM_BUCKET_BIN1_ENTRY_FLD = 2, + CFA_BLD_EM_BUCKET_BIN1_HASH_MSBS_FLD = 3, + CFA_BLD_EM_BUCKET_BIN2_ENTRY_FLD = 4, + CFA_BLD_EM_BUCKET_BIN2_HASH_MSBS_FLD = 5, + CFA_BLD_EM_BUCKET_BIN3_ENTRY_FLD = 6, + CFA_BLD_EM_BUCKET_BIN3_HASH_MSBS_FLD = 7, + CFA_BLD_EM_BUCKET_BIN4_ENTRY_FLD = 8, + CFA_BLD_EM_BUCKET_BIN4_HASH_MSBS_FLD = 9, + CFA_BLD_EM_BUCKET_BIN5_ENTRY_FLD = 10, + CFA_BLD_EM_BUCKET_BIN5_HASH_MSBS_FLD = 11, + CFA_BLD_EM_BUCKET_CHAIN_POINTER_FLD = 12, + CFA_BLD_EM_BUCKET_CHAIN_VALID_FLD = 13, + CFA_BLD_EM_BUCKET_MAX_FLD +}; + +/** + * Compact Action Record. The compact action record uses relative + * pointers to access needed data. This keeps the compact action record + * down to 64b. + */ +enum cfa_bld_compact_action_flds { + CFA_BLD_COMPACT_ACTION_TYPE_FLD = 0, + CFA_BLD_COMPACT_ACTION_DROP_FLD = 1, + CFA_BLD_COMPACT_ACTION_VLAN_DELETE_FLD = 2, + CFA_BLD_COMPACT_ACTION_DEST_FLD = 3, + CFA_BLD_COMPACT_ACTION_DEST_OP_FLD = 4, + CFA_BLD_COMPACT_ACTION_DECAP_FLD = 5, + CFA_BLD_COMPACT_ACTION_MIRRORING_FLD = 6, + CFA_BLD_COMPACT_ACTION_METER_PTR_FLD = 7, + CFA_BLD_COMPACT_ACTION_STAT0_OFF_FLD = 8, + CFA_BLD_COMPACT_ACTION_STAT0_OP_FLD = 9, + CFA_BLD_COMPACT_ACTION_STAT0_CTR_TYPE_FLD = 10, + CFA_BLD_COMPACT_ACTION_MOD_OFF_FLD = 11, + CFA_BLD_COMPACT_ACTION_ENC_OFF_FLD = 12, + CFA_BLD_COMPACT_ACTION_SRC_OFF_FLD = 13, + CFA_BLD_COMPACT_ACTION_UNUSED_0_FLD = 14, + CFA_BLD_COMPACT_ACTION_MAX_FLD +}; + +/** + * Full Action Record. The full action record uses full pointers to + * access needed data. It also allows access to all the action features. + * The Full Action record is 192b. + */ +enum cfa_bld_full_action_flds { + CFA_BLD_FULL_ACTION_TYPE_FLD = 0, + CFA_BLD_FULL_ACTION_DROP_FLD = 1, + CFA_BLD_FULL_ACTION_VLAN_DELETE_FLD = 2, + CFA_BLD_FULL_ACTION_DEST_FLD = 3, + CFA_BLD_FULL_ACTION_DEST_OP_FLD = 4, + CFA_BLD_FULL_ACTION_DECAP_FLD = 5, + CFA_BLD_FULL_ACTION_MIRRORING_FLD = 6, + CFA_BLD_FULL_ACTION_METER_PTR_FLD = 7, + CFA_BLD_FULL_ACTION_STAT0_PTR_FLD = 8, + CFA_BLD_FULL_ACTION_STAT0_OP_FLD = 9, + CFA_BLD_FULL_ACTION_STAT0_CTR_TYPE_FLD = 10, + CFA_BLD_FULL_ACTION_STAT1_PTR_FLD = 11, + CFA_BLD_FULL_ACTION_STAT1_OP_FLD = 12, + CFA_BLD_FULL_ACTION_STAT1_CTR_TYPE_FLD = 13, + CFA_BLD_FULL_ACTION_MOD_PTR_FLD = 14, + CFA_BLD_FULL_ACTION_ENC_PTR_FLD = 15, + CFA_BLD_FULL_ACTION_SRC_PTR_FLD = 16, + CFA_BLD_FULL_ACTION_UNUSED_0_FLD = 17, + CFA_BLD_FULL_ACTION_MAX_FLD +}; + +/** + * Multicast Group Action Record. This action is used to send the packet + * to multiple destinations. The MGC Action record is 256b. + */ +enum cfa_bld_mcg_action_flds { + CFA_BLD_MCG_ACTION_TYPE_FLD = 0, + CFA_BLD_MCG_ACTION_SRC_KO_EN_FLD = 1, + CFA_BLD_MCG_ACTION_UNUSED_0_FLD = 2, + CFA_BLD_MCG_ACTION_NEXT_PTR_FLD = 3, + CFA_BLD_MCG_ACTION_PTR0_ACT_HINT_FLD = 4, + CFA_BLD_MCG_ACTION_PTR0_ACT_REC_PTR_FLD = 5, + CFA_BLD_MCG_ACTION_PTR1_ACT_HINT_FLD = 6, + CFA_BLD_MCG_ACTION_PTR1_ACT_REC_PTR_FLD = 7, + CFA_BLD_MCG_ACTION_PTR2_ACT_HINT_FLD = 8, + CFA_BLD_MCG_ACTION_PTR2_ACT_REC_PTR_FLD = 9, + CFA_BLD_MCG_ACTION_PTR3_ACT_HINT_FLD = 10, + CFA_BLD_MCG_ACTION_PTR3_ACT_REC_PTR_FLD = 11, + CFA_BLD_MCG_ACTION_PTR4_ACT_HINT_FLD = 12, + CFA_BLD_MCG_ACTION_PTR4_ACT_REC_PTR_FLD = 13, + CFA_BLD_MCG_ACTION_PTR5_ACT_HINT_FLD = 14, + CFA_BLD_MCG_ACTION_PTR5_ACT_REC_PTR_FLD = 15, + CFA_BLD_MCG_ACTION_PTR6_ACT_HINT_FLD = 16, + CFA_BLD_MCG_ACTION_PTR6_ACT_REC_PTR_FLD = 17, + CFA_BLD_MCG_ACTION_PTR7_ACT_HINT_FLD = 18, + CFA_BLD_MCG_ACTION_PTR7_ACT_REC_PTR_FLD = 19, + CFA_BLD_MCG_ACTION_MAX_FLD +}; + +/** + * Multicast Group Action Record. This action is used to send the packet + * to multiple destinations. The MGC Action record is 256b. + */ +enum cfa_bld_mcg_subseq_action_flds { + CFA_BLD_MCG_SUBSEQ_ACTION_TYPE_FLD = 0, + CFA_BLD_MCG_SUBSEQ_ACTION_UNUSED_0_FLD = 1, + CFA_BLD_MCG_SUBSEQ_ACTION_NEXT_PTR_FLD = 2, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR0_ACT_HINT_FLD = 3, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR0_ACT_REC_PTR_FLD = 4, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR1_ACT_HINT_FLD = 5, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR1_ACT_REC_PTR_FLD = 6, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR2_ACT_HINT_FLD = 7, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR2_ACT_REC_PTR_FLD = 8, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR3_ACT_HINT_FLD = 9, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR3_ACT_REC_PTR_FLD = 10, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR4_ACT_HINT_FLD = 11, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR4_ACT_REC_PTR_FLD = 12, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR5_ACT_HINT_FLD = 13, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR5_ACT_REC_PTR_FLD = 14, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR6_ACT_HINT_FLD = 15, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR6_ACT_REC_PTR_FLD = 16, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR7_ACT_HINT_FLD = 17, + CFA_BLD_MCG_SUBSEQ_ACTION_PTR7_ACT_REC_PTR_FLD = 18, + CFA_BLD_MCG_SUBSEQ_ACTION_MAX_FLD +}; + +/** + * Action Meter Formats + */ +enum cfa_bld_meters_flds { + CFA_BLD_METERS_BKT_C_FLD = 0, + CFA_BLD_METERS_BKT_E_FLD = 1, + CFA_BLD_METERS_FLAGS_MTR_VAL_FLD = 2, + CFA_BLD_METERS_FLAGS_ECN_RMP_EN_FLD = 3, + CFA_BLD_METERS_FLAGS_CF_FLD = 4, + CFA_BLD_METERS_FLAGS_PM_FLD = 5, + CFA_BLD_METERS_FLAGS_RFC2698_FLD = 6, + CFA_BLD_METERS_FLAGS_CBSM_FLD = 7, + CFA_BLD_METERS_FLAGS_EBSM_FLD = 8, + CFA_BLD_METERS_FLAGS_CBND_FLD = 9, + CFA_BLD_METERS_FLAGS_EBND_FLD = 10, + CFA_BLD_METERS_CBS_FLD = 11, + CFA_BLD_METERS_EBS_FLD = 12, + CFA_BLD_METERS_CIR_FLD = 13, + CFA_BLD_METERS_EIR_FLD = 14, + CFA_BLD_METERS_PROTECTION_SCOPE_FLD = 15, + CFA_BLD_METERS_PROTECTION_RSVD_FLD = 16, + CFA_BLD_METERS_PROTECTION_ENABLE_FLD = 17, + CFA_BLD_METERS_MAX_FLD +}; + +/** + * Enumeration for fkb + */ +enum cfa_bld_fkb_flds { + CFA_BLD_FKB_PROF_ID_FLD = 0, + CFA_BLD_FKB_L2CTXT_FLD = 1, + CFA_BLD_FKB_L2FUNC_FLD = 2, + CFA_BLD_FKB_PARIF_FLD = 3, + CFA_BLD_FKB_SPIF_FLD = 4, + CFA_BLD_FKB_SVIF_FLD = 5, + CFA_BLD_FKB_LCOS_FLD = 6, + CFA_BLD_FKB_META_HI_FLD = 7, + CFA_BLD_FKB_META_LO_FLD = 8, + CFA_BLD_FKB_RCYC_CNT_FLD = 9, + CFA_BLD_FKB_LOOPBACK_FLD = 10, + CFA_BLD_FKB_OTL2_TYPE_FLD = 11, + CFA_BLD_FKB_OTL2_DMAC_FLD = 12, + CFA_BLD_FKB_OTL2_SMAC_FLD = 13, + CFA_BLD_FKB_OTL2_DT_FLD = 14, + CFA_BLD_FKB_OTL2_SA_FLD = 15, + CFA_BLD_FKB_OTL2_NVT_FLD = 16, + CFA_BLD_FKB_OTL2_OVP_FLD = 17, + CFA_BLD_FKB_OTL2_OVD_FLD = 18, + CFA_BLD_FKB_OTL2_OVV_FLD = 19, + CFA_BLD_FKB_OTL2_OVT_FLD = 20, + CFA_BLD_FKB_OTL2_IVP_FLD = 21, + CFA_BLD_FKB_OTL2_IVD_FLD = 22, + CFA_BLD_FKB_OTL2_IVV_FLD = 23, + CFA_BLD_FKB_OTL2_IVT_FLD = 24, + CFA_BLD_FKB_OTL2_ETYPE_FLD = 25, + CFA_BLD_FKB_OTL3_TYPE_FLD = 26, + CFA_BLD_FKB_OTL3_SIP3_FLD = 27, + CFA_BLD_FKB_OTL3_SIP2_FLD = 28, + CFA_BLD_FKB_OTL3_SIP1_FLD = 29, + CFA_BLD_FKB_OTL3_SIP0_FLD = 30, + CFA_BLD_FKB_OTL3_DIP3_FLD = 31, + CFA_BLD_FKB_OTL3_DIP2_FLD = 32, + CFA_BLD_FKB_OTL3_DIP1_FLD = 33, + CFA_BLD_FKB_OTL3_DIP0_FLD = 34, + CFA_BLD_FKB_OTL3_TTL_FLD = 35, + CFA_BLD_FKB_OTL3_PROT_FLD = 36, + CFA_BLD_FKB_OTL3_FID_FLD = 37, + CFA_BLD_FKB_OTL3_QOS_FLD = 38, + CFA_BLD_FKB_OTL3_IEH_NONEXT_FLD = 39, + CFA_BLD_FKB_OTL3_IEH_SEP_FLD = 40, + CFA_BLD_FKB_OTL3_IEH_AUTH_FLD = 41, + CFA_BLD_FKB_OTL3_IEH_DEST_FLD = 42, + CFA_BLD_FKB_OTL3_IEH_FRAG_FLD = 43, + CFA_BLD_FKB_OTL3_IEH_RTHDR_FLD = 44, + CFA_BLD_FKB_OTL3_IEH_HOP_FLD = 45, + CFA_BLD_FKB_OTL3_IEH_1FRAG_FLD = 46, + CFA_BLD_FKB_OTL3_DF_FLD = 47, + CFA_BLD_FKB_OTL3_L3ERR_FLD = 48, + CFA_BLD_FKB_OTL4_TYPE_FLD = 49, + CFA_BLD_FKB_OTL4_SRC_FLD = 50, + CFA_BLD_FKB_OTL4_DST_FLD = 51, + CFA_BLD_FKB_OTL4_FLAGS_FLD = 52, + CFA_BLD_FKB_OTL4_SEQ_FLD = 53, + CFA_BLD_FKB_OTL4_PA_FLD = 54, + CFA_BLD_FKB_OTL4_OPT_FLD = 55, + CFA_BLD_FKB_OTL4_TCPTS_FLD = 56, + CFA_BLD_FKB_OTL4_ERR_FLD = 57, + CFA_BLD_FKB_OT_TYPE_FLD = 58, + CFA_BLD_FKB_OT_FLAGS_FLD = 59, + CFA_BLD_FKB_OT_IDS_FLD = 60, + CFA_BLD_FKB_OT_ID_FLD = 61, + CFA_BLD_FKB_OT_CTXTS_FLD = 62, + CFA_BLD_FKB_OT_CTXT_FLD = 63, + CFA_BLD_FKB_OT_QOS_FLD = 64, + CFA_BLD_FKB_OT_ERR_FLD = 65, + CFA_BLD_FKB_TL2_TYPE_FLD = 66, + CFA_BLD_FKB_TL2_DMAC_FLD = 67, + CFA_BLD_FKB_TL2_SMAC_FLD = 68, + CFA_BLD_FKB_TL2_DT_FLD = 69, + CFA_BLD_FKB_TL2_SA_FLD = 70, + CFA_BLD_FKB_TL2_NVT_FLD = 71, + CFA_BLD_FKB_TL2_OVP_FLD = 72, + CFA_BLD_FKB_TL2_OVD_FLD = 73, + CFA_BLD_FKB_TL2_OVV_FLD = 74, + CFA_BLD_FKB_TL2_OVT_FLD = 75, + CFA_BLD_FKB_TL2_IVP_FLD = 76, + CFA_BLD_FKB_TL2_IVD_FLD = 77, + CFA_BLD_FKB_TL2_IVV_FLD = 78, + CFA_BLD_FKB_TL2_IVT_FLD = 79, + CFA_BLD_FKB_TL2_ETYPE_FLD = 80, + CFA_BLD_FKB_TL3_TYPE_FLD = 81, + CFA_BLD_FKB_TL3_SIP3_FLD = 82, + CFA_BLD_FKB_TL3_SIP2_FLD = 83, + CFA_BLD_FKB_TL3_SIP1_FLD = 84, + CFA_BLD_FKB_TL3_SIP0_FLD = 85, + CFA_BLD_FKB_TL3_DIP3_FLD = 86, + CFA_BLD_FKB_TL3_DIP2_FLD = 87, + CFA_BLD_FKB_TL3_DIP1_FLD = 88, + CFA_BLD_FKB_TL3_DIP0_FLD = 89, + CFA_BLD_FKB_TL3_TTL_FLD = 90, + CFA_BLD_FKB_TL3_PROT_FLD = 91, + CFA_BLD_FKB_TL3_FID_FLD = 92, + CFA_BLD_FKB_TL3_QOS_FLD = 93, + CFA_BLD_FKB_TL3_IEH_NONEXT_FLD = 94, + CFA_BLD_FKB_TL3_IEH_SEP_FLD = 95, + CFA_BLD_FKB_TL3_IEH_AUTH_FLD = 96, + CFA_BLD_FKB_TL3_IEH_DEST_FLD = 97, + CFA_BLD_FKB_TL3_IEH_FRAG_FLD = 98, + CFA_BLD_FKB_TL3_IEH_RTHDR_FLD = 99, + CFA_BLD_FKB_TL3_IEH_HOP_FLD = 100, + CFA_BLD_FKB_TL3_IEH_1FRAG_FLD = 101, + CFA_BLD_FKB_TL3_DF_FLD = 102, + CFA_BLD_FKB_TL3_L3ERR_FLD = 103, + CFA_BLD_FKB_TL4_TYPE_FLD = 104, + CFA_BLD_FKB_TL4_SRC_FLD = 105, + CFA_BLD_FKB_TL4_DST_FLD = 106, + CFA_BLD_FKB_TL4_FLAGS_FLD = 107, + CFA_BLD_FKB_TL4_SEQ_FLD = 108, + CFA_BLD_FKB_TL4_PA_FLD = 109, + CFA_BLD_FKB_TL4_OPT_FLD = 110, + CFA_BLD_FKB_TL4_TCPTS_FLD = 111, + CFA_BLD_FKB_TL4_ERR_FLD = 112, + CFA_BLD_FKB_T_TYPE_FLD = 113, + CFA_BLD_FKB_T_FLAGS_FLD = 114, + CFA_BLD_FKB_T_IDS_FLD = 115, + CFA_BLD_FKB_T_ID_FLD = 116, + CFA_BLD_FKB_T_CTXTS_FLD = 117, + CFA_BLD_FKB_T_CTXT_FLD = 118, + CFA_BLD_FKB_T_QOS_FLD = 119, + CFA_BLD_FKB_T_ERR_FLD = 120, + CFA_BLD_FKB_L2_TYPE_FLD = 121, + CFA_BLD_FKB_L2_DMAC_FLD = 122, + CFA_BLD_FKB_L2_SMAC_FLD = 123, + CFA_BLD_FKB_L2_DT_FLD = 124, + CFA_BLD_FKB_L2_SA_FLD = 125, + CFA_BLD_FKB_L2_NVT_FLD = 126, + CFA_BLD_FKB_L2_OVP_FLD = 127, + CFA_BLD_FKB_L2_OVD_FLD = 128, + CFA_BLD_FKB_L2_OVV_FLD = 129, + CFA_BLD_FKB_L2_OVT_FLD = 130, + CFA_BLD_FKB_L2_IVP_FLD = 131, + CFA_BLD_FKB_L2_IVD_FLD = 132, + CFA_BLD_FKB_L2_IVV_FLD = 133, + CFA_BLD_FKB_L2_IVT_FLD = 134, + CFA_BLD_FKB_L2_ETYPE_FLD = 135, + CFA_BLD_FKB_L3_TYPE_FLD = 136, + CFA_BLD_FKB_L3_SIP3_FLD = 137, + CFA_BLD_FKB_L3_SIP2_FLD = 138, + CFA_BLD_FKB_L3_SIP1_FLD = 139, + CFA_BLD_FKB_L3_SIP0_FLD = 140, + CFA_BLD_FKB_L3_DIP3_FLD = 141, + CFA_BLD_FKB_L3_DIP2_FLD = 142, + CFA_BLD_FKB_L3_DIP1_FLD = 143, + CFA_BLD_FKB_L3_DIP0_FLD = 144, + CFA_BLD_FKB_L3_TTL_FLD = 145, + CFA_BLD_FKB_L3_PROT_FLD = 146, + CFA_BLD_FKB_L3_FID_FLD = 147, + CFA_BLD_FKB_L3_QOS_FLD = 148, + CFA_BLD_FKB_L3_IEH_NONEXT_FLD = 149, + CFA_BLD_FKB_L3_IEH_SEP_FLD = 150, + CFA_BLD_FKB_L3_IEH_AUTH_FLD = 151, + CFA_BLD_FKB_L3_IEH_DEST_FLD = 152, + CFA_BLD_FKB_L3_IEH_FRAG_FLD = 153, + CFA_BLD_FKB_L3_IEH_RTHDR_FLD = 154, + CFA_BLD_FKB_L3_IEH_HOP_FLD = 155, + CFA_BLD_FKB_L3_IEH_1FRAG_FLD = 156, + CFA_BLD_FKB_L3_DF_FLD = 157, + CFA_BLD_FKB_L3_L3ERR_FLD = 158, + CFA_BLD_FKB_L4_TYPE_FLD = 159, + CFA_BLD_FKB_L4_SRC_FLD = 160, + CFA_BLD_FKB_L4_DST_FLD = 161, + CFA_BLD_FKB_L4_FLAGS_FLD = 162, + CFA_BLD_FKB_L4_SEQ_FLD = 163, + CFA_BLD_FKB_L4_ACK_FLD = 164, + CFA_BLD_FKB_L4_WIN_FLD = 165, + CFA_BLD_FKB_L4_PA_FLD = 166, + CFA_BLD_FKB_L4_OPT_FLD = 167, + CFA_BLD_FKB_L4_TCPTS_FLD = 168, + CFA_BLD_FKB_L4_TSVAL_FLD = 169, + CFA_BLD_FKB_L4_TXECR_FLD = 170, + CFA_BLD_FKB_L4_ERR_FLD = 171, + CFA_BLD_FKB_MAX_FLD +}; + +/** + * Enumeration for wc tcam fkb + */ +enum cfa_bld_wc_tcam_fkb_flds { + CFA_BLD_WC_TCAM_FKB_PROF_ID_FLD = 0, + CFA_BLD_WC_TCAM_FKB_L2CTXT_FLD = 1, + CFA_BLD_WC_TCAM_FKB_L2FUNC_FLD = 2, + CFA_BLD_WC_TCAM_FKB_PARIF_FLD = 3, + CFA_BLD_WC_TCAM_FKB_SPIF_FLD = 4, + CFA_BLD_WC_TCAM_FKB_SVIF_FLD = 5, + CFA_BLD_WC_TCAM_FKB_LCOS_FLD = 6, + CFA_BLD_WC_TCAM_FKB_META_HI_FLD = 7, + CFA_BLD_WC_TCAM_FKB_META_LO_FLD = 8, + CFA_BLD_WC_TCAM_FKB_RCYC_CNT_FLD = 9, + CFA_BLD_WC_TCAM_FKB_LOOPBACK_FLD = 10, + CFA_BLD_WC_TCAM_FKB_OTL2_TYPE_FLD = 11, + CFA_BLD_WC_TCAM_FKB_OTL2_DMAC_FLD = 12, + CFA_BLD_WC_TCAM_FKB_OTL2_SMAC_FLD = 13, + CFA_BLD_WC_TCAM_FKB_OTL2_DT_FLD = 14, + CFA_BLD_WC_TCAM_FKB_OTL2_SA_FLD = 15, + CFA_BLD_WC_TCAM_FKB_OTL2_NVT_FLD = 16, + CFA_BLD_WC_TCAM_FKB_OTL2_OVP_FLD = 17, + CFA_BLD_WC_TCAM_FKB_OTL2_OVD_FLD = 18, + CFA_BLD_WC_TCAM_FKB_OTL2_OVV_FLD = 19, + CFA_BLD_WC_TCAM_FKB_OTL2_OVT_FLD = 20, + CFA_BLD_WC_TCAM_FKB_OTL2_IVP_FLD = 21, + CFA_BLD_WC_TCAM_FKB_OTL2_IVD_FLD = 22, + CFA_BLD_WC_TCAM_FKB_OTL2_IVV_FLD = 23, + CFA_BLD_WC_TCAM_FKB_OTL2_IVT_FLD = 24, + CFA_BLD_WC_TCAM_FKB_OTL2_ETYPE_FLD = 25, + CFA_BLD_WC_TCAM_FKB_OTL3_TYPE_FLD = 26, + CFA_BLD_WC_TCAM_FKB_OTL3_SIP3_FLD = 27, + CFA_BLD_WC_TCAM_FKB_OTL3_SIP2_FLD = 28, + CFA_BLD_WC_TCAM_FKB_OTL3_SIP1_FLD = 29, + CFA_BLD_WC_TCAM_FKB_OTL3_SIP0_FLD = 30, + CFA_BLD_WC_TCAM_FKB_OTL3_DIP3_FLD = 31, + CFA_BLD_WC_TCAM_FKB_OTL3_DIP2_FLD = 32, + CFA_BLD_WC_TCAM_FKB_OTL3_DIP1_FLD = 33, + CFA_BLD_WC_TCAM_FKB_OTL3_DIP0_FLD = 34, + CFA_BLD_WC_TCAM_FKB_OTL3_TTL_FLD = 35, + CFA_BLD_WC_TCAM_FKB_OTL3_PROT_FLD = 36, + CFA_BLD_WC_TCAM_FKB_OTL3_FID_FLD = 37, + CFA_BLD_WC_TCAM_FKB_OTL3_QOS_FLD = 38, + CFA_BLD_WC_TCAM_FKB_OTL3_IEH_NONEXT_FLD = 39, + CFA_BLD_WC_TCAM_FKB_OTL3_IEH_SEP_FLD = 40, + CFA_BLD_WC_TCAM_FKB_OTL3_IEH_AUTH_FLD = 41, + CFA_BLD_WC_TCAM_FKB_OTL3_IEH_DEST_FLD = 42, + CFA_BLD_WC_TCAM_FKB_OTL3_IEH_FRAG_FLD = 43, + CFA_BLD_WC_TCAM_FKB_OTL3_IEH_RTHDR_FLD = 44, + CFA_BLD_WC_TCAM_FKB_OTL3_IEH_HOP_FLD = 45, + CFA_BLD_WC_TCAM_FKB_OTL3_IEH_1FRAG_FLD = 46, + CFA_BLD_WC_TCAM_FKB_OTL3_DF_FLD = 47, + CFA_BLD_WC_TCAM_FKB_OTL3_L3ERR_FLD = 48, + CFA_BLD_WC_TCAM_FKB_OTL4_TYPE_FLD = 49, + CFA_BLD_WC_TCAM_FKB_OTL4_SRC_FLD = 50, + CFA_BLD_WC_TCAM_FKB_OTL4_DST_FLD = 51, + CFA_BLD_WC_TCAM_FKB_OTL4_FLAGS_FLD = 52, + CFA_BLD_WC_TCAM_FKB_OTL4_SEQ_FLD = 53, + CFA_BLD_WC_TCAM_FKB_OTL4_PA_FLD = 54, + CFA_BLD_WC_TCAM_FKB_OTL4_OPT_FLD = 55, + CFA_BLD_WC_TCAM_FKB_OTL4_TCPTS_FLD = 56, + CFA_BLD_WC_TCAM_FKB_OTL4_ERR_FLD = 57, + CFA_BLD_WC_TCAM_FKB_OT_TYPE_FLD = 58, + CFA_BLD_WC_TCAM_FKB_OT_FLAGS_FLD = 59, + CFA_BLD_WC_TCAM_FKB_OT_IDS_FLD = 60, + CFA_BLD_WC_TCAM_FKB_OT_ID_FLD = 61, + CFA_BLD_WC_TCAM_FKB_OT_CTXTS_FLD = 62, + CFA_BLD_WC_TCAM_FKB_OT_CTXT_FLD = 63, + CFA_BLD_WC_TCAM_FKB_OT_QOS_FLD = 64, + CFA_BLD_WC_TCAM_FKB_OT_ERR_FLD = 65, + CFA_BLD_WC_TCAM_FKB_TL2_TYPE_FLD = 66, + CFA_BLD_WC_TCAM_FKB_TL2_DMAC_FLD = 67, + CFA_BLD_WC_TCAM_FKB_TL2_SMAC_FLD = 68, + CFA_BLD_WC_TCAM_FKB_TL2_DT_FLD = 69, + CFA_BLD_WC_TCAM_FKB_TL2_SA_FLD = 70, + CFA_BLD_WC_TCAM_FKB_TL2_NVT_FLD = 71, + CFA_BLD_WC_TCAM_FKB_TL2_OVP_FLD = 72, + CFA_BLD_WC_TCAM_FKB_TL2_OVD_FLD = 73, + CFA_BLD_WC_TCAM_FKB_TL2_OVV_FLD = 74, + CFA_BLD_WC_TCAM_FKB_TL2_OVT_FLD = 75, + CFA_BLD_WC_TCAM_FKB_TL2_IVP_FLD = 76, + CFA_BLD_WC_TCAM_FKB_TL2_IVD_FLD = 77, + CFA_BLD_WC_TCAM_FKB_TL2_IVV_FLD = 78, + CFA_BLD_WC_TCAM_FKB_TL2_IVT_FLD = 79, + CFA_BLD_WC_TCAM_FKB_TL2_ETYPE_FLD = 80, + CFA_BLD_WC_TCAM_FKB_TL3_TYPE_FLD = 81, + CFA_BLD_WC_TCAM_FKB_TL3_SIP3_FLD = 82, + CFA_BLD_WC_TCAM_FKB_TL3_SIP2_FLD = 83, + CFA_BLD_WC_TCAM_FKB_TL3_SIP1_FLD = 84, + CFA_BLD_WC_TCAM_FKB_TL3_SIP0_FLD = 85, + CFA_BLD_WC_TCAM_FKB_TL3_DIP3_FLD = 86, + CFA_BLD_WC_TCAM_FKB_TL3_DIP2_FLD = 87, + CFA_BLD_WC_TCAM_FKB_TL3_DIP1_FLD = 88, + CFA_BLD_WC_TCAM_FKB_TL3_DIP0_FLD = 89, + CFA_BLD_WC_TCAM_FKB_TL3_TTL_FLD = 90, + CFA_BLD_WC_TCAM_FKB_TL3_PROT_FLD = 91, + CFA_BLD_WC_TCAM_FKB_TL3_FID_FLD = 92, + CFA_BLD_WC_TCAM_FKB_TL3_QOS_FLD = 93, + CFA_BLD_WC_TCAM_FKB_TL3_IEH_NONEXT_FLD = 94, + CFA_BLD_WC_TCAM_FKB_TL3_IEH_SEP_FLD = 95, + CFA_BLD_WC_TCAM_FKB_TL3_IEH_AUTH_FLD = 96, + CFA_BLD_WC_TCAM_FKB_TL3_IEH_DEST_FLD = 97, + CFA_BLD_WC_TCAM_FKB_TL3_IEH_FRAG_FLD = 98, + CFA_BLD_WC_TCAM_FKB_TL3_IEH_RTHDR_FLD = 99, + CFA_BLD_WC_TCAM_FKB_TL3_IEH_HOP_FLD = 100, + CFA_BLD_WC_TCAM_FKB_TL3_IEH_1FRAG_FLD = 101, + CFA_BLD_WC_TCAM_FKB_TL3_DF_FLD = 102, + CFA_BLD_WC_TCAM_FKB_TL3_L3ERR_FLD = 103, + CFA_BLD_WC_TCAM_FKB_TL4_TYPE_FLD = 104, + CFA_BLD_WC_TCAM_FKB_TL4_SRC_FLD = 105, + CFA_BLD_WC_TCAM_FKB_TL4_DST_FLD = 106, + CFA_BLD_WC_TCAM_FKB_TL4_FLAGS_FLD = 107, + CFA_BLD_WC_TCAM_FKB_TL4_SEQ_FLD = 108, + CFA_BLD_WC_TCAM_FKB_TL4_PA_FLD = 109, + CFA_BLD_WC_TCAM_FKB_TL4_OPT_FLD = 110, + CFA_BLD_WC_TCAM_FKB_TL4_TCPTS_FLD = 111, + CFA_BLD_WC_TCAM_FKB_TL4_ERR_FLD = 112, + CFA_BLD_WC_TCAM_FKB_T_TYPE_FLD = 113, + CFA_BLD_WC_TCAM_FKB_T_FLAGS_FLD = 114, + CFA_BLD_WC_TCAM_FKB_T_IDS_FLD = 115, + CFA_BLD_WC_TCAM_FKB_T_ID_FLD = 116, + CFA_BLD_WC_TCAM_FKB_T_CTXTS_FLD = 117, + CFA_BLD_WC_TCAM_FKB_T_CTXT_FLD = 118, + CFA_BLD_WC_TCAM_FKB_T_QOS_FLD = 119, + CFA_BLD_WC_TCAM_FKB_T_ERR_FLD = 120, + CFA_BLD_WC_TCAM_FKB_L2_TYPE_FLD = 121, + CFA_BLD_WC_TCAM_FKB_L2_DMAC_FLD = 122, + CFA_BLD_WC_TCAM_FKB_L2_SMAC_FLD = 123, + CFA_BLD_WC_TCAM_FKB_L2_DT_FLD = 124, + CFA_BLD_WC_TCAM_FKB_L2_SA_FLD = 125, + CFA_BLD_WC_TCAM_FKB_L2_NVT_FLD = 126, + CFA_BLD_WC_TCAM_FKB_L2_OVP_FLD = 127, + CFA_BLD_WC_TCAM_FKB_L2_OVD_FLD = 128, + CFA_BLD_WC_TCAM_FKB_L2_OVV_FLD = 129, + CFA_BLD_WC_TCAM_FKB_L2_OVT_FLD = 130, + CFA_BLD_WC_TCAM_FKB_L2_IVP_FLD = 131, + CFA_BLD_WC_TCAM_FKB_L2_IVD_FLD = 132, + CFA_BLD_WC_TCAM_FKB_L2_IVV_FLD = 133, + CFA_BLD_WC_TCAM_FKB_L2_IVT_FLD = 134, + CFA_BLD_WC_TCAM_FKB_L2_ETYPE_FLD = 135, + CFA_BLD_WC_TCAM_FKB_L3_TYPE_FLD = 136, + CFA_BLD_WC_TCAM_FKB_L3_SIP3_FLD = 137, + CFA_BLD_WC_TCAM_FKB_L3_SIP2_FLD = 138, + CFA_BLD_WC_TCAM_FKB_L3_SIP1_FLD = 139, + CFA_BLD_WC_TCAM_FKB_L3_SIP0_FLD = 140, + CFA_BLD_WC_TCAM_FKB_L3_DIP3_FLD = 141, + CFA_BLD_WC_TCAM_FKB_L3_DIP2_FLD = 142, + CFA_BLD_WC_TCAM_FKB_L3_DIP1_FLD = 143, + CFA_BLD_WC_TCAM_FKB_L3_DIP0_FLD = 144, + CFA_BLD_WC_TCAM_FKB_L3_TTL_FLD = 145, + CFA_BLD_WC_TCAM_FKB_L3_PROT_FLD = 146, + CFA_BLD_WC_TCAM_FKB_L3_FID_FLD = 147, + CFA_BLD_WC_TCAM_FKB_L3_QOS_FLD = 148, + CFA_BLD_WC_TCAM_FKB_L3_IEH_NONEXT_FLD = 149, + CFA_BLD_WC_TCAM_FKB_L3_IEH_SEP_FLD = 150, + CFA_BLD_WC_TCAM_FKB_L3_IEH_AUTH_FLD = 151, + CFA_BLD_WC_TCAM_FKB_L3_IEH_DEST_FLD = 152, + CFA_BLD_WC_TCAM_FKB_L3_IEH_FRAG_FLD = 153, + CFA_BLD_WC_TCAM_FKB_L3_IEH_RTHDR_FLD = 154, + CFA_BLD_WC_TCAM_FKB_L3_IEH_HOP_FLD = 155, + CFA_BLD_WC_TCAM_FKB_L3_IEH_1FRAG_FLD = 156, + CFA_BLD_WC_TCAM_FKB_L3_DF_FLD = 157, + CFA_BLD_WC_TCAM_FKB_L3_L3ERR_FLD = 158, + CFA_BLD_WC_TCAM_FKB_L4_TYPE_FLD = 159, + CFA_BLD_WC_TCAM_FKB_L4_SRC_FLD = 160, + CFA_BLD_WC_TCAM_FKB_L4_DST_FLD = 161, + CFA_BLD_WC_TCAM_FKB_L4_FLAGS_FLD = 162, + CFA_BLD_WC_TCAM_FKB_L4_SEQ_FLD = 163, + CFA_BLD_WC_TCAM_FKB_L4_ACK_FLD = 164, + CFA_BLD_WC_TCAM_FKB_L4_WIN_FLD = 165, + CFA_BLD_WC_TCAM_FKB_L4_PA_FLD = 166, + CFA_BLD_WC_TCAM_FKB_L4_OPT_FLD = 167, + CFA_BLD_WC_TCAM_FKB_L4_TCPTS_FLD = 168, + CFA_BLD_WC_TCAM_FKB_L4_TSVAL_FLD = 169, + CFA_BLD_WC_TCAM_FKB_L4_TXECR_FLD = 170, + CFA_BLD_WC_TCAM_FKB_L4_ERR_FLD = 171, + CFA_BLD_WC_TCAM_FKB_MAX_FLD +}; + +/** + * Enumeration for em fkb + */ +enum cfa_bld_em_fkb_flds { + CFA_BLD_EM_FKB_PROF_ID_FLD = 0, + CFA_BLD_EM_FKB_L2CTXT_FLD = 1, + CFA_BLD_EM_FKB_L2FUNC_FLD = 2, + CFA_BLD_EM_FKB_PARIF_FLD = 3, + CFA_BLD_EM_FKB_SPIF_FLD = 4, + CFA_BLD_EM_FKB_SVIF_FLD = 5, + CFA_BLD_EM_FKB_LCOS_FLD = 6, + CFA_BLD_EM_FKB_META_HI_FLD = 7, + CFA_BLD_EM_FKB_META_LO_FLD = 8, + CFA_BLD_EM_FKB_RCYC_CNT_FLD = 9, + CFA_BLD_EM_FKB_LOOPBACK_FLD = 10, + CFA_BLD_EM_FKB_OTL2_TYPE_FLD = 11, + CFA_BLD_EM_FKB_OTL2_DMAC_FLD = 12, + CFA_BLD_EM_FKB_OTL2_SMAC_FLD = 13, + CFA_BLD_EM_FKB_OTL2_DT_FLD = 14, + CFA_BLD_EM_FKB_OTL2_SA_FLD = 15, + CFA_BLD_EM_FKB_OTL2_NVT_FLD = 16, + CFA_BLD_EM_FKB_OTL2_OVP_FLD = 17, + CFA_BLD_EM_FKB_OTL2_OVD_FLD = 18, + CFA_BLD_EM_FKB_OTL2_OVV_FLD = 19, + CFA_BLD_EM_FKB_OTL2_OVT_FLD = 20, + CFA_BLD_EM_FKB_OTL2_IVP_FLD = 21, + CFA_BLD_EM_FKB_OTL2_IVD_FLD = 22, + CFA_BLD_EM_FKB_OTL2_IVV_FLD = 23, + CFA_BLD_EM_FKB_OTL2_IVT_FLD = 24, + CFA_BLD_EM_FKB_OTL2_ETYPE_FLD = 25, + CFA_BLD_EM_FKB_OTL3_TYPE_FLD = 26, + CFA_BLD_EM_FKB_OTL3_SIP3_FLD = 27, + CFA_BLD_EM_FKB_OTL3_SIP2_FLD = 28, + CFA_BLD_EM_FKB_OTL3_SIP1_FLD = 29, + CFA_BLD_EM_FKB_OTL3_SIP0_FLD = 30, + CFA_BLD_EM_FKB_OTL3_DIP3_FLD = 31, + CFA_BLD_EM_FKB_OTL3_DIP2_FLD = 32, + CFA_BLD_EM_FKB_OTL3_DIP1_FLD = 33, + CFA_BLD_EM_FKB_OTL3_DIP0_FLD = 34, + CFA_BLD_EM_FKB_OTL3_TTL_FLD = 35, + CFA_BLD_EM_FKB_OTL3_PROT_FLD = 36, + CFA_BLD_EM_FKB_OTL3_FID_FLD = 37, + CFA_BLD_EM_FKB_OTL3_QOS_FLD = 38, + CFA_BLD_EM_FKB_OTL3_IEH_NONEXT_FLD = 39, + CFA_BLD_EM_FKB_OTL3_IEH_SEP_FLD = 40, + CFA_BLD_EM_FKB_OTL3_IEH_AUTH_FLD = 41, + CFA_BLD_EM_FKB_OTL3_IEH_DEST_FLD = 42, + CFA_BLD_EM_FKB_OTL3_IEH_FRAG_FLD = 43, + CFA_BLD_EM_FKB_OTL3_IEH_RTHDR_FLD = 44, + CFA_BLD_EM_FKB_OTL3_IEH_HOP_FLD = 45, + CFA_BLD_EM_FKB_OTL3_IEH_1FRAG_FLD = 46, + CFA_BLD_EM_FKB_OTL3_DF_FLD = 47, + CFA_BLD_EM_FKB_OTL3_L3ERR_FLD = 48, + CFA_BLD_EM_FKB_OTL4_TYPE_FLD = 49, + CFA_BLD_EM_FKB_OTL4_SRC_FLD = 50, + CFA_BLD_EM_FKB_OTL4_DST_FLD = 51, + CFA_BLD_EM_FKB_OTL4_FLAGS_FLD = 52, + CFA_BLD_EM_FKB_OTL4_SEQ_FLD = 53, + CFA_BLD_EM_FKB_OTL4_PA_FLD = 54, + CFA_BLD_EM_FKB_OTL4_OPT_FLD = 55, + CFA_BLD_EM_FKB_OTL4_TCPTS_FLD = 56, + CFA_BLD_EM_FKB_OTL4_ERR_FLD = 57, + CFA_BLD_EM_FKB_OT_TYPE_FLD = 58, + CFA_BLD_EM_FKB_OT_FLAGS_FLD = 59, + CFA_BLD_EM_FKB_OT_IDS_FLD = 60, + CFA_BLD_EM_FKB_OT_ID_FLD = 61, + CFA_BLD_EM_FKB_OT_CTXTS_FLD = 62, + CFA_BLD_EM_FKB_OT_CTXT_FLD = 63, + CFA_BLD_EM_FKB_OT_QOS_FLD = 64, + CFA_BLD_EM_FKB_OT_ERR_FLD = 65, + CFA_BLD_EM_FKB_TL2_TYPE_FLD = 66, + CFA_BLD_EM_FKB_TL2_DMAC_FLD = 67, + CFA_BLD_EM_FKB_TL2_SMAC_FLD = 68, + CFA_BLD_EM_FKB_TL2_DT_FLD = 69, + CFA_BLD_EM_FKB_TL2_SA_FLD = 70, + CFA_BLD_EM_FKB_TL2_NVT_FLD = 71, + CFA_BLD_EM_FKB_TL2_OVP_FLD = 72, + CFA_BLD_EM_FKB_TL2_OVD_FLD = 73, + CFA_BLD_EM_FKB_TL2_OVV_FLD = 74, + CFA_BLD_EM_FKB_TL2_OVT_FLD = 75, + CFA_BLD_EM_FKB_TL2_IVP_FLD = 76, + CFA_BLD_EM_FKB_TL2_IVD_FLD = 77, + CFA_BLD_EM_FKB_TL2_IVV_FLD = 78, + CFA_BLD_EM_FKB_TL2_IVT_FLD = 79, + CFA_BLD_EM_FKB_TL2_ETYPE_FLD = 80, + CFA_BLD_EM_FKB_TL3_TYPE_FLD = 81, + CFA_BLD_EM_FKB_TL3_SIP3_FLD = 82, + CFA_BLD_EM_FKB_TL3_SIP2_FLD = 83, + CFA_BLD_EM_FKB_TL3_SIP1_FLD = 84, + CFA_BLD_EM_FKB_TL3_SIP0_FLD = 85, + CFA_BLD_EM_FKB_TL3_DIP3_FLD = 86, + CFA_BLD_EM_FKB_TL3_DIP2_FLD = 87, + CFA_BLD_EM_FKB_TL3_DIP1_FLD = 88, + CFA_BLD_EM_FKB_TL3_DIP0_FLD = 89, + CFA_BLD_EM_FKB_TL3_TTL_FLD = 90, + CFA_BLD_EM_FKB_TL3_PROT_FLD = 91, + CFA_BLD_EM_FKB_TL3_FID_FLD = 92, + CFA_BLD_EM_FKB_TL3_QOS_FLD = 93, + CFA_BLD_EM_FKB_TL3_IEH_NONEXT_FLD = 94, + CFA_BLD_EM_FKB_TL3_IEH_SEP_FLD = 95, + CFA_BLD_EM_FKB_TL3_IEH_AUTH_FLD = 96, + CFA_BLD_EM_FKB_TL3_IEH_DEST_FLD = 97, + CFA_BLD_EM_FKB_TL3_IEH_FRAG_FLD = 98, + CFA_BLD_EM_FKB_TL3_IEH_RTHDR_FLD = 99, + CFA_BLD_EM_FKB_TL3_IEH_HOP_FLD = 100, + CFA_BLD_EM_FKB_TL3_IEH_1FRAG_FLD = 101, + CFA_BLD_EM_FKB_TL3_DF_FLD = 102, + CFA_BLD_EM_FKB_TL3_L3ERR_FLD = 103, + CFA_BLD_EM_FKB_TL4_TYPE_FLD = 104, + CFA_BLD_EM_FKB_TL4_SRC_FLD = 105, + CFA_BLD_EM_FKB_TL4_DST_FLD = 106, + CFA_BLD_EM_FKB_TL4_FLAGS_FLD = 107, + CFA_BLD_EM_FKB_TL4_SEQ_FLD = 108, + CFA_BLD_EM_FKB_TL4_PA_FLD = 109, + CFA_BLD_EM_FKB_TL4_OPT_FLD = 110, + CFA_BLD_EM_FKB_TL4_TCPTS_FLD = 111, + CFA_BLD_EM_FKB_TL4_ERR_FLD = 112, + CFA_BLD_EM_FKB_T_TYPE_FLD = 113, + CFA_BLD_EM_FKB_T_FLAGS_FLD = 114, + CFA_BLD_EM_FKB_T_IDS_FLD = 115, + CFA_BLD_EM_FKB_T_ID_FLD = 116, + CFA_BLD_EM_FKB_T_CTXTS_FLD = 117, + CFA_BLD_EM_FKB_T_CTXT_FLD = 118, + CFA_BLD_EM_FKB_T_QOS_FLD = 119, + CFA_BLD_EM_FKB_T_ERR_FLD = 120, + CFA_BLD_EM_FKB_L2_TYPE_FLD = 121, + CFA_BLD_EM_FKB_L2_DMAC_FLD = 122, + CFA_BLD_EM_FKB_L2_SMAC_FLD = 123, + CFA_BLD_EM_FKB_L2_DT_FLD = 124, + CFA_BLD_EM_FKB_L2_SA_FLD = 125, + CFA_BLD_EM_FKB_L2_NVT_FLD = 126, + CFA_BLD_EM_FKB_L2_OVP_FLD = 127, + CFA_BLD_EM_FKB_L2_OVD_FLD = 128, + CFA_BLD_EM_FKB_L2_OVV_FLD = 129, + CFA_BLD_EM_FKB_L2_OVT_FLD = 130, + CFA_BLD_EM_FKB_L2_IVP_FLD = 131, + CFA_BLD_EM_FKB_L2_IVD_FLD = 132, + CFA_BLD_EM_FKB_L2_IVV_FLD = 133, + CFA_BLD_EM_FKB_L2_IVT_FLD = 134, + CFA_BLD_EM_FKB_L2_ETYPE_FLD = 135, + CFA_BLD_EM_FKB_L3_TYPE_FLD = 136, + CFA_BLD_EM_FKB_L3_SIP3_FLD = 137, + CFA_BLD_EM_FKB_L3_SIP2_FLD = 138, + CFA_BLD_EM_FKB_L3_SIP1_FLD = 139, + CFA_BLD_EM_FKB_L3_SIP0_FLD = 140, + CFA_BLD_EM_FKB_L3_DIP3_FLD = 141, + CFA_BLD_EM_FKB_L3_DIP2_FLD = 142, + CFA_BLD_EM_FKB_L3_DIP1_FLD = 143, + CFA_BLD_EM_FKB_L3_DIP0_FLD = 144, + CFA_BLD_EM_FKB_L3_TTL_FLD = 145, + CFA_BLD_EM_FKB_L3_PROT_FLD = 146, + CFA_BLD_EM_FKB_L3_FID_FLD = 147, + CFA_BLD_EM_FKB_L3_QOS_FLD = 148, + CFA_BLD_EM_FKB_L3_IEH_NONEXT_FLD = 149, + CFA_BLD_EM_FKB_L3_IEH_SEP_FLD = 150, + CFA_BLD_EM_FKB_L3_IEH_AUTH_FLD = 151, + CFA_BLD_EM_FKB_L3_IEH_DEST_FLD = 152, + CFA_BLD_EM_FKB_L3_IEH_FRAG_FLD = 153, + CFA_BLD_EM_FKB_L3_IEH_RTHDR_FLD = 154, + CFA_BLD_EM_FKB_L3_IEH_HOP_FLD = 155, + CFA_BLD_EM_FKB_L3_IEH_1FRAG_FLD = 156, + CFA_BLD_EM_FKB_L3_DF_FLD = 157, + CFA_BLD_EM_FKB_L3_L3ERR_FLD = 158, + CFA_BLD_EM_FKB_L4_TYPE_FLD = 159, + CFA_BLD_EM_FKB_L4_SRC_FLD = 160, + CFA_BLD_EM_FKB_L4_DST_FLD = 161, + CFA_BLD_EM_FKB_L4_FLAGS_FLD = 162, + CFA_BLD_EM_FKB_L4_SEQ_FLD = 163, + CFA_BLD_EM_FKB_L4_ACK_FLD = 164, + CFA_BLD_EM_FKB_L4_WIN_FLD = 165, + CFA_BLD_EM_FKB_L4_PA_FLD = 166, + CFA_BLD_EM_FKB_L4_OPT_FLD = 167, + CFA_BLD_EM_FKB_L4_TCPTS_FLD = 168, + CFA_BLD_EM_FKB_L4_TSVAL_FLD = 169, + CFA_BLD_EM_FKB_L4_TXECR_FLD = 170, + CFA_BLD_EM_FKB_L4_ERR_FLD = 171, + CFA_BLD_EM_FKB_MAX_FLD +}; + +/** + * Enumeration for em key layout + */ +enum cfa_bld_em_key_layout_flds { + CFA_BLD_EM_KL_RANGE_IDX_FLD = 0, + CFA_BLD_EM_KL_RANGE_PROFILE_FLD = 1, + CFA_BLD_EM_KL_CREC_TIMER_VALUE_FLD = 2, + CFA_BLD_EM_KL_CREC_STATE_FLD = 3, + CFA_BLD_EM_KL_CREC_TCP_MSB_OPP_INIT_FLD = 4, + CFA_BLD_EM_KL_CREC_TCP_MSB_OPP_FLD = 5, + CFA_BLD_EM_KL_CREC_TCP_MSB_LOC_FLD = 6, + CFA_BLD_EM_KL_CREC_TCP_WIN_FLD = 7, + CFA_BLD_EM_KL_CREC_TCP_UPDT_EN_FLD = 8, + CFA_BLD_EM_KL_CREC_TCP_DIR_FLD = 9, + CFA_BLD_EM_KL_METADATA_FLD = 10, + CFA_BLD_EM_KL_PROF_FUNC_FLD = 11, + CFA_BLD_EM_KL_META_PROF_FLD = 12, + CFA_BLD_EM_KL_RECYCLE_DEST_FLD = 13, + CFA_BLD_EM_KL_FC_PTR_FLD = 14, + CFA_BLD_EM_KL_FC_TYPE_FLD = 15, + CFA_BLD_EM_KL_FC_OP_FLD = 16, + CFA_BLD_EM_KL_PATHS_M1_FLD = 17, + CFA_BLD_EM_KL_ACT_REC_SIZE_FLD = 18, + CFA_BLD_EM_KL_RING_TABLE_IDX_FLD = 19, + CFA_BLD_EM_KL_DESTINATION_FLD = 20, + CFA_BLD_EM_KL_ACT_REC_PTR_FLD = 21, + CFA_BLD_EM_KL_ACT_HINT_FLD = 22, + CFA_BLD_EM_KL_STRENGTH_FLD = 23, + CFA_BLD_EM_KL_OPCODE_FLD = 24, + CFA_BLD_EM_KL_EPOCH1_FLD = 25, + CFA_BLD_EM_KL_EPOCH0_FLD = 26, + CFA_BLD_EM_KL_REC_SIZE_FLD = 27, + CFA_BLD_EM_KL_VALID_FLD = 28, + CFA_BLD_EM_KL_PROF_ID_FLD = 29, + CFA_BLD_EM_KL_L2CTXT_FLD = 30, + CFA_BLD_EM_KL_L2FUNC_FLD = 31, + CFA_BLD_EM_KL_PARIF_FLD = 32, + CFA_BLD_EM_KL_SPIF_FLD = 33, + CFA_BLD_EM_KL_SVIF_FLD = 34, + CFA_BLD_EM_KL_LCOS_FLD = 35, + CFA_BLD_EM_KL_META_HI_FLD = 36, + CFA_BLD_EM_KL_META_LO_FLD = 37, + CFA_BLD_EM_KL_RCYC_CNT_FLD = 38, + CFA_BLD_EM_KL_LOOPBACK_FLD = 39, + CFA_BLD_EM_KL_OTL2_TYPE_FLD = 40, + CFA_BLD_EM_KL_OTL2_DMAC_FLD = 41, + CFA_BLD_EM_KL_OTL2_SMAC_FLD = 42, + CFA_BLD_EM_KL_OTL2_DT_FLD = 43, + CFA_BLD_EM_KL_OTL2_SA_FLD = 44, + CFA_BLD_EM_KL_OTL2_NVT_FLD = 45, + CFA_BLD_EM_KL_OTL2_OVP_FLD = 46, + CFA_BLD_EM_KL_OTL2_OVD_FLD = 47, + CFA_BLD_EM_KL_OTL2_OVV_FLD = 48, + CFA_BLD_EM_KL_OTL2_OVT_FLD = 49, + CFA_BLD_EM_KL_OTL2_IVP_FLD = 50, + CFA_BLD_EM_KL_OTL2_IVD_FLD = 51, + CFA_BLD_EM_KL_OTL2_IVV_FLD = 52, + CFA_BLD_EM_KL_OTL2_IVT_FLD = 53, + CFA_BLD_EM_KL_OTL2_ETYPE_FLD = 54, + CFA_BLD_EM_KL_OTL3_TYPE_FLD = 55, + CFA_BLD_EM_KL_OTL3_SIP3_FLD = 56, + CFA_BLD_EM_KL_OTL3_SIP2_FLD = 57, + CFA_BLD_EM_KL_OTL3_SIP1_FLD = 58, + CFA_BLD_EM_KL_OTL3_SIP0_FLD = 59, + CFA_BLD_EM_KL_OTL3_DIP3_FLD = 60, + CFA_BLD_EM_KL_OTL3_DIP2_FLD = 61, + CFA_BLD_EM_KL_OTL3_DIP1_FLD = 62, + CFA_BLD_EM_KL_OTL3_DIP0_FLD = 63, + CFA_BLD_EM_KL_OTL3_TTL_FLD = 64, + CFA_BLD_EM_KL_OTL3_PROT_FLD = 65, + CFA_BLD_EM_KL_OTL3_FID_FLD = 66, + CFA_BLD_EM_KL_OTL3_QOS_FLD = 67, + CFA_BLD_EM_KL_OTL3_IEH_NONEXT_FLD = 68, + CFA_BLD_EM_KL_OTL3_IEH_SEP_FLD = 69, + CFA_BLD_EM_KL_OTL3_IEH_AUTH_FLD = 70, + CFA_BLD_EM_KL_OTL3_IEH_DEST_FLD = 71, + CFA_BLD_EM_KL_OTL3_IEH_FRAG_FLD = 72, + CFA_BLD_EM_KL_OTL3_IEH_RTHDR_FLD = 73, + CFA_BLD_EM_KL_OTL3_IEH_HOP_FLD = 74, + CFA_BLD_EM_KL_OTL3_IEH_1FRAG_FLD = 75, + CFA_BLD_EM_KL_OTL3_DF_FLD = 76, + CFA_BLD_EM_KL_OTL3_L3ERR_FLD = 77, + CFA_BLD_EM_KL_OTL4_TYPE_FLD = 78, + CFA_BLD_EM_KL_OTL4_SRC_FLD = 79, + CFA_BLD_EM_KL_OTL4_DST_FLD = 80, + CFA_BLD_EM_KL_OTL4_FLAGS_FLD = 81, + CFA_BLD_EM_KL_OTL4_SEQ_FLD = 82, + CFA_BLD_EM_KL_OTL4_PA_FLD = 83, + CFA_BLD_EM_KL_OTL4_OPT_FLD = 84, + CFA_BLD_EM_KL_OTL4_TCPTS_FLD = 85, + CFA_BLD_EM_KL_OTL4_ERR_FLD = 86, + CFA_BLD_EM_KL_OT_TYPE_FLD = 87, + CFA_BLD_EM_KL_OT_FLAGS_FLD = 88, + CFA_BLD_EM_KL_OT_IDS_FLD = 89, + CFA_BLD_EM_KL_OT_ID_FLD = 90, + CFA_BLD_EM_KL_OT_CTXTS_FLD = 91, + CFA_BLD_EM_KL_OT_CTXT_FLD = 92, + CFA_BLD_EM_KL_OT_QOS_FLD = 93, + CFA_BLD_EM_KL_OT_ERR_FLD = 94, + CFA_BLD_EM_KL_TL2_TYPE_FLD = 95, + CFA_BLD_EM_KL_TL2_DMAC_FLD = 96, + CFA_BLD_EM_KL_TL2_SMAC_FLD = 97, + CFA_BLD_EM_KL_TL2_DT_FLD = 98, + CFA_BLD_EM_KL_TL2_SA_FLD = 99, + CFA_BLD_EM_KL_TL2_NVT_FLD = 100, + CFA_BLD_EM_KL_TL2_OVP_FLD = 101, + CFA_BLD_EM_KL_TL2_OVD_FLD = 102, + CFA_BLD_EM_KL_TL2_OVV_FLD = 103, + CFA_BLD_EM_KL_TL2_OVT_FLD = 104, + CFA_BLD_EM_KL_TL2_IVP_FLD = 105, + CFA_BLD_EM_KL_TL2_IVD_FLD = 106, + CFA_BLD_EM_KL_TL2_IVV_FLD = 107, + CFA_BLD_EM_KL_TL2_IVT_FLD = 108, + CFA_BLD_EM_KL_TL2_ETYPE_FLD = 109, + CFA_BLD_EM_KL_TL3_TYPE_FLD = 110, + CFA_BLD_EM_KL_TL3_SIP3_FLD = 111, + CFA_BLD_EM_KL_TL3_SIP2_FLD = 112, + CFA_BLD_EM_KL_TL3_SIP1_FLD = 113, + CFA_BLD_EM_KL_TL3_SIP0_FLD = 114, + CFA_BLD_EM_KL_TL3_DIP3_FLD = 115, + CFA_BLD_EM_KL_TL3_DIP2_FLD = 116, + CFA_BLD_EM_KL_TL3_DIP1_FLD = 117, + CFA_BLD_EM_KL_TL3_DIP0_FLD = 118, + CFA_BLD_EM_KL_TL3_TTL_FLD = 119, + CFA_BLD_EM_KL_TL3_PROT_FLD = 120, + CFA_BLD_EM_KL_TL3_FID_FLD = 121, + CFA_BLD_EM_KL_TL3_QOS_FLD = 122, + CFA_BLD_EM_KL_TL3_IEH_NONEXT_FLD = 123, + CFA_BLD_EM_KL_TL3_IEH_SEP_FLD = 124, + CFA_BLD_EM_KL_TL3_IEH_AUTH_FLD = 125, + CFA_BLD_EM_KL_TL3_IEH_DEST_FLD = 126, + CFA_BLD_EM_KL_TL3_IEH_FRAG_FLD = 127, + CFA_BLD_EM_KL_TL3_IEH_RTHDR_FLD = 128, + CFA_BLD_EM_KL_TL3_IEH_HOP_FLD = 129, + CFA_BLD_EM_KL_TL3_IEH_1FRAG_FLD = 130, + CFA_BLD_EM_KL_TL3_DF_FLD = 131, + CFA_BLD_EM_KL_TL3_L3ERR_FLD = 132, + CFA_BLD_EM_KL_TL4_TYPE_FLD = 133, + CFA_BLD_EM_KL_TL4_SRC_FLD = 134, + CFA_BLD_EM_KL_TL4_DST_FLD = 135, + CFA_BLD_EM_KL_TL4_FLAGS_FLD = 136, + CFA_BLD_EM_KL_TL4_SEQ_FLD = 137, + CFA_BLD_EM_KL_TL4_PA_FLD = 138, + CFA_BLD_EM_KL_TL4_OPT_FLD = 139, + CFA_BLD_EM_KL_TL4_TCPTS_FLD = 140, + CFA_BLD_EM_KL_TL4_ERR_FLD = 141, + CFA_BLD_EM_KL_T_TYPE_FLD = 142, + CFA_BLD_EM_KL_T_FLAGS_FLD = 143, + CFA_BLD_EM_KL_T_IDS_FLD = 144, + CFA_BLD_EM_KL_T_ID_FLD = 145, + CFA_BLD_EM_KL_T_CTXTS_FLD = 146, + CFA_BLD_EM_KL_T_CTXT_FLD = 147, + CFA_BLD_EM_KL_T_QOS_FLD = 148, + CFA_BLD_EM_KL_T_ERR_FLD = 149, + CFA_BLD_EM_KL_L2_TYPE_FLD = 150, + CFA_BLD_EM_KL_L2_DMAC_FLD = 151, + CFA_BLD_EM_KL_L2_SMAC_FLD = 152, + CFA_BLD_EM_KL_L2_DT_FLD = 153, + CFA_BLD_EM_KL_L2_SA_FLD = 154, + CFA_BLD_EM_KL_L2_NVT_FLD = 155, + CFA_BLD_EM_KL_L2_OVP_FLD = 156, + CFA_BLD_EM_KL_L2_OVD_FLD = 157, + CFA_BLD_EM_KL_L2_OVV_FLD = 158, + CFA_BLD_EM_KL_L2_OVT_FLD = 159, + CFA_BLD_EM_KL_L2_IVP_FLD = 160, + CFA_BLD_EM_KL_L2_IVD_FLD = 161, + CFA_BLD_EM_KL_L2_IVV_FLD = 162, + CFA_BLD_EM_KL_L2_IVT_FLD = 163, + CFA_BLD_EM_KL_L2_ETYPE_FLD = 164, + CFA_BLD_EM_KL_L3_TYPE_FLD = 165, + CFA_BLD_EM_KL_L3_SIP3_FLD = 166, + CFA_BLD_EM_KL_L3_SIP2_FLD = 167, + CFA_BLD_EM_KL_L3_SIP1_FLD = 168, + CFA_BLD_EM_KL_L3_SIP0_FLD = 169, + CFA_BLD_EM_KL_L3_DIP3_FLD = 170, + CFA_BLD_EM_KL_L3_DIP2_FLD = 171, + CFA_BLD_EM_KL_L3_DIP1_FLD = 172, + CFA_BLD_EM_KL_L3_DIP0_FLD = 173, + CFA_BLD_EM_KL_L3_TTL_FLD = 174, + CFA_BLD_EM_KL_L3_PROT_FLD = 175, + CFA_BLD_EM_KL_L3_FID_FLD = 176, + CFA_BLD_EM_KL_L3_QOS_FLD = 177, + CFA_BLD_EM_KL_L3_IEH_NONEXT_FLD = 178, + CFA_BLD_EM_KL_L3_IEH_SEP_FLD = 179, + CFA_BLD_EM_KL_L3_IEH_AUTH_FLD = 180, + CFA_BLD_EM_KL_L3_IEH_DEST_FLD = 181, + CFA_BLD_EM_KL_L3_IEH_FRAG_FLD = 182, + CFA_BLD_EM_KL_L3_IEH_RTHDR_FLD = 183, + CFA_BLD_EM_KL_L3_IEH_HOP_FLD = 184, + CFA_BLD_EM_KL_L3_IEH_1FRAG_FLD = 185, + CFA_BLD_EM_KL_L3_DF_FLD = 186, + CFA_BLD_EM_KL_L3_L3ERR_FLD = 187, + CFA_BLD_EM_KL_L4_TYPE_FLD = 188, + CFA_BLD_EM_KL_L4_SRC_FLD = 189, + CFA_BLD_EM_KL_L4_DST_FLD = 190, + CFA_BLD_EM_KL_L4_FLAGS_FLD = 191, + CFA_BLD_EM_KL_L4_SEQ_FLD = 192, + CFA_BLD_EM_KL_L4_ACK_FLD = 193, + CFA_BLD_EM_KL_L4_WIN_FLD = 194, + CFA_BLD_EM_KL_L4_PA_FLD = 195, + CFA_BLD_EM_KL_L4_OPT_FLD = 196, + CFA_BLD_EM_KL_L4_TCPTS_FLD = 197, + CFA_BLD_EM_KL_L4_TSVAL_FLD = 198, + CFA_BLD_EM_KL_L4_TXECR_FLD = 199, + CFA_BLD_EM_KL_L4_ERR_FLD = 200, + CFA_BLD_EM_KEY_LAYOUT_MAX_FLD = 201, +}; + +/** + * Enumeration for action + */ +enum cfa_bld_action_flds { + CFA_BLD_ACT_TYPE_FLD = 0, + CFA_BLD_ACT_DROP_FLD = 1, + CFA_BLD_ACT_VLAN_DELETE_FLD = 2, + CFA_BLD_ACT_DEST_FLD = 3, + CFA_BLD_ACT_DEST_OP_FLD = 4, + CFA_BLD_ACT_DECAP_FLD = 5, + CFA_BLD_ACT_MIRRORING_FLD = 6, + CFA_BLD_ACT_METER_PTR_FLD = 7, + CFA_BLD_ACT_STAT0_OFF_FLD = 8, + CFA_BLD_ACT_STAT0_OP_FLD = 9, + CFA_BLD_ACT_STAT0_CTR_TYPE_FLD = 10, + CFA_BLD_ACT_MOD_OFF_FLD = 11, + CFA_BLD_ACT_ENC_OFF_FLD = 12, + CFA_BLD_ACT_SRC_OFF_FLD = 13, + CFA_BLD_ACT_COMPACT_RSVD_0_FLD = 14, + CFA_BLD_ACT_STAT0_PTR_FLD = 15, + CFA_BLD_ACT_STAT1_PTR_FLD = 16, + CFA_BLD_ACT_STAT1_OP_FLD = 17, + CFA_BLD_ACT_STAT1_CTR_TYPE_FLD = 18, + CFA_BLD_ACT_MOD_PTR_FLD = 19, + CFA_BLD_ACT_ENC_PTR_FLD = 20, + CFA_BLD_ACT_SRC_PTR_FLD = 21, + CFA_BLD_ACT_FULL_RSVD_0_FLD = 22, + CFA_BLD_ACT_SRC_KO_EN_FLD = 23, + CFA_BLD_ACT_MCG_RSVD_0_FLD = 24, + CFA_BLD_ACT_NEXT_PTR_FLD = 25, + CFA_BLD_ACT_PTR0_ACT_HINT_FLD = 26, + CFA_BLD_ACT_PTR0_ACT_REC_PTR_FLD = 27, + CFA_BLD_ACT_PTR1_ACT_HINT_FLD = 28, + CFA_BLD_ACT_PTR1_ACT_REC_PTR_FLD = 29, + CFA_BLD_ACT_PTR2_ACT_HINT_FLD = 30, + CFA_BLD_ACT_PTR2_ACT_REC_PTR_FLD = 31, + CFA_BLD_ACT_PTR3_ACT_HINT_FLD = 32, + CFA_BLD_ACT_PTR3_ACT_REC_PTR_FLD = 33, + CFA_BLD_ACT_PTR4_ACT_HINT_FLD = 34, + CFA_BLD_ACT_PTR4_ACT_REC_PTR_FLD = 35, + CFA_BLD_ACT_PTR5_ACT_HINT_FLD = 36, + CFA_BLD_ACT_PTR5_ACT_REC_PTR_FLD = 37, + CFA_BLD_ACT_PTR6_ACT_HINT_FLD = 38, + CFA_BLD_ACT_PTR6_ACT_REC_PTR_FLD = 39, + CFA_BLD_ACT_PTR7_ACT_HINT_FLD = 40, + CFA_BLD_ACT_PTR7_ACT_REC_PTR_FLD = 41, + CFA_BLD_ACT_MCG_SUBSEQ_RSVD_0_FLD = 42, + CFA_BLD_ACT_MOD_MODIFY_ACT_HDR_FLD = 43, + CFA_BLD_ACT_MOD_MD_UPDT_DATA_FLD = 44, + CFA_BLD_ACT_MOD_MD_UPDT_PROF_FLD = 45, + CFA_BLD_ACT_MOD_MD_UPDT_OP_FLD = 46, + CFA_BLD_ACT_MOD_MD_UPDT_RSVD_0_FLD = 47, + CFA_BLD_ACT_MOD_MD_UPDT_TOP_FLD = 48, + CFA_BLD_ACT_MOD_RM_OVLAN_FLD = 49, + CFA_BLD_ACT_MOD_RM_IVLAN_FLD = 50, + CFA_BLD_ACT_MOD_RPL_IVLAN_FLD = 51, + CFA_BLD_ACT_MOD_RPL_OVLAN_FLD = 52, + CFA_BLD_ACT_MOD_TTL_UPDT_OP_FLD = 53, + CFA_BLD_ACT_MOD_TTL_UPDT_ALT_VID_FLD = 54, + CFA_BLD_ACT_MOD_TTL_UPDT_ALT_PFID_FLD = 55, + CFA_BLD_ACT_MOD_TTL_UPDT_TOP_FLD = 56, + CFA_BLD_ACT_MOD_TNL_MODIFY_DEL_FLD = 57, + CFA_BLD_ACT_MOD_TNL_MODIFY_8B_NEW_PROT_FLD = 58, + CFA_BLD_ACT_MOD_TNL_MODIFY_8B_EXIST_PROT_FLD = 59, + CFA_BLD_ACT_MOD_TNL_MODIFY_8B_VEC_FLD = 60, + CFA_BLD_ACT_MOD_TNL_MODIFY_8B_TOP_FLD = 61, + CFA_BLD_ACT_MOD_TNL_MODIFY_16B_NEW_PROT_FLD = 62, + CFA_BLD_ACT_MOD_TNL_MODIFY_16B_EXIST_PROT_FLD = 63, + CFA_BLD_ACT_MOD_TNL_MODIFY_16B_VEC_FLD = 64, + CFA_BLD_ACT_MOD_TNL_MODIFY_16B_TOP_FLD = 65, + CFA_BLD_ACT_MOD_UPDT_FIELD_DATA0_FLD = 66, + CFA_BLD_ACT_MOD_UPDT_FIELD_VEC_RSVD_FLD = 67, + CFA_BLD_ACT_MOD_UPDT_FIELD_VEC_KID_FLD = 68, + CFA_BLD_ACT_MOD_UPDT_FIELD_TOP_FLD = 69, + CFA_BLD_ACT_MOD_SMAC_FLD = 70, + CFA_BLD_ACT_MOD_DMAC_FLD = 71, + CFA_BLD_ACT_MOD_SIPV6_FLD = 72, + CFA_BLD_ACT_MOD_DIPV6_FLD = 73, + CFA_BLD_ACT_MOD_SIPV4_FLD = 74, + CFA_BLD_ACT_MOD_DIPV4_FLD = 75, + CFA_BLD_ACT_MOD_SPORT_FLD = 76, + CFA_BLD_ACT_MOD_DPORT_FLD = 77, + CFA_BLD_ACT_ENC_ECV_TNL_FLD = 78, + CFA_BLD_ACT_ENC_ECV_L4_FLD = 79, + CFA_BLD_ACT_ENC_ECV_L3_FLD = 80, + CFA_BLD_ACT_ENC_ECV_L2_FLD = 81, + CFA_BLD_ACT_ENC_ECV_VTAG_FLD = 82, + CFA_BLD_ACT_ENC_ECV_EC_FLD = 83, + CFA_BLD_ACT_ENC_ECV_VALID_FLD = 84, + CFA_BLD_ACT_ENC_EC_IP_TTL_IH_FLD = 85, + CFA_BLD_ACT_ENC_EC_IP_TOS_IH_FLD = 86, + CFA_BLD_ACT_ENC_EC_TUN_QOS_FLD = 87, + CFA_BLD_ACT_ENC_EC_GRE_SET_K_FLD = 88, + CFA_BLD_ACT_ENC_EC_DMAC_OVR_FLD = 89, + CFA_BLD_ACT_ENC_EC_VLAN_OVR_FLD = 90, + CFA_BLD_ACT_ENC_EC_SMAC_OVR_FLD = 91, + CFA_BLD_ACT_ENC_EC_IPV4_ID_CTRL_FLD = 92, + CFA_BLD_ACT_ENC_L2_DMAC_FLD = 93, + CFA_BLD_ACT_ENC_VLAN1_TAG_VID_FLD = 94, + CFA_BLD_ACT_ENC_VLAN1_TAG_DE_FLD = 95, + CFA_BLD_ACT_ENC_VLAN1_TAG_PRI_FLD = 96, + CFA_BLD_ACT_ENC_VLAN1_TAG_TPID_FLD = 97, + CFA_BLD_ACT_ENC_VLAN2_IT_VID_FLD = 98, + CFA_BLD_ACT_ENC_VLAN2_IT_DE_FLD = 99, + CFA_BLD_ACT_ENC_VLAN2_IT_PRI_FLD = 100, + CFA_BLD_ACT_ENC_VLAN2_IT_TPID_FLD = 101, + CFA_BLD_ACT_ENC_VLAN2_OT_VID_FLD = 102, + CFA_BLD_ACT_ENC_VLAN2_OT_DE_FLD = 103, + CFA_BLD_ACT_ENC_VLAN2_OT_PRI_FLD = 104, + CFA_BLD_ACT_ENC_VLAN2_OT_TPID_FLD = 105, + CFA_BLD_ACT_ENC_IPV4_ID_FLD = 106, + CFA_BLD_ACT_ENC_IPV4_TOS_FLD = 107, + CFA_BLD_ACT_ENC_IPV4_HLEN_FLD = 108, + CFA_BLD_ACT_ENC_IPV4_VER_FLD = 109, + CFA_BLD_ACT_ENC_IPV4_PROT_FLD = 110, + CFA_BLD_ACT_ENC_IPV4_TTL_FLD = 111, + CFA_BLD_ACT_ENC_IPV4_FRAG_FLD = 112, + CFA_BLD_ACT_ENC_IPV4_FLAGS_FLD = 113, + CFA_BLD_ACT_ENC_IPV4_DEST_FLD = 114, + CFA_BLD_ACT_ENC_IPV6_FLOW_LABEL_FLD = 115, + CFA_BLD_ACT_ENC_IPV6_TRAFFIC_CLASS_FLD = 116, + CFA_BLD_ACT_ENC_IPV6_VER_FLD = 117, + CFA_BLD_ACT_ENC_IPV6_HOP_LIMIT_FLD = 118, + CFA_BLD_ACT_ENC_IPV6_NEXT_HEADER_FLD = 119, + CFA_BLD_ACT_ENC_IPV6_PAYLOAD_LENGTH_FLD = 120, + CFA_BLD_ACT_ENC_IPV6_DEST_FLD = 121, + CFA_BLD_ACT_ENC_MPLS_TAG1_FLD = 122, + CFA_BLD_ACT_ENC_MPLS_TAG2_FLD = 123, + CFA_BLD_ACT_ENC_MPLS_TAG3_FLD = 124, + CFA_BLD_ACT_ENC_MPLS_TAG4_FLD = 125, + CFA_BLD_ACT_ENC_MPLS_TAG5_FLD = 126, + CFA_BLD_ACT_ENC_MPLS_TAG6_FLD = 127, + CFA_BLD_ACT_ENC_MPLS_TAG7_FLD = 128, + CFA_BLD_ACT_ENC_MPLS_TAG8_FLD = 129, + CFA_BLD_ACT_ENC_L4_DEST_PORT_FLD = 130, + CFA_BLD_ACT_ENC_L4_SRC_PORT_FLD = 131, + CFA_BLD_ACT_ENC_TNL_VXLAN_NEXT_PROT_FLD = 132, + CFA_BLD_ACT_ENC_TNL_VXLAN_RSVD_0_FLD = 133, + CFA_BLD_ACT_ENC_TNL_VXLAN_FLAGS_FLD = 134, + CFA_BLD_ACT_ENC_TNL_VXLAN_RSVD_1_FLD = 135, + CFA_BLD_ACT_ENC_TNL_VXLAN_VNI_FLD = 136, + CFA_BLD_ACT_ENC_TNL_NGE_PROT_TYPE_FLD = 137, + CFA_BLD_ACT_ENC_TNL_NGE_RSVD_0_FLD = 138, + CFA_BLD_ACT_ENC_TNL_NGE_FLAGS_C_FLD = 139, + CFA_BLD_ACT_ENC_TNL_NGE_FLAGS_O_FLD = 140, + CFA_BLD_ACT_ENC_TNL_NGE_FLAGS_OPT_LEN_FLD = 141, + CFA_BLD_ACT_ENC_TNL_NGE_FLAGS_VER_FLD = 142, + CFA_BLD_ACT_ENC_TNL_NGE_RSVD_1_FLD = 143, + CFA_BLD_ACT_ENC_TNL_NGE_VNI_FLD = 144, + CFA_BLD_ACT_ENC_TNL_NGE_OPTIONS_FLD = 145, + CFA_BLD_ACT_ENC_TNL_NVGRE_FLOW_ID_FLD = 146, + CFA_BLD_ACT_ENC_TNL_NVGRE_VSID_FLD = 147, + CFA_BLD_ACT_ENC_TNL_GRE_KEY_FLD = 148, + CFA_BLD_ACT_ENC_TNL_GENERIC_TID_FLD = 149, + CFA_BLD_ACT_ENC_TNL_GENERIC_LENGTH_FLD = 150, + CFA_BLD_ACT_ENC_TNL_GENERIC_HEADER_FLD = 151, + CFA_BLD_ACT_ENC_SPDNIC_SIZE_FLD = 152, + CFA_BLD_ACT_ENC_SPDNIC_TID_FLD = 153, + CFA_BLD_ACT_ENC_SPDNIC_FLAGS_FLD = 154, + CFA_BLD_ACT_ENC_SPDNIC_RSVD_FLD = 155, + CFA_BLD_ACT_SRC_MAC_FLD = 156, + CFA_BLD_ACT_SRC_IPV4_ADDR_FLD = 157, + CFA_BLD_ACT_SRC_IPV6_ADDR_FLD = 158, + CFA_BLD_ACT_STAT0_B16_FPC_FLD = 159, + CFA_BLD_ACT_STAT1_B16_FPC_FLD = 160, + CFA_BLD_ACT_STAT0_B16_FBC_FLD = 161, + CFA_BLD_ACT_STAT1_B16_FBC_FLD = 162, + CFA_BLD_ACT_STAT0_B24_FPC_FLD = 163, + CFA_BLD_ACT_STAT1_B24_FPC_FLD = 164, + CFA_BLD_ACT_STAT0_B24_FBC_FLD = 165, + CFA_BLD_ACT_STAT1_B24_FBC_FLD = 166, + CFA_BLD_ACT_STAT0_B24_TIMESTAMP_FLD = 167, + CFA_BLD_ACT_STAT1_B24_TIMESTAMP_FLD = 168, + CFA_BLD_ACT_STAT0_B24_TCP_FLAGS_FLD = 169, + CFA_BLD_ACT_STAT1_B24_TCP_FLAGS_FLD = 170, + CFA_BLD_ACT_STAT0_B24_UNUSED_0_FLD = 171, + CFA_BLD_ACT_STAT1_B24_UNUSED_0_FLD = 172, + CFA_BLD_ACT_STAT0_B32A_FPC_FLD = 173, + CFA_BLD_ACT_STAT1_B32A_FPC_FLD = 174, + CFA_BLD_ACT_STAT0_B32A_FBC_FLD = 175, + CFA_BLD_ACT_STAT1_B32A_FBC_FLD = 176, + CFA_BLD_ACT_STAT0_B32A_MPC_FLD = 177, + CFA_BLD_ACT_STAT1_B32A_MPC_FLD = 178, + CFA_BLD_ACT_STAT0_B32A_MBC_FLD = 179, + CFA_BLD_ACT_STAT1_B32A_MBC_FLD = 180, + CFA_BLD_ACT_STAT0_B32B_FPC_FLD = 181, + CFA_BLD_ACT_STAT1_B32B_FPC_FLD = 182, + CFA_BLD_ACT_STAT0_B32B_FBC_FLD = 183, + CFA_BLD_ACT_STAT1_B32B_FBC_FLD = 184, + CFA_BLD_ACT_STAT0_B32B_TIMESTAMP_FLD = 185, + CFA_BLD_ACT_STAT1_B32B_TIMESTAMP_FLD = 186, + CFA_BLD_ACT_STAT0_B32B_TCP_FLAGS_FLD = 187, + CFA_BLD_ACT_STAT1_B32B_TCP_FLAGS_FLD = 188, + CFA_BLD_ACT_STAT0_B32B_UNUSED_0_FLD = 189, + CFA_BLD_ACT_STAT1_B32B_UNUSED_0_FLD = 190, + CFA_BLD_ACT_STAT0_B32B_MPC15_0_FLD = 191, + CFA_BLD_ACT_STAT1_B32B_MPC15_0_FLD = 192, + CFA_BLD_ACT_STAT0_B32B_MPC37_16_FLD = 193, + CFA_BLD_ACT_STAT1_B32B_MPC37_16_FLD = 194, + CFA_BLD_ACT_STAT0_B32B_MBC_FLD = 195, + CFA_BLD_ACT_STAT1_B32B_MBC_FLD = 196, + CFA_BLD_ACTION_MAX_FLD = 197, +}; + +#endif /* _CFA_BLD_FIELD_IDS_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_mpc_field_ids.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_mpc_field_ids.h new file mode 100644 index 0000000000..b546366127 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_mpc_field_ids.h @@ -0,0 +1,1286 @@ +/**************************************************************************** + * Copyright(c) 2001-2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * Name: cfa_bld_mpc_field_ids.h + * + * Description: Enumeration definitions for the MPC command/response fields + * across multiple hw versions of CFA. + * + * This file is independent of the CFA HW version and defines the + * superset of the enumeration values for MPC command/response + * structure fields. This file is meant for use by host applications + * that support multiple devices with different CFA Hw versions. + * + * These enum definitions should be updated whenever any of the + * definitions in the auto-generated header 'cfa_bld_pxx_field_ids.h' + * file gets any new enum values. + * + ****************************************************************************/ +#ifndef _CFA_BLD_MPC_FIELD_IDS_H_ +#define _CFA_BLD_MPC_FIELD_IDS_H_ + +/** + * CFA Hardware Cache Table Type + */ +enum cfa_bld_mpc_hw_table_type { + CFA_BLD_MPC_HW_TABLE_TYPE_ACTION, /**< CFA Action Record Table */ + CFA_BLD_MPC_HW_TABLE_TYPE_LOOKUP, /**< CFA EM Lookup Record Table */ + CFA_BLD_MPC_HW_TABLE_TYPE_MAX +}; + +/* + * CFA MPC Cache access reading mode + * To be used as a value for CFA_BLD_MPC_READ_CMD_CACHE_OPTION_FLD + */ +enum cfa_bld_mpc_read_mode { + CFA_BLD_MPC_RD_NORMAL, /**< Normal read mode */ + CFA_BLD_MPC_RD_EVICT, /**< Read the cache and evict the cache line */ + CFA_BLD_MPC_RD_DEBUG_LINE, /**< Debug read line mode */ + CFA_BLD_MPC_RD_DEBUG_TAG, /**< Debug read tag mode */ + CFA_BLD_MPC_RD_MODE_MAX +}; + +/** + * CFA MPC Cache access writing mode + * To be used as a value for CFA_BLD_MPC_WRITE_CMD_CACHE_OPTION_FLD + */ +enum cfa_bld_mpc_write_mode { + CFA_BLD_MPC_WR_WRITE_THRU, /**< Write to cache in Write through mode */ + CFA_BLD_MPC_WR_WRITE_BACK, /**< Write to cache in Write back mode */ + CFA_BLD_MPC_WR_MODE_MAX +}; + +/** + * CFA MPC Cache access eviction mode + * To be used as a value for CFA_BLD_MPC_INVALIDATE_CMD_CACHE_OPTION_FLD + */ +enum cfa_bld_mpc_evict_mode { + /** + * Line evict: These modes evict a single cache line + * In these modes, the eviction occurs regardless of the cache line + * state (CLEAN/CLEAN_FAST_EVICT/DIRTY) + */ + /* Cache line addressed by set/way is evicted */ + CFA_BLD_MPC_EV_EVICT_LINE, + /* Cache line hit with the table scope/address tuple is evicted */ + CFA_BLD_MPC_EV_EVICT_SCOPE_ADDRESS, + + /** + * Set Evict: These modes evict cache lines that meet certain criteria + * from the entire cache set. + */ + /* + * Cache lines only in CLEAN state are evicted from the set + * derived from the address + */ + CFA_BLD_MPC_EV_EVICT_CLEAN_LINES, + /* + * Cache lines only in CLEAN_FAST_EVICT state are evicted from + * the set derived from the address + */ + CFA_BLD_MPC_EV_EVICT_CLEAN_FAST_EVICT_LINES, + /* + * Cache lines in both CLEAN and CLEAN_FAST_EVICT states are + * evicted from the set derived from the address + */ + CFA_BLD_MPC_EV_EVICT_CLEAN_AND_CLEAN_FAST_EVICT_LINES, + /* + * All Cache lines in the set identified by the address and + * belonging to the table scope are evicted. + */ + CFA_BLD_MPC_EV_EVICT_TABLE_SCOPE, + CFA_BLD_MPC_EV_MODE_MAX, +}; + +/** + * MPC CFA Command completion status + */ +enum cfa_bld_mpc_cmpl_status { + /* Command success */ + CFA_BLD_MPC_OK, + /* Unsupported CFA opcode */ + CFA_BLD_MPC_UNSPRT_ERR, + /* CFA command format error */ + CFA_BLD_MPC_FMT_ERR, + /* SVIF-Table Scope error */ + CFA_BLD_MPC_SCOPE_ERR, + /* Address error: Only used if EM command or TABLE_TYPE=EM */ + CFA_BLD_MPC_ADDR_ERR, + /* Cache operation error */ + CFA_BLD_MPC_CACHE_ERR, + /* EM_SEARCH or EM_DELETE did not find a matching EM entry */ + CFA_BLD_MPC_EM_MISS, + /* EM_INSERT found a matching EM entry and REPLACE=0 in the command */ + CFA_BLD_MPC_EM_DUPLICATE, + /* EM_EVENT_COLLECTION_FAIL no events to return */ + CFA_BLD_MPC_EM_EVENT_COLLECTION_FAIL, + /* + * EM_INSERT required a dynamic bucket to be added to the chain + * to successfully insert the EM entry, but the entry provided + * for use as dynamic bucket was invalid. (bucket_idx == 0) + */ + CFA_BLD_MPC_EM_ABORT, +}; + +/** + * Field IDS for READ_CMD: This command reads 1-4 consecutive 32B words + * from the specified address within a table scope. + */ +enum cfa_bld_mpc_read_cmd_fields { + CFA_BLD_MPC_READ_CMD_OPAQUE_FLD = 0, + /* This value selects the table type to be acted upon. */ + CFA_BLD_MPC_READ_CMD_TABLE_TYPE_FLD = 1, + /* Table scope to access. */ + CFA_BLD_MPC_READ_CMD_TABLE_SCOPE_FLD = 2, + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + CFA_BLD_MPC_READ_CMD_DATA_SIZE_FLD = 3, + /* + * Test field for CFA MPC builder validation, added to introduce + * a hold in the field mapping array + */ + CFA_BLD_MPC_READ_CMD_RANDOM_TEST_FLD = 4, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_BLD_MPC_READ_CMD_CACHE_OPTION_FLD = 5, + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + CFA_BLD_MPC_READ_CMD_TABLE_INDEX_FLD = 6, + /* + * The 64-bit host address to which to write the DMA data returned in + * the completion. The data will be written to the same function as the + * one that owns the SQ this command is read from. DATA_SIZE determines + * the maximum size of the data written. If HOST_ADDRESS[1:0] is not 0, + * CFA aborts processing and reports FMT_ERR status. + */ + CFA_BLD_MPC_READ_CMD_HOST_ADDRESS_FLD = 7, + CFA_BLD_MPC_READ_CMD_MAX_FLD = 8, +}; + +/** + * Field IDS for WRITE_CMD: This command writes 1-4 consecutive 32B + * words to the specified address within a table scope. + */ +enum cfa_bld_mpc_write_cmd_fields { + CFA_BLD_MPC_WRITE_CMD_OPAQUE_FLD = 0, + /* This value selects the table type to be acted upon. */ + CFA_BLD_MPC_WRITE_CMD_TABLE_TYPE_FLD = 1, + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + CFA_BLD_MPC_WRITE_CMD_WRITE_THROUGH_FLD = 2, + /* Table scope to access. */ + CFA_BLD_MPC_WRITE_CMD_TABLE_SCOPE_FLD = 3, + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + CFA_BLD_MPC_WRITE_CMD_DATA_SIZE_FLD = 4, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_BLD_MPC_WRITE_CMD_CACHE_OPTION_FLD = 5, + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + CFA_BLD_MPC_WRITE_CMD_TABLE_INDEX_FLD = 6, + CFA_BLD_MPC_WRITE_CMD_MAX_FLD = 7, +}; + +/** + * Field IDS for READ_CLR_CMD: This command performs a read-modify-write + * to the specified 32B address using a 16b mask that specifies up to 16 + * 16b words to clear before writing the data back. It returns the 32B + * data word read from cache (not the value written after the clear + * operation). + */ +enum cfa_bld_mpc_read_clr_cmd_fields { + CFA_BLD_MPC_READ_CLR_CMD_OPAQUE_FLD = 0, + /* This value selects the table type to be acted upon. */ + CFA_BLD_MPC_READ_CLR_CMD_TABLE_TYPE_FLD = 1, + /* Table scope to access. */ + CFA_BLD_MPC_READ_CLR_CMD_TABLE_SCOPE_FLD = 2, + /* + * This field is no longer used. The READ_CLR command always reads (and + * does a mask-clear) on a single cache line. This field was added for + * SR2 A0 to avoid an ADDR_ERR when TABLE_INDEX=0 and TABLE_TYPE=EM (see + * CUMULUS-17872). That issue was fixed in SR2 B0. + */ + CFA_BLD_MPC_READ_CLR_CMD_DATA_SIZE_FLD = 3, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_BLD_MPC_READ_CLR_CMD_CACHE_OPTION_FLD = 4, + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + CFA_BLD_MPC_READ_CLR_CMD_TABLE_INDEX_FLD = 5, + /* + * The 64-bit host address to which to write the DMA data returned in + * the completion. The data will be written to the same function as the + * one that owns the SQ this command is read from. DATA_SIZE determines + * the maximum size of the data written. If HOST_ADDRESS[1:0] is not 0, + * CFA aborts processing and reports FMT_ERR status. + */ + CFA_BLD_MPC_READ_CLR_CMD_HOST_ADDRESS_FLD = 6, + /* + * Specifies bits in 32B data word to clear. For x=0..15, when + * clear_mask[x]=1, data[x*16+15:x*16] is set to 0. + */ + CFA_BLD_MPC_READ_CLR_CMD_CLEAR_MASK_FLD = 7, + CFA_BLD_MPC_READ_CLR_CMD_MAX_FLD = 8, +}; + +/** + * Field IDS for INVALIDATE_CMD: This command forces an explicit evict + * of 1-4 consecutive cache lines such that the next time the structure + * is used it will be re-read from its backing store location. + */ +enum cfa_bld_mpc_invalidate_cmd_fields { + CFA_BLD_MPC_INVALIDATE_CMD_OPAQUE_FLD = 0, + /* This value selects the table type to be acted upon. */ + CFA_BLD_MPC_INVALIDATE_CMD_TABLE_TYPE_FLD = 1, + /* Table scope to access. */ + CFA_BLD_MPC_INVALIDATE_CMD_TABLE_SCOPE_FLD = 2, + /* + * This value identifies the number of cache lines to invalidate. A + * FMT_ERR is reported if the value is not in the range of [1, 4]. + */ + CFA_BLD_MPC_INVALIDATE_CMD_DATA_SIZE_FLD = 3, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_BLD_MPC_INVALIDATE_CMD_CACHE_OPTION_FLD = 4, + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + CFA_BLD_MPC_INVALIDATE_CMD_TABLE_INDEX_FLD = 5, + CFA_BLD_MPC_INVALIDATE_CMD_MAX_FLD = 6, +}; + +/** + * Field IDS for EM_SEARCH_CMD: This command supplies an exact match + * entry of 1-4 32B words to search for in the exact match table. CFA + * first computes the hash value of the key in the entry, and determines + * the static bucket address to search from the hash and the + * (EM_BUCKETS, EM_SIZE) for TABLE_SCOPE. It then searches that static + * bucket chain for an entry with a matching key (the LREC in the + * command entry is ignored). If a matching entry is found, CFA reports + * OK status in the completion. Otherwise, assuming no errors abort the + * search before it completes, it reports EM_MISS status. + */ +enum cfa_bld_mpc_em_search_cmd_fields { + CFA_BLD_MPC_EM_SEARCH_CMD_OPAQUE_FLD = 0, + /* Table scope to access. */ + CFA_BLD_MPC_EM_SEARCH_CMD_TABLE_SCOPE_FLD = 1, + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + CFA_BLD_MPC_EM_SEARCH_CMD_DATA_SIZE_FLD = 2, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_BLD_MPC_EM_SEARCH_CMD_CACHE_OPTION_FLD = 3, + CFA_BLD_MPC_EM_SEARCH_CMD_MAX_FLD = 4, +}; + +/** + * Field IDS for EM_INSERT_CMD: This command supplies an exact match + * entry of 1-4 32B words to insert in the exact match table. CFA first + * computes the hash value of the key in the entry, and determines the + * static bucket address to search from the hash and the (EM_BUCKETS, + * EM_SIZE) for TABLE_SCOPE. It then writes the 1-4 32B words of the + * exact match entry starting at the TABLE_INDEX location in the + * command. When the entry write completes, it searches the static + * bucket chain for an existing entry with a key matching the key in the + * insert entry (the LREC does not need to match). If a matching entry + * is found: * If REPLACE=0, the CFA aborts the insert and returns + * EM_DUPLICATE status. * If REPLACE=1, the CFA overwrites the matching + * entry with the new entry. REPLACED_ENTRY=1 in the completion in this + * case to signal that an entry was replaced. The location of the entry + * is provided in the completion. If no match is found, CFA adds the new + * entry to the lowest unused entry in the tail bucket. If the current + * tail bucket is full, this requires adding a new bucket to the tail. + * Then entry is then inserted at entry number 0. TABLE_INDEX2 provides + * the address of the new tail bucket, if needed. If set to 0, the + * insert is aborted and returns EM_ABORT status instead of adding a new + * bucket to the tail. CHAIN_UPD in the completion indicates whether a + * new bucket was added (1) or not (0). For locked scopes, if the read + * of the static bucket gives a locked scope miss error, indicating that + * the address is not in the cache, the static bucket is assumed empty. + * In this case, TAI creates a new bucket, setting entry 0 to the new + * entry fields and initializing all other fields to 0. It writes this + * new bucket to the static bucket address, which installs it in the + * cache. + */ +enum cfa_bld_mpc_em_insert_cmd_fields { + CFA_BLD_MPC_EM_INSERT_CMD_OPAQUE_FLD = 0, + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + CFA_BLD_MPC_EM_INSERT_CMD_WRITE_THROUGH_FLD = 1, + /* Table scope to access. */ + CFA_BLD_MPC_EM_INSERT_CMD_TABLE_SCOPE_FLD = 2, + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + CFA_BLD_MPC_EM_INSERT_CMD_DATA_SIZE_FLD = 3, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_BLD_MPC_EM_INSERT_CMD_CACHE_OPTION_FLD = 4, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Starting + * address to write exact match entry being inserted. + */ + CFA_BLD_MPC_EM_INSERT_CMD_TABLE_INDEX_FLD = 5, + /* + * Determines setting of OPTION field for all cache write requests for + * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support + * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0. + */ + CFA_BLD_MPC_EM_INSERT_CMD_CACHE_OPTION2_FLD = 6, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Only used + * when no duplicate entry is found and the tail bucket in the chain + * searched has no unused entries. In this case, TABLE_INDEX2 provides + * the index to the 32B dynamic bucket to add to the tail of the chain + * (it is the new tail bucket). In this case, the CFA first writes + * TABLE_INDEX2 with a new bucket: * Entry 0 of the bucket sets the + * HASH_MSBS computed from the hash and ENTRY_PTR to TABLE_INDEX. * + * Entries 1-5 of the bucket set HASH_MSBS and ENTRY_PTR to 0. * CHAIN=0 + * and CHAIN_PTR is set to CHAIN_PTR from to original tail bucket to + * maintain the background chaining. CFA then sets CHAIN=1 and + * CHAIN_PTR=TABLE_INDEX2 in the original tail bucket to link the new + * bucket to the chain. CHAIN_UPD=1 in the completion to signal that the + * new bucket at TABLE_INDEX2 was added to the tail of the chain. + */ + CFA_BLD_MPC_EM_INSERT_CMD_TABLE_INDEX2_FLD = 7, + /* + * Only used if an entry is found whose key matches the exact match + * entry key in the command: * REPLACE=0: The insert is aborted and + * EM_DUPLICATE status is returned, signaling that the insert failed. + * The index of the matching entry that blocked the insertion is + * returned in the completion. * REPLACE=1: The matching entry is + * replaced with that from the command (ENTRY_PTR in the bucket is + * overwritten with TABLE_INDEX from the command). HASH_MSBS for the + * entry number never changes in this case since it had to match the new + * entry key HASH_MSBS to match. When an entry is replaced, + * REPLACED_ENTRY=1 in the completion and the index of the matching + * entry is returned in the completion so that software can de-allocate + * the entry. + */ + CFA_BLD_MPC_EM_INSERT_CMD_REPLACE_FLD = 8, + CFA_BLD_MPC_EM_INSERT_CMD_MAX_FLD = 9, +}; + +/** + * Field IDS for EM_DELETE_CMD: This command searches for an exact match + * entry index in the static bucket chain and deletes it if found. + * TABLE_INDEX give the entry index to delete and TABLE_INDEX2 gives the + * static bucket index. If a matching entry is found: * If the matching + * entry is the last valid entry in the tail bucket, its entry fields + * (HASH_MSBS and ENTRY_PTR) are set to 0 to delete the entry. * If the + * matching entry is not the last valid entry in the tail bucket, the + * entry fields from that last entry are moved to the matching entry, + * and the fields of that last entry are set to 0. * If any of the + * previous processing results in the tail bucket not having any valid + * entries, the tail bucket is the static bucket, the scope is a locked + * scope, and CHAIN_PTR=0, hardware evicts the static bucket from the + * cache and the completion signals this case with CHAIN_UPD=1. * If any + * of the previous processing results in the tail bucket not having any + * valid entries, and the tail bucket is not the static bucket, the tail + * bucket is removed from the chain. In this case, the penultimate + * bucket in the chain becomes the tail bucket. It has CHAIN set to 0 to + * unlink the tail bucket, and CHAIN_PTR set to that from the original + * tail bucket to preserve background chaining. The completion signals + * this case with CHAIN_UPD=1 and returns the index to the bucket + * removed so that software can de-allocate it. CFA returns OK status if + * the entry was successfully deleted. Otherwise, it returns EM_MISS + * status assuming there were no errors that caused processing to be + * aborted. + */ +enum cfa_bld_mpc_em_delete_cmd_fields { + CFA_BLD_MPC_EM_DELETE_CMD_OPAQUE_FLD = 0, + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + CFA_BLD_MPC_EM_DELETE_CMD_WRITE_THROUGH_FLD = 1, + /* Table scope to access. */ + CFA_BLD_MPC_EM_DELETE_CMD_TABLE_SCOPE_FLD = 2, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_BLD_MPC_EM_DELETE_CMD_CACHE_OPTION_FLD = 3, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Entry index + * to delete. + */ + CFA_BLD_MPC_EM_DELETE_CMD_TABLE_INDEX_FLD = 4, + /* + * Determines setting of OPTION field for all cache write requests for + * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support + * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0. + */ + CFA_BLD_MPC_EM_DELETE_CMD_CACHE_OPTION2_FLD = 5, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Static + * bucket address for bucket chain. + */ + CFA_BLD_MPC_EM_DELETE_CMD_TABLE_INDEX2_FLD = 6, + CFA_BLD_MPC_EM_DELETE_CMD_MAX_FLD = 7, +}; + +/** + * Field IDS for EM_CHAIN_CMD: This command updates CHAIN_PTR in the + * tail bucket of a static bucket chain, supplying both the static + * bucket and the new CHAIN_PTR value. TABLE_INDEX is the new CHAIN_PTR + * value and TABLE_INDEX2[23:0] is the static bucket. This command + * provides software a means to update background chaining coherently + * with other bucket updates. The value of CHAIN is unaffected (stays at + * 0). For locked scopes, if the static bucket is the tail bucket, it is + * empty (all of its ENTRY_PTR values are 0), and TABLE_INDEX=0 (the + * CHAIN_PTR is being set to 0), instead of updating the static bucket + * it is evicted from the cache. In this case, CHAIN_UPD=1 in the + * completion. + */ +enum cfa_bld_mpc_em_chain_cmd_fields { + CFA_BLD_MPC_EM_CHAIN_CMD_OPAQUE_FLD = 0, + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + CFA_BLD_MPC_EM_CHAIN_CMD_WRITE_THROUGH_FLD = 1, + /* Table scope to access. */ + CFA_BLD_MPC_EM_CHAIN_CMD_TABLE_SCOPE_FLD = 2, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_BLD_MPC_EM_CHAIN_CMD_CACHE_OPTION_FLD = 3, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. New + * CHAIN_PTR to write to tail bucket. + */ + CFA_BLD_MPC_EM_CHAIN_CMD_TABLE_INDEX_FLD = 4, + /* + * Determines setting of OPTION field for all cache write requests for + * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support + * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0. + */ + CFA_BLD_MPC_EM_CHAIN_CMD_CACHE_OPTION2_FLD = 5, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Static + * bucket address for bucket chain. + */ + CFA_BLD_MPC_EM_CHAIN_CMD_TABLE_INDEX2_FLD = 6, + CFA_BLD_MPC_EM_CHAIN_CMD_MAX_FLD = 7, +}; + +/** + * Field IDS for READ_CMP: When no errors, teturns 1-4 consecutive 32B + * words from the TABLE_INDEX within the TABLE_SCOPE specified in the + * command, writing them to HOST_ADDRESS from the command. + */ +enum cfa_bld_mpc_read_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_BLD_MPC_READ_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_BLD_MPC_READ_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_BLD_MPC_READ_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_BLD_MPC_READ_CMP_OPCODE_FLD = 3, + /* + * The length of the DMA that accompanies the completion in units of + * DWORDs (32b). Valid values are [0, 128]. A value of zero indicates + * that there is no DMA that accompanies the completion. + */ + CFA_BLD_MPC_READ_CMP_DMA_LENGTH_FLD = 4, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_BLD_MPC_READ_CMP_OPAQUE_FLD = 5, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_READ_CMP_V_FLD = 6, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_BLD_MPC_READ_CMP_HASH_MSB_FLD = 7, + /* TABLE_TYPE from the command. */ + CFA_BLD_MPC_READ_CMP_TABLE_TYPE_FLD = 8, + /* TABLE_SCOPE from the command. */ + CFA_BLD_MPC_READ_CMP_TABLE_SCOPE_FLD = 9, + /* TABLE_INDEX from the command. */ + CFA_BLD_MPC_READ_CMP_TABLE_INDEX_FLD = 10, + CFA_BLD_MPC_READ_CMP_MAX_FLD = 11, +}; + +/** + * Field IDS for WRITE_CMP: Returns status of the write of 1-4 + * consecutive 32B words starting at TABLE_INDEX in the table specified + * by (TABLE_TYPE, TABLE_SCOPE). + */ +enum cfa_bld_mpc_write_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_BLD_MPC_WRITE_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_BLD_MPC_WRITE_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_BLD_MPC_WRITE_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_BLD_MPC_WRITE_CMP_OPCODE_FLD = 3, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_BLD_MPC_WRITE_CMP_OPAQUE_FLD = 4, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_WRITE_CMP_V_FLD = 5, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_BLD_MPC_WRITE_CMP_HASH_MSB_FLD = 6, + /* TABLE_TYPE from the command. */ + CFA_BLD_MPC_WRITE_CMP_TABLE_TYPE_FLD = 7, + /* TABLE_SCOPE from the command. */ + CFA_BLD_MPC_WRITE_CMP_TABLE_SCOPE_FLD = 8, + /* TABLE_INDEX from the command. */ + CFA_BLD_MPC_WRITE_CMP_TABLE_INDEX_FLD = 9, + CFA_BLD_MPC_WRITE_CMP_MAX_FLD = 10, +}; + +/** + * Field IDS for READ_CLR_CMP: When no errors, returns 1 32B word from + * TABLE_INDEX in the table specified by (TABLE_TYPE, TABLE_SCOPE). The + * data returned is the value prior to the clear. + */ +enum cfa_bld_mpc_read_clr_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_BLD_MPC_READ_CLR_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_BLD_MPC_READ_CLR_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_BLD_MPC_READ_CLR_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_BLD_MPC_READ_CLR_CMP_OPCODE_FLD = 3, + /* + * The length of the DMA that accompanies the completion in units of + * DWORDs (32b). Valid values are [0, 128]. A value of zero indicates + * that there is no DMA that accompanies the completion. + */ + CFA_BLD_MPC_READ_CLR_CMP_DMA_LENGTH_FLD = 4, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_BLD_MPC_READ_CLR_CMP_OPAQUE_FLD = 5, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_READ_CLR_CMP_V_FLD = 6, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_BLD_MPC_READ_CLR_CMP_HASH_MSB_FLD = 7, + /* TABLE_TYPE from the command. */ + CFA_BLD_MPC_READ_CLR_CMP_TABLE_TYPE_FLD = 8, + /* TABLE_SCOPE from the command. */ + CFA_BLD_MPC_READ_CLR_CMP_TABLE_SCOPE_FLD = 9, + /* TABLE_INDEX from the command. */ + CFA_BLD_MPC_READ_CLR_CMP_TABLE_INDEX_FLD = 10, + CFA_BLD_MPC_READ_CLR_CMP_MAX_FLD = 11, +}; + +/** + * Field IDS for INVALIDATE_CMP: Returns status for INVALIDATE commands. + */ +enum cfa_bld_mpc_invalidate_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_BLD_MPC_INVALIDATE_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_BLD_MPC_INVALIDATE_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_BLD_MPC_INVALIDATE_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_BLD_MPC_INVALIDATE_CMP_OPCODE_FLD = 3, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_BLD_MPC_INVALIDATE_CMP_OPAQUE_FLD = 4, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_INVALIDATE_CMP_V_FLD = 5, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_BLD_MPC_INVALIDATE_CMP_HASH_MSB_FLD = 6, + /* TABLE_TYPE from the command. */ + CFA_BLD_MPC_INVALIDATE_CMP_TABLE_TYPE_FLD = 7, + /* TABLE_SCOPE from the command. */ + CFA_BLD_MPC_INVALIDATE_CMP_TABLE_SCOPE_FLD = 8, + /* TABLE_INDEX from the command. */ + CFA_BLD_MPC_INVALIDATE_CMP_TABLE_INDEX_FLD = 9, + CFA_BLD_MPC_INVALIDATE_CMP_MAX_FLD = 10, +}; + +/** + * Field IDS for EM_SEARCH_CMP: For OK status, returns the index of the + * matching entry found for the EM key supplied in the command. Returns + * EM_MISS status if no match was found. + */ +enum cfa_bld_mpc_em_search_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_BLD_MPC_EM_SEARCH_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_BLD_MPC_EM_SEARCH_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_BLD_MPC_EM_SEARCH_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_BLD_MPC_EM_SEARCH_CMP_OPCODE_FLD = 3, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_BLD_MPC_EM_SEARCH_CMP_OPAQUE_FLD = 4, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_EM_SEARCH_CMP_V1_FLD = 5, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_BLD_MPC_EM_SEARCH_CMP_HASH_MSB_FLD = 6, + /* TABLE_SCOPE from the command. */ + CFA_BLD_MPC_EM_SEARCH_CMP_TABLE_SCOPE_FLD = 7, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK + * status, gives ENTRY_PTR[25:0] of the matching entry found. Otherwise, + * set to 0. + */ + CFA_BLD_MPC_EM_SEARCH_CMP_TABLE_INDEX_FLD = 8, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. If the hash + * is computed (no errors during initial processing of the command), + * TABLE_INDEX2[23:0] is the static bucket address determined from the + * hash of the exact match entry key in the command and the (EM_SIZE, + * EM_BUCKETS) configuration for TABLE_SCOPE of the command. Bits 25:24 + * in this case are set to 0. For any other status, it is always 0. + */ + CFA_BLD_MPC_EM_SEARCH_CMP_TABLE_INDEX2_FLD = 9, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_EM_SEARCH_CMP_V2_FLD = 10, + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + CFA_BLD_MPC_EM_SEARCH_CMP_BKT_NUM_FLD = 11, + /* See BKT_NUM description. */ + CFA_BLD_MPC_EM_SEARCH_CMP_NUM_ENTRIES_FLD = 12, + CFA_BLD_MPC_EM_SEARCH_CMP_MAX_FLD = 13, +}; + +/** + * Field IDS for EM_INSERT_CMP: OK status indicates that the exact match + * entry from the command was successfully inserted. EM_DUPLICATE status + * indicates that the insert was aborted because an entry with the same + * exact match key was found and REPLACE=0 in the command. EM_ABORT + * status indicates that no duplicate was found, the tail bucket in the + * chain was full, and TABLE_INDEX2=0. No changes are made to the + * database in this case. TABLE_INDEX is the starting address at which + * to insert the exact match entry (from the command). TABLE_INDEX2 is + * the address at which to insert a new bucket at the tail of the static + * bucket chain if needed (from the command). CHAIN_UPD=1 if a new + * bucket was added at this address. TABLE_INDEX3 is the static bucket + * address for the chain, determined from hashing the exact match entry. + * Software needs this address and TABLE_INDEX in order to delete the + * entry using an EM_DELETE command. TABLE_INDEX4 is the index of an + * entry found that had a matching exact match key to the command entry + * key. If no matching entry was found, it is set to 0. There are two + * cases when there is a matching entry, depending on REPLACE from the + * command: * REPLACE=0: EM_DUPLICATE status is reported and the insert + * is aborted. Software can use the static bucket address + * (TABLE_INDEX3[23:0]) and the matching entry (TABLE_INDEX4) in an + * EM_DELETE command if it wishes to explicity delete the matching + * entry. * REPLACE=1: REPLACED_ENTRY=1 to signal that the entry at + * TABLE_INDEX4 was replaced by the insert entry. REPLACED_ENTRY will + * only be 1 if reporting OK status in this case. Software can de- + * allocate the entry at TABLE_INDEX4. + */ +enum cfa_bld_mpc_em_insert_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_BLD_MPC_EM_INSERT_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_BLD_MPC_EM_INSERT_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_BLD_MPC_EM_INSERT_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_BLD_MPC_EM_INSERT_CMP_OPCODE_FLD = 3, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_BLD_MPC_EM_INSERT_CMP_OPAQUE_FLD = 4, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_EM_INSERT_CMP_V1_FLD = 5, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_BLD_MPC_EM_INSERT_CMP_HASH_MSB_FLD = 6, + /* TABLE_SCOPE from the command. */ + CFA_BLD_MPC_EM_INSERT_CMP_TABLE_SCOPE_FLD = 7, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX + * from the command, which is the starting address at which to insert + * the exact match entry. + */ + CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX_FLD = 8, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2 + * from the command, which is the index for the new tail bucket to add + * if needed (CHAIN_UPD=1 if it was used). + */ + CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX2_FLD = 9, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. If the hash + * is computed (no errors during initial processing of the command), + * TABLE_INDEX2[23:0] is the static bucket address determined from the + * hash of the exact match entry key in the command and the (EM_SIZE, + * EM_BUCKETS) configuration for TABLE_SCOPE of the command. Bits 25:24 + * in this case are set to 0. For any other status, it is always 0. + */ + CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX3_FLD = 10, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_EM_INSERT_CMP_V2_FLD = 11, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. ENTRY_PTR of + * matching entry found. Set to 0 if no matching entry found. If + * REPLACED_ENTRY=1, that indicates a matching entry was found and + * REPLACE=1 in the command. In this case, the matching entry was + * replaced by the new entry in the command and this index can therefore + * by de-allocated. + */ + CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX4_FLD = 12, + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + CFA_BLD_MPC_EM_INSERT_CMP_BKT_NUM_FLD = 13, + /* See BKT_NUM description. */ + CFA_BLD_MPC_EM_INSERT_CMP_NUM_ENTRIES_FLD = 14, + /* + * Specifies if the chain was updated while processing the command: Set + * to 1 when a new bucket is added to the tail of the static bucket + * chain at TABLE_INDEX2. This occurs if and only if the insert requires + * adding a new entry and the tail bucket is full. If set to 0, + * TABLE_INDEX2 was not used and is therefore still free. + */ + CFA_BLD_MPC_EM_INSERT_CMP_CHAIN_UPD_FLD = 15, + /* + * Set to 1 if a matching entry was found and REPLACE=1 in command. In + * the case, the entry starting at TABLE_INDEX4 was replaced and can + * therefore be de-allocated. Otherwise, this flag is set to 0. + */ + CFA_BLD_MPC_EM_INSERT_CMP_REPLACED_ENTRY_FLD = 16, + CFA_BLD_MPC_EM_INSERT_CMP_MAX_FLD = 17, +}; + +/** + * Field IDS for EM_DELETE_CMP: OK status indicates that an ENTRY_PTR + * matching TABLE_INDEX was found in the static bucket chain specified + * and was therefore deleted. EM_MISS status indicates that no match was + * found. TABLE_INDEX is from the command. It is the index of the entry + * to delete. TABLE_INDEX2 is from the command. It is the static bucket + * address. TABLE_INDEX3 is the index of the tail bucket of the static + * bucket chain prior to processing the command. TABLE_INDEX4 is the + * index of the tail bucket of the static bucket chain after processing + * the command. If CHAIN_UPD=1 and TABLE_INDEX4==TABLE_INDEX2, the + * static bucket was the tail bucket, it became empty after the delete, + * the scope is a locked scope, and CHAIN_PTR was 0. In this case, the + * static bucket has been evicted from the cache. Otherwise, if + * CHAIN_UPD=1, the original tail bucket given by TABLE_INDEX3 was + * removed from the chain because it went empty. It can therefore be de- + * allocated. + */ +enum cfa_bld_mpc_em_delete_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_BLD_MPC_EM_DELETE_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_BLD_MPC_EM_DELETE_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_BLD_MPC_EM_DELETE_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_BLD_MPC_EM_DELETE_CMP_OPCODE_FLD = 3, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_BLD_MPC_EM_DELETE_CMP_OPAQUE_FLD = 4, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_EM_DELETE_CMP_V1_FLD = 5, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_BLD_MPC_EM_DELETE_CMP_HASH_MSB_FLD = 6, + /* TABLE_SCOPE from the command. */ + CFA_BLD_MPC_EM_DELETE_CMP_TABLE_SCOPE_FLD = 7, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX + * from the command, which is the index of the entry to delete. + */ + CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX_FLD = 8, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2 + * from the command. + */ + CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX2_FLD = 9, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK or + * EM_MISS status, the index of the tail bucket of the chain prior to + * processing the command. If CHAIN_UPD=1, the bucket was removed and + * this index can be de-allocated. For other status values, it is set to + * 0. + */ + CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX3_FLD = 10, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_EM_DELETE_CMP_V2_FLD = 11, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK or + * EM_MISS status, the index of the tail bucket of the chain prior to + * after the command. If CHAIN_UPD=0 (always for EM_MISS status), it is + * always equal to TABLE_INDEX3 as the chain was not updated. For other + * status values, it is set to 0. + */ + CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX4_FLD = 12, + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + CFA_BLD_MPC_EM_DELETE_CMP_BKT_NUM_FLD = 13, + /* See BKT_NUM description. */ + CFA_BLD_MPC_EM_DELETE_CMP_NUM_ENTRIES_FLD = 14, + /* + * Specifies if the chain was updated while processing the command: Set + * to 1 when a bucket is removed from the static bucket chain. This + * occurs if after the delete, the tail bucket is a dynamic bucket and + * no longer has any valid entries. In this case, software should de- + * allocate the dynamic bucket at TABLE_INDEX3. It is also set to 1 when + * the static bucket is evicted, which only occurs for locked scopes. + * See the EM_DELETE command description for details. + */ + CFA_BLD_MPC_EM_DELETE_CMP_CHAIN_UPD_FLD = 15, + CFA_BLD_MPC_EM_DELETE_CMP_MAX_FLD = 16, +}; + +/** + * Field IDS for EM_CHAIN_CMP: OK status indicates that the CHAIN_PTR of + * the tail bucket was successfully updated. TABLE_INDEX is from the + * command. It is the value of the new CHAIN_PTR. TABLE_INDEX2 is from + * the command. TABLE_INDEX3 is the index of the tail bucket of the + * static bucket chain. + */ +enum cfa_bld_mpc_em_chain_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_BLD_MPC_EM_CHAIN_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_BLD_MPC_EM_CHAIN_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_BLD_MPC_EM_CHAIN_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_BLD_MPC_EM_CHAIN_CMP_OPCODE_FLD = 3, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_BLD_MPC_EM_CHAIN_CMP_OPAQUE_FLD = 4, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_EM_CHAIN_CMP_V1_FLD = 5, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_BLD_MPC_EM_CHAIN_CMP_HASH_MSB_FLD = 6, + /* TABLE_SCOPE from the command. */ + CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_SCOPE_FLD = 7, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX + * from the command, which is the new CHAIN_PTR for the tail bucket of + * the static bucket chain. + */ + CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_INDEX_FLD = 8, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2 + * from the command. + */ + CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_INDEX2_FLD = 9, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK + * status, the index of the tail bucket of the chain. Otherwise, set to + * 0. + */ + CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_INDEX3_FLD = 10, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_BLD_MPC_EM_CHAIN_CMP_V2_FLD = 11, + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + CFA_BLD_MPC_EM_CHAIN_CMP_BKT_NUM_FLD = 12, + /* See BKT_NUM description. */ + CFA_BLD_MPC_EM_CHAIN_CMP_NUM_ENTRIES_FLD = 13, + /* + * Set to 1 when the scope is a locked scope, the tail bucket is the + * static bucket, the bucket is empty (all of its ENTRY_PTR values are + * 0), and TABLE_INDEX=0 in the command. In this case, the static bucket + * is evicted. For all other cases, it is set to 0. + */ + CFA_BLD_MPC_EM_CHAIN_CMP_CHAIN_UPD_FLD = 14, + CFA_BLD_MPC_EM_CHAIN_CMP_MAX_FLD = 15, +}; + +#endif /* _CFA_BLD_MPC_FIELD_IDS_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_mpcops.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_mpcops.h new file mode 100644 index 0000000000..5f607e0caa --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/host/cfa_bld_mpcops.h @@ -0,0 +1,598 @@ +/**************************************************************************** + * Copyright(c) 2021 - 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_mpcops.h + * + * @brief CFA Builder MPC ops interface for host applications + */ + +#ifndef _CFA_BLD_MPCOPS_H_ +#define _CFA_BLD_MPCOPS_H_ + +#include +#include "cfa_types.h" + +/** + * CFA HW data object definition + */ +struct cfa_mpc_data_obj { + /** [in] MPC field identifier */ + uint16_t field_id; + /** [in] Value of the HW field */ + uint64_t val; +}; + +struct cfa_bld_mpcops; + +/** + * @addtogroup CFA_BLD CFA Builder Library + * \ingroup CFA_V3 + * @{ + */ + +/** + * CFA MPC ops interface + */ +struct cfa_bld_mpcinfo { + /** [out] CFA MPC Builder operations function pointer table */ + const struct cfa_bld_mpcops *mpcops; +}; + +/** + * @name CFA_BLD_MPC CFA Builder Host MPC OPS API + * CFA builder host specific API used by host CFA application to bind + * to different CFA devices and access device by using MPC OPS. + */ + +/**@{*/ +/** CFA builder MPC bind API + * + * This API retrieves the CFA global MPC configuration. + * + * @param[in] hw_ver + * hardware version of the CFA + * + * @param[out] mpc_info + * CFA MPC interface + * + * @return + * 0 for SUCCESS, negative value for FAILURE + */ +int cfa_bld_mpc_bind(enum cfa_ver hw_ver, struct cfa_bld_mpcinfo *mpc_info); + +/** CFA device specific function hooks for CFA MPC command composition + * and response parsing + * + * The following device hooks can be defined; unless noted otherwise, they are + * optional and can be filled with a null pointer. The pupose of these hooks + * to support CFA device operations for different device variants. + */ +struct cfa_bld_mpcops { + /** Build MPC Cache read command + * + * This API composes the MPC cache read command given the list + * of read parameters specified as an array of cfa_mpc_data_obj objects. + * + * @param[in] cmd + * MPC command buffer to compose the cache read command into. + * + * @param[in,out] cmd_buff_len + * Pointer to command buffer length variable. The caller sets this + * to the size of the 'cmd' buffer in byes. The api updates this to + * the actual size of the composed command. If the buffer length + * passed is not large enough to hold the composed command, an error + * is returned by the api. + * + * @param[in] fields + * Array of CFA data objects indexed by CFA_BLD_MPC_READ_CMD_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_READ_CMD_MAX_FLD. If the caller intends to set a + * specific field in the MPC command, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself (See example + * below). Otherwise set the field_id to INVALID_U16. If the caller + * sets the field_id for a field that is not valid for the device + * an error is returned. + * + * To set the table type to EM: + * fields[CFA_BLD_MPC_READ_CMD_TABLE_TYPE_FLD].field_id = + * CFA_BLD_MPC_READ_CMD_TABLE_TYPE_FLD; + * fields[CFA_BLD_MPC_READ_CMD_TABLE_TYPE_FLD].val = + * CFA_HW_TABLE_LOOKUP; + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_build_cache_read)(uint8_t *cmd, + uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields); + + /** Build MPC Cache Write command + * + * This API composes the MPC cache write command given the list + * of write parameters specified as an array of cfa_mpc_data_obj + * objects. + * + * @param[in] cmd + * MPC command buffer to compose the cache write command into. + * + * @param[in,out] cmd_buff_len + * Pointer to command buffer length variable. The caller sets this + * to the size of the 'cmd' buffer in byes. The api updates this to + * the actual size of the composed command. If the buffer length + * passed is not large enough to hold the composed command, an error + * is returned by the api. + * + * @param[in] data + * Pointer to the data to be written. Note that this data is just + * copied at the right offset into the command buffer. The actual MPC + * write happens when the command is issued over the MPC interface. + * + * @param[in] fields + * Array of CFA data objects indexed by CFA_BLD_MPC_WRITE_CMD_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_WRITE_CMD_MAX_FLD. If the caller intends to set a + * specific field in the MPC command, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise + * set the field_id to INVALID_U16. If the caller sets the field_id for + * a field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_build_cache_write)(uint8_t *cmd, + uint32_t *cmd_buff_len, + const uint8_t *data, + struct cfa_mpc_data_obj *fields); + + /** Build MPC Cache Invalidate (Evict) command + * + * This API composes the MPC cache evict command given the list + * of evict parameters specified as an array of cfa_mpc_data_obj + * objects. + * + * @param[in] cmd + * MPC command buffer to compose the cache evict command into. + * + * @param[in,out] cmd_buff_len + * Pointer to command buffer length variable. The caller sets this + * to the size of the 'cmd' buffer in byes. The api updates this to + * the actual size of the composed command. If the buffer length + * passed is not large enough to hold the composed command, an error + * is returned by the api. + * + * @param[in] fields + * Array of cfa_mpc_data_obj indexed by + * CFA_BLD_MPC_INVALIDATE_CMD_XXX_FLD enum values. The size of this + * array shall be CFA_BLD_MPC_INVALIDATE_CMD_MAX_FLD. If the caller + * intends to set a specific field in the MPC command, the caller + * should set the field_id in cfa_mpc_data_obj to the array index + * itself. Otherwise set the field_id to INVALID_U16. If the caller + * sets the field_id for a field that is not valid for the device an + * error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_build_cache_evict)(uint8_t *cmd, + uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields); + + /** Build MPC Cache read and clear command + * + * This API composes the MPC cache read-n-clear command given the list + * of read parameters specified as an array of cfa_mpc_data_obj objects. + * + * @param[in] cmd + * MPC command buffer to compose the cache read-n-clear command into. + * + * @param[in,out] cmd_buff_len + * Pointer to command buffer length variable. The caller sets this + * to the size of the 'cmd' buffer in byes. The api updates this to + * the actual size of the composed command. If the buffer length + * passed is not large enough to hold the composed command, an error + * is returned by the api. + * + * @param[in] fields + * Array of cfa_mpc_data_obj indexed by + * CFA_BLD_MPC_READ_CLR_CMD_XXX_FLD enum values. The size of this + * array shall be CFA_BLD_MPC_READ_CLR_CMD_MAX_FLD. If the caller + * intends to set a specific field in the MPC command, the caller + * should set the field_id in cfa_mpc_data_obj to the array index + * itself. Otherwise set the field_id to INVALID_U16. If the caller + * sets the field_id for a field that is not valid for the device + * an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_build_cache_read_clr)(uint8_t *cmd, + uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields); + + /** Build MPC EM search command + * + * This API composes the MPC EM search command given the list + * of EM search parameters specified as an array of cfa_mpc_data_obj + * objects + * + * @param[in] cmd + * MPC command buffer to compose the EM search command into. + * + * @param[in,out] cmd_buff_len + * Pointer to command buffer length variable. The caller sets this + * to the size of the 'cmd' buffer in byes. The api updates this to + * the actual size of the composed command. If the buffer length + * passed is not large enough to hold the composed command, an error + * is returned by the api. + * + * @param[in] em_entry + * Pointer to the em_entry to be searched. + * + * @param[in] fields + * Array of cfa_mpc_data_obj indexed by + * CFA_BLD_MPC_EM_SEARCH_CMD_XXX_FLD enum values. The size of this + * array shall be CFA_BLD_MPC_EM_SEARCH_CMD_MAX_FLD. If the caller + * intends to set a specific field in the MPC command, the caller + * should set the field_id in cfa_mpc_data_obj to the array index + * itself. Otherwise set the field_id to INVALID_U16. If the caller + * sets the field_id for a field that is not valid for the device an + * error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_build_em_search)(uint8_t *cmd, uint32_t *cmd_buff_len, + uint8_t *em_entry, + struct cfa_mpc_data_obj *fields); + + /** Build MPC EM insert command + * + * This API composes the MPC EM insert command given the list + * of EM insert parameters specified as an array of cfa_mpc_data_obj objects + * + * @param[in] cmd + * MPC command buffer to compose the EM insert command into. + * + * @param[in,out] cmd_buff_len + * Pointer to command buffer length variable. The caller sets this + * to the size of the 'cmd' buffer in bytes. The api updates this to + * the actual size of the composed command. If the buffer length + * passed is not large enough to hold the composed command, an error + * is returned by the api. + * + * @param[in] em_entry + * Pointer to the em_entry to be inserted. + * + * @param[in] fields + * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_INSERT_CMD_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_EM_INSERT_CMD_MAX_FLD. If the caller intends to set a + * specific field in the MPC command, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_build_em_insert)(uint8_t *cmd, uint32_t *cmd_buff_len, + const uint8_t *em_entry, + struct cfa_mpc_data_obj *fields); + + /** Build MPC EM delete command + * + * This API composes the MPC EM delete command given the list + * of EM delete parameters specified as an array of cfa_mpc_data_obj objects + * + * @param[in] cmd + * MPC command buffer to compose the EM delete command into. + * + * @param[in,out] cmd_buff_len + * Pointer to command buffer length variable. The caller sets this + * to the size of the 'cmd' buffer in byes. The api updates this to + * the actual size of the composed command. If the buffer length + * passed is not large enough to hold the composed command, an error + * is returned by the api. + * + * @param[in] fields + * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_DELETE_CMD_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_EM_DELETE_CMD_MAX_FLD. If the caller intends to set a + * specific field in the MPC command, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_build_em_delete)(uint8_t *cmd, uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields); + + /** Build MPC EM chain command + * + * This API composes the MPC EM chain command given the list + * of EM chain parameters specified as an array of cfa_mpc_data_obj objects + * + * @param[in] cmd + * MPC command buffer to compose the EM chain command into. + * + * @param[in,out] cmd_buff_len + * Pointer to command buffer length variable. The caller sets this + * to the size of the 'cmd' buffer in byes. The api updates this to + * the actual size of the composed command. If the buffer length + * passed is not large enough to hold the composed command, an error + * is returned by the api. + * + * @param[in] fields + * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_CHAIN_CMD_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_EM_CHAIN_CMD_MAX_FLD. If the caller intends to set a + * specific field in the MPC command, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_build_em_chain)(uint8_t *cmd, uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields); + + /** Parse MPC Cache read response + * + * This API parses the MPC cache read response message and returns + * the read parameters as an array of cfa_mpc_data_obj objects. + * + * @param[in] resp + * MPC response buffer containing the cache read response. + * + * @param[in] resp_buff_len + * Response buffer length in bytes + * + * @param[in] rd_data + * Buffer to copy the MPC read data into + * + * @param[in] rd_data_len + * Size of the rd_data buffer in bytes + * + * @param[out] fields + * Array of CFA data objects indexed by CFA_BLD_MPC_READ_CMP_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_READ_CMP_MAX_FLD. If the caller intends to retrieve a + * specific field in the MPC response, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_parse_cache_read)(uint8_t *resp, + uint32_t resp_buff_len, + uint8_t *rd_data, + uint32_t rd_data_len, + struct cfa_mpc_data_obj *fields); + + /** Parse MPC Cache Write response + * + * This API parses the MPC cache write response message and returns + * the write response fields as an array of cfa_mpc_data_obj objects. + * + * @param[in] resp + * MPC response buffer containing the cache write response. + * + * @param[in] resp_buff_len + * Response buffer length in bytes + * + * @param[out] fields + * Array of CFA data objects indexed by CFA_BLD_MPC_WRITE_CMP_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_WRITE_CMP_MAX_FLD. If the caller intends to retrieve a + * specific field in the MPC response, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_parse_cache_write)(uint8_t *resp, + uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields); + + /** Parse MPC Cache Invalidate (Evict) response + * + * This API parses the MPC cache evict response message and returns + * the evict response fields as an array of cfa_mpc_data_obj objects. + * + * @param[in] resp + * MPC response buffer containing the cache evict response. + * + * @param[in] resp_buff_len + * Response buffer length in bytes + * + * @param[out] fields + * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_INVALIDATE_CMP_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_INVALIDATE_CMP_MAX_FLD. If the caller intends to get a + * specific field in the MPC response, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_parse_cache_evict)(uint8_t *resp, + uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields); + + /* clang-format off */ + /** Parse MPC Cache read and clear response + * + * This API parses the MPC cache read-n-clear response message and + * returns the read response fields as an array of cfa_mpc_data_obj objects. + * + * @param[in] resp + * MPC response buffer containing the cache read-n-clear response. + * + * @param[in] resp_buff_len + * Response buffer length in bytes + * + * @param[in] rd_data + * Buffer to copy the MPC read data into + * + * @param[in] rd_data_len + * Size of the rd_data buffer in bytes + * + * @param[out] fields + * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_READ_CLR_CMP_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_READ_CLR_CMP_MAX_FLD. If the caller intends to get a + * specific field in the MPC response, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_parse_cache_read_clr)(uint8_t *resp, + uint32_t resp_buff_len, uint8_t *rd_data, + uint32_t rd_data_len, struct cfa_mpc_data_obj *fields); + + /* clang-format on */ + /** Parse MPC EM search response + * + * This API parses the MPC EM search response message and returns + * the EM search response fields as an array of cfa_mpc_data_obj objects + * + * @param[in] resp + * MPC response buffer containing the EM search response. + * + * @param[in] resp_buff_len + * Response buffer length in bytes + * + * @param[out] fields + * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_SEARCH_CMP_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_EM_SEARCH_CMP_MAX_FLD. If the caller intends to get a + * specific field in the MPC response, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_parse_em_search)(uint8_t *resp, + uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields); + + /** Parse MPC EM insert response + * + * This API parses the MPC EM insert response message and returns + * the EM insert response fields as an array of cfa_mpc_data_obj objects + * + * @param[in] resp + * MPC response buffer containing the EM insert response. + * + * @param[in] resp_buff_len + * Response buffer length in bytes + * + * @param[out] fields + * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_INSERT_CMP_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_EM_INSERT_CMP_MAX_FLD. If the caller intends to get a + * specific field in the MPC response, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_parse_em_insert)(uint8_t *resp, + uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields); + + /** Parse MPC EM delete response + * + * This API parses the MPC EM delete response message and returns + * the EM delete response fields as an array of cfa_mpc_data_obj objects + * + * @param[in] resp + * MPC response buffer containing the EM delete response. + * + * @param[in] resp_buff_len + * Response buffer length in bytes + * + * @param[out] fields + * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_DELETE_CMP_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_EM_DELETE_CMP_MAX_FLD. If the caller intends to get a + * specific field in the MPC response, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_parse_em_delete)(uint8_t *resp, + uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields); + + /** Parse MPC EM chain response + * + * This API parses the MPC EM chain response message and returns + * the EM chain response fields as an array of cfa_mpc_data_obj objects + * + * @param[in] resp + * MPC response buffer containing the EM chain response. + * + * @param[in] resp_buff_len + * Response buffer length in bytes + * + * @param[out] fields + * Array of cfa_mpc_data_obj indexed by CFA_BLD_MPC_EM_CHAIN_CMP_XXX_FLD + * enum values. The size of this array shall be + * CFA_BLD_MPC_EM_CHAIN_CMP_MAX_FLD. If the caller intends to get a + * specific field in the MPC response, the caller should set the + * field_id in cfa_mpc_data_obj to the array index itself. Otherwise set + * the field_id to INVALID_U16. If the caller sets the field_id for a + * field that is not valid for the device an error is returned. + * + * @return + * 0 for SUCCESS, negative errno for FAILURE + * + */ + int (*cfa_bld_mpc_parse_em_chain)(uint8_t *resp, uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields); +}; + +/**@}*/ + +/**@}*/ +#endif /* _CFA_BLD_DEVOPS_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_defs.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_defs.h new file mode 100644 index 0000000000..b2e3cf14f7 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_defs.h @@ -0,0 +1,543 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_p70.h + * + * @brief CFA Phase 7.0 specific Builder public definitions + */ + +#ifndef _CFA_BLD_P70_H_ +#define _CFA_BLD_P70_H_ + +#include "sys_util.h" +#include "cfa_bld_defs.h" +#include "cfa_bld_p70_field_ids.h" + +/** + * Maximum key array size + */ +#define CFA_P70_KEY_MAX_FIELD_CNT \ + MAX((uint16_t)CFA_P70_EM_KEY_LAYOUT_MAX_FLD, \ + (uint16_t)CFA_P70_WC_TCAM_FKB_MAX_FLD) +#define CFA_P70_ACT_MAX_TEMPLATE_SZ sizeof(struct cfa_bld_p70_action_template) + +#define CFA_P70_PROF_MAX_KEYS 4 +enum cfa_p70_mac_sel_mode { + CFA_P70_MAC_SEL_MODE_FIRST = 0, + CFA_P70_MAC_SEL_MODE_LOWEST = 1 +}; + +struct cfa_p70_prof_key_cfg { + uint8_t mac_sel[CFA_P70_PROF_MAX_KEYS]; +#define CFA_PROF_P70_MAC_SEL_DMAC0 (1 << 0) +#define CFA_PROF_P70_MAC_SEL_T_MAC0 (1 << 1) +#define CFA_PROF_P70_MAC_SEL_OUTERMOST_MAC0 (1 << 2) +#define CFA_PROF_P70_MAC_SEL_DMAC1 (1 << 3) +#define CFA_PROF_P70_MAC_SEL_T_MAC1 (1 << 4) +#define CFA_PROF_P70_MAC_OUTERMOST_MAC1 (1 << 5) + uint8_t vlan_sel[CFA_P70_PROF_MAX_KEYS]; +#define CFA_PROF_P70_VLAN_SEL_INNER_HDR 0 +#define CFA_PROF_P70_VLAN_SEL_TUNNEL_HDR 1 +#define CFA_PROF_P70_VLAN_SEL_OUTERMOST_HDR 2 + uint8_t pass_cnt; + enum cfa_p70_mac_sel_mode mode; +}; + +/* + * Field id remap function pointer. Passed by cfa-v3 caller + * to builder apis if the caller requires the apis to remap + * the field ids before using them to update key/action layout + * objects. An example of one such api is action_compute_ptr() + * which updates the offsets for the modify/encap/source/stat + * records in the action record. If the caller is remapping + * the field ids (to save memory in fw builds for example), then + * this remap api is required to be passed. If passed as NULL, + * the field ids are not remapped and used directly to index + * into the layout. + * + * @param Input field id + * + * @return Remapped field id on success, UNIT16_MAX on failure. + */ +typedef uint16_t(cfa_fld_remap)(uint16_t); + +/** + * CFA P70 action layout definition + */ + +enum action_type_p70 { + /** Select this type to build an Full Action Record Object + */ + CFA_P70_ACT_OBJ_TYPE_FULL_ACT, + /** Select this type to build an Compact Action Record Object + */ + CFA_P70_ACT_OBJ_TYPE_COMPACT_ACT, + /** Select this type to build an MCG Action Record Object + */ + CFA_P70_ACT_OBJ_TYPE_MCG_ACT, + /** Select this type to build Standalone Modify Action Record Object */ + CFA_P70_ACT_OBJ_TYPE_MODIFY, + /** Select this type to build Standalone Stat Action Record Object */ + CFA_P70_ACT_OBJ_TYPE_STAT, + /** Select this type to build Standalone Source Action Record Object */ + CFA_P70_ACT_OBJ_TYPE_SRC_PROP, + /** Select this type to build Standalone Encap Action Record Object */ + CFA_P70_ACT_OBJ_TYPE_ENCAP, +}; + +enum stat_op_p70 { + /** Set to statistic to ingress to CFA + */ + CFA_P70_STAT_OP_INGRESS = 0, + /** Set to statistic to egress from CFA + */ + CFA_P70_STAT_OP_EGRESS = 1, +}; + +enum stat_type_p70 { + /** Set to statistic to Foward packet count(64b)/Foward byte + * count(64b) + */ + CFA_P70_STAT_COUNTER_SIZE_16B = 0, + /** Set to statistic to Forward packet count(64b)/Forward byte + * count(64b)/ TCP Flags(16b)/Timestamp(32b) + */ + CFA_P70_STAT_COUNTER_SIZE_24B = 1, + /** Set to statistic to Forward packet count(64b)/Forward byte + * count(64b)/Meter(drop or red) packet count(64b)/Meter(drop + * or red) byte count(64b) + */ + CFA_P70_STAT_COUNTER_SIZE_32B = 2, + /** Set to statistic to Forward packet count(64b)/Forward byte + * count(64b)/Meter(drop or red) packet count(38b)/Meter(drop + * or red) byte count(42b)/TCP Flags(16b)/Timestamp(32b) + */ + CFA_P70_STAT_COUNTER_SIZE_32B_ALL = 3, +}; + +enum encap_vtag_p70 { + CFA_P70_ACT_ENCAP_VTAGS_PUSH_0 = 0, + CFA_P70_ACT_ENCAP_VTAGS_PUSH_1, + CFA_P70_ACT_ENCAP_VTAGS_PUSH_2 +}; + +enum encap_l3_p70 { + /** Set to disable any L3 encapsulation + * processing, default + */ + CFA_P70_ACT_ENCAP_L3_NONE = 0, + /** Set to enable L3 IPv4 encapsulation + */ + CFA_P70_ACT_ENCAP_L3_IPV4 = 4, + /** Set to enable L3 IPv6 encapsulation + */ + CFA_P70_ACT_ENCAP_L3_IPV6 = 5, + /** Set to enable L3 MPLS 8847 encapsulation + */ + CFA_P70_ACT_ENCAP_L3_MPLS_8847 = 6, + /** Set to enable L3 MPLS 8848 encapsulation + */ + CFA_P70_ACT_ENCAP_L3_MPLS_8848 = 7 +}; + +enum encap_tunnel_p70 { + /** Set to disable Tunnel header encapsulation + * processing, default + */ + CFA_P70_ACT_ENCAP_TNL_NONE = 0, + /** Set to enable Tunnel Generic Full header + * encapsulation + */ + CFA_P70_ACT_ENCAP_TNL_GENERIC_FULL, + /** Set to enable VXLAN header encapsulation + */ + CFA_P70_ACT_ENCAP_TNL_VXLAN, + /** Set to enable NGE (VXLAN2) header encapsulation + */ + CFA_P70_ACT_ENCAP_TNL_NGE, + /** Set to enable NVGRE header encapsulation + */ + CFA_P70_ACT_ENCAP_TNL_NVGRE, + /** Set to enable GRE header encapsulation + */ + CFA_P70_ACT_ENCAP_TNL_GRE, + /** Set to enable Generic header after Tunnel + * L4 encapsulation + */ + CFA_P70_ACT_ENCAP_TNL_GENERIC_AFTER_TL4, + /** Set to enable Generic header after Tunnel + * encapsulation + */ + CFA_P70_ACT_ENCAP_TNL_GENERIC_AFTER_TNL +}; + +enum source_rec_type_p70 { + /** Set to Source MAC Address + */ + CFA_P70_SOURCE_MAC = 0, + /** Set to Source MAC and IPv4 Addresses + */ + CFA_P70_SOURCE_MAC_IPV4 = 1, + /** Set to Source MAC and IPv6 Addresses + */ + CFA_P70_SOURCE_MAC_IPV6 = 2, +}; + +/** + * From CFA phase 7.0 onwards, setting the modify vector bit + * 'ACT_MODIFY_TUNNEL_MODIFY' requires corresponding data fields to be + * set. This enum defines the parameters that determine the + * layout of this associated data fields. This structure + * is not used for versions older than CFA Phase 7.0 and setting + * the 'ACT_MODIFY_TUNNEL_MODIFY' bit will just delete the internal tunnel + */ +enum tunnel_modify_mode_p70 { + /* No change to tunnel protocol */ + CFA_P70_ACT_MOD_TNL_NO_PROTO_CHANGE = 0, + /* 8-bit tunnel protocol change */ + CFA_P70_ACT_MOD_TNL_8B_PROTO_CHANGE = 1, + /* 16-bit tunnel protocol change */ + CFA_P70_ACT_MOD_TNL_16B_PROTO_CHANGE = 2, + CFA_P70_ACT_MOD_TNL_MAX +}; + +/** + * Action object template structure + * + * Template structure presents data fields that are necessary to know + * at the beginning of Action Builder (AB) processing. Like before the + * AB compilation. One such example could be a template that is + * flexible in size (Encap Record) and the presence of these fields + * allows for determining the template size as well as where the + * fields are located in the record. + * + * The template may also present fields that are not made visible to + * the caller by way of the action fields. + * + * Template fields also allow for additional checking on user visible + * fields. One such example could be the encap pointer behavior on a + * CFA_P70_ACT_OBJ_TYPE_ACT or CFA_P70_ACT_OBJ_TYPE_ACT_SRAM. + */ +struct cfa_bld_p70_action_template { + /** Action Object type + * + * Controls the type of the Action Template + */ + enum action_type_p70 obj_type; + + /** Action Control + * + * Controls the internals of the Action Template + * + * act is valid when: + * ((obj_type == CFA_P70_ACT_OBJ_TYPE_FULL_ACT) + * || + * (obj_type == CFA_P70_ACT_OBJ_TYPE_COMPACT_ACT)) + * + * Specifies whether each action is to be in-line or not. + */ + struct { + /** Set to true to enable statistics + */ + uint8_t stat_enable; + /** Set to true to enable statistics to be inlined + */ + uint8_t stat_inline; + /** Set to true to enable statistics 1 + */ + uint8_t stat1_enable; + /** Set to true to enable statistics 1 to be inlined + */ + uint8_t stat1_inline; + /** Set to true to enable encapsulation + */ + uint8_t encap_enable; + /** Set to true to enable encapsulation to be inlined + */ + uint8_t encap_inline; + /** Set to true to align the encap record to cache + * line + */ + uint8_t encap_align; + /** Set to true to source + */ + uint8_t source_enable; + /** Set to true to enable source to be inlined + */ + uint8_t source_inline; + /** Set to true to enable modfication + */ + uint8_t mod_enable; + /** Set to true to enable modify to be inlined + */ + uint8_t mod_inline; + /** Set to true to enable subsequent MCGs + */ + uint8_t mcg_subseq_enable; + } act; + + /** Statistic Control + * Controls the type of statistic the template is describing + * + * stat is valid when: + * ((obj_type == CFA_P70_ACT_OBJ_TYPE_FULL_ACT) || + * (obj_type == CFA_P70_ACT_OBJ_TYPE_COMPACT_ACT)) && + * act.stat_enable || act.stat_inline) + */ + struct { + enum stat_op_p70 op; + enum stat_type_p70 type; + } stat; + + /** Encap Control + * Controls the type of encapsulation the template is + * describing + * + * encap is valid when: + * ((obj_type == CFA_P70_ACT_OBJ_TYPE_FULL_ACT) || + * (obj_type == CFA_P70_ACT_OBJ_TYPE_COMPACT_ACT) && + * act.encap_enable || act.encap_inline) + */ + struct { + /** Set to true to enable L2 capability in the + * template + */ + uint8_t l2_enable; + /** vtag controls the Encap Vector - VTAG Encoding, 4 bits + * + *
    + *
  • CFA_P70_ACT_ENCAP_VTAGS_PUSH_0, default, no VLAN + * Tags applied + *
  • CFA_P70_ACT_ENCAP_VTAGS_PUSH_1, adds capability to + * set 1 VLAN Tag. Action Template compile adds + * the following field to the action object + * TF_ER_VLAN1 + *
  • CFA_P70_ACT_ENCAP_VTAGS_PUSH_2, adds capability to + * set 2 VLAN Tags. Action Template compile adds + * the following fields to the action object + * TF_ER_VLAN1 and TF_ER_VLAN2 + *
+ */ + enum encap_vtag_p70 vtag; + + /* + * The remaining fields are NOT supported when + * direction is RX and ((obj_type == + * CFA_P70_ACT_OBJ_TYPE_ACT) && act.encap_enable). + * cfa_bld_p70_action_compile_layout will perform the + * checking and skip remaining fields. + */ + /** L3 Encap controls the Encap Vector - L3 Encoding, + * 3 bits. Defines the type of L3 Encapsulation the + * template is describing. + *
    + *
  • CFA_P70_ACT_ENCAP_L3_NONE, default, no L3 + * Encapsulation processing. + *
  • CFA_P70_ACT_ENCAP_L3_IPV4, enables L3 IPv4 + * Encapsulation. + *
  • CFA_P70_ACT_ENCAP_L3_IPV6, enables L3 IPv6 + * Encapsulation. + *
  • CFA_P70_ACT_ENCAP_L3_MPLS_8847, enables L3 MPLS + * 8847 Encapsulation. + *
  • CFA_P70_ACT_ENCAP_L3_MPLS_8848, enables L3 MPLS + * 8848 Encapsulation. + *
+ */ + enum encap_l3_p70 l3; + +#define CFA_P70_ACT_ENCAP_MAX_MPLS_LABELS 8 + /** 1-8 labels, valid when + * (l3 == CFA_P70_ACT_ENCAP_L3_MPLS_8847) || + * (l3 == CFA_P70_ACT_ENCAP_L3_MPLS_8848) + * + * MAX number of MPLS Labels 8. + */ + uint8_t l3_num_mpls_labels; + + /** Set to true to enable L4 capability in the + * template. + * + * true adds TF_EN_UDP_SRC_PORT and + * TF_EN_UDP_DST_PORT to the template. + */ + uint8_t l4_enable; + + /** Tunnel Encap controls the Encap Vector - Tunnel + * Encap, 3 bits. Defines the type of Tunnel + * encapsulation the template is describing + *
    + *
  • CFA_P70_ACT_ENCAP_TNL_NONE, default, no Tunnel + * Encapsulation processing. + *
  • CFA_P70_ACT_ENCAP_TNL_GENERIC_FULL + *
  • CFA_P70_ACT_ENCAP_TNL_VXLAN. NOTE: Expects + * l4_enable set to true; + *
  • CFA_P70_ACT_ENCAP_TNL_NGE. NOTE: Expects l4_enable + * set to true; + *
  • CFA_P70_ACT_ENCAP_TNL_NVGRE. NOTE: only valid if + * l4_enable set to false. + *
  • CFA_P70_ACT_ENCAP_TNL_GRE.NOTE: only valid if + * l4_enable set to false. + *
  • CFA_P70_ACT_ENCAP_TNL_GENERIC_AFTER_TL4 + *
  • CFA_P70_ACT_ENCAP_TNL_GENERIC_AFTER_TNL + *
+ */ + enum encap_tunnel_p70 tnl; + +#define CFA_P70_ACT_ENCAP_MAX_TUNNEL_GENERIC_SIZE 128 + /** Number of bytes of generic tunnel header, + * valid when + * (tnl == CFA_P70_ACT_ENCAP_TNL_GENERIC_FULL) || + * (tnl == CFA_P70_ACT_ENCAP_TNL_GENERIC_AFTER_TL4) || + * (tnl == CFA_P70_ACT_ENCAP_TNL_GENERIC_AFTER_TNL) + */ + uint8_t tnl_generic_size; + +#define CFA_P70_ACT_ENCAP_MAX_OPLEN 15 + /** Number of 32b words of nge options, + * valid when + * (tnl == CFA_P70_ACT_ENCAP_TNL_NGE) + */ + uint8_t tnl_nge_op_len; + + /** Set to true to enable MAC/VLAN/IP/TNL overrides in the + * template + */ + bool encap_override; + /* Currently not planned */ + /* Custom Header */ + /* uint8_t custom_enable; */ + } encap; + + /** Modify Control + * + * Controls the type of the Modify Action the template is + * describing + * + * modify is valid when: + * ((obj_type == CFA_P70_ACT_OBJ_TYPE_FULL_ACT) || + * (obj_type == CFA_P70_ACT_OBJ_TYPE_COMPACT_ACT) && + * act.modify_enable || act.modify_inline) + */ +/** Set to enable Modify of Metadata + */ +#define CFA_P70_ACT_MODIFY_META 0x1 +/** Set to enable Delete of Outer VLAN + */ +#define CFA_P70_ACT_MODIFY_DEL_OVLAN 0x2 +/** Set to enable Delete of Inner VLAN + */ +#define CFA_P70_ACT_MODIFY_DEL_IVLAN 0x4 +/** Set to enable Replace or Add of Outer VLAN + */ +#define CFA_P70_ACT_MODIFY_REPL_ADD_OVLAN 0x8 +/** Set to enable Replace or Add of Inner VLAN + */ +#define CFA_P70_ACT_MODIFY_REPL_ADD_IVLAN 0x10 +/** Set to enable Modify of TTL + */ +#define CFA_P70_ACT_MODIFY_TTL_UPDATE 0x20 +/** Set to enable delete of INT Tunnel + */ +#define CFA_P70_ACT_MODIFY_DEL_INT_TNL 0x40 +/** For phase 7.0 this bit can be used to modify the + * tunnel protocol in addition to deleting internal + * or outer tunnel + */ +#define CFA_P70_ACT_MODIFY_TUNNEL_MODIFY CFA_P70_ACT_MODIFY_DEL_INT_TNL +/** Set to enable Modify of Field + */ +#define CFA_P70_ACT_MODIFY_FIELD 0x80 +/** Set to enable Modify of Destination MAC + */ +#define CFA_P70_ACT_MODIFY_DMAC 0x100 +/** Set to enable Modify of Source MAC + */ +#define CFA_P70_ACT_MODIFY_SMAC 0x200 +/** Set to enable Modify of Source IPv6 Address + */ +#define CFA_P70_ACT_MODIFY_SRC_IPV6 0x400 +/** Set to enable Modify of Destination IPv6 Address + */ +#define CFA_P70_ACT_MODIFY_DST_IPV6 0x800 +/** Set to enable Modify of Source IPv4 Address + */ +#define CFA_P70_ACT_MODIFY_SRC_IPV4 0x1000 +/** Set to enable Modify of Destination IPv4 Address + */ +#define CFA_P70_ACT_MODIFY_DST_IPV4 0x2000 +/** Set to enable Modify of L4 Source Port + */ +#define CFA_P70_ACT_MODIFY_SRC_PORT 0x4000 +/** Set to enable Modify of L4 Destination Port + */ +#define CFA_P70_ACT_MODIFY_DST_PORT 0x8000 + uint16_t modify; + +/** Set to enable Modify of KID + */ +#define CFA_P70_ACT_MODIFY_FIELD_KID 0x1 + uint16_t field_modify; + + /* Valid for phase 7.0 or higher */ + enum tunnel_modify_mode_p70 tnl_mod_mode; + + /** Source Control + * + * Controls the type of the Source Action the template is + * describing + * + * source is valid when: + * ((obj_type == CFA_P70_ACT_OBJ_TYPE_FULL_ACT) || + * (obj_type == CFA_P70_ACT_OBJ_TYPE_COMPACT_ACT) && + * act.source_enable || act.source_inline) + */ + enum source_rec_type_p70 source; +}; + +/** + * Key template consists of key fields that can be enabled/disabled + * individually. + */ +struct cfa_p70_key_template { + /** [in] Identify if the key template is for TCAM. If false, the + * key template is for EM. This field is mandantory for device that + * only support fix key formats. + */ + bool is_wc_tcam_key; + /** [in] Identify if the key template will be use for IPv6 Keys. + * + * Note: This is important for SR2 as the field length for the Flow Id + * is dependent on the L3 flow type. For SR2 for IPv4 Keys, the Flow + * Id field is 16 bits, for all other types (IPv6, ARP, PTP, EAP, RoCE, + * FCoE, UPAR), the Flow Id field length is 20 bits. + */ + bool is_ipv6_key; + /** [in] key field enable field array, set 1 to the correspeonding + * field enable to make a field valid + */ + uint8_t field_en[CFA_P70_KEY_MAX_FIELD_CNT]; +}; + +/** + * Action template consists of action fields that can be enabled/disabled + * individually. + */ +struct cfa_p70_action_template { + /** [in] CFA version for the action template */ + enum cfa_ver hw_ver; + /** [in] action field enable field array, set 1 to the correspeonding + * field enable to make a field valid + */ + uint8_t data[CFA_P70_ACT_MAX_TEMPLATE_SZ]; +}; + +#define CFA_PROF_L2CTXT_TCAM_MAX_FIELD_CNT CFA_P70_PROF_L2_CTXT_TCAM_MAX_FLD +#define CFA_PROF_L2CTXT_REMAP_MAX_FIELD_CNT CFA_P70_PROF_L2_CTXT_RMP_DR_MAX_FLD +#define CFA_PROF_MAX_KEY_CFG_SZ sizeof(struct cfa_p70_prof_key_cfg) + +#endif /* _CFA_BLD_P70_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_field_ids.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_field_ids.h new file mode 100644 index 0000000000..8fd04f6cf9 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_field_ids.h @@ -0,0 +1,1542 @@ +/**************************************************************************** + * Copyright(c) 2001-2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * Name: cfa_bld_p70_field_ids.h + * + * Description: Enumerations definitions for CFA phase 7.0 HW table fields + * Action record fields and Lookup Key (EM/WC-TCAM) fields. + * + * Date: 09/29/22 11:50:37 + * + * Note: This file is scripted generated by ./cfa_header_gen.py. + * DO NOT modify this file manually !!!! + * + ****************************************************************************/ +#ifndef _CFA_BLD_P70_FIELD_IDS_H_ +#define _CFA_BLD_P70_FIELD_IDS_H_ + +/* clang-format off */ + +/** + * Lookup Field Range Check Range Memory Fields: + */ +enum cfa_p70_lkup_frc_profile_flds { + CFA_P70_LKUP_FRC_PROFILE_FIELD_SEL_1_FLD = 0, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_1_FLD = 1, + CFA_P70_LKUP_FRC_PROFILE_FIELD_SEL_0_FLD = 2, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_FLD = 3, + CFA_P70_LKUP_FRC_PROFILE_MAX_FLD +}; + +/** + * Lookup Connection Tracking State Memory Fields: + */ +enum cfa_p70_lkup_ct_state_flds { + CFA_P70_LKUP_CT_STATE_NOTIFY_FLD = 0, + CFA_P70_LKUP_CT_STATE_NOTIFY_STATE_FLD = 1, + CFA_P70_LKUP_CT_STATE_ACTION_FLD = 2, + CFA_P70_LKUP_CT_STATE_TIMER_SELECT_FLD = 3, + CFA_P70_LKUP_CT_STATE_TIMER_PRELOAD_FLD = 4, + CFA_P70_LKUP_CT_STATE_MAX_FLD +}; + +/** + * Lookup Connection Tracking State Machine Rule Memory Fields: + */ +enum cfa_p70_lkup_ct_rule_flds { + CFA_P70_LKUP_CT_RULE_VALID_FLD = 0, + CFA_P70_LKUP_CT_RULE_MASK_FLD = 1, + CFA_P70_LKUP_CT_RULE_PKT_NOT_BG_FLD = 2, + CFA_P70_LKUP_CT_RULE_STATE_FLD = 3, + CFA_P70_LKUP_CT_RULE_TCP_FLAGS_FLD = 4, + CFA_P70_LKUP_CT_RULE_PROT_IS_TCP_FLD = 5, + CFA_P70_LKUP_CT_RULE_MSB_UPDT_FLD = 6, + CFA_P70_LKUP_CT_RULE_FLAGS_FAILED_FLD = 7, + CFA_P70_LKUP_CT_RULE_WIN_FAILED_FLD = 8, + CFA_P70_LKUP_CT_RULE_MAX_FLD +}; + +/** + * Lookup Connection Tracking State Machine Rule Record Memory Fields: + */ +enum cfa_p70_lkup_ct_rule_record_flds { + CFA_P70_LKUP_CT_RULE_RECORD_ACTION_FLD = 0, + CFA_P70_LKUP_CT_RULE_RECORD_NEXT_STATE_FLD = 1, + CFA_P70_LKUP_CT_RULE_RECORD_SEND_FLD = 2, + CFA_P70_LKUP_CT_RULE_RECORD_MAX_FLD +}; + +/** + * VEB Destination Bitmap Remap Table. Fields: + */ +enum cfa_p70_act_veb_rmp_flds { + CFA_P70_ACT_VEB_RMP_MODE_FLD = 0, + CFA_P70_ACT_VEB_RMP_ENABLE_FLD = 1, + CFA_P70_ACT_VEB_RMP_BITMAP_FLD = 2, + CFA_P70_ACT_VEB_RMP_MAX_FLD +}; + +/** + * Lookup Field Range Check Range Memory Fields: + */ +enum cfa_p70_lkup_frc_range_flds { + CFA_P70_LKUP_FRC_RANGE_RANGE_LO_FLD = 0, + CFA_P70_LKUP_FRC_RANGE_RANGE_HI_FLD = 1, + CFA_P70_LKUP_FRC_RANGE_MAX_FLD +}; + +/** + * L2 Context TCAM. Fields: + */ +enum cfa_p70_prof_l2_ctxt_tcam_flds { + CFA_P70_PROF_L2_CTXT_TCAM_VALID_FLD = 0, + CFA_P70_PROF_L2_CTXT_TCAM_SPARE_FLD = 1, + CFA_P70_PROF_L2_CTXT_TCAM_MPASS_CNT_FLD = 2, + CFA_P70_PROF_L2_CTXT_TCAM_RCYC_FLD = 3, + CFA_P70_PROF_L2_CTXT_TCAM_LOOPBACK_FLD = 4, + CFA_P70_PROF_L2_CTXT_TCAM_SPIF_FLD = 5, + CFA_P70_PROF_L2_CTXT_TCAM_PARIF_FLD = 6, + CFA_P70_PROF_L2_CTXT_TCAM_SVIF_FLD = 7, + CFA_P70_PROF_L2_CTXT_TCAM_METADATA_FLD = 8, + CFA_P70_PROF_L2_CTXT_TCAM_L2_FUNC_FLD = 9, + CFA_P70_PROF_L2_CTXT_TCAM_ROCE_FLD = 10, + CFA_P70_PROF_L2_CTXT_TCAM_PURE_LLC_FLD = 11, + CFA_P70_PROF_L2_CTXT_TCAM_OT_HDR_TYPE_FLD = 12, + CFA_P70_PROF_L2_CTXT_TCAM_T_HDR_TYPE_FLD = 13, + CFA_P70_PROF_L2_CTXT_TCAM_ID_CTXT_FLD = 14, + CFA_P70_PROF_L2_CTXT_TCAM_MAC0_FLD = 15, + CFA_P70_PROF_L2_CTXT_TCAM_MAC1_FLD = 16, + CFA_P70_PROF_L2_CTXT_TCAM_VTAG_PRESENT_FLD = 17, + CFA_P70_PROF_L2_CTXT_TCAM_TWO_VTAGS_FLD = 18, + CFA_P70_PROF_L2_CTXT_TCAM_OVLAN_VID_FLD = 19, + CFA_P70_PROF_L2_CTXT_TCAM_OVLAN_TPID_SEL_FLD = 20, + CFA_P70_PROF_L2_CTXT_TCAM_IVLAN_VID_FLD = 21, + CFA_P70_PROF_L2_CTXT_TCAM_IVLAN_TPID_SEL_FLD = 22, + CFA_P70_PROF_L2_CTXT_TCAM_ETYPE_FLD = 23, + CFA_P70_PROF_L2_CTXT_TCAM_MAX_FLD +}; + +/** + * Profiler Profile Lookup TCAM Fields: + */ +enum cfa_p70_prof_profile_tcam_flds { + CFA_P70_PROF_PROFILE_TCAM_VALID_FLD = 0, + CFA_P70_PROF_PROFILE_TCAM_SPARE_FLD = 1, + CFA_P70_PROF_PROFILE_TCAM_LOOPBACK_FLD = 2, + CFA_P70_PROF_PROFILE_TCAM_PKT_TYPE_FLD = 3, + CFA_P70_PROF_PROFILE_TCAM_RCYC_FLD = 4, + CFA_P70_PROF_PROFILE_TCAM_METADATA_FLD = 5, + CFA_P70_PROF_PROFILE_TCAM_AGG_ERROR_FLD = 6, + CFA_P70_PROF_PROFILE_TCAM_L2_FUNC_FLD = 7, + CFA_P70_PROF_PROFILE_TCAM_PROF_FUNC_FLD = 8, + CFA_P70_PROF_PROFILE_TCAM_HREC_NEXT_FLD = 9, + CFA_P70_PROF_PROFILE_TCAM_INT_HDR_TYPE_FLD = 10, + CFA_P70_PROF_PROFILE_TCAM_INT_HDR_GROUP_FLD = 11, + CFA_P70_PROF_PROFILE_TCAM_INT_IFA_TAIL_FLD = 12, + CFA_P70_PROF_PROFILE_TCAM_OTL2_HDR_VALID_FLD = 13, + CFA_P70_PROF_PROFILE_TCAM_OTL2_HDR_TYPE_FLD = 14, + CFA_P70_PROF_PROFILE_TCAM_OTL2_UC_MC_BC_FLD = 15, + CFA_P70_PROF_PROFILE_TCAM_OTL2_VTAG_PRESENT_FLD = 16, + CFA_P70_PROF_PROFILE_TCAM_OTL2_TWO_VTAGS_FLD = 17, + CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_VALID_FLD = 18, + CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_ERROR_FLD = 19, + CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_TYPE_FLD = 20, + CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_ISIP_FLD = 21, + CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_VALID_FLD = 22, + CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_ERROR_FLD = 23, + CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_TYPE_FLD = 24, + CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_IS_UDP_TCP_FLD = 25, + CFA_P70_PROF_PROFILE_TCAM_OT_HDR_VALID_FLD = 26, + CFA_P70_PROF_PROFILE_TCAM_OT_HDR_ERROR_FLD = 27, + CFA_P70_PROF_PROFILE_TCAM_OT_HDR_TYPE_FLD = 28, + CFA_P70_PROF_PROFILE_TCAM_OT_HDR_FLAGS_FLD = 29, + CFA_P70_PROF_PROFILE_TCAM_TL2_HDR_VALID_FLD = 30, + CFA_P70_PROF_PROFILE_TCAM_TL2_HDR_TYPE_FLD = 31, + CFA_P70_PROF_PROFILE_TCAM_TL2_UC_MC_BC_FLD = 32, + CFA_P70_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_FLD = 33, + CFA_P70_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_FLD = 34, + CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_VALID_FLD = 35, + CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_ERROR_FLD = 36, + CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_TYPE_FLD = 37, + CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_ISIP_FLD = 38, + CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_VALID_FLD = 39, + CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_ERROR_FLD = 40, + CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_TYPE_FLD = 41, + CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_FLD = 42, + CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_VALID_FLD = 43, + CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_ERROR_FLD = 44, + CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_TYPE_FLD = 45, + CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_FLD = 46, + CFA_P70_PROF_PROFILE_TCAM_L2_HDR_VALID_FLD = 47, + CFA_P70_PROF_PROFILE_TCAM_L2_HDR_ERROR_FLD = 48, + CFA_P70_PROF_PROFILE_TCAM_L2_HDR_TYPE_FLD = 49, + CFA_P70_PROF_PROFILE_TCAM_L2_UC_MC_BC_FLD = 50, + CFA_P70_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_FLD = 51, + CFA_P70_PROF_PROFILE_TCAM_L2_TWO_VTAGS_FLD = 52, + CFA_P70_PROF_PROFILE_TCAM_L3_HDR_VALID_FLD = 53, + CFA_P70_PROF_PROFILE_TCAM_L3_HDR_ERROR_FLD = 54, + CFA_P70_PROF_PROFILE_TCAM_L3_HDR_TYPE_FLD = 55, + CFA_P70_PROF_PROFILE_TCAM_L3_HDR_ISIP_FLD = 56, + CFA_P70_PROF_PROFILE_TCAM_L3_PROT_FLD = 57, + CFA_P70_PROF_PROFILE_TCAM_L4_HDR_VALID_FLD = 58, + CFA_P70_PROF_PROFILE_TCAM_L4_HDR_ERROR_FLD = 59, + CFA_P70_PROF_PROFILE_TCAM_L4_HDR_TYPE_FLD = 60, + CFA_P70_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_FLD = 61, + CFA_P70_PROF_PROFILE_TCAM_L4_HDR_SUBTYPE_FLD = 62, + CFA_P70_PROF_PROFILE_TCAM_L4_HDR_FLAGS_FLD = 63, + CFA_P70_PROF_PROFILE_TCAM_L4_DCN_PRESENT_FLD = 64, + CFA_P70_PROF_PROFILE_TCAM_MAX_FLD +}; + +/** + * Action VEB TCAM. TX Fields (VEB Remap Mode): + */ +enum cfa_p70_act_veb_tcam_tx_flds { + CFA_P70_ACT_VEB_TCAM_TX_VALID_FLD = 0, + CFA_P70_ACT_VEB_TCAM_TX_PARIF_IN_FLD = 1, + CFA_P70_ACT_VEB_TCAM_TX_NUM_VTAGS_FLD = 2, + CFA_P70_ACT_VEB_TCAM_TX_DMAC_FLD = 3, + CFA_P70_ACT_VEB_TCAM_TX_OVID_FLD = 4, + CFA_P70_ACT_VEB_TCAM_TX_IVID_FLD = 5, + CFA_P70_ACT_VEB_TCAM_TX_MAX_FLD +}; + +/** + * RX Fields (Source Knockout Mode): + */ +enum cfa_p70_act_veb_tcam_rx_flds { + CFA_P70_ACT_VEB_TCAM_RX_VALID_FLD = 0, + CFA_P70_ACT_VEB_TCAM_RX_SPARE_FLD = 1, + CFA_P70_ACT_VEB_TCAM_RX_PADDING_FLD = 2, + CFA_P70_ACT_VEB_TCAM_RX_UNICAST_FLD = 3, + CFA_P70_ACT_VEB_TCAM_RX_MULTICAST_FLD = 4, + CFA_P70_ACT_VEB_TCAM_RX_BROADCAST_FLD = 5, + CFA_P70_ACT_VEB_TCAM_RX_PFID_FLD = 6, + CFA_P70_ACT_VEB_TCAM_RX_VFID_FLD = 7, + CFA_P70_ACT_VEB_TCAM_RX_SMAC_FLD = 8, + CFA_P70_ACT_VEB_TCAM_RX_MAX_FLD +}; + +/** + * Action Feature Chaining TCAM. + */ +enum cfa_p70_act_fc_tcam_flds { + CFA_P70_ACT_FC_TCAM_FC_VALID_FLD = 0, + CFA_P70_ACT_FC_TCAM_FC_RSVD_FLD = 1, + CFA_P70_ACT_FC_TCAM_FC_METADATA_FLD = 2, + CFA_P70_ACT_FC_TCAM_MAX_FLD +}; + +/** + * Feature Chaining TCAM Remap Table Fields: + */ +enum cfa_p70_act_fc_rmp_dr_flds { + CFA_P70_ACT_FC_RMP_DR_METADATA_FLD = 0, + CFA_P70_ACT_FC_RMP_DR_METAMASK_FLD = 1, + CFA_P70_ACT_FC_RMP_DR_L2_FUNC_FLD = 2, + CFA_P70_ACT_FC_RMP_DR_MAX_FLD +}; + +/** + * Profile Input Lookup Table Memory Fields: + */ +enum cfa_p70_prof_ilt_dr_flds { + CFA_P70_PROF_ILT_DR_ILT_META_EN_FLD = 0, + CFA_P70_PROF_ILT_DR_META_PROF_FLD = 1, + CFA_P70_PROF_ILT_DR_METADATA_FLD = 2, + CFA_P70_PROF_ILT_DR_PARIF_FLD = 3, + CFA_P70_PROF_ILT_DR_L2_FUNC_FLD = 4, + CFA_P70_PROF_ILT_DR_EN_BD_META_FLD = 5, + CFA_P70_PROF_ILT_DR_EN_BD_ACTION_FLD = 6, + CFA_P70_PROF_ILT_DR_EN_ILT_DEST_FLD = 7, + CFA_P70_PROF_ILT_DR_ILT_FWD_OP_FLD = 8, + CFA_P70_PROF_ILT_DR_ILT_ACT_HINT_FLD = 9, + CFA_P70_PROF_ILT_DR_ILT_SCOPE_FLD = 10, + CFA_P70_PROF_ILT_DR_ILT_ACT_REC_PTR_FLD = 11, + CFA_P70_PROF_ILT_DR_ILT_DESTINATION_FLD = 12, + CFA_P70_PROF_ILT_DR_MAX_FLD +}; + +/** + * Profile Lookup TCAM Remap Table Fields: + */ +enum cfa_p70_prof_profile_rmp_dr_flds { + CFA_P70_PROF_PROFILE_RMP_DR_PL_BYP_LKUP_EN_FLD = 0, + CFA_P70_PROF_PROFILE_RMP_DR_EM_SEARCH_EN_FLD = 1, + CFA_P70_PROF_PROFILE_RMP_DR_EM_PROFILE_ID_FLD = 2, + CFA_P70_PROF_PROFILE_RMP_DR_EM_KEY_ID_FLD = 3, + CFA_P70_PROF_PROFILE_RMP_DR_EM_SCOPE_FLD = 4, + CFA_P70_PROF_PROFILE_RMP_DR_TCAM_SEARCH_EN_FLD = 5, + CFA_P70_PROF_PROFILE_RMP_DR_TCAM_PROFILE_ID_FLD = 6, + CFA_P70_PROF_PROFILE_RMP_DR_TCAM_KEY_ID_FLD = 7, + CFA_P70_PROF_PROFILE_RMP_DR_TCAM_SCOPE_FLD = 8, + CFA_P70_PROF_PROFILE_RMP_DR_MAX_FLD +}; + +/** + * PROF_PROFILE_RMP_DR_BYP + */ +enum cfa_p70_prof_profile_rmp_dr_byp_flds { + CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_BYP_LKUP_EN_FLD = 0, + CFA_P70_PROF_PROFILE_RMP_DR_BYP_RESERVED_FLD = 1, + CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_FLD = 2, + CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_ACT_HINT_FLD = 3, + CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_SCOPE_FLD = 4, + CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_ACT_REC_PTR_FLD = 5, + CFA_P70_PROF_PROFILE_RMP_DR_BYP_MAX_FLD +}; + +/** + * VNIC-SVIF Properties Table Fields: TX SVIF Properties Table + */ +enum cfa_p70_act_vspt_dr_tx_flds { + CFA_P70_ACT_VSPT_DR_TX_TPID_AS_CTL_FLD = 0, + CFA_P70_ACT_VSPT_DR_TX_ALWD_TPID_FLD = 1, + CFA_P70_ACT_VSPT_DR_TX_DFLT_TPID_FLD = 2, + CFA_P70_ACT_VSPT_DR_TX_PRI_AS_CTL_FLD = 3, + CFA_P70_ACT_VSPT_DR_TX_ALWD_PRI_FLD = 4, + CFA_P70_ACT_VSPT_DR_TX_DFLT_PRI_FLD = 5, + CFA_P70_ACT_VSPT_DR_TX_MIR_FLD = 6, + CFA_P70_ACT_VSPT_DR_TX_MAX_FLD +}; + +/** + * RX VNIC Properties Table + */ +enum cfa_p70_act_vspt_dr_rx_flds { + CFA_P70_ACT_VSPT_DR_RX_RSVD_FLD = 0, + CFA_P70_ACT_VSPT_DR_RX_METAFMT_FLD = 1, + CFA_P70_ACT_VSPT_DR_RX_FID_FLD = 2, + CFA_P70_ACT_VSPT_DR_RX_MIR_FLD = 3, + CFA_P70_ACT_VSPT_DR_RX_MAX_FLD +}; + +/** + * LAG ID Balance Table Fields: + */ +enum cfa_p70_act_lbt_dr_flds { + CFA_P70_ACT_LBT_DR_DST_BMP_FLD = 0, + CFA_P70_ACT_LBT_DR_MAX_FLD +}; + +/** + * L2 Context Lookup Remap Table Fields: + */ +enum cfa_p70_prof_l2_ctxt_rmp_dr_flds { + CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_PARIF_FLD = 0, + CFA_P70_PROF_L2_CTXT_RMP_DR_PARIF_FLD = 1, + CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_L2IP_CTXT_FLD = 2, + CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_CTXT_FLD = 3, + CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_PROF_FUNC_FLD = 4, + CFA_P70_PROF_L2_CTXT_RMP_DR_PROF_FUNC_FLD = 5, + CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_FLD = 6, + CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_META_ENB_FLD = 7, + CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_META_FLD = 8, + CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_ACT_ENB_FLD = 9, + CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_ACT_DATA_FLD = 10, + CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_RFS_ENB_FLD = 11, + CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_RFS_DATA_FLD = 12, + CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_DEST_ENB_FLD = 13, + CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_DEST_DATA_FLD = 14, + CFA_P70_PROF_L2_CTXT_RMP_DR_MAX_FLD +}; + +/** + * Multi Field Register. + */ +enum cfa_p70_act_fc_tcam_result_flds { + CFA_P70_ACT_FC_TCAM_RESULT_SEARCH_RESULT_FLD = 0, + CFA_P70_ACT_FC_TCAM_RESULT_UNUSED_0_FLD = 1, + CFA_P70_ACT_FC_TCAM_RESULT_SEARCH_HIT_FLD = 2, + CFA_P70_ACT_FC_TCAM_RESULT_MAX_FLD +}; + +/** + * Multi Field Register. + */ +enum cfa_p70_act_mirror_flds { + CFA_P70_ACT_MIRROR_UNUSED_0_FLD = 0, + CFA_P70_ACT_MIRROR_RELATIVE_FLD = 1, + CFA_P70_ACT_MIRROR_HINT_FLD = 2, + CFA_P70_ACT_MIRROR_SAMP_FLD = 3, + CFA_P70_ACT_MIRROR_TRUNC_FLD = 4, + CFA_P70_ACT_MIRROR_IGN_DROP_FLD = 5, + CFA_P70_ACT_MIRROR_MODE_FLD = 6, + CFA_P70_ACT_MIRROR_COND_FLD = 7, + CFA_P70_ACT_MIRROR_AR_PTR_FLD = 8, + CFA_P70_ACT_MIRROR_SAMP_CFG_FLD = 9, + CFA_P70_ACT_MIRROR_MAX_FLD +}; + +/** + * WC LREC Lookup Record + */ +enum cfa_p70_wc_lrec_flds { + CFA_P70_WC_LREC_METADATA_FLD = 0, + CFA_P70_WC_LREC_META_PROF_FLD = 1, + CFA_P70_WC_LREC_PROF_FUNC_FLD = 2, + CFA_P70_WC_LREC_RECYCLE_DEST_FLD = 3, + CFA_P70_WC_LREC_FC_PTR_FLD = 4, + CFA_P70_WC_LREC_FC_TYPE_FLD = 5, + CFA_P70_WC_LREC_FC_OP_FLD = 6, + CFA_P70_WC_LREC_PATHS_M1_FLD = 7, + CFA_P70_WC_LREC_ACT_REC_SIZE_FLD = 8, + CFA_P70_WC_LREC_RING_TABLE_IDX_FLD = 9, + CFA_P70_WC_LREC_DESTINATION_FLD = 10, + CFA_P70_WC_LREC_ACT_REC_PTR_FLD = 11, + CFA_P70_WC_LREC_ACT_HINT_FLD = 12, + CFA_P70_WC_LREC_STRENGTH_FLD = 13, + CFA_P70_WC_LREC_OPCODE_FLD = 14, + CFA_P70_WC_LREC_EPOCH1_FLD = 15, + CFA_P70_WC_LREC_EPOCH0_FLD = 16, + CFA_P70_WC_LREC_REC_SIZE_FLD = 17, + CFA_P70_WC_LREC_VALID_FLD = 18, + CFA_P70_WC_LREC_MAX_FLD +}; + +/** + * EM LREC Lookup Record + */ +enum cfa_p70_em_lrec_flds { + CFA_P70_EM_LREC_RANGE_IDX_FLD = 0, + CFA_P70_EM_LREC_RANGE_PROFILE_FLD = 1, + CFA_P70_EM_LREC_CREC_TIMER_VALUE_FLD = 2, + CFA_P70_EM_LREC_CREC_STATE_FLD = 3, + CFA_P70_EM_LREC_CREC_TCP_MSB_OPP_INIT_FLD = 4, + CFA_P70_EM_LREC_CREC_TCP_MSB_OPP_FLD = 5, + CFA_P70_EM_LREC_CREC_TCP_MSB_LOC_FLD = 6, + CFA_P70_EM_LREC_CREC_TCP_WIN_FLD = 7, + CFA_P70_EM_LREC_CREC_TCP_UPDT_EN_FLD = 8, + CFA_P70_EM_LREC_CREC_TCP_DIR_FLD = 9, + CFA_P70_EM_LREC_METADATA_FLD = 10, + CFA_P70_EM_LREC_PROF_FUNC_FLD = 11, + CFA_P70_EM_LREC_META_PROF_FLD = 12, + CFA_P70_EM_LREC_RECYCLE_DEST_FLD = 13, + CFA_P70_EM_LREC_FC_PTR_FLD = 14, + CFA_P70_EM_LREC_FC_TYPE_FLD = 15, + CFA_P70_EM_LREC_FC_OP_FLD = 16, + CFA_P70_EM_LREC_PATHS_M1_FLD = 17, + CFA_P70_EM_LREC_ACT_REC_SIZE_FLD = 18, + CFA_P70_EM_LREC_RING_TABLE_IDX_FLD = 19, + CFA_P70_EM_LREC_DESTINATION_FLD = 20, + CFA_P70_EM_LREC_ACT_REC_PTR_FLD = 21, + CFA_P70_EM_LREC_ACT_HINT_FLD = 22, + CFA_P70_EM_LREC_STRENGTH_FLD = 23, + CFA_P70_EM_LREC_OPCODE_FLD = 24, + CFA_P70_EM_LREC_EPOCH1_FLD = 25, + CFA_P70_EM_LREC_EPOCH0_FLD = 26, + CFA_P70_EM_LREC_REC_SIZE_FLD = 27, + CFA_P70_EM_LREC_VALID_FLD = 28, + CFA_P70_EM_LREC_MAX_FLD +}; + +/** + * EM Lookup Bucket Format + */ +enum cfa_p70_em_bucket_flds { + CFA_P70_EM_BUCKET_BIN0_ENTRY_FLD = 0, + CFA_P70_EM_BUCKET_BIN0_HASH_MSBS_FLD = 1, + CFA_P70_EM_BUCKET_BIN1_ENTRY_FLD = 2, + CFA_P70_EM_BUCKET_BIN1_HASH_MSBS_FLD = 3, + CFA_P70_EM_BUCKET_BIN2_ENTRY_FLD = 4, + CFA_P70_EM_BUCKET_BIN2_HASH_MSBS_FLD = 5, + CFA_P70_EM_BUCKET_BIN3_ENTRY_FLD = 6, + CFA_P70_EM_BUCKET_BIN3_HASH_MSBS_FLD = 7, + CFA_P70_EM_BUCKET_BIN4_ENTRY_FLD = 8, + CFA_P70_EM_BUCKET_BIN4_HASH_MSBS_FLD = 9, + CFA_P70_EM_BUCKET_BIN5_ENTRY_FLD = 10, + CFA_P70_EM_BUCKET_BIN5_HASH_MSBS_FLD = 11, + CFA_P70_EM_BUCKET_CHAIN_POINTER_FLD = 12, + CFA_P70_EM_BUCKET_CHAIN_VALID_FLD = 13, + CFA_P70_EM_BUCKET_MAX_FLD +}; + +/** + * Compact Action Record. The compact action record uses relative + * pointers to access needed data. This keeps the compact action record + * down to 64b. + */ +enum cfa_p70_compact_action_flds { + CFA_P70_COMPACT_ACTION_TYPE_FLD = 0, + CFA_P70_COMPACT_ACTION_DROP_FLD = 1, + CFA_P70_COMPACT_ACTION_VLAN_DELETE_FLD = 2, + CFA_P70_COMPACT_ACTION_DEST_FLD = 3, + CFA_P70_COMPACT_ACTION_DEST_OP_FLD = 4, + CFA_P70_COMPACT_ACTION_DECAP_FLD = 5, + CFA_P70_COMPACT_ACTION_MIRRORING_FLD = 6, + CFA_P70_COMPACT_ACTION_METER_PTR_FLD = 7, + CFA_P70_COMPACT_ACTION_STAT0_OFF_FLD = 8, + CFA_P70_COMPACT_ACTION_STAT0_OP_FLD = 9, + CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_FLD = 10, + CFA_P70_COMPACT_ACTION_MOD_OFF_FLD = 11, + CFA_P70_COMPACT_ACTION_ENC_OFF_FLD = 12, + CFA_P70_COMPACT_ACTION_SRC_OFF_FLD = 13, + CFA_P70_COMPACT_ACTION_UNUSED_0_FLD = 14, + CFA_P70_COMPACT_ACTION_MAX_FLD +}; + +/** + * Full Action Record. The full action record uses full pointers to + * access needed data. It also allows access to all the action features. + * The Full Action record is 192b. + */ +enum cfa_p70_full_action_flds { + CFA_P70_FULL_ACTION_TYPE_FLD = 0, + CFA_P70_FULL_ACTION_DROP_FLD = 1, + CFA_P70_FULL_ACTION_VLAN_DELETE_FLD = 2, + CFA_P70_FULL_ACTION_DEST_FLD = 3, + CFA_P70_FULL_ACTION_DEST_OP_FLD = 4, + CFA_P70_FULL_ACTION_DECAP_FLD = 5, + CFA_P70_FULL_ACTION_MIRRORING_FLD = 6, + CFA_P70_FULL_ACTION_METER_PTR_FLD = 7, + CFA_P70_FULL_ACTION_STAT0_PTR_FLD = 8, + CFA_P70_FULL_ACTION_STAT0_OP_FLD = 9, + CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_FLD = 10, + CFA_P70_FULL_ACTION_STAT1_PTR_FLD = 11, + CFA_P70_FULL_ACTION_STAT1_OP_FLD = 12, + CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_FLD = 13, + CFA_P70_FULL_ACTION_MOD_PTR_FLD = 14, + CFA_P70_FULL_ACTION_ENC_PTR_FLD = 15, + CFA_P70_FULL_ACTION_SRC_PTR_FLD = 16, + CFA_P70_FULL_ACTION_UNUSED_0_FLD = 17, + CFA_P70_FULL_ACTION_MAX_FLD +}; + +/** + * Multicast Group Action Record. This action is used to send the packet + * to multiple destinations. The MGC Action record is 256b. + */ +enum cfa_p70_mcg_action_flds { + CFA_P70_MCG_ACTION_TYPE_FLD = 0, + CFA_P70_MCG_ACTION_SRC_KO_EN_FLD = 1, + CFA_P70_MCG_ACTION_UNUSED_0_FLD = 2, + CFA_P70_MCG_ACTION_NEXT_PTR_FLD = 3, + CFA_P70_MCG_ACTION_PTR0_ACT_HINT_FLD = 4, + CFA_P70_MCG_ACTION_PTR0_ACT_REC_PTR_FLD = 5, + CFA_P70_MCG_ACTION_PTR1_ACT_HINT_FLD = 6, + CFA_P70_MCG_ACTION_PTR1_ACT_REC_PTR_FLD = 7, + CFA_P70_MCG_ACTION_PTR2_ACT_HINT_FLD = 8, + CFA_P70_MCG_ACTION_PTR2_ACT_REC_PTR_FLD = 9, + CFA_P70_MCG_ACTION_PTR3_ACT_HINT_FLD = 10, + CFA_P70_MCG_ACTION_PTR3_ACT_REC_PTR_FLD = 11, + CFA_P70_MCG_ACTION_PTR4_ACT_HINT_FLD = 12, + CFA_P70_MCG_ACTION_PTR4_ACT_REC_PTR_FLD = 13, + CFA_P70_MCG_ACTION_PTR5_ACT_HINT_FLD = 14, + CFA_P70_MCG_ACTION_PTR5_ACT_REC_PTR_FLD = 15, + CFA_P70_MCG_ACTION_PTR6_ACT_HINT_FLD = 16, + CFA_P70_MCG_ACTION_PTR6_ACT_REC_PTR_FLD = 17, + CFA_P70_MCG_ACTION_PTR7_ACT_HINT_FLD = 18, + CFA_P70_MCG_ACTION_PTR7_ACT_REC_PTR_FLD = 19, + CFA_P70_MCG_ACTION_MAX_FLD +}; + +/** + * Multicast Group Action Record. This action is used to send the packet + * to multiple destinations. The MGC Action record is 256b. + */ +enum cfa_p70_mcg_subseq_action_flds { + CFA_P70_MCG_SUBSEQ_ACTION_TYPE_FLD = 0, + CFA_P70_MCG_SUBSEQ_ACTION_UNUSED_0_FLD = 1, + CFA_P70_MCG_SUBSEQ_ACTION_NEXT_PTR_FLD = 2, + CFA_P70_MCG_SUBSEQ_ACTION_PTR0_ACT_HINT_FLD = 3, + CFA_P70_MCG_SUBSEQ_ACTION_PTR0_ACT_REC_PTR_FLD = 4, + CFA_P70_MCG_SUBSEQ_ACTION_PTR1_ACT_HINT_FLD = 5, + CFA_P70_MCG_SUBSEQ_ACTION_PTR1_ACT_REC_PTR_FLD = 6, + CFA_P70_MCG_SUBSEQ_ACTION_PTR2_ACT_HINT_FLD = 7, + CFA_P70_MCG_SUBSEQ_ACTION_PTR2_ACT_REC_PTR_FLD = 8, + CFA_P70_MCG_SUBSEQ_ACTION_PTR3_ACT_HINT_FLD = 9, + CFA_P70_MCG_SUBSEQ_ACTION_PTR3_ACT_REC_PTR_FLD = 10, + CFA_P70_MCG_SUBSEQ_ACTION_PTR4_ACT_HINT_FLD = 11, + CFA_P70_MCG_SUBSEQ_ACTION_PTR4_ACT_REC_PTR_FLD = 12, + CFA_P70_MCG_SUBSEQ_ACTION_PTR5_ACT_HINT_FLD = 13, + CFA_P70_MCG_SUBSEQ_ACTION_PTR5_ACT_REC_PTR_FLD = 14, + CFA_P70_MCG_SUBSEQ_ACTION_PTR6_ACT_HINT_FLD = 15, + CFA_P70_MCG_SUBSEQ_ACTION_PTR6_ACT_REC_PTR_FLD = 16, + CFA_P70_MCG_SUBSEQ_ACTION_PTR7_ACT_HINT_FLD = 17, + CFA_P70_MCG_SUBSEQ_ACTION_PTR7_ACT_REC_PTR_FLD = 18, + CFA_P70_MCG_SUBSEQ_ACTION_MAX_FLD +}; + +/** + * Action Meter Formats + */ +enum cfa_p70_meters_flds { + CFA_P70_METERS_BKT_C_FLD = 0, + CFA_P70_METERS_BKT_E_FLD = 1, + CFA_P70_METERS_FLAGS_MTR_VAL_FLD = 2, + CFA_P70_METERS_FLAGS_ECN_RMP_EN_FLD = 3, + CFA_P70_METERS_FLAGS_CF_FLD = 4, + CFA_P70_METERS_FLAGS_PM_FLD = 5, + CFA_P70_METERS_FLAGS_RFC2698_FLD = 6, + CFA_P70_METERS_FLAGS_CBSM_FLD = 7, + CFA_P70_METERS_FLAGS_EBSM_FLD = 8, + CFA_P70_METERS_FLAGS_CBND_FLD = 9, + CFA_P70_METERS_FLAGS_EBND_FLD = 10, + CFA_P70_METERS_CBS_FLD = 11, + CFA_P70_METERS_EBS_FLD = 12, + CFA_P70_METERS_CIR_FLD = 13, + CFA_P70_METERS_EIR_FLD = 14, + CFA_P70_METERS_PROTECTION_SCOPE_FLD = 15, + CFA_P70_METERS_PROTECTION_RSVD_FLD = 16, + CFA_P70_METERS_PROTECTION_ENABLE_FLD = 17, + CFA_P70_METERS_MAX_FLD +}; + +/** + * Enumeration for fkb + */ +enum cfa_p70_fkb_flds { + CFA_P70_FKB_PROF_ID_FLD = 0, + CFA_P70_FKB_L2CTXT_FLD = 1, + CFA_P70_FKB_L2FUNC_FLD = 2, + CFA_P70_FKB_PARIF_FLD = 3, + CFA_P70_FKB_SPIF_FLD = 4, + CFA_P70_FKB_SVIF_FLD = 5, + CFA_P70_FKB_LCOS_FLD = 6, + CFA_P70_FKB_META_HI_FLD = 7, + CFA_P70_FKB_META_LO_FLD = 8, + CFA_P70_FKB_RCYC_CNT_FLD = 9, + CFA_P70_FKB_LOOPBACK_FLD = 10, + CFA_P70_FKB_OTL2_TYPE_FLD = 11, + CFA_P70_FKB_OTL2_DMAC_FLD = 12, + CFA_P70_FKB_OTL2_SMAC_FLD = 13, + CFA_P70_FKB_OTL2_DT_FLD = 14, + CFA_P70_FKB_OTL2_SA_FLD = 15, + CFA_P70_FKB_OTL2_NVT_FLD = 16, + CFA_P70_FKB_OTL2_OVP_FLD = 17, + CFA_P70_FKB_OTL2_OVD_FLD = 18, + CFA_P70_FKB_OTL2_OVV_FLD = 19, + CFA_P70_FKB_OTL2_OVT_FLD = 20, + CFA_P70_FKB_OTL2_IVP_FLD = 21, + CFA_P70_FKB_OTL2_IVD_FLD = 22, + CFA_P70_FKB_OTL2_IVV_FLD = 23, + CFA_P70_FKB_OTL2_IVT_FLD = 24, + CFA_P70_FKB_OTL2_ETYPE_FLD = 25, + CFA_P70_FKB_OTL3_TYPE_FLD = 26, + CFA_P70_FKB_OTL3_SIP3_FLD = 27, + CFA_P70_FKB_OTL3_SIP2_FLD = 28, + CFA_P70_FKB_OTL3_SIP1_FLD = 29, + CFA_P70_FKB_OTL3_SIP0_FLD = 30, + CFA_P70_FKB_OTL3_DIP3_FLD = 31, + CFA_P70_FKB_OTL3_DIP2_FLD = 32, + CFA_P70_FKB_OTL3_DIP1_FLD = 33, + CFA_P70_FKB_OTL3_DIP0_FLD = 34, + CFA_P70_FKB_OTL3_TTL_FLD = 35, + CFA_P70_FKB_OTL3_PROT_FLD = 36, + CFA_P70_FKB_OTL3_FID_FLD = 37, + CFA_P70_FKB_OTL3_QOS_FLD = 38, + CFA_P70_FKB_OTL3_IEH_NONEXT_FLD = 39, + CFA_P70_FKB_OTL3_IEH_SEP_FLD = 40, + CFA_P70_FKB_OTL3_IEH_AUTH_FLD = 41, + CFA_P70_FKB_OTL3_IEH_DEST_FLD = 42, + CFA_P70_FKB_OTL3_IEH_FRAG_FLD = 43, + CFA_P70_FKB_OTL3_IEH_RTHDR_FLD = 44, + CFA_P70_FKB_OTL3_IEH_HOP_FLD = 45, + CFA_P70_FKB_OTL3_IEH_1FRAG_FLD = 46, + CFA_P70_FKB_OTL3_DF_FLD = 47, + CFA_P70_FKB_OTL3_L3ERR_FLD = 48, + CFA_P70_FKB_OTL4_TYPE_FLD = 49, + CFA_P70_FKB_OTL4_SRC_FLD = 50, + CFA_P70_FKB_OTL4_DST_FLD = 51, + CFA_P70_FKB_OTL4_FLAGS_FLD = 52, + CFA_P70_FKB_OTL4_SEQ_FLD = 53, + CFA_P70_FKB_OTL4_PA_FLD = 54, + CFA_P70_FKB_OTL4_OPT_FLD = 55, + CFA_P70_FKB_OTL4_TCPTS_FLD = 56, + CFA_P70_FKB_OTL4_ERR_FLD = 57, + CFA_P70_FKB_OT_TYPE_FLD = 58, + CFA_P70_FKB_OT_FLAGS_FLD = 59, + CFA_P70_FKB_OT_IDS_FLD = 60, + CFA_P70_FKB_OT_ID_FLD = 61, + CFA_P70_FKB_OT_CTXTS_FLD = 62, + CFA_P70_FKB_OT_CTXT_FLD = 63, + CFA_P70_FKB_OT_QOS_FLD = 64, + CFA_P70_FKB_OT_ERR_FLD = 65, + CFA_P70_FKB_TL2_TYPE_FLD = 66, + CFA_P70_FKB_TL2_DMAC_FLD = 67, + CFA_P70_FKB_TL2_SMAC_FLD = 68, + CFA_P70_FKB_TL2_DT_FLD = 69, + CFA_P70_FKB_TL2_SA_FLD = 70, + CFA_P70_FKB_TL2_NVT_FLD = 71, + CFA_P70_FKB_TL2_OVP_FLD = 72, + CFA_P70_FKB_TL2_OVD_FLD = 73, + CFA_P70_FKB_TL2_OVV_FLD = 74, + CFA_P70_FKB_TL2_OVT_FLD = 75, + CFA_P70_FKB_TL2_IVP_FLD = 76, + CFA_P70_FKB_TL2_IVD_FLD = 77, + CFA_P70_FKB_TL2_IVV_FLD = 78, + CFA_P70_FKB_TL2_IVT_FLD = 79, + CFA_P70_FKB_TL2_ETYPE_FLD = 80, + CFA_P70_FKB_TL3_TYPE_FLD = 81, + CFA_P70_FKB_TL3_SIP3_FLD = 82, + CFA_P70_FKB_TL3_SIP2_FLD = 83, + CFA_P70_FKB_TL3_SIP1_FLD = 84, + CFA_P70_FKB_TL3_SIP0_FLD = 85, + CFA_P70_FKB_TL3_DIP3_FLD = 86, + CFA_P70_FKB_TL3_DIP2_FLD = 87, + CFA_P70_FKB_TL3_DIP1_FLD = 88, + CFA_P70_FKB_TL3_DIP0_FLD = 89, + CFA_P70_FKB_TL3_TTL_FLD = 90, + CFA_P70_FKB_TL3_PROT_FLD = 91, + CFA_P70_FKB_TL3_FID_FLD = 92, + CFA_P70_FKB_TL3_QOS_FLD = 93, + CFA_P70_FKB_TL3_IEH_NONEXT_FLD = 94, + CFA_P70_FKB_TL3_IEH_SEP_FLD = 95, + CFA_P70_FKB_TL3_IEH_AUTH_FLD = 96, + CFA_P70_FKB_TL3_IEH_DEST_FLD = 97, + CFA_P70_FKB_TL3_IEH_FRAG_FLD = 98, + CFA_P70_FKB_TL3_IEH_RTHDR_FLD = 99, + CFA_P70_FKB_TL3_IEH_HOP_FLD = 100, + CFA_P70_FKB_TL3_IEH_1FRAG_FLD = 101, + CFA_P70_FKB_TL3_DF_FLD = 102, + CFA_P70_FKB_TL3_L3ERR_FLD = 103, + CFA_P70_FKB_TL4_TYPE_FLD = 104, + CFA_P70_FKB_TL4_SRC_FLD = 105, + CFA_P70_FKB_TL4_DST_FLD = 106, + CFA_P70_FKB_TL4_FLAGS_FLD = 107, + CFA_P70_FKB_TL4_SEQ_FLD = 108, + CFA_P70_FKB_TL4_PA_FLD = 109, + CFA_P70_FKB_TL4_OPT_FLD = 110, + CFA_P70_FKB_TL4_TCPTS_FLD = 111, + CFA_P70_FKB_TL4_ERR_FLD = 112, + CFA_P70_FKB_T_TYPE_FLD = 113, + CFA_P70_FKB_T_FLAGS_FLD = 114, + CFA_P70_FKB_T_IDS_FLD = 115, + CFA_P70_FKB_T_ID_FLD = 116, + CFA_P70_FKB_T_CTXTS_FLD = 117, + CFA_P70_FKB_T_CTXT_FLD = 118, + CFA_P70_FKB_T_QOS_FLD = 119, + CFA_P70_FKB_T_ERR_FLD = 120, + CFA_P70_FKB_L2_TYPE_FLD = 121, + CFA_P70_FKB_L2_DMAC_FLD = 122, + CFA_P70_FKB_L2_SMAC_FLD = 123, + CFA_P70_FKB_L2_DT_FLD = 124, + CFA_P70_FKB_L2_SA_FLD = 125, + CFA_P70_FKB_L2_NVT_FLD = 126, + CFA_P70_FKB_L2_OVP_FLD = 127, + CFA_P70_FKB_L2_OVD_FLD = 128, + CFA_P70_FKB_L2_OVV_FLD = 129, + CFA_P70_FKB_L2_OVT_FLD = 130, + CFA_P70_FKB_L2_IVP_FLD = 131, + CFA_P70_FKB_L2_IVD_FLD = 132, + CFA_P70_FKB_L2_IVV_FLD = 133, + CFA_P70_FKB_L2_IVT_FLD = 134, + CFA_P70_FKB_L2_ETYPE_FLD = 135, + CFA_P70_FKB_L3_TYPE_FLD = 136, + CFA_P70_FKB_L3_SIP3_FLD = 137, + CFA_P70_FKB_L3_SIP2_FLD = 138, + CFA_P70_FKB_L3_SIP1_FLD = 139, + CFA_P70_FKB_L3_SIP0_FLD = 140, + CFA_P70_FKB_L3_DIP3_FLD = 141, + CFA_P70_FKB_L3_DIP2_FLD = 142, + CFA_P70_FKB_L3_DIP1_FLD = 143, + CFA_P70_FKB_L3_DIP0_FLD = 144, + CFA_P70_FKB_L3_TTL_FLD = 145, + CFA_P70_FKB_L3_PROT_FLD = 146, + CFA_P70_FKB_L3_FID_FLD = 147, + CFA_P70_FKB_L3_QOS_FLD = 148, + CFA_P70_FKB_L3_IEH_NONEXT_FLD = 149, + CFA_P70_FKB_L3_IEH_SEP_FLD = 150, + CFA_P70_FKB_L3_IEH_AUTH_FLD = 151, + CFA_P70_FKB_L3_IEH_DEST_FLD = 152, + CFA_P70_FKB_L3_IEH_FRAG_FLD = 153, + CFA_P70_FKB_L3_IEH_RTHDR_FLD = 154, + CFA_P70_FKB_L3_IEH_HOP_FLD = 155, + CFA_P70_FKB_L3_IEH_1FRAG_FLD = 156, + CFA_P70_FKB_L3_DF_FLD = 157, + CFA_P70_FKB_L3_L3ERR_FLD = 158, + CFA_P70_FKB_L4_TYPE_FLD = 159, + CFA_P70_FKB_L4_SRC_FLD = 160, + CFA_P70_FKB_L4_DST_FLD = 161, + CFA_P70_FKB_L4_FLAGS_FLD = 162, + CFA_P70_FKB_L4_SEQ_FLD = 163, + CFA_P70_FKB_L4_ACK_FLD = 164, + CFA_P70_FKB_L4_WIN_FLD = 165, + CFA_P70_FKB_L4_PA_FLD = 166, + CFA_P70_FKB_L4_OPT_FLD = 167, + CFA_P70_FKB_L4_TCPTS_FLD = 168, + CFA_P70_FKB_L4_TSVAL_FLD = 169, + CFA_P70_FKB_L4_TXECR_FLD = 170, + CFA_P70_FKB_L4_ERR_FLD = 171, + CFA_P70_FKB_MAX_FLD = 172, +}; + +/** + * Enumeration for wc tcam fkb + */ +enum cfa_p70_wc_tcam_fkb_flds { + CFA_P70_WC_TCAM_FKB_PROF_ID_FLD = 0, + CFA_P70_WC_TCAM_FKB_L2CTXT_FLD = 1, + CFA_P70_WC_TCAM_FKB_L2FUNC_FLD = 2, + CFA_P70_WC_TCAM_FKB_PARIF_FLD = 3, + CFA_P70_WC_TCAM_FKB_SPIF_FLD = 4, + CFA_P70_WC_TCAM_FKB_SVIF_FLD = 5, + CFA_P70_WC_TCAM_FKB_LCOS_FLD = 6, + CFA_P70_WC_TCAM_FKB_META_HI_FLD = 7, + CFA_P70_WC_TCAM_FKB_META_LO_FLD = 8, + CFA_P70_WC_TCAM_FKB_RCYC_CNT_FLD = 9, + CFA_P70_WC_TCAM_FKB_LOOPBACK_FLD = 10, + CFA_P70_WC_TCAM_FKB_OTL2_TYPE_FLD = 11, + CFA_P70_WC_TCAM_FKB_OTL2_DMAC_FLD = 12, + CFA_P70_WC_TCAM_FKB_OTL2_SMAC_FLD = 13, + CFA_P70_WC_TCAM_FKB_OTL2_DT_FLD = 14, + CFA_P70_WC_TCAM_FKB_OTL2_SA_FLD = 15, + CFA_P70_WC_TCAM_FKB_OTL2_NVT_FLD = 16, + CFA_P70_WC_TCAM_FKB_OTL2_OVP_FLD = 17, + CFA_P70_WC_TCAM_FKB_OTL2_OVD_FLD = 18, + CFA_P70_WC_TCAM_FKB_OTL2_OVV_FLD = 19, + CFA_P70_WC_TCAM_FKB_OTL2_OVT_FLD = 20, + CFA_P70_WC_TCAM_FKB_OTL2_IVP_FLD = 21, + CFA_P70_WC_TCAM_FKB_OTL2_IVD_FLD = 22, + CFA_P70_WC_TCAM_FKB_OTL2_IVV_FLD = 23, + CFA_P70_WC_TCAM_FKB_OTL2_IVT_FLD = 24, + CFA_P70_WC_TCAM_FKB_OTL2_ETYPE_FLD = 25, + CFA_P70_WC_TCAM_FKB_OTL3_TYPE_FLD = 26, + CFA_P70_WC_TCAM_FKB_OTL3_SIP3_FLD = 27, + CFA_P70_WC_TCAM_FKB_OTL3_SIP2_FLD = 28, + CFA_P70_WC_TCAM_FKB_OTL3_SIP1_FLD = 29, + CFA_P70_WC_TCAM_FKB_OTL3_SIP0_FLD = 30, + CFA_P70_WC_TCAM_FKB_OTL3_DIP3_FLD = 31, + CFA_P70_WC_TCAM_FKB_OTL3_DIP2_FLD = 32, + CFA_P70_WC_TCAM_FKB_OTL3_DIP1_FLD = 33, + CFA_P70_WC_TCAM_FKB_OTL3_DIP0_FLD = 34, + CFA_P70_WC_TCAM_FKB_OTL3_TTL_FLD = 35, + CFA_P70_WC_TCAM_FKB_OTL3_PROT_FLD = 36, + CFA_P70_WC_TCAM_FKB_OTL3_FID_FLD = 37, + CFA_P70_WC_TCAM_FKB_OTL3_QOS_FLD = 38, + CFA_P70_WC_TCAM_FKB_OTL3_IEH_NONEXT_FLD = 39, + CFA_P70_WC_TCAM_FKB_OTL3_IEH_SEP_FLD = 40, + CFA_P70_WC_TCAM_FKB_OTL3_IEH_AUTH_FLD = 41, + CFA_P70_WC_TCAM_FKB_OTL3_IEH_DEST_FLD = 42, + CFA_P70_WC_TCAM_FKB_OTL3_IEH_FRAG_FLD = 43, + CFA_P70_WC_TCAM_FKB_OTL3_IEH_RTHDR_FLD = 44, + CFA_P70_WC_TCAM_FKB_OTL3_IEH_HOP_FLD = 45, + CFA_P70_WC_TCAM_FKB_OTL3_IEH_1FRAG_FLD = 46, + CFA_P70_WC_TCAM_FKB_OTL3_DF_FLD = 47, + CFA_P70_WC_TCAM_FKB_OTL3_L3ERR_FLD = 48, + CFA_P70_WC_TCAM_FKB_OTL4_TYPE_FLD = 49, + CFA_P70_WC_TCAM_FKB_OTL4_SRC_FLD = 50, + CFA_P70_WC_TCAM_FKB_OTL4_DST_FLD = 51, + CFA_P70_WC_TCAM_FKB_OTL4_FLAGS_FLD = 52, + CFA_P70_WC_TCAM_FKB_OTL4_SEQ_FLD = 53, + CFA_P70_WC_TCAM_FKB_OTL4_PA_FLD = 54, + CFA_P70_WC_TCAM_FKB_OTL4_OPT_FLD = 55, + CFA_P70_WC_TCAM_FKB_OTL4_TCPTS_FLD = 56, + CFA_P70_WC_TCAM_FKB_OTL4_ERR_FLD = 57, + CFA_P70_WC_TCAM_FKB_OT_TYPE_FLD = 58, + CFA_P70_WC_TCAM_FKB_OT_FLAGS_FLD = 59, + CFA_P70_WC_TCAM_FKB_OT_IDS_FLD = 60, + CFA_P70_WC_TCAM_FKB_OT_ID_FLD = 61, + CFA_P70_WC_TCAM_FKB_OT_CTXTS_FLD = 62, + CFA_P70_WC_TCAM_FKB_OT_CTXT_FLD = 63, + CFA_P70_WC_TCAM_FKB_OT_QOS_FLD = 64, + CFA_P70_WC_TCAM_FKB_OT_ERR_FLD = 65, + CFA_P70_WC_TCAM_FKB_TL2_TYPE_FLD = 66, + CFA_P70_WC_TCAM_FKB_TL2_DMAC_FLD = 67, + CFA_P70_WC_TCAM_FKB_TL2_SMAC_FLD = 68, + CFA_P70_WC_TCAM_FKB_TL2_DT_FLD = 69, + CFA_P70_WC_TCAM_FKB_TL2_SA_FLD = 70, + CFA_P70_WC_TCAM_FKB_TL2_NVT_FLD = 71, + CFA_P70_WC_TCAM_FKB_TL2_OVP_FLD = 72, + CFA_P70_WC_TCAM_FKB_TL2_OVD_FLD = 73, + CFA_P70_WC_TCAM_FKB_TL2_OVV_FLD = 74, + CFA_P70_WC_TCAM_FKB_TL2_OVT_FLD = 75, + CFA_P70_WC_TCAM_FKB_TL2_IVP_FLD = 76, + CFA_P70_WC_TCAM_FKB_TL2_IVD_FLD = 77, + CFA_P70_WC_TCAM_FKB_TL2_IVV_FLD = 78, + CFA_P70_WC_TCAM_FKB_TL2_IVT_FLD = 79, + CFA_P70_WC_TCAM_FKB_TL2_ETYPE_FLD = 80, + CFA_P70_WC_TCAM_FKB_TL3_TYPE_FLD = 81, + CFA_P70_WC_TCAM_FKB_TL3_SIP3_FLD = 82, + CFA_P70_WC_TCAM_FKB_TL3_SIP2_FLD = 83, + CFA_P70_WC_TCAM_FKB_TL3_SIP1_FLD = 84, + CFA_P70_WC_TCAM_FKB_TL3_SIP0_FLD = 85, + CFA_P70_WC_TCAM_FKB_TL3_DIP3_FLD = 86, + CFA_P70_WC_TCAM_FKB_TL3_DIP2_FLD = 87, + CFA_P70_WC_TCAM_FKB_TL3_DIP1_FLD = 88, + CFA_P70_WC_TCAM_FKB_TL3_DIP0_FLD = 89, + CFA_P70_WC_TCAM_FKB_TL3_TTL_FLD = 90, + CFA_P70_WC_TCAM_FKB_TL3_PROT_FLD = 91, + CFA_P70_WC_TCAM_FKB_TL3_FID_FLD = 92, + CFA_P70_WC_TCAM_FKB_TL3_QOS_FLD = 93, + CFA_P70_WC_TCAM_FKB_TL3_IEH_NONEXT_FLD = 94, + CFA_P70_WC_TCAM_FKB_TL3_IEH_SEP_FLD = 95, + CFA_P70_WC_TCAM_FKB_TL3_IEH_AUTH_FLD = 96, + CFA_P70_WC_TCAM_FKB_TL3_IEH_DEST_FLD = 97, + CFA_P70_WC_TCAM_FKB_TL3_IEH_FRAG_FLD = 98, + CFA_P70_WC_TCAM_FKB_TL3_IEH_RTHDR_FLD = 99, + CFA_P70_WC_TCAM_FKB_TL3_IEH_HOP_FLD = 100, + CFA_P70_WC_TCAM_FKB_TL3_IEH_1FRAG_FLD = 101, + CFA_P70_WC_TCAM_FKB_TL3_DF_FLD = 102, + CFA_P70_WC_TCAM_FKB_TL3_L3ERR_FLD = 103, + CFA_P70_WC_TCAM_FKB_TL4_TYPE_FLD = 104, + CFA_P70_WC_TCAM_FKB_TL4_SRC_FLD = 105, + CFA_P70_WC_TCAM_FKB_TL4_DST_FLD = 106, + CFA_P70_WC_TCAM_FKB_TL4_FLAGS_FLD = 107, + CFA_P70_WC_TCAM_FKB_TL4_SEQ_FLD = 108, + CFA_P70_WC_TCAM_FKB_TL4_PA_FLD = 109, + CFA_P70_WC_TCAM_FKB_TL4_OPT_FLD = 110, + CFA_P70_WC_TCAM_FKB_TL4_TCPTS_FLD = 111, + CFA_P70_WC_TCAM_FKB_TL4_ERR_FLD = 112, + CFA_P70_WC_TCAM_FKB_T_TYPE_FLD = 113, + CFA_P70_WC_TCAM_FKB_T_FLAGS_FLD = 114, + CFA_P70_WC_TCAM_FKB_T_IDS_FLD = 115, + CFA_P70_WC_TCAM_FKB_T_ID_FLD = 116, + CFA_P70_WC_TCAM_FKB_T_CTXTS_FLD = 117, + CFA_P70_WC_TCAM_FKB_T_CTXT_FLD = 118, + CFA_P70_WC_TCAM_FKB_T_QOS_FLD = 119, + CFA_P70_WC_TCAM_FKB_T_ERR_FLD = 120, + CFA_P70_WC_TCAM_FKB_L2_TYPE_FLD = 121, + CFA_P70_WC_TCAM_FKB_L2_DMAC_FLD = 122, + CFA_P70_WC_TCAM_FKB_L2_SMAC_FLD = 123, + CFA_P70_WC_TCAM_FKB_L2_DT_FLD = 124, + CFA_P70_WC_TCAM_FKB_L2_SA_FLD = 125, + CFA_P70_WC_TCAM_FKB_L2_NVT_FLD = 126, + CFA_P70_WC_TCAM_FKB_L2_OVP_FLD = 127, + CFA_P70_WC_TCAM_FKB_L2_OVD_FLD = 128, + CFA_P70_WC_TCAM_FKB_L2_OVV_FLD = 129, + CFA_P70_WC_TCAM_FKB_L2_OVT_FLD = 130, + CFA_P70_WC_TCAM_FKB_L2_IVP_FLD = 131, + CFA_P70_WC_TCAM_FKB_L2_IVD_FLD = 132, + CFA_P70_WC_TCAM_FKB_L2_IVV_FLD = 133, + CFA_P70_WC_TCAM_FKB_L2_IVT_FLD = 134, + CFA_P70_WC_TCAM_FKB_L2_ETYPE_FLD = 135, + CFA_P70_WC_TCAM_FKB_L3_TYPE_FLD = 136, + CFA_P70_WC_TCAM_FKB_L3_SIP3_FLD = 137, + CFA_P70_WC_TCAM_FKB_L3_SIP2_FLD = 138, + CFA_P70_WC_TCAM_FKB_L3_SIP1_FLD = 139, + CFA_P70_WC_TCAM_FKB_L3_SIP0_FLD = 140, + CFA_P70_WC_TCAM_FKB_L3_DIP3_FLD = 141, + CFA_P70_WC_TCAM_FKB_L3_DIP2_FLD = 142, + CFA_P70_WC_TCAM_FKB_L3_DIP1_FLD = 143, + CFA_P70_WC_TCAM_FKB_L3_DIP0_FLD = 144, + CFA_P70_WC_TCAM_FKB_L3_TTL_FLD = 145, + CFA_P70_WC_TCAM_FKB_L3_PROT_FLD = 146, + CFA_P70_WC_TCAM_FKB_L3_FID_FLD = 147, + CFA_P70_WC_TCAM_FKB_L3_QOS_FLD = 148, + CFA_P70_WC_TCAM_FKB_L3_IEH_NONEXT_FLD = 149, + CFA_P70_WC_TCAM_FKB_L3_IEH_SEP_FLD = 150, + CFA_P70_WC_TCAM_FKB_L3_IEH_AUTH_FLD = 151, + CFA_P70_WC_TCAM_FKB_L3_IEH_DEST_FLD = 152, + CFA_P70_WC_TCAM_FKB_L3_IEH_FRAG_FLD = 153, + CFA_P70_WC_TCAM_FKB_L3_IEH_RTHDR_FLD = 154, + CFA_P70_WC_TCAM_FKB_L3_IEH_HOP_FLD = 155, + CFA_P70_WC_TCAM_FKB_L3_IEH_1FRAG_FLD = 156, + CFA_P70_WC_TCAM_FKB_L3_DF_FLD = 157, + CFA_P70_WC_TCAM_FKB_L3_L3ERR_FLD = 158, + CFA_P70_WC_TCAM_FKB_L4_TYPE_FLD = 159, + CFA_P70_WC_TCAM_FKB_L4_SRC_FLD = 160, + CFA_P70_WC_TCAM_FKB_L4_DST_FLD = 161, + CFA_P70_WC_TCAM_FKB_L4_FLAGS_FLD = 162, + CFA_P70_WC_TCAM_FKB_L4_SEQ_FLD = 163, + CFA_P70_WC_TCAM_FKB_L4_ACK_FLD = 164, + CFA_P70_WC_TCAM_FKB_L4_WIN_FLD = 165, + CFA_P70_WC_TCAM_FKB_L4_PA_FLD = 166, + CFA_P70_WC_TCAM_FKB_L4_OPT_FLD = 167, + CFA_P70_WC_TCAM_FKB_L4_TCPTS_FLD = 168, + CFA_P70_WC_TCAM_FKB_L4_TSVAL_FLD = 169, + CFA_P70_WC_TCAM_FKB_L4_TXECR_FLD = 170, + CFA_P70_WC_TCAM_FKB_L4_ERR_FLD = 171, + CFA_P70_WC_TCAM_FKB_MAX_FLD = 172, +}; + +/** + * Enumeration for em fkb + */ +enum cfa_p70_em_fkb_flds { + CFA_P70_EM_FKB_PROF_ID_FLD = 0, + CFA_P70_EM_FKB_L2CTXT_FLD = 1, + CFA_P70_EM_FKB_L2FUNC_FLD = 2, + CFA_P70_EM_FKB_PARIF_FLD = 3, + CFA_P70_EM_FKB_SPIF_FLD = 4, + CFA_P70_EM_FKB_SVIF_FLD = 5, + CFA_P70_EM_FKB_LCOS_FLD = 6, + CFA_P70_EM_FKB_META_HI_FLD = 7, + CFA_P70_EM_FKB_META_LO_FLD = 8, + CFA_P70_EM_FKB_RCYC_CNT_FLD = 9, + CFA_P70_EM_FKB_LOOPBACK_FLD = 10, + CFA_P70_EM_FKB_OTL2_TYPE_FLD = 11, + CFA_P70_EM_FKB_OTL2_DMAC_FLD = 12, + CFA_P70_EM_FKB_OTL2_SMAC_FLD = 13, + CFA_P70_EM_FKB_OTL2_DT_FLD = 14, + CFA_P70_EM_FKB_OTL2_SA_FLD = 15, + CFA_P70_EM_FKB_OTL2_NVT_FLD = 16, + CFA_P70_EM_FKB_OTL2_OVP_FLD = 17, + CFA_P70_EM_FKB_OTL2_OVD_FLD = 18, + CFA_P70_EM_FKB_OTL2_OVV_FLD = 19, + CFA_P70_EM_FKB_OTL2_OVT_FLD = 20, + CFA_P70_EM_FKB_OTL2_IVP_FLD = 21, + CFA_P70_EM_FKB_OTL2_IVD_FLD = 22, + CFA_P70_EM_FKB_OTL2_IVV_FLD = 23, + CFA_P70_EM_FKB_OTL2_IVT_FLD = 24, + CFA_P70_EM_FKB_OTL2_ETYPE_FLD = 25, + CFA_P70_EM_FKB_OTL3_TYPE_FLD = 26, + CFA_P70_EM_FKB_OTL3_SIP3_FLD = 27, + CFA_P70_EM_FKB_OTL3_SIP2_FLD = 28, + CFA_P70_EM_FKB_OTL3_SIP1_FLD = 29, + CFA_P70_EM_FKB_OTL3_SIP0_FLD = 30, + CFA_P70_EM_FKB_OTL3_DIP3_FLD = 31, + CFA_P70_EM_FKB_OTL3_DIP2_FLD = 32, + CFA_P70_EM_FKB_OTL3_DIP1_FLD = 33, + CFA_P70_EM_FKB_OTL3_DIP0_FLD = 34, + CFA_P70_EM_FKB_OTL3_TTL_FLD = 35, + CFA_P70_EM_FKB_OTL3_PROT_FLD = 36, + CFA_P70_EM_FKB_OTL3_FID_FLD = 37, + CFA_P70_EM_FKB_OTL3_QOS_FLD = 38, + CFA_P70_EM_FKB_OTL3_IEH_NONEXT_FLD = 39, + CFA_P70_EM_FKB_OTL3_IEH_SEP_FLD = 40, + CFA_P70_EM_FKB_OTL3_IEH_AUTH_FLD = 41, + CFA_P70_EM_FKB_OTL3_IEH_DEST_FLD = 42, + CFA_P70_EM_FKB_OTL3_IEH_FRAG_FLD = 43, + CFA_P70_EM_FKB_OTL3_IEH_RTHDR_FLD = 44, + CFA_P70_EM_FKB_OTL3_IEH_HOP_FLD = 45, + CFA_P70_EM_FKB_OTL3_IEH_1FRAG_FLD = 46, + CFA_P70_EM_FKB_OTL3_DF_FLD = 47, + CFA_P70_EM_FKB_OTL3_L3ERR_FLD = 48, + CFA_P70_EM_FKB_OTL4_TYPE_FLD = 49, + CFA_P70_EM_FKB_OTL4_SRC_FLD = 50, + CFA_P70_EM_FKB_OTL4_DST_FLD = 51, + CFA_P70_EM_FKB_OTL4_FLAGS_FLD = 52, + CFA_P70_EM_FKB_OTL4_SEQ_FLD = 53, + CFA_P70_EM_FKB_OTL4_PA_FLD = 54, + CFA_P70_EM_FKB_OTL4_OPT_FLD = 55, + CFA_P70_EM_FKB_OTL4_TCPTS_FLD = 56, + CFA_P70_EM_FKB_OTL4_ERR_FLD = 57, + CFA_P70_EM_FKB_OT_TYPE_FLD = 58, + CFA_P70_EM_FKB_OT_FLAGS_FLD = 59, + CFA_P70_EM_FKB_OT_IDS_FLD = 60, + CFA_P70_EM_FKB_OT_ID_FLD = 61, + CFA_P70_EM_FKB_OT_CTXTS_FLD = 62, + CFA_P70_EM_FKB_OT_CTXT_FLD = 63, + CFA_P70_EM_FKB_OT_QOS_FLD = 64, + CFA_P70_EM_FKB_OT_ERR_FLD = 65, + CFA_P70_EM_FKB_TL2_TYPE_FLD = 66, + CFA_P70_EM_FKB_TL2_DMAC_FLD = 67, + CFA_P70_EM_FKB_TL2_SMAC_FLD = 68, + CFA_P70_EM_FKB_TL2_DT_FLD = 69, + CFA_P70_EM_FKB_TL2_SA_FLD = 70, + CFA_P70_EM_FKB_TL2_NVT_FLD = 71, + CFA_P70_EM_FKB_TL2_OVP_FLD = 72, + CFA_P70_EM_FKB_TL2_OVD_FLD = 73, + CFA_P70_EM_FKB_TL2_OVV_FLD = 74, + CFA_P70_EM_FKB_TL2_OVT_FLD = 75, + CFA_P70_EM_FKB_TL2_IVP_FLD = 76, + CFA_P70_EM_FKB_TL2_IVD_FLD = 77, + CFA_P70_EM_FKB_TL2_IVV_FLD = 78, + CFA_P70_EM_FKB_TL2_IVT_FLD = 79, + CFA_P70_EM_FKB_TL2_ETYPE_FLD = 80, + CFA_P70_EM_FKB_TL3_TYPE_FLD = 81, + CFA_P70_EM_FKB_TL3_SIP3_FLD = 82, + CFA_P70_EM_FKB_TL3_SIP2_FLD = 83, + CFA_P70_EM_FKB_TL3_SIP1_FLD = 84, + CFA_P70_EM_FKB_TL3_SIP0_FLD = 85, + CFA_P70_EM_FKB_TL3_DIP3_FLD = 86, + CFA_P70_EM_FKB_TL3_DIP2_FLD = 87, + CFA_P70_EM_FKB_TL3_DIP1_FLD = 88, + CFA_P70_EM_FKB_TL3_DIP0_FLD = 89, + CFA_P70_EM_FKB_TL3_TTL_FLD = 90, + CFA_P70_EM_FKB_TL3_PROT_FLD = 91, + CFA_P70_EM_FKB_TL3_FID_FLD = 92, + CFA_P70_EM_FKB_TL3_QOS_FLD = 93, + CFA_P70_EM_FKB_TL3_IEH_NONEXT_FLD = 94, + CFA_P70_EM_FKB_TL3_IEH_SEP_FLD = 95, + CFA_P70_EM_FKB_TL3_IEH_AUTH_FLD = 96, + CFA_P70_EM_FKB_TL3_IEH_DEST_FLD = 97, + CFA_P70_EM_FKB_TL3_IEH_FRAG_FLD = 98, + CFA_P70_EM_FKB_TL3_IEH_RTHDR_FLD = 99, + CFA_P70_EM_FKB_TL3_IEH_HOP_FLD = 100, + CFA_P70_EM_FKB_TL3_IEH_1FRAG_FLD = 101, + CFA_P70_EM_FKB_TL3_DF_FLD = 102, + CFA_P70_EM_FKB_TL3_L3ERR_FLD = 103, + CFA_P70_EM_FKB_TL4_TYPE_FLD = 104, + CFA_P70_EM_FKB_TL4_SRC_FLD = 105, + CFA_P70_EM_FKB_TL4_DST_FLD = 106, + CFA_P70_EM_FKB_TL4_FLAGS_FLD = 107, + CFA_P70_EM_FKB_TL4_SEQ_FLD = 108, + CFA_P70_EM_FKB_TL4_PA_FLD = 109, + CFA_P70_EM_FKB_TL4_OPT_FLD = 110, + CFA_P70_EM_FKB_TL4_TCPTS_FLD = 111, + CFA_P70_EM_FKB_TL4_ERR_FLD = 112, + CFA_P70_EM_FKB_T_TYPE_FLD = 113, + CFA_P70_EM_FKB_T_FLAGS_FLD = 114, + CFA_P70_EM_FKB_T_IDS_FLD = 115, + CFA_P70_EM_FKB_T_ID_FLD = 116, + CFA_P70_EM_FKB_T_CTXTS_FLD = 117, + CFA_P70_EM_FKB_T_CTXT_FLD = 118, + CFA_P70_EM_FKB_T_QOS_FLD = 119, + CFA_P70_EM_FKB_T_ERR_FLD = 120, + CFA_P70_EM_FKB_L2_TYPE_FLD = 121, + CFA_P70_EM_FKB_L2_DMAC_FLD = 122, + CFA_P70_EM_FKB_L2_SMAC_FLD = 123, + CFA_P70_EM_FKB_L2_DT_FLD = 124, + CFA_P70_EM_FKB_L2_SA_FLD = 125, + CFA_P70_EM_FKB_L2_NVT_FLD = 126, + CFA_P70_EM_FKB_L2_OVP_FLD = 127, + CFA_P70_EM_FKB_L2_OVD_FLD = 128, + CFA_P70_EM_FKB_L2_OVV_FLD = 129, + CFA_P70_EM_FKB_L2_OVT_FLD = 130, + CFA_P70_EM_FKB_L2_IVP_FLD = 131, + CFA_P70_EM_FKB_L2_IVD_FLD = 132, + CFA_P70_EM_FKB_L2_IVV_FLD = 133, + CFA_P70_EM_FKB_L2_IVT_FLD = 134, + CFA_P70_EM_FKB_L2_ETYPE_FLD = 135, + CFA_P70_EM_FKB_L3_TYPE_FLD = 136, + CFA_P70_EM_FKB_L3_SIP3_FLD = 137, + CFA_P70_EM_FKB_L3_SIP2_FLD = 138, + CFA_P70_EM_FKB_L3_SIP1_FLD = 139, + CFA_P70_EM_FKB_L3_SIP0_FLD = 140, + CFA_P70_EM_FKB_L3_DIP3_FLD = 141, + CFA_P70_EM_FKB_L3_DIP2_FLD = 142, + CFA_P70_EM_FKB_L3_DIP1_FLD = 143, + CFA_P70_EM_FKB_L3_DIP0_FLD = 144, + CFA_P70_EM_FKB_L3_TTL_FLD = 145, + CFA_P70_EM_FKB_L3_PROT_FLD = 146, + CFA_P70_EM_FKB_L3_FID_FLD = 147, + CFA_P70_EM_FKB_L3_QOS_FLD = 148, + CFA_P70_EM_FKB_L3_IEH_NONEXT_FLD = 149, + CFA_P70_EM_FKB_L3_IEH_SEP_FLD = 150, + CFA_P70_EM_FKB_L3_IEH_AUTH_FLD = 151, + CFA_P70_EM_FKB_L3_IEH_DEST_FLD = 152, + CFA_P70_EM_FKB_L3_IEH_FRAG_FLD = 153, + CFA_P70_EM_FKB_L3_IEH_RTHDR_FLD = 154, + CFA_P70_EM_FKB_L3_IEH_HOP_FLD = 155, + CFA_P70_EM_FKB_L3_IEH_1FRAG_FLD = 156, + CFA_P70_EM_FKB_L3_DF_FLD = 157, + CFA_P70_EM_FKB_L3_L3ERR_FLD = 158, + CFA_P70_EM_FKB_L4_TYPE_FLD = 159, + CFA_P70_EM_FKB_L4_SRC_FLD = 160, + CFA_P70_EM_FKB_L4_DST_FLD = 161, + CFA_P70_EM_FKB_L4_FLAGS_FLD = 162, + CFA_P70_EM_FKB_L4_SEQ_FLD = 163, + CFA_P70_EM_FKB_L4_ACK_FLD = 164, + CFA_P70_EM_FKB_L4_WIN_FLD = 165, + CFA_P70_EM_FKB_L4_PA_FLD = 166, + CFA_P70_EM_FKB_L4_OPT_FLD = 167, + CFA_P70_EM_FKB_L4_TCPTS_FLD = 168, + CFA_P70_EM_FKB_L4_TSVAL_FLD = 169, + CFA_P70_EM_FKB_L4_TXECR_FLD = 170, + CFA_P70_EM_FKB_L4_ERR_FLD = 171, + CFA_P70_EM_FKB_MAX_FLD = 172, +}; + +/** + * Enumeration for em key layout + */ +enum cfa_p70_em_key_layout_flds { + CFA_P70_EM_KL_RANGE_IDX_FLD = 0, + CFA_P70_EM_KL_RANGE_PROFILE_FLD = 1, + CFA_P70_EM_KL_CREC_TIMER_VALUE_FLD = 2, + CFA_P70_EM_KL_CREC_STATE_FLD = 3, + CFA_P70_EM_KL_CREC_TCP_MSB_OPP_INIT_FLD = 4, + CFA_P70_EM_KL_CREC_TCP_MSB_OPP_FLD = 5, + CFA_P70_EM_KL_CREC_TCP_MSB_LOC_FLD = 6, + CFA_P70_EM_KL_CREC_TCP_WIN_FLD = 7, + CFA_P70_EM_KL_CREC_TCP_UPDT_EN_FLD = 8, + CFA_P70_EM_KL_CREC_TCP_DIR_FLD = 9, + CFA_P70_EM_KL_METADATA_FLD = 10, + CFA_P70_EM_KL_PROF_FUNC_FLD = 11, + CFA_P70_EM_KL_META_PROF_FLD = 12, + CFA_P70_EM_KL_RECYCLE_DEST_FLD = 13, + CFA_P70_EM_KL_FC_PTR_FLD = 14, + CFA_P70_EM_KL_FC_TYPE_FLD = 15, + CFA_P70_EM_KL_FC_OP_FLD = 16, + CFA_P70_EM_KL_PATHS_M1_FLD = 17, + CFA_P70_EM_KL_ACT_REC_SIZE_FLD = 18, + CFA_P70_EM_KL_RING_TABLE_IDX_FLD = 19, + CFA_P70_EM_KL_DESTINATION_FLD = 20, + CFA_P70_EM_KL_ACT_REC_PTR_FLD = 21, + CFA_P70_EM_KL_ACT_HINT_FLD = 22, + CFA_P70_EM_KL_STRENGTH_FLD = 23, + CFA_P70_EM_KL_OPCODE_FLD = 24, + CFA_P70_EM_KL_EPOCH1_FLD = 25, + CFA_P70_EM_KL_EPOCH0_FLD = 26, + CFA_P70_EM_KL_REC_SIZE_FLD = 27, + CFA_P70_EM_KL_VALID_FLD = 28, + CFA_P70_EM_KL_PROF_ID_FLD = 29, + CFA_P70_EM_KL_L2CTXT_FLD = 30, + CFA_P70_EM_KL_L2FUNC_FLD = 31, + CFA_P70_EM_KL_PARIF_FLD = 32, + CFA_P70_EM_KL_SPIF_FLD = 33, + CFA_P70_EM_KL_SVIF_FLD = 34, + CFA_P70_EM_KL_LCOS_FLD = 35, + CFA_P70_EM_KL_META_HI_FLD = 36, + CFA_P70_EM_KL_META_LO_FLD = 37, + CFA_P70_EM_KL_RCYC_CNT_FLD = 38, + CFA_P70_EM_KL_LOOPBACK_FLD = 39, + CFA_P70_EM_KL_OTL2_TYPE_FLD = 40, + CFA_P70_EM_KL_OTL2_DMAC_FLD = 41, + CFA_P70_EM_KL_OTL2_SMAC_FLD = 42, + CFA_P70_EM_KL_OTL2_DT_FLD = 43, + CFA_P70_EM_KL_OTL2_SA_FLD = 44, + CFA_P70_EM_KL_OTL2_NVT_FLD = 45, + CFA_P70_EM_KL_OTL2_OVP_FLD = 46, + CFA_P70_EM_KL_OTL2_OVD_FLD = 47, + CFA_P70_EM_KL_OTL2_OVV_FLD = 48, + CFA_P70_EM_KL_OTL2_OVT_FLD = 49, + CFA_P70_EM_KL_OTL2_IVP_FLD = 50, + CFA_P70_EM_KL_OTL2_IVD_FLD = 51, + CFA_P70_EM_KL_OTL2_IVV_FLD = 52, + CFA_P70_EM_KL_OTL2_IVT_FLD = 53, + CFA_P70_EM_KL_OTL2_ETYPE_FLD = 54, + CFA_P70_EM_KL_OTL3_TYPE_FLD = 55, + CFA_P70_EM_KL_OTL3_SIP3_FLD = 56, + CFA_P70_EM_KL_OTL3_SIP2_FLD = 57, + CFA_P70_EM_KL_OTL3_SIP1_FLD = 58, + CFA_P70_EM_KL_OTL3_SIP0_FLD = 59, + CFA_P70_EM_KL_OTL3_DIP3_FLD = 60, + CFA_P70_EM_KL_OTL3_DIP2_FLD = 61, + CFA_P70_EM_KL_OTL3_DIP1_FLD = 62, + CFA_P70_EM_KL_OTL3_DIP0_FLD = 63, + CFA_P70_EM_KL_OTL3_TTL_FLD = 64, + CFA_P70_EM_KL_OTL3_PROT_FLD = 65, + CFA_P70_EM_KL_OTL3_FID_FLD = 66, + CFA_P70_EM_KL_OTL3_QOS_FLD = 67, + CFA_P70_EM_KL_OTL3_IEH_NONEXT_FLD = 68, + CFA_P70_EM_KL_OTL3_IEH_SEP_FLD = 69, + CFA_P70_EM_KL_OTL3_IEH_AUTH_FLD = 70, + CFA_P70_EM_KL_OTL3_IEH_DEST_FLD = 71, + CFA_P70_EM_KL_OTL3_IEH_FRAG_FLD = 72, + CFA_P70_EM_KL_OTL3_IEH_RTHDR_FLD = 73, + CFA_P70_EM_KL_OTL3_IEH_HOP_FLD = 74, + CFA_P70_EM_KL_OTL3_IEH_1FRAG_FLD = 75, + CFA_P70_EM_KL_OTL3_DF_FLD = 76, + CFA_P70_EM_KL_OTL3_L3ERR_FLD = 77, + CFA_P70_EM_KL_OTL4_TYPE_FLD = 78, + CFA_P70_EM_KL_OTL4_SRC_FLD = 79, + CFA_P70_EM_KL_OTL4_DST_FLD = 80, + CFA_P70_EM_KL_OTL4_FLAGS_FLD = 81, + CFA_P70_EM_KL_OTL4_SEQ_FLD = 82, + CFA_P70_EM_KL_OTL4_PA_FLD = 83, + CFA_P70_EM_KL_OTL4_OPT_FLD = 84, + CFA_P70_EM_KL_OTL4_TCPTS_FLD = 85, + CFA_P70_EM_KL_OTL4_ERR_FLD = 86, + CFA_P70_EM_KL_OT_TYPE_FLD = 87, + CFA_P70_EM_KL_OT_FLAGS_FLD = 88, + CFA_P70_EM_KL_OT_IDS_FLD = 89, + CFA_P70_EM_KL_OT_ID_FLD = 90, + CFA_P70_EM_KL_OT_CTXTS_FLD = 91, + CFA_P70_EM_KL_OT_CTXT_FLD = 92, + CFA_P70_EM_KL_OT_QOS_FLD = 93, + CFA_P70_EM_KL_OT_ERR_FLD = 94, + CFA_P70_EM_KL_TL2_TYPE_FLD = 95, + CFA_P70_EM_KL_TL2_DMAC_FLD = 96, + CFA_P70_EM_KL_TL2_SMAC_FLD = 97, + CFA_P70_EM_KL_TL2_DT_FLD = 98, + CFA_P70_EM_KL_TL2_SA_FLD = 99, + CFA_P70_EM_KL_TL2_NVT_FLD = 100, + CFA_P70_EM_KL_TL2_OVP_FLD = 101, + CFA_P70_EM_KL_TL2_OVD_FLD = 102, + CFA_P70_EM_KL_TL2_OVV_FLD = 103, + CFA_P70_EM_KL_TL2_OVT_FLD = 104, + CFA_P70_EM_KL_TL2_IVP_FLD = 105, + CFA_P70_EM_KL_TL2_IVD_FLD = 106, + CFA_P70_EM_KL_TL2_IVV_FLD = 107, + CFA_P70_EM_KL_TL2_IVT_FLD = 108, + CFA_P70_EM_KL_TL2_ETYPE_FLD = 109, + CFA_P70_EM_KL_TL3_TYPE_FLD = 110, + CFA_P70_EM_KL_TL3_SIP3_FLD = 111, + CFA_P70_EM_KL_TL3_SIP2_FLD = 112, + CFA_P70_EM_KL_TL3_SIP1_FLD = 113, + CFA_P70_EM_KL_TL3_SIP0_FLD = 114, + CFA_P70_EM_KL_TL3_DIP3_FLD = 115, + CFA_P70_EM_KL_TL3_DIP2_FLD = 116, + CFA_P70_EM_KL_TL3_DIP1_FLD = 117, + CFA_P70_EM_KL_TL3_DIP0_FLD = 118, + CFA_P70_EM_KL_TL3_TTL_FLD = 119, + CFA_P70_EM_KL_TL3_PROT_FLD = 120, + CFA_P70_EM_KL_TL3_FID_FLD = 121, + CFA_P70_EM_KL_TL3_QOS_FLD = 122, + CFA_P70_EM_KL_TL3_IEH_NONEXT_FLD = 123, + CFA_P70_EM_KL_TL3_IEH_SEP_FLD = 124, + CFA_P70_EM_KL_TL3_IEH_AUTH_FLD = 125, + CFA_P70_EM_KL_TL3_IEH_DEST_FLD = 126, + CFA_P70_EM_KL_TL3_IEH_FRAG_FLD = 127, + CFA_P70_EM_KL_TL3_IEH_RTHDR_FLD = 128, + CFA_P70_EM_KL_TL3_IEH_HOP_FLD = 129, + CFA_P70_EM_KL_TL3_IEH_1FRAG_FLD = 130, + CFA_P70_EM_KL_TL3_DF_FLD = 131, + CFA_P70_EM_KL_TL3_L3ERR_FLD = 132, + CFA_P70_EM_KL_TL4_TYPE_FLD = 133, + CFA_P70_EM_KL_TL4_SRC_FLD = 134, + CFA_P70_EM_KL_TL4_DST_FLD = 135, + CFA_P70_EM_KL_TL4_FLAGS_FLD = 136, + CFA_P70_EM_KL_TL4_SEQ_FLD = 137, + CFA_P70_EM_KL_TL4_PA_FLD = 138, + CFA_P70_EM_KL_TL4_OPT_FLD = 139, + CFA_P70_EM_KL_TL4_TCPTS_FLD = 140, + CFA_P70_EM_KL_TL4_ERR_FLD = 141, + CFA_P70_EM_KL_T_TYPE_FLD = 142, + CFA_P70_EM_KL_T_FLAGS_FLD = 143, + CFA_P70_EM_KL_T_IDS_FLD = 144, + CFA_P70_EM_KL_T_ID_FLD = 145, + CFA_P70_EM_KL_T_CTXTS_FLD = 146, + CFA_P70_EM_KL_T_CTXT_FLD = 147, + CFA_P70_EM_KL_T_QOS_FLD = 148, + CFA_P70_EM_KL_T_ERR_FLD = 149, + CFA_P70_EM_KL_L2_TYPE_FLD = 150, + CFA_P70_EM_KL_L2_DMAC_FLD = 151, + CFA_P70_EM_KL_L2_SMAC_FLD = 152, + CFA_P70_EM_KL_L2_DT_FLD = 153, + CFA_P70_EM_KL_L2_SA_FLD = 154, + CFA_P70_EM_KL_L2_NVT_FLD = 155, + CFA_P70_EM_KL_L2_OVP_FLD = 156, + CFA_P70_EM_KL_L2_OVD_FLD = 157, + CFA_P70_EM_KL_L2_OVV_FLD = 158, + CFA_P70_EM_KL_L2_OVT_FLD = 159, + CFA_P70_EM_KL_L2_IVP_FLD = 160, + CFA_P70_EM_KL_L2_IVD_FLD = 161, + CFA_P70_EM_KL_L2_IVV_FLD = 162, + CFA_P70_EM_KL_L2_IVT_FLD = 163, + CFA_P70_EM_KL_L2_ETYPE_FLD = 164, + CFA_P70_EM_KL_L3_TYPE_FLD = 165, + CFA_P70_EM_KL_L3_SIP3_FLD = 166, + CFA_P70_EM_KL_L3_SIP2_FLD = 167, + CFA_P70_EM_KL_L3_SIP1_FLD = 168, + CFA_P70_EM_KL_L3_SIP0_FLD = 169, + CFA_P70_EM_KL_L3_DIP3_FLD = 170, + CFA_P70_EM_KL_L3_DIP2_FLD = 171, + CFA_P70_EM_KL_L3_DIP1_FLD = 172, + CFA_P70_EM_KL_L3_DIP0_FLD = 173, + CFA_P70_EM_KL_L3_TTL_FLD = 174, + CFA_P70_EM_KL_L3_PROT_FLD = 175, + CFA_P70_EM_KL_L3_FID_FLD = 176, + CFA_P70_EM_KL_L3_QOS_FLD = 177, + CFA_P70_EM_KL_L3_IEH_NONEXT_FLD = 178, + CFA_P70_EM_KL_L3_IEH_SEP_FLD = 179, + CFA_P70_EM_KL_L3_IEH_AUTH_FLD = 180, + CFA_P70_EM_KL_L3_IEH_DEST_FLD = 181, + CFA_P70_EM_KL_L3_IEH_FRAG_FLD = 182, + CFA_P70_EM_KL_L3_IEH_RTHDR_FLD = 183, + CFA_P70_EM_KL_L3_IEH_HOP_FLD = 184, + CFA_P70_EM_KL_L3_IEH_1FRAG_FLD = 185, + CFA_P70_EM_KL_L3_DF_FLD = 186, + CFA_P70_EM_KL_L3_L3ERR_FLD = 187, + CFA_P70_EM_KL_L4_TYPE_FLD = 188, + CFA_P70_EM_KL_L4_SRC_FLD = 189, + CFA_P70_EM_KL_L4_DST_FLD = 190, + CFA_P70_EM_KL_L4_FLAGS_FLD = 191, + CFA_P70_EM_KL_L4_SEQ_FLD = 192, + CFA_P70_EM_KL_L4_ACK_FLD = 193, + CFA_P70_EM_KL_L4_WIN_FLD = 194, + CFA_P70_EM_KL_L4_PA_FLD = 195, + CFA_P70_EM_KL_L4_OPT_FLD = 196, + CFA_P70_EM_KL_L4_TCPTS_FLD = 197, + CFA_P70_EM_KL_L4_TSVAL_FLD = 198, + CFA_P70_EM_KL_L4_TXECR_FLD = 199, + CFA_P70_EM_KL_L4_ERR_FLD = 200, + CFA_P70_EM_KEY_LAYOUT_MAX_FLD = 201, + CFA_P70_EM_KL_MAX_FLD = CFA_P70_EM_KEY_LAYOUT_MAX_FLD, +}; + +/** + * Enumeration for action + */ +enum cfa_p70_action_flds { + CFA_P70_ACT_TYPE_FLD = 0, + CFA_P70_ACT_DROP_FLD = 1, + CFA_P70_ACT_VLAN_DELETE_FLD = 2, + CFA_P70_ACT_DEST_FLD = 3, + CFA_P70_ACT_DEST_OP_FLD = 4, + CFA_P70_ACT_DECAP_FLD = 5, + CFA_P70_ACT_MIRRORING_FLD = 6, + CFA_P70_ACT_METER_PTR_FLD = 7, + CFA_P70_ACT_STAT0_OFF_FLD = 8, + CFA_P70_ACT_STAT0_OP_FLD = 9, + CFA_P70_ACT_STAT0_CTR_TYPE_FLD = 10, + CFA_P70_ACT_MOD_OFF_FLD = 11, + CFA_P70_ACT_ENC_OFF_FLD = 12, + CFA_P70_ACT_SRC_OFF_FLD = 13, + CFA_P70_ACT_COMPACT_RSVD_0_FLD = 14, + CFA_P70_ACT_STAT0_PTR_FLD = 15, + CFA_P70_ACT_STAT1_PTR_FLD = 16, + CFA_P70_ACT_STAT1_OP_FLD = 17, + CFA_P70_ACT_STAT1_CTR_TYPE_FLD = 18, + CFA_P70_ACT_MOD_PTR_FLD = 19, + CFA_P70_ACT_ENC_PTR_FLD = 20, + CFA_P70_ACT_SRC_PTR_FLD = 21, + CFA_P70_ACT_FULL_RSVD_0_FLD = 22, + CFA_P70_ACT_SRC_KO_EN_FLD = 23, + CFA_P70_ACT_MCG_RSVD_0_FLD = 24, + CFA_P70_ACT_NEXT_PTR_FLD = 25, + CFA_P70_ACT_PTR0_ACT_HINT_FLD = 26, + CFA_P70_ACT_PTR0_ACT_REC_PTR_FLD = 27, + CFA_P70_ACT_PTR1_ACT_HINT_FLD = 28, + CFA_P70_ACT_PTR1_ACT_REC_PTR_FLD = 29, + CFA_P70_ACT_PTR2_ACT_HINT_FLD = 30, + CFA_P70_ACT_PTR2_ACT_REC_PTR_FLD = 31, + CFA_P70_ACT_PTR3_ACT_HINT_FLD = 32, + CFA_P70_ACT_PTR3_ACT_REC_PTR_FLD = 33, + CFA_P70_ACT_PTR4_ACT_HINT_FLD = 34, + CFA_P70_ACT_PTR4_ACT_REC_PTR_FLD = 35, + CFA_P70_ACT_PTR5_ACT_HINT_FLD = 36, + CFA_P70_ACT_PTR5_ACT_REC_PTR_FLD = 37, + CFA_P70_ACT_PTR6_ACT_HINT_FLD = 38, + CFA_P70_ACT_PTR6_ACT_REC_PTR_FLD = 39, + CFA_P70_ACT_PTR7_ACT_HINT_FLD = 40, + CFA_P70_ACT_PTR7_ACT_REC_PTR_FLD = 41, + CFA_P70_ACT_MCG_SUBSEQ_RSVD_0_FLD = 42, + CFA_P70_ACT_MOD_MODIFY_ACT_HDR_FLD = 43, + CFA_P70_ACT_MOD_MD_UPDT_DATA_FLD = 44, + CFA_P70_ACT_MOD_MD_UPDT_PROF_FLD = 45, + CFA_P70_ACT_MOD_MD_UPDT_OP_FLD = 46, + CFA_P70_ACT_MOD_MD_UPDT_RSVD_0_FLD = 47, + CFA_P70_ACT_MOD_MD_UPDT_TOP_FLD = 48, + CFA_P70_ACT_MOD_RM_OVLAN_FLD = 49, + CFA_P70_ACT_MOD_RM_IVLAN_FLD = 50, + CFA_P70_ACT_MOD_RPL_IVLAN_FLD = 51, + CFA_P70_ACT_MOD_RPL_OVLAN_FLD = 52, + CFA_P70_ACT_MOD_TTL_UPDT_OP_FLD = 53, + CFA_P70_ACT_MOD_TTL_UPDT_ALT_VID_FLD = 54, + CFA_P70_ACT_MOD_TTL_UPDT_ALT_PFID_FLD = 55, + CFA_P70_ACT_MOD_TTL_UPDT_TOP_FLD = 56, + CFA_P70_ACT_MOD_TNL_MODIFY_DEL_FLD = 57, + CFA_P70_ACT_MOD_TNL_MODIFY_8B_NEW_PROT_FLD = 58, + CFA_P70_ACT_MOD_TNL_MODIFY_8B_EXIST_PROT_FLD = 59, + CFA_P70_ACT_MOD_TNL_MODIFY_8B_VEC_FLD = 60, + CFA_P70_ACT_MOD_TNL_MODIFY_8B_TOP_FLD = 61, + CFA_P70_ACT_MOD_TNL_MODIFY_16B_NEW_PROT_FLD = 62, + CFA_P70_ACT_MOD_TNL_MODIFY_16B_EXIST_PROT_FLD = 63, + CFA_P70_ACT_MOD_TNL_MODIFY_16B_VEC_FLD = 64, + CFA_P70_ACT_MOD_TNL_MODIFY_16B_TOP_FLD = 65, + CFA_P70_ACT_MOD_UPDT_FIELD_DATA0_FLD = 66, + CFA_P70_ACT_MOD_UPDT_FIELD_VEC_RSVD_FLD = 67, + CFA_P70_ACT_MOD_UPDT_FIELD_VEC_KID_FLD = 68, + CFA_P70_ACT_MOD_UPDT_FIELD_TOP_FLD = 69, + CFA_P70_ACT_MOD_SMAC_FLD = 70, + CFA_P70_ACT_MOD_DMAC_FLD = 71, + CFA_P70_ACT_MOD_SIPV6_FLD = 72, + CFA_P70_ACT_MOD_DIPV6_FLD = 73, + CFA_P70_ACT_MOD_SIPV4_FLD = 74, + CFA_P70_ACT_MOD_DIPV4_FLD = 75, + CFA_P70_ACT_MOD_SPORT_FLD = 76, + CFA_P70_ACT_MOD_DPORT_FLD = 77, + CFA_P70_ACT_ENC_ECV_TNL_FLD = 78, + CFA_P70_ACT_ENC_ECV_L4_FLD = 79, + CFA_P70_ACT_ENC_ECV_L3_FLD = 80, + CFA_P70_ACT_ENC_ECV_L2_FLD = 81, + CFA_P70_ACT_ENC_ECV_VTAG_FLD = 82, + CFA_P70_ACT_ENC_ECV_EC_FLD = 83, + CFA_P70_ACT_ENC_ECV_VALID_FLD = 84, + CFA_P70_ACT_ENC_EC_IP_TTL_IH_FLD = 85, + CFA_P70_ACT_ENC_EC_IP_TOS_IH_FLD = 86, + CFA_P70_ACT_ENC_EC_TUN_QOS_FLD = 87, + CFA_P70_ACT_ENC_EC_GRE_SET_K_FLD = 88, + CFA_P70_ACT_ENC_EC_DMAC_OVR_FLD = 89, + CFA_P70_ACT_ENC_EC_VLAN_OVR_FLD = 90, + CFA_P70_ACT_ENC_EC_SMAC_OVR_FLD = 91, + CFA_P70_ACT_ENC_EC_IPV4_ID_CTRL_FLD = 92, + CFA_P70_ACT_ENC_L2_DMAC_FLD = 93, + CFA_P70_ACT_ENC_VLAN1_TAG_VID_FLD = 94, + CFA_P70_ACT_ENC_VLAN1_TAG_DE_FLD = 95, + CFA_P70_ACT_ENC_VLAN1_TAG_PRI_FLD = 96, + CFA_P70_ACT_ENC_VLAN1_TAG_TPID_FLD = 97, + CFA_P70_ACT_ENC_VLAN2_IT_VID_FLD = 98, + CFA_P70_ACT_ENC_VLAN2_IT_DE_FLD = 99, + CFA_P70_ACT_ENC_VLAN2_IT_PRI_FLD = 100, + CFA_P70_ACT_ENC_VLAN2_IT_TPID_FLD = 101, + CFA_P70_ACT_ENC_VLAN2_OT_VID_FLD = 102, + CFA_P70_ACT_ENC_VLAN2_OT_DE_FLD = 103, + CFA_P70_ACT_ENC_VLAN2_OT_PRI_FLD = 104, + CFA_P70_ACT_ENC_VLAN2_OT_TPID_FLD = 105, + CFA_P70_ACT_ENC_IPV4_ID_FLD = 106, + CFA_P70_ACT_ENC_IPV4_TOS_FLD = 107, + CFA_P70_ACT_ENC_IPV4_HLEN_FLD = 108, + CFA_P70_ACT_ENC_IPV4_VER_FLD = 109, + CFA_P70_ACT_ENC_IPV4_PROT_FLD = 110, + CFA_P70_ACT_ENC_IPV4_TTL_FLD = 111, + CFA_P70_ACT_ENC_IPV4_FRAG_FLD = 112, + CFA_P70_ACT_ENC_IPV4_FLAGS_FLD = 113, + CFA_P70_ACT_ENC_IPV4_DEST_FLD = 114, + CFA_P70_ACT_ENC_IPV6_FLOW_LABEL_FLD = 115, + CFA_P70_ACT_ENC_IPV6_TRAFFIC_CLASS_FLD = 116, + CFA_P70_ACT_ENC_IPV6_VER_FLD = 117, + CFA_P70_ACT_ENC_IPV6_HOP_LIMIT_FLD = 118, + CFA_P70_ACT_ENC_IPV6_NEXT_HEADER_FLD = 119, + CFA_P70_ACT_ENC_IPV6_PAYLOAD_LENGTH_FLD = 120, + CFA_P70_ACT_ENC_IPV6_DEST_FLD = 121, + CFA_P70_ACT_ENC_MPLS_TAG1_FLD = 122, + CFA_P70_ACT_ENC_MPLS_TAG2_FLD = 123, + CFA_P70_ACT_ENC_MPLS_TAG3_FLD = 124, + CFA_P70_ACT_ENC_MPLS_TAG4_FLD = 125, + CFA_P70_ACT_ENC_MPLS_TAG5_FLD = 126, + CFA_P70_ACT_ENC_MPLS_TAG6_FLD = 127, + CFA_P70_ACT_ENC_MPLS_TAG7_FLD = 128, + CFA_P70_ACT_ENC_MPLS_TAG8_FLD = 129, + CFA_P70_ACT_ENC_L4_DEST_PORT_FLD = 130, + CFA_P70_ACT_ENC_L4_SRC_PORT_FLD = 131, + CFA_P70_ACT_ENC_TNL_VXLAN_NEXT_PROT_FLD = 132, + CFA_P70_ACT_ENC_TNL_VXLAN_RSVD_0_FLD = 133, + CFA_P70_ACT_ENC_TNL_VXLAN_FLAGS_FLD = 134, + CFA_P70_ACT_ENC_TNL_VXLAN_RSVD_1_FLD = 135, + CFA_P70_ACT_ENC_TNL_VXLAN_VNI_FLD = 136, + CFA_P70_ACT_ENC_TNL_NGE_PROT_TYPE_FLD = 137, + CFA_P70_ACT_ENC_TNL_NGE_RSVD_0_FLD = 138, + CFA_P70_ACT_ENC_TNL_NGE_FLAGS_C_FLD = 139, + CFA_P70_ACT_ENC_TNL_NGE_FLAGS_O_FLD = 140, + CFA_P70_ACT_ENC_TNL_NGE_FLAGS_OPT_LEN_FLD = 141, + CFA_P70_ACT_ENC_TNL_NGE_FLAGS_VER_FLD = 142, + CFA_P70_ACT_ENC_TNL_NGE_RSVD_1_FLD = 143, + CFA_P70_ACT_ENC_TNL_NGE_VNI_FLD = 144, + CFA_P70_ACT_ENC_TNL_NGE_OPTIONS_FLD = 145, + CFA_P70_ACT_ENC_TNL_NVGRE_FLOW_ID_FLD = 146, + CFA_P70_ACT_ENC_TNL_NVGRE_VSID_FLD = 147, + CFA_P70_ACT_ENC_TNL_GRE_KEY_FLD = 148, + CFA_P70_ACT_ENC_TNL_GENERIC_TID_FLD = 149, + CFA_P70_ACT_ENC_TNL_GENERIC_LENGTH_FLD = 150, + CFA_P70_ACT_ENC_TNL_GENERIC_HEADER_FLD = 151, + CFA_P70_ACT_SRC_MAC_FLD = 152, + CFA_P70_ACT_SRC_IPV4_ADDR_FLD = 153, + CFA_P70_ACT_SRC_IPV6_ADDR_FLD = 154, + CFA_P70_ACT_STAT0_B16_FPC_FLD = 155, + CFA_P70_ACT_STAT1_B16_FPC_FLD = 156, + CFA_P70_ACT_STAT0_B16_FBC_FLD = 157, + CFA_P70_ACT_STAT1_B16_FBC_FLD = 158, + CFA_P70_ACT_STAT0_B24_FPC_FLD = 159, + CFA_P70_ACT_STAT1_B24_FPC_FLD = 160, + CFA_P70_ACT_STAT0_B24_FBC_FLD = 161, + CFA_P70_ACT_STAT1_B24_FBC_FLD = 162, + CFA_P70_ACT_STAT0_B24_TIMESTAMP_FLD = 163, + CFA_P70_ACT_STAT1_B24_TIMESTAMP_FLD = 164, + CFA_P70_ACT_STAT0_B24_TCP_FLAGS_FLD = 165, + CFA_P70_ACT_STAT1_B24_TCP_FLAGS_FLD = 166, + CFA_P70_ACT_STAT0_B24_UNUSED_0_FLD = 167, + CFA_P70_ACT_STAT1_B24_UNUSED_0_FLD = 168, + CFA_P70_ACT_STAT0_B32A_FPC_FLD = 169, + CFA_P70_ACT_STAT1_B32A_FPC_FLD = 170, + CFA_P70_ACT_STAT0_B32A_FBC_FLD = 171, + CFA_P70_ACT_STAT1_B32A_FBC_FLD = 172, + CFA_P70_ACT_STAT0_B32A_MPC_FLD = 173, + CFA_P70_ACT_STAT1_B32A_MPC_FLD = 174, + CFA_P70_ACT_STAT0_B32A_MBC_FLD = 175, + CFA_P70_ACT_STAT1_B32A_MBC_FLD = 176, + CFA_P70_ACT_STAT0_B32B_FPC_FLD = 177, + CFA_P70_ACT_STAT1_B32B_FPC_FLD = 178, + CFA_P70_ACT_STAT0_B32B_FBC_FLD = 179, + CFA_P70_ACT_STAT1_B32B_FBC_FLD = 180, + CFA_P70_ACT_STAT0_B32B_TIMESTAMP_FLD = 181, + CFA_P70_ACT_STAT1_B32B_TIMESTAMP_FLD = 182, + CFA_P70_ACT_STAT0_B32B_TCP_FLAGS_FLD = 183, + CFA_P70_ACT_STAT1_B32B_TCP_FLAGS_FLD = 184, + CFA_P70_ACT_STAT0_B32B_UNUSED_0_FLD = 185, + CFA_P70_ACT_STAT1_B32B_UNUSED_0_FLD = 186, + CFA_P70_ACT_STAT0_B32B_MPC15_0_FLD = 187, + CFA_P70_ACT_STAT1_B32B_MPC15_0_FLD = 188, + CFA_P70_ACT_STAT0_B32B_MPC37_16_FLD = 189, + CFA_P70_ACT_STAT1_B32B_MPC37_16_FLD = 190, + CFA_P70_ACT_STAT0_B32B_MBC_FLD = 191, + CFA_P70_ACT_STAT1_B32B_MBC_FLD = 192, + CFA_P70_ACTION_MAX_FLD = 193, + CFA_P70_ACT_MAX_FLD = CFA_P70_ACTION_MAX_FLD, +}; + +#define CFA_P70_EM_KEY_LAYOUT_2_BASE_FLD(FLD) \ + ((FLD) - CFA_P70_EM_LREC_MAX_FLD) + +/* clang-format on */ + +#endif /* _CFA_BLD_P70_FIELD_IDS_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_mpc.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_mpc.h new file mode 100644 index 0000000000..21d79ab5f5 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_bld_p70_mpc.h @@ -0,0 +1,548 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_p70_mpc.h + * + * @brief CFA 7.0 Public api definitions to build CFA Mid-path commands and + * Parse CFA Mid-path Command completions + */ + +#ifndef _CFA_BLD_P70_MPC_H_ +#define _CFA_BLD_P70_MPC_H_ + +#include +#include + +/** + * CFA Mid-Path Command (MPC) opcodes. The MPC CFA operations + * are divided into 2 sub groups. Cache access operations + * and EM update operations. + */ +enum cfa_mpc_opcode { + /** + * MPC Cache access commands + */ + /* MPC Command to read Action/Lookup cache (up to 4 lines) */ + CFA_MPC_READ, + /* MPC Command to write to Action/Lookup cache (up to 4 lines) */ + CFA_MPC_WRITE, + /* MPC Cmd to Read and Clear Action/Lookup cache line (max 1 line) */ + CFA_MPC_READ_CLR, + /* MPC Cmd to Invalidate Action/Lkup cache lines (up to 4 lines) */ + CFA_MPC_INVALIDATE, + + /** + * MPC EM update commands + */ + /** + * MPC Command to search for an EM entry by its key in the + * EM bucket chain + */ + CFA_MPC_EM_SEARCH, + /* MPC command to insert a new EM entry to the EM bucket chain */ + CFA_MPC_EM_INSERT, + /* MPC Command to delete an EM entry from the EM bucket chain */ + CFA_MPC_EM_DELETE, + /* MPC Command to add an EM bucket to the tail of EM bucket chain */ + CFA_MPC_EM_CHAIN, + CFA_MPC_OPC_MAX, +}; + +/** + * CFA MPC Cache access reading mode + */ +enum cfa_mpc_read_mode { + CFA_MPC_RD_NORMAL, /**< Normal read mode */ + CFA_MPC_RD_EVICT, /**< Read the cache and evict the cache line */ + CFA_MPC_RD_DEBUG_LINE, /**< Debug read mode line */ + CFA_MPC_RD_DEBUG_TAG, /**< Debug read mode tag */ + CFA_MPC_RD_MODE_MAX +}; + +/** + * CFA MPC Cache access writing mode + */ +enum cfa_mpc_write_mode { + CFA_MPC_WR_WRITE_THRU, /**< Write to cache in Write through mode */ + CFA_MPC_WR_WRITE_BACK, /**< Write to cache in Write back mode */ + CFA_MPC_WR_MODE_MAX +}; + +/** + * CFA MPC Cache access eviction mode + */ +enum cfa_mpc_evict_mode { + /** + * Line evict: These modes evict a single cache line + * In these modes, the eviction occurs regardless of the cache line + * state (CLEAN/CLEAN_FAST_EVICT/DIRTY) + */ + /* Cache line addressed by set/way is evicted */ + CFA_MPC_EV_EVICT_LINE, + /* Cache line hit with the table scope/address tuple is evicted */ + CFA_MPC_EV_EVICT_SCOPE_ADDRESS, + + /** + * Set Evict: These modes evict cache lines that meet certain criteria + * from the entire cache set. + */ + /* + * Cache lines only in CLEAN state are evicted from the set + * derived from the address + */ + CFA_MPC_EV_EVICT_CLEAN_LINES, + /* + * Cache lines only in CLEAN_FAST_EVICT state are evicted from + * the set derived from the address + */ + CFA_MPC_EV_EVICT_CLEAN_FAST_EVICT_LINES, + /* + * Cache lines in both CLEAN and CLEAN_FAST_EVICT states are + * evicted from the set derived from the address + */ + CFA_MPC_EV_EVICT_CLEAN_AND_CLEAN_FAST_EVICT_LINES, + /* + * All Cache lines in the set identified by the address and + * belonging to the table scope are evicted. + */ + CFA_MPC_EV_EVICT_TABLE_SCOPE, + CFA_MPC_EV_MODE_MAX, +}; + +/** + * CFA Hardware Cache Table Type + */ +enum cfa_hw_table_type { + CFA_HW_TABLE_ACTION, /**< CFA Action Record Table */ + CFA_HW_TABLE_LOOKUP, /**< CFA EM Lookup Record Table */ + CFA_HW_TABLE_MAX +}; + +/** + * MPC Command parameters specific to Cache read operations + */ +struct cfa_mpc_cache_read_params { + /* Specifies the cache option for reading the cache lines */ + enum cfa_mpc_read_mode mode; + /** + * Clear mask to use for the Read-Clear operation + * Each bit in the mask correspond to 2 bytes in the + * cache line. Setting the corresponding mask bit, clears + * the corresponding data bytes in the cache line AFTER + * the read. This field is ignored for Read CMD. + */ + uint16_t clear_mask; + /** + * External host memory address + * + * The 64-bit IOVA host address to which to write the DMA data returned + * in the completion. The data will be written to the same function as + * the one that owns the queue this command is read from. Address must + * be 4 byte aligned. + */ + uint64_t host_address; +}; + +/** + * MPC Command parameters specific to Cache write operation + */ +struct cfa_mpc_cache_write_params { + /* Specifies the cache option for the write access */ + enum cfa_mpc_write_mode mode; + /* Pointer to data to be written to cache */ + const uint8_t *data_ptr; +}; + +/** + * MPC Command parameters specific to Cache evict/invalidate operation + */ +struct cfa_mpc_cache_evict_params { + /* Specifies the cache option for Invalidation operation */ + enum cfa_mpc_evict_mode mode; +}; + +/** + * MPC CFA Command parameters for cache related operations + */ +struct cfa_mpc_cache_axs_params { + /** Common parameters for cache operations */ + /* + * Opaque value that will be returned in the MPC CFA + * Completion message. This can be used by the caller to associate + * completions with commands. + */ + uint32_t opaque; + /* + * Table Scope to address the cache line. For Thor2 + * the table scope goes for 0 - 31. + */ + uint8_t tbl_scope; + /* + * Table Index to address the cache line. Note that + * this is the offset to the 32B record in the table + * scope backing store, expressed in 32B units. + */ + uint32_t tbl_index; + /* + * Number of cache lines (32B word) in the access + * This should be set to 1 for READ-CLEAR command and between 1 and + * 4 for all other cache access commands (READ/WRITE/INVALIDATE) + */ + uint8_t data_size; + /* CFA table type for which this Host IF hw operation is intended for */ + enum cfa_hw_table_type tbl_type; + + /* Cache operation specific params */ + union { + /** Read and Read clear specific parameters */ + struct cfa_mpc_cache_read_params read; + /** Cache write specific parameters */ + struct cfa_mpc_cache_write_params write; + /** Cache invalidate operation specific parameters */ + struct cfa_mpc_cache_evict_params evict; + }; +}; + +/** + * MPC CFA command parameters specific to EM insert operation + */ +struct cfa_mpc_em_insert_params { + /* + * Pointer to the Exact Match entry to search. The + * EM Key in the entry is used to for the search + */ + const uint8_t *em_entry; + /* Size of the EM entry in 32B words (1- 4) */ + uint8_t data_size; + /* Flag to indicate if a matching entry (if found) should be replaced */ + bool replace; + /* Table index to write the EM entry being inserted */ + uint32_t entry_idx; + /* + * Table index to the EM record that can be used to + * create a new EM bucket, if the insertion results + * in a EM bucket chain's tail update. + */ + uint32_t bucket_idx; +}; + +/** + * MPC CFA command parameters specific to EM search operation + */ +struct cfa_mpc_em_search_params { + /* + * Pointer to the Exact Match entry to search. The + * EM Key in the entry is used to for the search + */ + uint8_t *em_entry; + /* Size of the EM entry in 32B words (1- 4) */ + uint8_t data_size; +}; + +/** + * MPC CFA command parameters specific to EM delete operation + */ +struct cfa_mpc_em_delete_params { + /* Table index to the EM record to delete */ + uint32_t entry_idx; + /* + * Table index to the static bucket for the EM bucket chain. + * As part of EM Delete processing, the hw walks the EM bucket + * chain to determine if the entry_idx is part of the chain. + * If the entry_idx is found to be a part of the chain, it is + * deleted from the chain and the EM bucket is repacked. If the + * tail of the bucket has only one valid entry, then the delete + * operation results in a tail update and one free EM entry + */ + uint32_t bucket_idx; +}; + +/** + * MPC CFA command parameters specific to EM chain operation + */ +struct cfa_mpc_em_chain_params { + /* + * Table index that will form the chain + * pointer to the tail bucket in the EM bucket chain + */ + uint32_t entry_idx; + /* + * Table index to the static bucket for + * EM bucket chain to be updated. + */ + uint32_t bucket_idx; +}; + +/** + * MPC CFA Command parameters for EM operations + */ +struct cfa_mpc_em_op_params { + /** Common parameters for EM update operations */ + /* + * Opaque value that will be returned in the MPC CFA + * Completion message. This can be used by the caller to associate + * completions with commands. + */ + uint32_t opaque; + /* + * Table Scope to address the cache line. For Thor2 + * the table scope goes for 0 - 31. + */ + uint8_t tbl_scope; + /** EM update operation specific params */ + union { + /** EM Search operation params */ + struct cfa_mpc_em_search_params search; + /** EM Insert operation params */ + struct cfa_mpc_em_insert_params insert; + /** EM Delete operation params */ + struct cfa_mpc_em_delete_params del; + /** EM Chain operation params */ + struct cfa_mpc_em_chain_params chain; + }; +}; + +/** + * MPC CFA Command completion status + */ +enum cfa_mpc_cmpl_status { + /* Command success */ + CFA_MPC_OK = 0, + /* Unsupported CFA opcode */ + CFA_MPC_UNSPRT_ERR = 1, + /* CFA command format error */ + CFA_MPC_FMT_ERR = 2, + /* SVIF-Table Scope error */ + CFA_MPC_SCOPE_ERR = 3, + /* Address error: Only used if EM command or TABLE_TYPE=EM */ + CFA_MPC_ADDR_ERR = 4, + /* Cache operation error */ + CFA_MPC_CACHE_ERR = 5, + /* EM_SEARCH or EM_DELETE did not find a matching EM entry */ + CFA_MPC_EM_MISS = 6, + /* EM_INSERT found a matching EM entry and REPLACE=0 in the command */ + CFA_MPC_EM_DUPLICATE = 7, + /* EM_EVENT_COLLECTION_FAIL no events to return */ + CFA_MPC_EM_EVENT_COLLECTION_FAIL = 8, + /* + * EM_INSERT required a dynamic bucket to be added to the chain + * to successfully insert the EM entry, but the entry provided + * for use as dynamic bucket was invalid. (bucket_idx == 0) + */ + CFA_MPC_EM_ABORT = 9, +}; + +/** + * MPC Cache access command completion result + */ +struct cfa_mpc_cache_axs_result { + /* + * Opaque value returned in the completion message. This can + * be used by the caller to associate completions with commands. + */ + uint32_t opaque; + /* MPC Command completion status code */ + enum cfa_mpc_cmpl_status status; + /* + * Additional error information + * when status code is one of FMT, SCOPE, ADDR or CACHE error + */ + uint32_t error_data; + /* + * Pointer to buffer to copy read data to. + * Needs to be valid for READ, READ-CLEAR operations + * Not set for write and evict operations + */ + uint8_t *rd_data; + /* + * Size of the data buffer in Bytes. Should be at least + * be data_size * 32 for MPC cache reads + */ + uint16_t data_len; +}; + +/** + * MPC EM search operation result + */ +struct cfa_mpc_em_search_result { + uint32_t bucket_num; /**< See CFA EAS */ + uint32_t num_entries; /**< See CFA EAS */ + /* Set to HASH[35:24] of the hash computed from the EM entry key. */ + uint32_t hash_msb; + /* + * IF a match is found, this field is set + * to the table index of the matching EM entry + */ + uint32_t match_idx; + /* + * Table index to the static bucket determined by hashing the EM entry + * key + */ + uint32_t bucket_idx; +}; + +/** + * MPC EM insert operation result + */ +struct cfa_mpc_em_insert_result { + uint32_t bucket_num; /**< See CFA EAS */ + uint32_t num_entries; /**< See CFA EAS */ + /* Set to HASH[35:24] of the hash computed from the EM entry key. */ + uint32_t hash_msb; + /* + * If replace = 1 and a matchng entry is found, this field is + * updated with the table index of the replaced entry. This table + * index is therefore free for use. + */ + uint32_t match_idx; + /* + * Table index to the static bucket determined by hashing the EM entry + * key + */ + uint32_t bucket_idx; + /* Flag: Matching entry was found and replace */ + uint8_t replaced : 1; + /* Flag: EM bucket chain was updated */ + uint8_t chain_update : 1; +}; + +/** + * MPC EM delete operation result + */ +struct cfa_mpc_em_delete_result { + uint32_t bucket_num; /**< See CFA EAS */ + uint32_t num_entries; /**< See CFA EAS */ + /* + * Table index to EM bucket tail BEFORE the delete command + * was processed with a OK or EM_MISS status. If chain update = 1, then + * this bucket can be freed + */ + uint32_t prev_tail; + /* + * Table index to EM bucket tail AFTER the delete command + * was processed with a OK or EM_MISS status. Same as prev_tail + * if chain_update = 0. + */ + uint32_t new_tail; + /* Flag: EM bucket chain was updated */ + uint8_t chain_update : 1; +}; + +/** + * MPC EM chain operation result + */ +struct cfa_mpc_em_chain_result { + uint32_t bucket_num; /**< See CFA EAS */ + uint32_t num_entries; /**< See CFA EAS */ +}; + +/** + * MPC EM operation completion result + */ +struct cfa_mpc_em_op_result { + /* + * Opaque value returned in the completion message. This can + * be used by the caller to associate completions with commands. + */ + uint32_t opaque; + /* MPC Command completion status code */ + enum cfa_mpc_cmpl_status status; + /* + * Additional error information + * when status code is one of FMT, SCOPE, ADDR or CACHE error + */ + uint32_t error_data; + union { + /** EM Search specific results */ + struct cfa_mpc_em_search_result search; + /** EM Insert specific results */ + struct cfa_mpc_em_insert_result insert; + /** EM Delete specific results */ + struct cfa_mpc_em_delete_result del; + /** EM Chain specific results */ + struct cfa_mpc_em_chain_result chain; + }; +}; + +/** + * Build MPC CFA Cache access command + * + * @param [in] opc MPC opcode + * + * @param [out] cmd_buff Command data buffer to write the command to + * + * @param [in/out] cmd_buff_len Pointer to command buffer size param + * Set by caller to indicate the input cmd_buff size. + * Set to the actual size of the command generated by the api. + * + * @param [in] parms Pointer to MPC cache access command parameters + * + * @return 0 on Success, negative errno on failure + */ +int cfa_mpc_build_cache_axs_cmd(enum cfa_mpc_opcode opc, uint8_t *cmd_buff, + uint32_t *cmd_buff_len, + struct cfa_mpc_cache_axs_params *parms); + +/** + * Parse MPC CFA Cache access command completion result + * + * @param [in] opc MPC cache access opcode + * + * @param [in] resp_buff Data buffer containing the response to parse + * + * @param [in] resp_buff_len Response buffer size + * + * @param [out] result Pointer to MPC cache access result object. This + * object will contain the fields parsed and extracted from the + * response buffer. + * + * @return 0 on Success, negative errno on failure + */ +int cfa_mpc_parse_cache_axs_resp(enum cfa_mpc_opcode opc, uint8_t *resp_buff, + uint32_t resp_buff_len, + struct cfa_mpc_cache_axs_result *result); + +/** + * Build MPC CFA EM operation command + * + * @param [in] opc MPC EM opcode + * + * @param [in] cmd_buff Command data buffer to write the command to + * + * @param [in/out] cmd_buff_len Pointer to command buffer size param + * Set by caller to indicate the input cmd_buff size. + * Set to the actual size of the command generated by the api. + * + * @param [in] parms Pointer to MPC cache access command parameters + * + * @return 0 on Success, negative errno on failure + */ +int cfa_mpc_build_em_op_cmd(enum cfa_mpc_opcode opc, uint8_t *cmd_buff, + uint32_t *cmd_buff_len, + struct cfa_mpc_em_op_params *parms); + +/** + * Parse MPC CFA EM operation command completion result + * + * @param [in] opc MPC cache access opcode + * + * @param [in] resp_buff Data buffer containing the response to parse + * + * @param [in] resp_buff_len Response buffer size + * + * @param [out] result Pointer to MPC EM operation result object. This + * object will contain the fields parsed and extracted from the + * response buffer. + * + * @return 0 on Success, negative errno on failure + */ +int cfa_mpc_parse_em_op_resp(enum cfa_mpc_opcode opc, uint8_t *resp_buff, + uint32_t resp_buff_len, + struct cfa_mpc_em_op_result *result); + +#endif /* _CFA_BLD_P70_MPC_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70.h new file mode 100644 index 0000000000..5119813cc5 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70.h @@ -0,0 +1,164 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file + * + * @brief + */ + +#ifndef _CFA_P70_H_ +#define _CFA_P70_H_ + +#include "sys_util.h" +#include "cfa_p70_hw.h" + +#define BITS_TO_BYTES(n) (((n) + 7) / 8) +#define BYTES_TO_WORDS(n) (((n) + 3) / 4) + +/* EM Lrec size */ +#define CFA_P70_EM_LREC_SZ CFA_P70_EM_LREC_TOTAL_NUM_BITS +/* Encap header length */ +#define CFA_P70_ACT_ENCAP_MIN_HDR_LEN 64 +/* Max AR pointers per MCG record */ +#define CFA_P70_ACT_MCG_MAX_AR_PTR 8 +/* Max Key fields */ +#define CFA_P70_KEY_FLD_ID_MAX CFA_P70_EM_KEY_LAYOUT_MAX_FLD + +/* profiler ILT, l2ctxt remap, and profile remap are 32-bit accessed */ +#define CFA_PROF_P7P0_ILT_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_PROF_ILT_DR_TOTAL_NUM_BITS) +#define CFA_PROF_P7P0_L2_CTXT_RMP_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_PROF_L2_CTXT_RMP_DR_TOTAL_NUM_BITS) +#define CFA_PROF_P7P0_PROFILE_RMP_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_PROF_PROFILE_RMP_DR_TOTAL_NUM_BITS) +/* profiler TCAM and L2 ctxt TCAM are accessed via Wide-bus */ +#define CFA_PROF_P7P0_PROFILE_TCAM_NUM_WORDS \ + NUM_WORDS_ALIGN_128BIT(CFA_P70_PROF_PROFILE_TCAM_TOTAL_NUM_BITS) +#define CFA_PROF_P7P0_L2_CTXT_TCAM_NUM_WORDS \ + NUM_WORDS_ALIGN_128BIT(CFA_P70_PROF_L2_CTXT_TCAM_TOTAL_NUM_BITS) +/* FKB are accessed via Wide-bus */ +#define CFA_P70_EM_FKB_NUM_WORDS NUM_WORDS_ALIGN_128BIT(CFA_P70_EM_FKB_MAX_FLD) +#define CFA_P70_EM_FKB_NUM_ENTRIES 128 + +/* EM FKB Mask */ +/* EM_FKB_MASK total num bits defined in CFA EAS section 3.3.9.2.2 EM Key */ +#define CFA_P70_EM_FKB_MASK_TOTAL_NUM_BITS 896 +#define CFA_P70_EM_FKB_MASK_NUM_WORDS \ + NUM_WORDS_ALIGN_128BIT(CFA_P70_EM_FKB_MASK_TOTAL_NUM_BITS) +#define CFA_P70_EM_FKB_MASK_NUM_ENTRIES 128 + +#define CFA_P70_WC_TCAM_FKB_NUM_WORDS \ + NUM_WORDS_ALIGN_128BIT(CFA_P70_WC_TCAM_FKB_MAX_FLD) +#define CFA_P70_WC_TCAM_FKB_NUM_ENTRIES 128 +/* VNIC-SVIF Properties Table are accessed via Wide-bus */ +#define CFA_ACT_P7P0_VSPT_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_ACT_VSPT_DR_TX_TOTAL_NUM_BITS) +#define CFA_P70_ACT_VEB_TCAM_NUM_WORDS \ + NUM_WORDS_ALIGN_128BIT(CFA_P70_ACT_VEB_TCAM_RX_TOTAL_NUM_BITS) +#define CFA_P70_ACT_MIRROR_NUM_WORDS \ + NUM_WORDS_ALIGN_128BIT(CFA_P70_ACT_MIRROR_TOTAL_NUM_BITS) +#define CFA_P7P0_ACT_VEB_RMP_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_ACT_VEB_RMP_TOTAL_NUM_BITS) +#define CFA_P7P0_ACT_LBT_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_ACT_LBT_DR_TOTAL_NUM_BITS) +#define CFA_P70_LKUP_EM_ENTRY_SIZE_IN_BITS 256 +#define CFA_P70_LKUP_EM_MAX_ENTRIES 4 +#define CFA_P70_LKUP_EM_MAX_ENTRY_SIZE_IN_BITS \ + (CFA_P70_LKUP_EM_ENTRY_SIZE_IN_BITS * CFA_P70_LKUP_EM_MAX_ENTRIES) +/* Maximum EM key size in bits */ +#define CFA_P70_LKUP_EM_DATA_SIZE_IN_BITS \ + (CFA_P70_LKUP_EM_MAX_ENTRY_SIZE_IN_BITS - CFA_P70_EM_LREC_SZ) +#define CFA_P70_LKUP_WC_DATA_SIZE_IN_BITS 688 +#define CFA_P70_LKUP_WC_DATA_SIZE_WITH_CTRL_INFO_IN_BITS 700 +#define CFA_P70_LKUP_WC_DATA_SIZE \ + (BITS_TO_BYTES(CFA_P70_LKUP_WC_DATA_SIZE_IN_BITS)) +#define CFA_P70_LKUP_WC_MAX_DATA_SIZE \ + (BITS_TO_BYTES(CFA_P70_LKUP_WC_DATA_SIZE_WITH_CTRL_INFO_IN_BITS)) +#define CFA_P70_LKUP_WC_NUM_WORDS (BYTES_TO_WORDS(CFA_P70_LKUP_WC_DATA_SIZE)) +#define CFA_P70_LKUP_WC_NUM_WORDS_PER_BANK (CFA_P70_LKUP_WC_NUM_WORDS / 2) +#define CFA_P70_LKUP_WC_LREC_DATA_SIZE \ + (BITS_TO_BYTES(CFA_P70_WC_LREC_TOTAL_NUM_BITS)) +#define CFA_P70_LKUP_WC_LREC_NUM_WORDS \ + (BYTES_TO_WORDS(CFA_P70_LKUP_WC_LREC_DATA_SIZE)) +#define CFA_P70_LKUP_WC_SLICE_LEN_WITH_CTRL_INFO 175 +#define CFA_P70_LKUP_WC_SLICE_LEN 172 +#define CFA_P70_LKUP_WC_TCAM_IDX_MASK 0x1fff +#define CFA_P70_LKUP_WC_ROW_IDX_SFT 2 +#define CFA_P70_LKUP_WC_SLICE_IDX_MASK 0x3 +#define CFA_P70_LKUP_WC_NUM_SLICES 4 +#define CFA_P70_LKUP_WC_NUM_SLICES_PER_BANK 2 +#define CFA_P70_LKUP_WC_TCAM_CTRL_172B_KEY 0 +#define CFA_P70_LKUP_WC_TCAM_CTRL_344B_KEY 1 +#define CFA_P70_LKUP_WC_TCAM_CTRL_688B_KEY 2 +#define CFA_P70_LKUP_WC_TCAM_CTRL_MODE_SFT 29 +#define CFA_P70_LKUP_WC_TCAM_CTRL_MODE_MASK 0x3 +#define CFA_P70_LKUP_WC_TCAM_CTRL_VALID_SFT 31 +#define CFA_P70_LKUP_WC_TCAM_CTRL_VALID_MASK 0x1 +#define CFA_P70_LKUP_WC_TCAM_CTRL_NUM_BITS 3 +#define CFA_P70_LKUP_WC_TCAM_CTRL_MODE_NUM_BITS 2 +#define GET_NUM_SLICES_FROM_MODE(mode) (1 << (mode)) +#define CFA_P70_LKUP_WC_SLICE_NUM_BYTES \ + (BITS_TO_BYTES(CFA_P70_LKUP_WC_SLICE_LEN_WITH_CTRL_INFO)) +#define CFA_P70_LKUP_WC_SLICE_NUM_WORDS \ + (BYTES_TO_WORDS(CFA_P70_LKUP_WC_SLICE_NUM_BYTES)) +#define CFA_P70_WC_TCAM_GET_NUM_SLICES_FROM_NUM_BYTES(n) \ + ((((n) << 3) + CFA_P70_LKUP_WC_SLICE_LEN_WITH_CTRL_INFO - 1) / \ + CFA_P70_LKUP_WC_SLICE_LEN_WITH_CTRL_INFO) +#define CFA_MASK32(N) (((N) < 32) ? ((1U << (N)) - 1) : 0xffffffff) +#define CFA_P70_ECV_VTAG_ADD0_IMMED CFA_P70_ECV_VTAG_ADD0_IMMED_PRI0 +#define CFA_P70_ECV_VTAG_PRI_MASK \ + (~CFA_P70_ECV_VTAG_ADD0_IMMED & \ + CFA_MASK32(CFA_P70_ACT_ENC_ECV_VTAG_NUM_BITS)) + +#define CFA_P70_LKUP_EPOCH0_NUM_WORDS 1 +#define CFA_P70_LKUP_EPOCH1_NUM_WORDS 1 +#define CFA_P70_LKUP_EPOCH0_ENTRIES 4096 +#define CFA_P70_LKUP_EPOCH1_ENTRIES 256 + +/* Field range check table register widths */ +#define CFA_P70_FRC_PROF_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_LKUP_FRC_PROFILE_TOTAL_NUM_BITS) +#define CFA_P70_FRC_ENTRY_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_LKUP_FRC_RANGE_TOTAL_NUM_BITS) + +/* Connection tracking table register widths */ +#define CFA_P70_CT_STATE_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_LKUP_CT_STATE_TOTAL_NUM_BITS) +#define CFA_P70_CT_RULE_TCAM_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_LKUP_CT_RULE_TOTAL_NUM_BITS) +#define CFA_P70_CT_RULE_TCAM_RMP_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_LKUP_CT_RULE_RECORD_TOTAL_NUM_BITS) + +/* Feature Chain table register widths */ +#define CFA_P70_ACT_FC_TCAM_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_ACT_FC_TCAM_TOTAL_NUM_BITS) +#define CFA_P70_ACT_FC_TCAM_RMP_NUM_WORDS \ + NUM_WORDS_ALIGN_32BIT(CFA_P70_ACT_FC_TCAM_RESULT_TOTAL_NUM_BITS) +/* Feature Context table register width */ +#define CFA_P70_ACT_FC_NUM_WORDS \ + NUM_WORDS_ALIGN_128BIT(CFA_P70_ACT_FC_RMP_DR_TOTAL_NUM_BITS) + +/* Meter instance table register width */ +#define CFA_P70_ACT_METER_NUM_WORDS \ + NUM_WORDS_ALIGN_128BIT(CFA_P70_METERS_TOTAL_NUM_BITS) + +/* Metadata Mask table register widths */ +#define CFA_P70_METAMASK_PROF_NUM_WORDS 1 +#define CFA_P70_METAMASK_LKUP_NUM_WORDS 1 +#define CFA_P70_METAMASK_ACT_NUM_WORDS 1 +#define MAX_METAMASK_PROF(chip_cfg) 8 +#define MAX_METAMASK_LKUP(chip_cfg) 8 +#define MAX_METAMASK_ACT(chip_cfg) 16 + +#define CFA_P70_VEB_TCAM_NUM_SLICES 1 +#define CFA_P70_CT_TCAM_NUM_SLICES 1 +#define CFA_P70_FC_TCAM_NUM_SLICES 1 +#define CFA_P70_L2CTXT_TCAM_NUM_SLICES 1 +#define CFA_P70_PROF_TCAM_NUM_SLICES 1 + +#endif /* _CFA_P70_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70_hw.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70_hw.h new file mode 100644 index 0000000000..a6df5be179 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70_hw.h @@ -0,0 +1,4286 @@ +/**************************************************************************** + * Copyright(c) 2001-2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * Name: cfa_p70_hw.h + * + * Description: CFA HW table layout field position/length definitions + * + * Date: 09/29/22 11:50:37 + * + * Note: This file is scripted generated by ./cfa_header_gen.py. + * DO NOT modify this file manually !!!! + * + ****************************************************************************/ +#ifndef _CFA_P70_HW_H_ +#define _CFA_P70_HW_H_ + +/* clang-format off */ +#include "cfa_bld_p70_field_ids.h" + + +/** + * Field code selection 1 for range checking (for idx 1 ...) + */ +#define CFA_P70_LKUP_FRC_PROFILE_FIELD_SEL_1_BITPOS 36 +#define CFA_P70_LKUP_FRC_PROFILE_FIELD_SEL_1_NUM_BITS 4 + +/** + * Mask of ranges to check against FIELD_SEL_1 + */ +#define CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_1_BITPOS 20 +#define CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_1_NUM_BITS 16 + +/** + * Field code selection 0 for range checking + */ +#define CFA_P70_LKUP_FRC_PROFILE_FIELD_SEL_0_BITPOS 16 +#define CFA_P70_LKUP_FRC_PROFILE_FIELD_SEL_0_NUM_BITS 4 + +/** + * Mask of ranges to check against FIELD_SEL_0 The following shows the + * FIELD_SEL code points: + */ +#define CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_BITPOS 0 +#define CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_NUM_BITS 16 +/** + * Mask of ranges to check against FIELD_SEL_0 The following shows the + * FIELD_SEL code points: + */ +enum cfa_p70_lkup_frc_profile_range_check_0 { + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_TL2_OVLAN_VID = 0, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_TL2_IVLAN_VID = 1, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_TL4_SRC = 2, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_TL4_DEST = 3, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_L2_OVLAN_VID = 4, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_L2_IVLAN_VID = 5, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_IP_LENGTH = 6, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_L4_SRC = 7, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_L4_DEST = 8, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_TUN_ID = 9, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_TUN_CTXT = 10, + CFA_P70_LKUP_FRC_PROFILE_RANGE_CHECK_0_0 = 15, +}; + +/** + * Total number of bits for LKUP_FRC_PROFILE + */ +#define CFA_P70_LKUP_FRC_PROFILE_TOTAL_NUM_BITS 40 + +/** + * When 1, block rule searches and do host notify during background + * visit + */ +#define CFA_P70_LKUP_CT_STATE_NOTIFY_BITPOS 13 +#define CFA_P70_LKUP_CT_STATE_NOTIFY_NUM_BITS 1 + +/** + * Next state to go to after host notify (only used when NOTIFY=1) + */ +#define CFA_P70_LKUP_CT_STATE_NOTIFY_STATE_BITPOS 8 +#define CFA_P70_LKUP_CT_STATE_NOTIFY_STATE_NUM_BITS 5 + +/** + * Default forwarding action (0=fwd, 1=miss, 2/3=copy) + */ +#define CFA_P70_LKUP_CT_STATE_ACTION_BITPOS 6 +#define CFA_P70_LKUP_CT_STATE_ACTION_NUM_BITS 2 + +/** + * Specifies timer (0=disabled, 1-3=timers 1-3) + */ +#define CFA_P70_LKUP_CT_STATE_TIMER_SELECT_BITPOS 4 +#define CFA_P70_LKUP_CT_STATE_TIMER_SELECT_NUM_BITS 2 + +/** + * Timer preload value for connections in this state + */ +#define CFA_P70_LKUP_CT_STATE_TIMER_PRELOAD_BITPOS 0 +#define CFA_P70_LKUP_CT_STATE_TIMER_PRELOAD_NUM_BITS 4 + +/** + * Total number of bits for LKUP_CT_STATE + */ +#define CFA_P70_LKUP_CT_STATE_TOTAL_NUM_BITS 14 + +/** + * Rule only used if VALID=1 (for idx 1 ...) + */ +#define CFA_P70_LKUP_CT_RULE_VALID_BITPOS 38 +#define CFA_P70_LKUP_CT_RULE_VALID_NUM_BITS 1 + +/** + * Mask + */ +#define CFA_P70_LKUP_CT_RULE_MASK_BITPOS 19 +#define CFA_P70_LKUP_CT_RULE_MASK_NUM_BITS 19 + +/** + * Rule for packet (1) or background (0) + */ +#define CFA_P70_LKUP_CT_RULE_PKT_NOT_BG_BITPOS 18 +#define CFA_P70_LKUP_CT_RULE_PKT_NOT_BG_NUM_BITS 1 + +/** + * Current connection state + */ +#define CFA_P70_LKUP_CT_RULE_STATE_BITPOS 13 +#define CFA_P70_LKUP_CT_RULE_STATE_NUM_BITS 5 + +/** + * TCP packet flags + */ +#define CFA_P70_LKUP_CT_RULE_TCP_FLAGS_BITPOS 4 +#define CFA_P70_LKUP_CT_RULE_TCP_FLAGS_NUM_BITS 9 + +/** + * Packet protocol is TCP + */ +#define CFA_P70_LKUP_CT_RULE_PROT_IS_TCP_BITPOS 3 +#define CFA_P70_LKUP_CT_RULE_PROT_IS_TCP_NUM_BITS 1 + +/** + * Updating tcp_msb_loc + */ +#define CFA_P70_LKUP_CT_RULE_MSB_UPDT_BITPOS 2 +#define CFA_P70_LKUP_CT_RULE_MSB_UPDT_NUM_BITS 1 + +/** + * Packet flag error + */ +#define CFA_P70_LKUP_CT_RULE_FLAGS_FAILED_BITPOS 1 +#define CFA_P70_LKUP_CT_RULE_FLAGS_FAILED_NUM_BITS 1 + +/** + * Packet failed TCP window check If VALID=0, the rule is ignored during + * searches. When VALID=1, MASK[18:0] provides a mask for bits 18:0. If + * the mask bit is set to 0, the corresponding bit is ignored during + * searches (does not need to match for the rule to match). During + * background updates, all fields in the search key other than STATE are + * always 0 (PKT_NOT_BG=0 and the other fields are unused). During + * packet updates when PROT_IS_TCP=0, PKT_NOT_BG=1 and STATE is set to + * the current state but the other fields will always be 0. If there is + * a matching rule found, the record in LKUP_CT_RULE_RECORD for that + * rule number is used. + */ +#define CFA_P70_LKUP_CT_RULE_WIN_FAILED_BITPOS 0 +#define CFA_P70_LKUP_CT_RULE_WIN_FAILED_NUM_BITS 1 + +/** + * Total number of bits for LKUP_CT_RULE + */ +#define CFA_P70_LKUP_CT_RULE_TOTAL_NUM_BITS 39 + +/** + * Forward action (packet only): 0=fwd, 1=miss, 2/3=copy + */ +#define CFA_P70_LKUP_CT_RULE_RECORD_ACTION_BITPOS 7 +#define CFA_P70_LKUP_CT_RULE_RECORD_ACTION_NUM_BITS 2 + +/** + * Next state for the connection + */ +#define CFA_P70_LKUP_CT_RULE_RECORD_NEXT_STATE_BITPOS 2 +#define CFA_P70_LKUP_CT_RULE_RECORD_NEXT_STATE_NUM_BITS 5 + +/** + * Signals whether to send message to other CFA.k When SEND=0, no + * message is sent. Otherwise, SEND[1] indicates that TCP_MSB_LOC in the + * message is valid and SEND[0] that STATE is valid. + */ +#define CFA_P70_LKUP_CT_RULE_RECORD_SEND_BITPOS 0 +#define CFA_P70_LKUP_CT_RULE_RECORD_SEND_NUM_BITS 2 + +/** + * Total number of bits for LKUP_CT_RULE_RECORD + */ +#define CFA_P70_LKUP_CT_RULE_RECORD_TOTAL_NUM_BITS 9 + +/** + * destination remap mode when enabled + */ +#define CFA_P70_ACT_VEB_RMP_MODE_BITPOS 6 +#define CFA_P70_ACT_VEB_RMP_MODE_NUM_BITS 1 +/** + * destination remap mode when enabled + */ +enum cfa_p70_act_veb_rmp_mode { + /* over write existing bitmap with entry */ + CFA_P70_ACT_VEB_RMP_MODE_OVRWRT = 0, + /* or entry bit map with existing */ + CFA_P70_ACT_VEB_RMP_MODE_ORTGTHR = 1, +}; + +/** + * enable remap the bitmap + */ +#define CFA_P70_ACT_VEB_RMP_ENABLE_BITPOS 5 +#define CFA_P70_ACT_VEB_RMP_ENABLE_NUM_BITS 1 + +/** + * destination bitmap #CAS_SW_REF + * Action.CFA.VEB.Remap.tx.veb.remap.entry + */ +#define CFA_P70_ACT_VEB_RMP_BITMAP_BITPOS 0 +#define CFA_P70_ACT_VEB_RMP_BITMAP_NUM_BITS 5 + +/** + * Total number of bits for ACT_VEB_RMP + */ +#define CFA_P70_ACT_VEB_RMP_TOTAL_NUM_BITS 7 + +/** + * Range low + */ +#define CFA_P70_LKUP_FRC_RANGE_RANGE_LO_BITPOS 16 +#define CFA_P70_LKUP_FRC_RANGE_RANGE_LO_NUM_BITS 16 + +/** + * Range high Field matches range when in [range_lo, range_hi] + * (inclusive). A read/write to this register causes a read/write to the + * LKUP_FRC_RANGE memory at address LKUP_FRC_RANGE_ADDR. + */ +#define CFA_P70_LKUP_FRC_RANGE_RANGE_HI_BITPOS 0 +#define CFA_P70_LKUP_FRC_RANGE_RANGE_HI_NUM_BITS 16 + +/** + * Total number of bits for LKUP_FRC_RANGE + */ +#define CFA_P70_LKUP_FRC_RANGE_TOTAL_NUM_BITS 32 + +/** + * TCAM entry is valid (for idx 7 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_VALID_BITPOS 255 +#define CFA_P70_PROF_L2_CTXT_TCAM_VALID_NUM_BITS 1 + +/** + * spare bits (for idx 7 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_SPARE_BITPOS 253 +#define CFA_P70_PROF_L2_CTXT_TCAM_SPARE_NUM_BITS 2 + +/** + * Multi-pass cycle count (for idx 7 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_MPASS_CNT_BITPOS 251 +#define CFA_P70_PROF_L2_CTXT_TCAM_MPASS_CNT_NUM_BITS 2 + +/** + * Recycle count from prof_in (for idx 7 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_RCYC_BITPOS 247 +#define CFA_P70_PROF_L2_CTXT_TCAM_RCYC_NUM_BITS 4 + +/** + * loopback input from prof_in (for idx 7 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_LOOPBACK_BITPOS 246 +#define CFA_P70_PROF_L2_CTXT_TCAM_LOOPBACK_NUM_BITS 1 + +/** + * Source network port from prof_in (for idx 7 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_SPIF_BITPOS 244 +#define CFA_P70_PROF_L2_CTXT_TCAM_SPIF_NUM_BITS 2 + +/** + * Partition provided by input block (for idx 7 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_PARIF_BITPOS 239 +#define CFA_P70_PROF_L2_CTXT_TCAM_PARIF_NUM_BITS 5 + +/** + * Source network port or vnic (for idx 7 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_SVIF_BITPOS 228 +#define CFA_P70_PROF_L2_CTXT_TCAM_SVIF_NUM_BITS 11 + +/** + * Metadata provided by Input block + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_METADATA_BITPOS 196 +#define CFA_P70_PROF_L2_CTXT_TCAM_METADATA_NUM_BITS 32 + +/** + * L2 function + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_L2_FUNC_BITPOS 188 +#define CFA_P70_PROF_L2_CTXT_TCAM_L2_FUNC_NUM_BITS 8 + +/** + * ROCE Packet detected by the Parser (for idx 5 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_ROCE_BITPOS 187 +#define CFA_P70_PROF_L2_CTXT_TCAM_ROCE_NUM_BITS 1 + +/** + * Pure LLC Packet detected by the Parser. (for idx 5 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_PURE_LLC_BITPOS 186 +#define CFA_P70_PROF_L2_CTXT_TCAM_PURE_LLC_NUM_BITS 1 + +/** + * 5b enc Outer Tunnel Type (for idx 5 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_OT_HDR_TYPE_BITPOS 181 +#define CFA_P70_PROF_L2_CTXT_TCAM_OT_HDR_TYPE_NUM_BITS 5 + +/** + * 5b enc Tunnel Type The id_ctxt field is tunnel id or tunnel context + * selected from outer tunnel header or tunnel header. (for idx 5 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_T_HDR_TYPE_BITPOS 176 +#define CFA_P70_PROF_L2_CTXT_TCAM_T_HDR_TYPE_NUM_BITS 5 + +/** + * FLDS Tunnel Status ID or Context. Each of these fields are from the + * selected outer tunnel, tunnel, inner, or outermost L2 header + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_ID_CTXT_BITPOS 144 +#define CFA_P70_PROF_L2_CTXT_TCAM_ID_CTXT_NUM_BITS 32 + +/** + * Selected DMAC/SMAC + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_MAC0_BITPOS 96 +#define CFA_P70_PROF_L2_CTXT_TCAM_MAC0_NUM_BITS 48 + +/** + * Selected DMAC/SMAC + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_MAC1_BITPOS 48 +#define CFA_P70_PROF_L2_CTXT_TCAM_MAC1_NUM_BITS 48 + +/** + * 1+ VLAN tags present (for idx 1 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_VTAG_PRESENT_BITPOS 47 +#define CFA_P70_PROF_L2_CTXT_TCAM_VTAG_PRESENT_NUM_BITS 1 + +/** + * 2 VLAN tags present (for idx 1 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_TWO_VTAGS_BITPOS 46 +#define CFA_P70_PROF_L2_CTXT_TCAM_TWO_VTAGS_NUM_BITS 1 + +/** + * Outer VLAN VID (for idx 1 ...) + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_OVLAN_VID_BITPOS 34 +#define CFA_P70_PROF_L2_CTXT_TCAM_OVLAN_VID_NUM_BITS 12 + +/** + * Outer VLAN TPID, 3b encoded + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_OVLAN_TPID_SEL_BITPOS 31 +#define CFA_P70_PROF_L2_CTXT_TCAM_OVLAN_TPID_SEL_NUM_BITS 3 + +/** + * Inner VLAN VID + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_IVLAN_VID_BITPOS 19 +#define CFA_P70_PROF_L2_CTXT_TCAM_IVLAN_VID_NUM_BITS 12 + +/** + * Inner VLAN TPID, 3b encoded + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_IVLAN_TPID_SEL_BITPOS 16 +#define CFA_P70_PROF_L2_CTXT_TCAM_IVLAN_TPID_SEL_NUM_BITS 3 + +/** + * Ethertype. #CAS_SW_REF Profiler.l2ip.context.tcam.key #CAS_SW_REF + * Profiler.l2ip.context.ipv6.tcam.key + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_ETYPE_BITPOS 0 +#define CFA_P70_PROF_L2_CTXT_TCAM_ETYPE_NUM_BITS 16 + +/** + * Total number of bits for PROF_L2_CTXT_TCAM + */ +#define CFA_P70_PROF_L2_CTXT_TCAM_TOTAL_NUM_BITS 256 + +/** + * Valid(1)/Invalid(0) TCAM entry. (for idx 5 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_VALID_BITPOS 183 +#define CFA_P70_PROF_PROFILE_TCAM_VALID_NUM_BITS 1 + +/** + * spare bits. (for idx 5 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_SPARE_BITPOS 181 +#define CFA_P70_PROF_PROFILE_TCAM_SPARE_NUM_BITS 2 + +/** + * Loopback bit. (for idx 5 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_LOOPBACK_BITPOS 180 +#define CFA_P70_PROF_PROFILE_TCAM_LOOPBACK_NUM_BITS 1 + +/** + * Packet type directly from prof_in (for idx 5 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_PKT_TYPE_BITPOS 176 +#define CFA_P70_PROF_PROFILE_TCAM_PKT_TYPE_NUM_BITS 4 + +/** + * Recycle count from prof_in (for idx 5 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_RCYC_BITPOS 172 +#define CFA_P70_PROF_PROFILE_TCAM_RCYC_NUM_BITS 4 + +/** + * From L2 Context Lookup stage. + */ +#define CFA_P70_PROF_PROFILE_TCAM_METADATA_BITPOS 140 +#define CFA_P70_PROF_PROFILE_TCAM_METADATA_NUM_BITS 32 + +/** + * Aggregate error flag from Input stage. (for idx 4 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_AGG_ERROR_BITPOS 139 +#define CFA_P70_PROF_PROFILE_TCAM_AGG_ERROR_NUM_BITS 1 + +/** + * L2 function (for idx 4 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_L2_FUNC_BITPOS 131 +#define CFA_P70_PROF_PROFILE_TCAM_L2_FUNC_NUM_BITS 8 + +/** + * Profile function from L2 Context Lookup stage. + */ +#define CFA_P70_PROF_PROFILE_TCAM_PROF_FUNC_BITPOS 123 +#define CFA_P70_PROF_PROFILE_TCAM_PROF_FUNC_NUM_BITS 8 + +/** + * From FLDS Input General Status tunnel(1)/no tunnel(0) (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_HREC_NEXT_BITPOS 121 +#define CFA_P70_PROF_PROFILE_TCAM_HREC_NEXT_NUM_BITS 2 + +/** + * INT header type. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_INT_HDR_TYPE_BITPOS 119 +#define CFA_P70_PROF_PROFILE_TCAM_INT_HDR_TYPE_NUM_BITS 2 + +/** + * INT header group. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_INT_HDR_GROUP_BITPOS 117 +#define CFA_P70_PROF_PROFILE_TCAM_INT_HDR_GROUP_NUM_BITS 2 + +/** + * INT metadata is tail stamp. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_INT_IFA_TAIL_BITPOS 116 +#define CFA_P70_PROF_PROFILE_TCAM_INT_IFA_TAIL_NUM_BITS 1 + +/** + * resolved flds_otl2_hdr_valid. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_HDR_VALID_BITPOS 115 +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_HDR_VALID_NUM_BITS 1 + +/** + * Outer Tunnel L2 header type. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_HDR_TYPE_BITPOS 113 +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_HDR_TYPE_NUM_BITS 2 + +/** + * flds_otl2_dst_type remapped: UC(0)/MC(2)/BC(3) (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_UC_MC_BC_BITPOS 111 +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_UC_MC_BC_NUM_BITS 2 + +/** + * 1+ VLAN tags present in Outer Tunnel L2 header (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_VTAG_PRESENT_BITPOS 110 +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_VTAG_PRESENT_NUM_BITS 1 + +/** + * 2 VLAN tags present in Outer Tunnel L2 header (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_TWO_VTAGS_BITPOS 109 +#define CFA_P70_PROF_PROFILE_TCAM_OTL2_TWO_VTAGS_NUM_BITS 1 + +/** + * resolved flds_otl3_hdr_valid. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_VALID_BITPOS 108 +#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_VALID_NUM_BITS 1 + +/** + * flds_otl3_hdr_valid is stop_w_error. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_ERROR_BITPOS 107 +#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_ERROR_NUM_BITS 1 + +/** + * Outer Tunnel L3 header type directly from FLDS. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_TYPE_BITPOS 103 +#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_TYPE_NUM_BITS 4 + +/** + * Outer Tunnel L3 header is IPV4 or IPV6. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_ISIP_BITPOS 102 +#define CFA_P70_PROF_PROFILE_TCAM_OTL3_HDR_ISIP_NUM_BITS 1 + +/** + * resolved flds_otl4_hdr_valid. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_VALID_BITPOS 101 +#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_VALID_NUM_BITS 1 + +/** + * flds_otl4_hdr_valid is stop_w_error. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_ERROR_BITPOS 100 +#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_ERROR_NUM_BITS 1 + +/** + * Outer Tunnel L4 header type. (for idx 3 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_TYPE_BITPOS 96 +#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_TYPE_NUM_BITS 4 + +/** + * OTL4 header is UDP or TCP. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_IS_UDP_TCP_BITPOS 95 +#define CFA_P70_PROF_PROFILE_TCAM_OTL4_HDR_IS_UDP_TCP_NUM_BITS 1 + +/** + * resolved flds_ot_hdr_valid. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_VALID_BITPOS 94 +#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_VALID_NUM_BITS 1 + +/** + * flds_ot_hdr_valid is stop_w_error. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_ERROR_BITPOS 93 +#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_ERROR_NUM_BITS 1 + +/** + * Outer Tunnel header type. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_TYPE_BITPOS 88 +#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_TYPE_NUM_BITS 5 + +/** + * Outer Tunnel header flags. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_FLAGS_BITPOS 80 +#define CFA_P70_PROF_PROFILE_TCAM_OT_HDR_FLAGS_NUM_BITS 8 + +/** + * resolved flds_tl2_hdr_valid. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL2_HDR_VALID_BITPOS 79 +#define CFA_P70_PROF_PROFILE_TCAM_TL2_HDR_VALID_NUM_BITS 1 + +/** + * Tunnel L2 header type directly from FLDS. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL2_HDR_TYPE_BITPOS 77 +#define CFA_P70_PROF_PROFILE_TCAM_TL2_HDR_TYPE_NUM_BITS 2 + +/** + * flds_tl2_dst_type remapped: UC(0)/MC(2)/BC(3) (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL2_UC_MC_BC_BITPOS 75 +#define CFA_P70_PROF_PROFILE_TCAM_TL2_UC_MC_BC_NUM_BITS 2 + +/** + * 1+ VLAN tags present in Tunnel L2 header (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_BITPOS 74 +#define CFA_P70_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_NUM_BITS 1 + +/** + * 2 VLAN tags present in Tunnel L2 header (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_BITPOS 73 +#define CFA_P70_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_NUM_BITS 1 + +/** + * resolved flds_tl3_hdr_valid. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_VALID_BITPOS 72 +#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_VALID_NUM_BITS 1 + +/** + * flds_tl3_hdr_valid is stop_w_error. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_ERROR_BITPOS 71 +#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_ERROR_NUM_BITS 1 + +/** + * Tunnel L3 header type directly from FLDS. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_TYPE_BITPOS 67 +#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_TYPE_NUM_BITS 4 + +/** + * Tunnel L3 header is IPV4 or IPV6. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_ISIP_BITPOS 66 +#define CFA_P70_PROF_PROFILE_TCAM_TL3_HDR_ISIP_NUM_BITS 1 + +/** + * resolved flds_tl4_hdr_valid. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_VALID_BITPOS 65 +#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_VALID_NUM_BITS 1 + +/** + * flds_tl4_hdr_valid is stop_w_error. (for idx 2 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_ERROR_BITPOS 64 +#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_ERROR_NUM_BITS 1 + +/** + * Tunnel L4 header type directly from FLDS. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_TYPE_BITPOS 60 +#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_TYPE_NUM_BITS 4 + +/** + * TL4 header is UDP or TCP. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_BITPOS 59 +#define CFA_P70_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_NUM_BITS 1 + +/** + * resolved flds_tun_hdr_valid. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_VALID_BITPOS 58 +#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_VALID_NUM_BITS 1 + +/** + * flds_tun_hdr_valid is stop_w_error. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_ERROR_BITPOS 57 +#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_ERROR_NUM_BITS 1 + +/** + * Tunnel header type directly from FLDS. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_TYPE_BITPOS 52 +#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_TYPE_NUM_BITS 5 + +/** + * Tunnel header flags directly from FLDS. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_BITPOS 44 +#define CFA_P70_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_NUM_BITS 8 + +/** + * resolved flds_l2_hdr_valid. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_L2_HDR_VALID_BITPOS 43 +#define CFA_P70_PROF_PROFILE_TCAM_L2_HDR_VALID_NUM_BITS 1 + +/** + * flds_l2_hdr_valid is stop_w_error. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_L2_HDR_ERROR_BITPOS 42 +#define CFA_P70_PROF_PROFILE_TCAM_L2_HDR_ERROR_NUM_BITS 1 + +/** + * L2 header type directly from FLDS. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_L2_HDR_TYPE_BITPOS 40 +#define CFA_P70_PROF_PROFILE_TCAM_L2_HDR_TYPE_NUM_BITS 2 + +/** + * flds_l2_dst_type remapped: UC(0)/MC(2)/BC(3). (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_L2_UC_MC_BC_BITPOS 38 +#define CFA_P70_PROF_PROFILE_TCAM_L2_UC_MC_BC_NUM_BITS 2 + +/** + * 1+ VLAN tags present in inner L2 header. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_BITPOS 37 +#define CFA_P70_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_NUM_BITS 1 + +/** + * 2 VLAN tags present in inner L2 header. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_L2_TWO_VTAGS_BITPOS 36 +#define CFA_P70_PROF_PROFILE_TCAM_L2_TWO_VTAGS_NUM_BITS 1 + +/** + * resolved flds_l3_hdr_valid. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_VALID_BITPOS 35 +#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_VALID_NUM_BITS 1 + +/** + * flds_l3_hdr_valid is stop_w_error. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_ERROR_BITPOS 34 +#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_ERROR_NUM_BITS 1 + +/** + * L3 header type directly from FLDS. + */ +#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_TYPE_BITPOS 30 +#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_TYPE_NUM_BITS 4 + +/** + * L3 header is IPV4 or IPV6. + */ +#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_ISIP_BITPOS 29 +#define CFA_P70_PROF_PROFILE_TCAM_L3_HDR_ISIP_NUM_BITS 1 + +/** + * L3 header next protocol directly from FLDS. + */ +#define CFA_P70_PROF_PROFILE_TCAM_L3_PROT_BITPOS 21 +#define CFA_P70_PROF_PROFILE_TCAM_L3_PROT_NUM_BITS 8 + +/** + * resolved flds_l4_hdr_valid. + */ +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_VALID_BITPOS 20 +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_VALID_NUM_BITS 1 + +/** + * flds_l4_hdr_valid is stop_w_error. + */ +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_ERROR_BITPOS 19 +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_ERROR_NUM_BITS 1 + +/** + * L4 header type directly from FLDS. + */ +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_TYPE_BITPOS 15 +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_TYPE_NUM_BITS 4 + +/** + * L4 header is UDP or TCP.2 + */ +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_BITPOS 14 +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_NUM_BITS 1 + +/** + * L4 header subtype directly from FLDS. + */ +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_SUBTYPE_BITPOS 11 +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_SUBTYPE_NUM_BITS 3 + +/** + * L4 header flags directly from FLDS. + */ +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_FLAGS_BITPOS 2 +#define CFA_P70_PROF_PROFILE_TCAM_L4_HDR_FLAGS_NUM_BITS 9 + +/** + * DCN present bits directly from FLDS. #CAS_SW_REF + * Profiler.profile.lookup.tcam.key + */ +#define CFA_P70_PROF_PROFILE_TCAM_L4_DCN_PRESENT_BITPOS 0 +#define CFA_P70_PROF_PROFILE_TCAM_L4_DCN_PRESENT_NUM_BITS 2 + +/** + * Total number of bits for PROF_PROFILE_TCAM + */ +#define CFA_P70_PROF_PROFILE_TCAM_TOTAL_NUM_BITS 184 + +/** + * Valid entry (for idx 2 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_TX_VALID_BITPOS 79 +#define CFA_P70_ACT_VEB_TCAM_TX_VALID_NUM_BITS 1 + +/** + * PF Parif Number (for idx 2 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_TX_PARIF_IN_BITPOS 74 +#define CFA_P70_ACT_VEB_TCAM_TX_PARIF_IN_NUM_BITS 5 + +/** + * Number of VLAN Tags. (for idx 2 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_TX_NUM_VTAGS_BITPOS 72 +#define CFA_P70_ACT_VEB_TCAM_TX_NUM_VTAGS_NUM_BITS 2 + +/** + * Dest. MAC Address + */ +#define CFA_P70_ACT_VEB_TCAM_TX_DMAC_BITPOS 24 +#define CFA_P70_ACT_VEB_TCAM_TX_DMAC_NUM_BITS 48 + +/** + * Outer VLAN Tag ID + */ +#define CFA_P70_ACT_VEB_TCAM_TX_OVID_BITPOS 12 +#define CFA_P70_ACT_VEB_TCAM_TX_OVID_NUM_BITS 12 + +/** + * Inner VLAN Tag ID #CAS_SW_REF Action.CFA.VEB.TCAM.tx.veb.tcam.entry + */ +#define CFA_P70_ACT_VEB_TCAM_TX_IVID_BITPOS 0 +#define CFA_P70_ACT_VEB_TCAM_TX_IVID_NUM_BITS 12 + +/** + * Total number of bits for ACT_VEB_TCAM_TX + */ +#define CFA_P70_ACT_VEB_TCAM_TX_TOTAL_NUM_BITS 80 + +/** + * Valid entry (for idx 2 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_RX_VALID_BITPOS 79 +#define CFA_P70_ACT_VEB_TCAM_RX_VALID_NUM_BITS 1 + +/** + * spare (for idx 2 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_RX_SPARE_BITPOS 78 +#define CFA_P70_ACT_VEB_TCAM_RX_SPARE_NUM_BITS 1 + +/** + * program to zero (for idx 2 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_RX_PADDING_BITPOS 68 +#define CFA_P70_ACT_VEB_TCAM_RX_PADDING_NUM_BITS 10 + +/** + * DMAC is unicast address (for idx 2 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_RX_UNICAST_BITPOS 67 +#define CFA_P70_ACT_VEB_TCAM_RX_UNICAST_NUM_BITS 1 + +/** + * DMAC is multicast address (for idx 2 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_RX_MULTICAST_BITPOS 66 +#define CFA_P70_ACT_VEB_TCAM_RX_MULTICAST_NUM_BITS 1 + +/** + * DMAC is broadcast address (for idx 2 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_RX_BROADCAST_BITPOS 65 +#define CFA_P70_ACT_VEB_TCAM_RX_BROADCAST_NUM_BITS 1 + +/** + * pfid + */ +#define CFA_P70_ACT_VEB_TCAM_RX_PFID_BITPOS 60 +#define CFA_P70_ACT_VEB_TCAM_RX_PFID_NUM_BITS 5 + +/** + * vfid (for idx 1 ...) + */ +#define CFA_P70_ACT_VEB_TCAM_RX_VFID_BITPOS 48 +#define CFA_P70_ACT_VEB_TCAM_RX_VFID_NUM_BITS 12 + +/** + * source mac #CAS_SW_REF AAction.CFA.VEB.TCAM.rx.veb.tcam.entry + */ +#define CFA_P70_ACT_VEB_TCAM_RX_SMAC_BITPOS 0 +#define CFA_P70_ACT_VEB_TCAM_RX_SMAC_NUM_BITS 48 + +/** + * Total number of bits for ACT_VEB_TCAM_RX + */ +#define CFA_P70_ACT_VEB_TCAM_RX_TOTAL_NUM_BITS 80 + +/** + * Valid entry (for idx 1 ...) + */ +#define CFA_P70_ACT_FC_TCAM_FC_VALID_BITPOS 33 +#define CFA_P70_ACT_FC_TCAM_FC_VALID_NUM_BITS 1 + +/** + * Reserved (for idx 1 ...) + */ +#define CFA_P70_ACT_FC_TCAM_FC_RSVD_BITPOS 32 +#define CFA_P70_ACT_FC_TCAM_FC_RSVD_NUM_BITS 1 + +/** + * Updated metadata. #CAS_SW_REF Action.CFA.FC.TCAM.fc.tcam.meta.entry + * #CAS_SW_REF Action.CFA.FC.TCAM.fc.tcam.l2ip.func.entry #CAS_SW_REF + * Action.CFA.FC.TCAM.fc.tcam.l2.ctxt.entry #CAS_SW_REF + * Action.CFA.FC.TCAM.fc.tcam.l2ipf.ctxt.entry + */ +#define CFA_P70_ACT_FC_TCAM_FC_METADATA_BITPOS 0 +#define CFA_P70_ACT_FC_TCAM_FC_METADATA_NUM_BITS 32 + +/** + * Total number of bits for ACT_FC_TCAM + */ +#define CFA_P70_ACT_FC_TCAM_TOTAL_NUM_BITS 34 + +/** + * New metadata. + */ +#define CFA_P70_ACT_FC_RMP_DR_METADATA_BITPOS 40 +#define CFA_P70_ACT_FC_RMP_DR_METADATA_NUM_BITS 32 + +/** + * Metadata merge control mask. + */ +#define CFA_P70_ACT_FC_RMP_DR_METAMASK_BITPOS 8 +#define CFA_P70_ACT_FC_RMP_DR_METAMASK_NUM_BITS 32 + +/** + * New L2 function. #CAS_SW_REF Action.CFA.FC.Remap.fc.remap.entry + */ +#define CFA_P70_ACT_FC_RMP_DR_L2_FUNC_BITPOS 0 +#define CFA_P70_ACT_FC_RMP_DR_L2_FUNC_NUM_BITS 8 + +/** + * Total number of bits for ACT_FC_RMP_DR + */ +#define CFA_P70_ACT_FC_RMP_DR_TOTAL_NUM_BITS 72 + +/** + * enables ilt metadata (for idx 3 ...) + */ +#define CFA_P70_PROF_ILT_DR_ILT_META_EN_BITPOS 104 +#define CFA_P70_PROF_ILT_DR_ILT_META_EN_NUM_BITS 1 + +/** + * meta profile register index (for idx 3 ...) + */ +#define CFA_P70_PROF_ILT_DR_META_PROF_BITPOS 101 +#define CFA_P70_PROF_ILT_DR_META_PROF_NUM_BITS 3 + +/** + * ilt metadata, used when ilt_meta_en is set + */ +#define CFA_P70_PROF_ILT_DR_METADATA_BITPOS 69 +#define CFA_P70_PROF_ILT_DR_METADATA_NUM_BITS 32 + +/** + * Partition (for idx 2 ...) + */ +#define CFA_P70_PROF_ILT_DR_PARIF_BITPOS 64 +#define CFA_P70_PROF_ILT_DR_PARIF_NUM_BITS 5 + +/** + * L2 function (for idx 1 ...) + */ +#define CFA_P70_PROF_ILT_DR_L2_FUNC_BITPOS 56 +#define CFA_P70_PROF_ILT_DR_L2_FUNC_NUM_BITS 8 + +/** + * When set cfa_meta opcode is allowed (for idx 1 ...) + */ +#define CFA_P70_PROF_ILT_DR_EN_BD_META_BITPOS 55 +#define CFA_P70_PROF_ILT_DR_EN_BD_META_NUM_BITS 1 + +/** + * When set act_rec_ptr is set to cfa_action if it is non-zero. + * Otherwise act_rec_ptr is set to act_rec_ptr from this table. (for idx + * 1 ...) + */ +#define CFA_P70_PROF_ILT_DR_EN_BD_ACTION_BITPOS 54 +#define CFA_P70_PROF_ILT_DR_EN_BD_ACTION_NUM_BITS 1 + +/** + * When set destination is set to destination from this table. Otherwise + * it is set to est_dest. (for idx 1 ...) + */ +#define CFA_P70_PROF_ILT_DR_EN_ILT_DEST_BITPOS 53 +#define CFA_P70_PROF_ILT_DR_EN_ILT_DEST_NUM_BITS 1 + +/** + * ILT opcode (for idx 1 ...) + */ +#define CFA_P70_PROF_ILT_DR_ILT_FWD_OP_BITPOS 50 +#define CFA_P70_PROF_ILT_DR_ILT_FWD_OP_NUM_BITS 3 +/** + * ILT opcode (for idx 1 ...) + */ +enum cfa_p70_prof_ilt_dr_ilt_fwd_op { + /* cfa is bypassed */ + CFA_P70_PROF_ILT_DR_ILT_FWD_OP_BYPASS_CFA = 0, + /* cfa is bypassed if packet is ROCE */ + CFA_P70_PROF_ILT_DR_ILT_FWD_OP_BYPASS_CFA_ROCE = 1, + /* profiler and lookup blocks are bypassed */ + CFA_P70_PROF_ILT_DR_ILT_FWD_OP_BYPASS_LKUP = 2, + /* packet proceeds to L2 Context Stage */ + CFA_P70_PROF_ILT_DR_ILT_FWD_OP_NORMAL_FLOW = 3, + /* mark packet for drop */ + CFA_P70_PROF_ILT_DR_ILT_FWD_OP_DROP = 4, +}; + +/** + * action hint used with act_rec_ptr (for idx 1 ...) + */ +#define CFA_P70_PROF_ILT_DR_ILT_ACT_HINT_BITPOS 48 +#define CFA_P70_PROF_ILT_DR_ILT_ACT_HINT_NUM_BITS 2 + +/** + * table scope used with act_rec_ptr (for idx 1 ...) + */ +#define CFA_P70_PROF_ILT_DR_ILT_SCOPE_BITPOS 43 +#define CFA_P70_PROF_ILT_DR_ILT_SCOPE_NUM_BITS 5 + +/** + * Default act_rec_ptr or explicit on Lookup Bypass. + */ +#define CFA_P70_PROF_ILT_DR_ILT_ACT_REC_PTR_BITPOS 17 +#define CFA_P70_PROF_ILT_DR_ILT_ACT_REC_PTR_NUM_BITS 26 + +/** + * used for destination #CAS_SW_REF Profiler.input.lookup.table.entry + */ +#define CFA_P70_PROF_ILT_DR_ILT_DESTINATION_BITPOS 0 +#define CFA_P70_PROF_ILT_DR_ILT_DESTINATION_NUM_BITS 17 + +/** + * Total number of bits for PROF_ILT_DR + */ +#define CFA_P70_PROF_ILT_DR_TOTAL_NUM_BITS 105 + +/** + * Normal operation. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_PL_BYP_LKUP_EN_BITPOS 42 +#define CFA_P70_PROF_PROFILE_RMP_DR_PL_BYP_LKUP_EN_NUM_BITS 1 + +/** + * Enable search in EM database. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_EM_SEARCH_EN_BITPOS 41 +#define CFA_P70_PROF_PROFILE_RMP_DR_EM_SEARCH_EN_NUM_BITS 1 + +/** + * ID to differentiate common EM keys. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_EM_PROFILE_ID_BITPOS 33 +#define CFA_P70_PROF_PROFILE_RMP_DR_EM_PROFILE_ID_NUM_BITS 8 + +/** + * Exact match key template select. + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_EM_KEY_ID_BITPOS 26 +#define CFA_P70_PROF_PROFILE_RMP_DR_EM_KEY_ID_NUM_BITS 7 + +/** + * Exact Match Lookup table scope. + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_EM_SCOPE_BITPOS 21 +#define CFA_P70_PROF_PROFILE_RMP_DR_EM_SCOPE_NUM_BITS 5 + +/** + * Enable search in TCAM database. + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_SEARCH_EN_BITPOS 20 +#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_SEARCH_EN_NUM_BITS 1 + +/** + * ID to differentiate common TCAM keys. + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_PROFILE_ID_BITPOS 12 +#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_PROFILE_ID_NUM_BITS 8 + +/** + * TCAM key template select. + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_KEY_ID_BITPOS 5 +#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_KEY_ID_NUM_BITS 7 + +/** + * Wild-card TCAM Lookup table scope. + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_SCOPE_BITPOS 0 +#define CFA_P70_PROF_PROFILE_RMP_DR_TCAM_SCOPE_NUM_BITS 5 + +/** + * Total number of bits for PROF_PROFILE_RMP_DR + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_TOTAL_NUM_BITS 43 + +/** + * Bypass operation. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_BYP_LKUP_EN_BITPOS 42 +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_BYP_LKUP_EN_NUM_BITS 1 + +/** + * Reserved for future use. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_RESERVED_BITPOS 36 +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_RESERVED_NUM_BITS 6 + +/** + * Bypass operations. (for idx 1 ...) + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_BITPOS 33 +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_NUM_BITS 3 +/** + * Bypass operations. (for idx 1 ...) + */ +enum cfa_p70_prof_profile_rmp_dr_byp_bypass_op { + /* cfa is bypassed */ + CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_BYPASS_CFA = 0, + /* Byass lookup use act_record_ptr from this table. */ + CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_BYPASS_LKUP = 1, + /* Byass lookup use Partition Default Action Record Pointer Table */ + CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_BYPASS_DEFAULT = 2, + /* Byass lookup use Partition Error Action Record Pointer Table. */ + CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_BYPASS_ERROR = 3, + /* set the drop flag. */ + CFA_P70_PROF_PROFILE_RMP_DR_BYP_BYPASS_OP_DROP = 4, +}; + +/** + * action hint used with plact_rec_ptr + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_ACT_HINT_BITPOS 31 +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_ACT_HINT_NUM_BITS 2 + +/** + * table scope used with pl_act_rec_ptr + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_SCOPE_BITPOS 26 +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_SCOPE_NUM_BITS 5 + +/** + * Used for BYPASS_LKUP. #CAS_SW_REF Profiler.profile.remap.entry.build + * #CAS_SW_REF Profiler.profile.remap.entry.bypass.cfa #CAS_SW_REF + * Profiler.profile.remap.entry.bypass.lkup #CAS_SW_REF + * Profiler.profile.remap.entry.other + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_ACT_REC_PTR_BITPOS 0 +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_PL_ACT_REC_PTR_NUM_BITS 26 + +/** + * Total number of bits for PROF_PROFILE_RMP_DR_BYP + */ +#define CFA_P70_PROF_PROFILE_RMP_DR_BYP_TOTAL_NUM_BITS 43 + +/** + * VLAN TPID anti-spoofing control. + */ +#define CFA_P70_ACT_VSPT_DR_TX_TPID_AS_CTL_BITPOS 29 +#define CFA_P70_ACT_VSPT_DR_TX_TPID_AS_CTL_NUM_BITS 2 +/** + * VLAN TPID anti-spoofing control. + */ +enum cfa_p70_act_vspt_dr_tx_tpid_as_ctl { + CFA_P70_ACT_VSPT_DR_TX_TPID_IGNORE = 0, + CFA_P70_ACT_VSPT_DR_TX_TPID_DEFAULT = 1, + CFA_P70_ACT_VSPT_DR_TX_TPID_DROP = 2, +}; + +/** + * VLAN allowed TPID bit map. + */ +#define CFA_P70_ACT_VSPT_DR_TX_ALWD_TPID_BITPOS 21 +#define CFA_P70_ACT_VSPT_DR_TX_ALWD_TPID_NUM_BITS 8 + +/** + * VLAN encoded default TPID. + */ +#define CFA_P70_ACT_VSPT_DR_TX_DFLT_TPID_BITPOS 18 +#define CFA_P70_ACT_VSPT_DR_TX_DFLT_TPID_NUM_BITS 3 + +/** + * VLAN PRIority anti-spoofing control. + */ +#define CFA_P70_ACT_VSPT_DR_TX_PRI_AS_CTL_BITPOS 16 +#define CFA_P70_ACT_VSPT_DR_TX_PRI_AS_CTL_NUM_BITS 2 +/** + * VLAN PRIority anti-spoofing control. + */ +enum cfa_p70_act_vspt_dr_tx_pri_as_ctl { + CFA_P70_ACT_VSPT_DR_TX_PRI_IGNORE = 0, + CFA_P70_ACT_VSPT_DR_TX_PRI_DEFAULT = 1, + CFA_P70_ACT_VSPT_DR_TX_PRI_DROP = 2, +}; + +/** + * VLAN allowed PRIority bit map. + */ +#define CFA_P70_ACT_VSPT_DR_TX_ALWD_PRI_BITPOS 8 +#define CFA_P70_ACT_VSPT_DR_TX_ALWD_PRI_NUM_BITS 8 + +/** + * VLAN default PRIority. + */ +#define CFA_P70_ACT_VSPT_DR_TX_DFLT_PRI_BITPOS 5 +#define CFA_P70_ACT_VSPT_DR_TX_DFLT_PRI_NUM_BITS 3 + +/** + * Mirror destination (1..31) or 5'h0=NO_MIRROR #CAS_SW_REF + * Action.CFA.DEST.SVIF.Property.Tables.tx.svif.property.entry + */ +#define CFA_P70_ACT_VSPT_DR_TX_MIR_BITPOS 0 +#define CFA_P70_ACT_VSPT_DR_TX_MIR_NUM_BITS 5 + +/** + * Total number of bits for ACT_VSPT_DR_TX + */ +#define CFA_P70_ACT_VSPT_DR_TX_TOTAL_NUM_BITS 31 + +/** + * Reserved for future use. + */ +#define CFA_P70_ACT_VSPT_DR_RX_RSVD_BITPOS 24 +#define CFA_P70_ACT_VSPT_DR_RX_RSVD_NUM_BITS 7 + +/** + * Output metadata format select. + */ +#define CFA_P70_ACT_VSPT_DR_RX_METAFMT_BITPOS 22 +#define CFA_P70_ACT_VSPT_DR_RX_METAFMT_NUM_BITS 2 +/** + * Output metadata format select. + */ +enum cfa_p70_act_vspt_dr_rx_metafmt { + CFA_P70_ACT_VSPT_DR_RX_METAFMT_ACT_REC_PTR = 0, + CFA_P70_ACT_VSPT_DR_RX_METAFMT_TUNNEL_ID = 1, + CFA_P70_ACT_VSPT_DR_RX_METAFMT_CSTM_HDR_DATA = 2, + CFA_P70_ACT_VSPT_DR_RX_METAFMT_HDR_OFFSETS = 3, +}; + +/** + * Function ID: 4 bit PF and 12 bit VID (VNIC ID) + */ +#define CFA_P70_ACT_VSPT_DR_RX_FID_BITPOS 5 +#define CFA_P70_ACT_VSPT_DR_RX_FID_NUM_BITS 17 + +/** + * Mirror destination (1..31) or 5'h0=NO_MIRROR #CAS_SW_REF + * Action.CFA.DEST.SVIF.Property.Tables.rx.destination.property.entry + */ +#define CFA_P70_ACT_VSPT_DR_RX_MIR_BITPOS 0 +#define CFA_P70_ACT_VSPT_DR_RX_MIR_NUM_BITS 5 + +/** + * Total number of bits for ACT_VSPT_DR_RX + */ +#define CFA_P70_ACT_VSPT_DR_RX_TOTAL_NUM_BITS 31 + +/** + * LAG destination bit map. + */ +#define CFA_P70_ACT_LBT_DR_DST_BMP_BITPOS 0 +#define CFA_P70_ACT_LBT_DR_DST_BMP_NUM_BITS 5 + +/** + * Total number of bits for ACT_LBT_DR + */ +#define CFA_P70_ACT_LBT_DR_TOTAL_NUM_BITS 5 + +/** + * Preserve incoming partition, don't remap (for idx 3 ...) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_PARIF_BITPOS 126 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_PARIF_NUM_BITS 1 + +/** + * Partition, replaces parif from input block (for idx 3 ...) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PARIF_BITPOS 121 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PARIF_NUM_BITS 5 + +/** + * Preserve incoming L2_CTXT (for idx 3 ...) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_L2IP_CTXT_BITPOS 120 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_L2IP_CTXT_NUM_BITS 1 + +/** + * L2 logical id which may be used in EM and WC Lookups. (for idx 3 ...) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_CTXT_BITPOS 109 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_CTXT_NUM_BITS 11 + +/** + * Preserve incoming PROF_FUNC (for idx 3 ...) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_PROF_FUNC_BITPOS 108 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PRSV_PROF_FUNC_NUM_BITS 1 + +/** + * Allow Profile TCAM Lookup Table to be logically partitioned. (for idx + * 3 ...) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PROF_FUNC_BITPOS 100 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_PROF_FUNC_NUM_BITS 8 + +/** + * Context operation code. (for idx 3 ...) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_BITPOS 98 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_NUM_BITS 2 +/** + * Context operation code. (for idx 3 ...) + */ +enum cfa_p70_prof_l2_ctxt_rmp_dr_ctxt_opcode { + /* def_ctxt_data provides destination */ + CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_BYPASS_CFA = 0, + /* def_ctxt_data provides act_rec_ptr */ + CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_BYPASS_LKUP = 1, + /* continue normal flow */ + CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_NORMAL_FLOW = 2, + /* mark packet for drop */ + CFA_P70_PROF_L2_CTXT_RMP_DR_CTXT_OPCODE_DROP = 3, +}; + +/** + * Enables remap of meta_data from Input block (for idx 3 ...) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_META_ENB_BITPOS 97 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_META_ENB_NUM_BITS 1 + +/** + * l2ip_meta_prof[2:0] = l2ip_meta[34:32], l2ip_meta_data[31:0] = + * l2ip_meta[31:0] + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_META_BITPOS 62 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_META_NUM_BITS 35 + +/** + * Enables remap of action record pointer from Input block (for idx 1 + * ...) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_ACT_ENB_BITPOS 61 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_ACT_ENB_NUM_BITS 1 + +/** + * l2ip_act_hint[1:0] = l2ip_act_data[32:31], l2ip_act_scope[4:0] = + * l2ip_act_data[30:26], l2ip_act_rec_ptr[25:0] = l2ip_act_data[25:0] + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_ACT_DATA_BITPOS 28 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_ACT_DATA_NUM_BITS 33 + +/** + * Enables remap of ring_table_idx + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_RFS_ENB_BITPOS 27 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_RFS_ENB_NUM_BITS 1 + +/** + * ring_table_idx[8:0] = l2ip_rfs_data[8:0] (rx only) + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_RFS_DATA_BITPOS 18 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_RFS_DATA_NUM_BITS 9 + +/** + * Enables remap of destination from input block + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_DEST_ENB_BITPOS 17 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_DEST_ENB_NUM_BITS 1 + +/** + * destination[16:0] = l2ip_dest_data[16:0] #CAS_SW_REF + * Profiler.l2ip.context.remap.table + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_DEST_DATA_BITPOS 0 +#define CFA_P70_PROF_L2_CTXT_RMP_DR_L2IP_DEST_DATA_NUM_BITS 17 + +/** + * Total number of bits for PROF_L2_CTXT_RMP_DR + */ +#define CFA_P70_PROF_L2_CTXT_RMP_DR_TOTAL_NUM_BITS 127 + +/** + * FC TCAM Search Result. + */ +#define CFA_P70_ACT_FC_TCAM_RESULT_SEARCH_RESULT_BITPOS 0 +#define CFA_P70_ACT_FC_TCAM_RESULT_SEARCH_RESULT_NUM_BITS 6 + +/** + * Unused Field. + */ +#define CFA_P70_ACT_FC_TCAM_RESULT_UNUSED_0_BITPOS 6 +#define CFA_P70_ACT_FC_TCAM_RESULT_UNUSED_0_NUM_BITS 25 + +/** + * FC TCAM Search Hit. + */ +#define CFA_P70_ACT_FC_TCAM_RESULT_SEARCH_HIT_BITPOS 31 +#define CFA_P70_ACT_FC_TCAM_RESULT_SEARCH_HIT_NUM_BITS 1 + +/** + * Total number of bits for ACT_FC_TCAM_RESULT + */ +#define CFA_P70_ACT_FC_TCAM_RESULT_TOTAL_NUM_BITS 32 + +/** + * Unused Field. + */ +#define CFA_P70_ACT_MIRROR_UNUSED_0_BITPOS 0 +#define CFA_P70_ACT_MIRROR_UNUSED_0_NUM_BITS 21 +#define CFA_P70_ACT_MIRROR_RELATIVE_BITPOS 21 +#define CFA_P70_ACT_MIRROR_RELATIVE_NUM_BITS 1 +/** + * RELATIVE + */ +enum cfa_p70_act_mirror_relative { + /* act_rec_ptr field is absolute. */ + CFA_P70_ACT_MIRROR_RELATIVE_ABSOLUTE = 0, + /* + * act_rec_ptr field is relative to the original action record pointer. + */ + CFA_P70_ACT_MIRROR_RELATIVE_RELATIVE = 1, +}; + +/** + * micr1_act_hint[1:0] - action hint used with act_rec_ptr. + */ +#define CFA_P70_ACT_MIRROR_HINT_BITPOS 22 +#define CFA_P70_ACT_MIRROR_HINT_NUM_BITS 2 + +/** + * Sampling mode. + */ +#define CFA_P70_ACT_MIRROR_SAMP_BITPOS 24 +#define CFA_P70_ACT_MIRROR_SAMP_NUM_BITS 2 +/** + * Sampling mode. + */ +enum cfa_p70_act_mirror_samp { + /* PRNG based. */ + CFA_P70_ACT_MIRROR_SAMP_STAT = 0, + /* packet count based. */ + CFA_P70_ACT_MIRROR_SAMP_PACKET = 1, + /* packet count w/jitter based. */ + CFA_P70_ACT_MIRROR_SAMP_JITTER = 2, + /* timer based. */ + CFA_P70_ACT_MIRROR_SAMP_TIMER = 3, +}; + +/** + * Truncation mode. + */ +#define CFA_P70_ACT_MIRROR_TRUNC_BITPOS 26 +#define CFA_P70_ACT_MIRROR_TRUNC_NUM_BITS 2 +/** + * Truncation mode. + */ +enum cfa_p70_act_mirror_trunc { + /* No Truncation. */ + CFA_P70_ACT_MIRROR_TRUNC_DISABLED = 0, + /* RFFU. */ + CFA_P70_ACT_MIRROR_TRUNC_RSVD = 1, + /* mirror copy will restrict outermost tunnel payload to 128B. */ + CFA_P70_ACT_MIRROR_TRUNC_B128 = 2, + /* mirror copy will restrict outermost tunnel payload to 256B. */ + CFA_P70_ACT_MIRROR_TRUNC_B256 = 3, +}; +#define CFA_P70_ACT_MIRROR_IGN_DROP_BITPOS 28 +#define CFA_P70_ACT_MIRROR_IGN_DROP_NUM_BITS 1 +/** + * IGN_DROP + */ +enum cfa_p70_act_mirror_ign_drop { + /* + * Honor Drop When set the mirror copy is made regardless if the initial + * action is to drop the packet or not. + */ + CFA_P70_ACT_MIRROR_IGN_DROP_HONOR = 0, + /* Ignore Drop */ + CFA_P70_ACT_MIRROR_IGN_DROP_IGNORE = 1, +}; +#define CFA_P70_ACT_MIRROR_MODE_BITPOS 29 +#define CFA_P70_ACT_MIRROR_MODE_NUM_BITS 2 +/** + * MODE + */ +enum cfa_p70_act_mirror_mode { + /* No Copy. */ + CFA_P70_ACT_MIRROR_MODE_DISABLED = 0, + /* Override AR. */ + CFA_P70_ACT_MIRROR_MODE_OVERRIDE = 1, + /* Ingress Copy. */ + CFA_P70_ACT_MIRROR_MODE_INGRESS = 2, + /* Egress Copy. */ + CFA_P70_ACT_MIRROR_MODE_EGRESS = 3, +}; +#define CFA_P70_ACT_MIRROR_COND_BITPOS 31 +#define CFA_P70_ACT_MIRROR_COND_NUM_BITS 1 +/** + * COND + */ +enum cfa_p70_act_mirror_cond { + /* mirror is only processed if Lookup copy bit is set */ + CFA_P70_ACT_MIRROR_COND_UNCONDITIONAL = 0, + /* mirror is processed unconditionally. */ + CFA_P70_ACT_MIRROR_COND_CONDITIONAL = 1, +}; + +/** + * Mirror Destination 1 Action Record Pointer. + */ +#define CFA_P70_ACT_MIRROR_AR_PTR_BITPOS 32 +#define CFA_P70_ACT_MIRROR_AR_PTR_NUM_BITS 26 + +/** + * Mirror Destination 1 Sampling Conifiguration. + */ +#define CFA_P70_ACT_MIRROR_SAMP_CFG_BITPOS 64 +#define CFA_P70_ACT_MIRROR_SAMP_CFG_NUM_BITS 32 + +/** + * Total number of bits for ACT_MIRROR + */ +#define CFA_P70_ACT_MIRROR_TOTAL_NUM_BITS 96 + +/** + * This is the new medadata that is merged with the existing packet + * metadata, based on the profile selected by META_PROF. + */ +#define CFA_P70_WC_LREC_METADATA_BITPOS 5 +#define CFA_P70_WC_LREC_METADATA_NUM_BITS 32 + +/** + * Specifies one of 8 metadata profile masks to use when merging the + * input metadata with the LREC metadata for recycling. + */ +#define CFA_P70_WC_LREC_META_PROF_BITPOS 37 +#define CFA_P70_WC_LREC_META_PROF_NUM_BITS 3 + +/** + * When a packet is recycled to the Profile TCAM, this value is used as + * the PROF_FUNC field in the TCAM search. + */ +#define CFA_P70_WC_LREC_PROF_FUNC_BITPOS 40 +#define CFA_P70_WC_LREC_PROF_FUNC_NUM_BITS 8 + +/** + * Indicates whether the packet will be recycled to the L2 Context TCAM, + * the Profile TCAM. When to the Profile TCAM, PROF_FUNC is used for the + * search key. + */ +#define CFA_P70_WC_LREC_RECYCLE_DEST_BITPOS 48 +#define CFA_P70_WC_LREC_RECYCLE_DEST_NUM_BITS 1 + +/** + * Flow counter pointer. + */ +#define CFA_P70_WC_LREC_FC_PTR_BITPOS 0 +#define CFA_P70_WC_LREC_FC_PTR_NUM_BITS 28 + +/** + * Flow counter type. + */ +#define CFA_P70_WC_LREC_FC_TYPE_BITPOS 28 +#define CFA_P70_WC_LREC_FC_TYPE_NUM_BITS 2 + +/** + * Flow counter op. + */ +#define CFA_P70_WC_LREC_FC_OP_BITPOS 30 +#define CFA_P70_WC_LREC_FC_OP_NUM_BITS 1 +/** + * Enumeration definition for field 'fc_op' + */ +enum cfa_p70_wc_lrec_fc_op { + /* ingress */ + CFA_P70_WC_LREC_FC_OP_INGRESS = 0, + /* egress */ + CFA_P70_WC_LREC_FC_OP_EGRESS = 1, +}; + +/** + * When not present, a value of 0 is used which disables ECMP. The final + * action record location is: ! ACT_REC_PTR += (ECMP_HASH % PATHS_M1 + + * 1)) * ACT_REC_SIZE + */ +#define CFA_P70_WC_LREC_PATHS_M1_BITPOS 31 +#define CFA_P70_WC_LREC_PATHS_M1_NUM_BITS 4 + +/** + * Specifies the size in 32B units of the action memory allocated for + * each ECMP path. + */ +#define CFA_P70_WC_LREC_ACT_REC_SIZE_BITPOS 35 +#define CFA_P70_WC_LREC_ACT_REC_SIZE_NUM_BITS 5 + +/** + * This field is used in flow steering applications such as Linux RFS. + * This field is used in conjunction with the VNIC destination in the + * action record on RX to steer the packet to a specific ring. + */ +#define CFA_P70_WC_LREC_RING_TABLE_IDX_BITPOS 40 +#define CFA_P70_WC_LREC_RING_TABLE_IDX_NUM_BITS 9 + +/** + * This field provides a destination for the packet, which goes directly + * to the output of CFA. + */ +#define CFA_P70_WC_LREC_DESTINATION_BITPOS 49 +#define CFA_P70_WC_LREC_DESTINATION_NUM_BITS 17 + +/** + * This is the action record pointer. This value points into the current + * scope action table. Not that when ACT_REC_SIZE and PATHS_M1 are + * preset and PATHS_M1 != 0, the value may be modified using this as the + * base pointer for ECMP. + */ +#define CFA_P70_WC_LREC_ACT_REC_PTR_BITPOS 49 +#define CFA_P70_WC_LREC_ACT_REC_PTR_NUM_BITS 26 + +/** + * This value provides a hit of the action record size to the Action + * block. + */ +#define CFA_P70_WC_LREC_ACT_HINT_BITPOS 75 +#define CFA_P70_WC_LREC_ACT_HINT_NUM_BITS 2 + +/** + * When both WC and EM have a hit, the one with the higher STRENGTH is + * used. If the STRENGTHs are equal, the LKUP_TIE_BREAKER register bit + * determines the winner. (0=WC, 1=EM) + */ +#define CFA_P70_WC_LREC_STRENGTH_BITPOS 77 +#define CFA_P70_WC_LREC_STRENGTH_NUM_BITS 2 + +/** + * This field defines the format for the LREC and the basic thing that + * will be done with the packet. + */ +#define CFA_P70_WC_LREC_OPCODE_BITPOS 79 +#define CFA_P70_WC_LREC_OPCODE_NUM_BITS 4 +/** + * Enumeration definition for field 'opcode' + */ +enum cfa_p70_wc_lrec_opcode { + /* + * This value means the packet will go to the action block for edit + * processing and that no RFS will be specified for the packet. + */ + CFA_P70_WC_LREC_OPCODE_NORMAL = 0, + /* + * This value means the packet will go to the action block for edit + * processing and that RFS will be specified for the packet. + */ + CFA_P70_WC_LREC_OPCODE_NORMAL_RFS = 1, + /* + * This value means the packet will go directly to the output, bypassing + * the action block and that no RFS will be specified for the packet. + */ + CFA_P70_WC_LREC_OPCODE_FAST = 2, + /* + * This value means the packet will go directly to the output, bypassing + * the action block and that RFS will be specified for the packet. + */ + CFA_P70_WC_LREC_OPCODE_FAST_RFS = 3, + /* + * This value Recycles the packet to the Profiler and provides LREC + * fields that determine the fields returned to the Profiler for further + * processing. + */ + CFA_P70_WC_LREC_OPCODE_RECYCLE = 8, +}; + +/** + * In addition to requiring VALID=1, the bits indexed by epoch1 must be + * set to '1' in the EPOCH1_MASK table, or the LREC is invalid. This is + * used to invalidate rules as a group. + */ +#define CFA_P70_WC_LREC_EPOCH1_BITPOS 83 +#define CFA_P70_WC_LREC_EPOCH1_NUM_BITS 6 + +/** + * In addition to requiring VALID=1, the bits indexed by epoch0 must be + * set to '1' in the EPOCH0_MASK table, or the LREC is invalid. This is + * used to invalidate rules as a group. + */ +#define CFA_P70_WC_LREC_EPOCH0_BITPOS 89 +#define CFA_P70_WC_LREC_EPOCH0_NUM_BITS 12 + +/** + * Record size in 32B words minus 1 (ignored by hardware). + */ +#define CFA_P70_WC_LREC_REC_SIZE_BITPOS 101 +#define CFA_P70_WC_LREC_REC_SIZE_NUM_BITS 2 + +/** + * When set to '0', the LREC is not valid. + */ +#define CFA_P70_WC_LREC_VALID_BITPOS 103 +#define CFA_P70_WC_LREC_VALID_NUM_BITS 1 + +/** + * Total number of bits for wc_lrec + */ +#define CFA_P70_WC_LREC_TOTAL_NUM_BITS 104 + +/** + * This value provides a base pointer to the LKUP_FRC_RANGE memory. Each + * packet can have up to 16 ranges. A value of 16'hFFFF disables FRC. + */ +#define CFA_P70_EM_LREC_RANGE_IDX_BITPOS 0 +#define CFA_P70_EM_LREC_RANGE_IDX_NUM_BITS 16 + +/** + * Selects one of 16 profiles for FRC in the LKUP_RANGE_PROFILE table, + * which specifies 2 packet fields to range check and gives a mask of 16 + * ranges determined by range_index. + */ +#define CFA_P70_EM_LREC_RANGE_PROFILE_BITPOS 16 +#define CFA_P70_EM_LREC_RANGE_PROFILE_NUM_BITS 4 + +/** + * Current timer value for the connection. + */ +#define CFA_P70_EM_LREC_CREC_TIMER_VALUE_BITPOS 20 +#define CFA_P70_EM_LREC_CREC_TIMER_VALUE_NUM_BITS 4 + +/** + * Current state of the connection. + */ +#define CFA_P70_EM_LREC_CREC_STATE_BITPOS 24 +#define CFA_P70_EM_LREC_CREC_STATE_NUM_BITS 5 + +/** + * Set to one by hardware whenever a notify of a valid tcp_msb_opp has + * been written into the connection record. Software can also initialize + * this to one if it initializes tcp_msb_opp to a valid value. + */ +#define CFA_P70_EM_LREC_CREC_TCP_MSB_OPP_INIT_BITPOS 29 +#define CFA_P70_EM_LREC_CREC_TCP_MSB_OPP_INIT_NUM_BITS 1 + +/** + * Bits 31:14 of seq# or ack# as seen in packets on the opposite path. + */ +#define CFA_P70_EM_LREC_CREC_TCP_MSB_OPP_BITPOS 30 +#define CFA_P70_EM_LREC_CREC_TCP_MSB_OPP_NUM_BITS 18 + +/** + * Bits 31:14 of seq# or ack# as seen in packets on the local path. + */ +#define CFA_P70_EM_LREC_CREC_TCP_MSB_LOC_BITPOS 48 +#define CFA_P70_EM_LREC_CREC_TCP_MSB_LOC_NUM_BITS 18 + +/** + * Window size is 1<inner (single shift) */ + CFA_P70_COMPACT_ACTION_DECAP_SHIFT_SINGLE = 14, + /* Un-parse (treat header as payload) */ + CFA_P70_COMPACT_ACTION_DECAP_UNPARSE = 15, + /* Shift outer tunnel->inner (double shift) */ + CFA_P70_COMPACT_ACTION_DECAP_SHIFT_DOUBLE = 18, + /* Decap through Outer Tunnel L2 header */ + CFA_P70_COMPACT_ACTION_DECAP_TO_OL2 = 20, + /* Decap through Outer Tunnel L3 header */ + CFA_P70_COMPACT_ACTION_DECAP_TO_OL3 = 21, + /* Decap through Outer Tunnel L4 header */ + CFA_P70_COMPACT_ACTION_DECAP_TO_OL4 = 22, + /* Decap through Outer Tunnel header */ + CFA_P70_COMPACT_ACTION_DECAP_TO_OT = 23, +}; + +/** + * The mirroring value selects one of 31 mirror destinations for the + * packet. A value of zero means that there is not Action Record + * mirroring for the packet. + */ +#define CFA_P70_COMPACT_ACTION_MIRRORING_BITPOS 24 +#define CFA_P70_COMPACT_ACTION_MIRRORING_NUM_BITS 5 + +/** + * This value points to one of the 1024 meter entries. If the meter has + * scope verification enabled, then the scope in the meter table entry + * must match the scope of this action record. + */ +#define CFA_P70_COMPACT_ACTION_METER_PTR_BITPOS 29 +#define CFA_P70_COMPACT_ACTION_METER_PTR_NUM_BITS 10 + +/** + * This is the offset to the statistic structure in 8B units from the + * start of the Action Record. A value of zero will disable the + * statistics action. + */ +#define CFA_P70_COMPACT_ACTION_STAT0_OFF_BITPOS 39 +#define CFA_P70_COMPACT_ACTION_STAT0_OFF_NUM_BITS 3 + +/** + * This value controls the packet size that is used for counted stats. + */ +#define CFA_P70_COMPACT_ACTION_STAT0_OP_BITPOS 42 +#define CFA_P70_COMPACT_ACTION_STAT0_OP_NUM_BITS 1 +/** + * Enumeration definition for field 'stat0_op' + */ +enum cfa_p70_compact_action_stat0_op { + /* Statistics count reflects packet at 'ingress' to CFA. */ + CFA_P70_COMPACT_ACTION_STAT0_OP_INGRESS = 0, + /* Statistics count reflects packet at 'egress' from CFA. */ + CFA_P70_COMPACT_ACTION_STAT0_OP_EGRESS = 1, +}; + +/** + * Selects counter type. In all cases, fields are packet little endian + * in the action memory. + */ +#define CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_BITPOS 43 +#define CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_NUM_BITS 2 +/** + * Enumeration definition for field 'stat0_ctr_type' + */ +enum cfa_p70_compact_action_stat0_ctr_type { + /* Forward packet count(64b)/byte count(64b) */ + CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_B16 = 0, + /* + * Forward packet count(64b)/byte count(64b) timestamp(32b) TCP + * Flags(16b) reserved(23b) + */ + CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_B24 = 1, + /* + * Forward packet count(64b)/byte count(64b) Meter (drop or red) packet + * count(64b)/byte count(64b) + */ + CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_B32A = 2, + /* + * Forward packet count(64b)/byte count(64b) Meter timestamp(32b) TCP + * Flags(16b) reserved(6b) (drop or red) packet count(38b)/byte + * count(42b) + */ + CFA_P70_COMPACT_ACTION_STAT0_CTR_TYPE_B32B = 3, +}; + +/** + * This is an offset to the modification record. This is the offset in + * 8B units from the start of the Action Record to get to dependent + * record data. A value of zero indicates no additional actions. + */ +#define CFA_P70_COMPACT_ACTION_MOD_OFF_BITPOS 45 +#define CFA_P70_COMPACT_ACTION_MOD_OFF_NUM_BITS 5 + +/** + * This is an offset to the encapsulation record. This is the offset in + * 8B units from the start of the Action Record to get to dependent + * record data. A value of zero indicates no additional actions. + */ +#define CFA_P70_COMPACT_ACTION_ENC_OFF_BITPOS 50 +#define CFA_P70_COMPACT_ACTION_ENC_OFF_NUM_BITS 6 + +/** + * This is an offset to the source record. This is the offset in 8B + * units from the start of the Action Record to get to dependent record + * data. A value of zero indicates no additional actions. + */ +#define CFA_P70_COMPACT_ACTION_SRC_OFF_BITPOS 56 +#define CFA_P70_COMPACT_ACTION_SRC_OFF_NUM_BITS 4 +#define CFA_P70_COMPACT_ACTION_UNUSED_0_BITPOS 60 +#define CFA_P70_COMPACT_ACTION_UNUSED_0_NUM_BITS 4 + +/** + * Total number of bits for compact_action + */ +#define CFA_P70_COMPACT_ACTION_TOTAL_NUM_BITS 64 + +/** + * The type field identifies the format of the action record to the + * hardware. + */ +#define CFA_P70_FULL_ACTION_TYPE_BITPOS 0 +#define CFA_P70_FULL_ACTION_TYPE_NUM_BITS 3 +/** + * Enumeration definition for field 'type' + */ +enum cfa_p70_full_action_type { + /* + * Full Action Record. The full action record uses full pointers to + * access needed data. It also allows access to all the action features. + * The Full Action record is 192b. + */ + CFA_P70_FULL_ACTION_TYPE_FULL_ACTION = 1, +}; + +/** + * When this value is '1', the packet will be dropped. + */ +#define CFA_P70_FULL_ACTION_DROP_BITPOS 3 +#define CFA_P70_FULL_ACTION_DROP_NUM_BITS 1 + +/** + * This value controls how the VLAN Delete/Report edit works. + */ +#define CFA_P70_FULL_ACTION_VLAN_DELETE_BITPOS 4 +#define CFA_P70_FULL_ACTION_VLAN_DELETE_NUM_BITS 2 +/** + * Enumeration definition for field 'vlan_delete' + */ +enum cfa_p70_full_action_vlan_delete { + /* The VLAN tag is left alone. */ + CFA_P70_FULL_ACTION_VLAN_DELETE_DISABLED = 0, + /* Strip/Report the outer VLAN tag. Leave the inner VLAN tag. */ + CFA_P70_FULL_ACTION_VLAN_DELETE_OUTER = 1, + /* + * Strip both the outer and inner VLAN tag. Report the inner VLAN tag. + */ + CFA_P70_FULL_ACTION_VLAN_DELETE_BOTH = 2, + /* + * If the outer VID != 0, strip and pass the outer VLAG tag and leave + * the inner VLAN tag. If outer VID == 0, then strip both VLAN tags and + * report the inner VLAN tag. + */ + CFA_P70_FULL_ACTION_VLAN_DELETE_COND = 3, +}; + +/** + * This value specifies the port destination mask for TX path and is the + * index into the VNIC Properties Table for the RX path. + */ +#define CFA_P70_FULL_ACTION_DEST_BITPOS 6 +#define CFA_P70_FULL_ACTION_DEST_NUM_BITS 7 +#define CFA_P70_FULL_ACTION_DEST_OP_BITPOS 17 +#define CFA_P70_FULL_ACTION_DEST_OP_NUM_BITS 2 +/** + * Enumeration definition for field 'dest_op' + */ +enum cfa_p70_full_action_dest_op { + /* Use the dest field from the Action Record. */ + CFA_P70_FULL_ACTION_DEST_OP_NORMAL = 0, + /* + * This value specifies that the default destination as determined by + * the Profiler/Lookup/MCG stages and passed into the Action Record + * Fetch should be used instead of the destination from the Action + * Record. For example this can be useful for applications where actions + * are desired on a packet but the destination is to be taken solely + * from the Profiler Input Lookup Table. + */ + CFA_P70_FULL_ACTION_DEST_OP_DEFAULT = 1, + /* + * This value specifies that the lower order bits of the metadata should + * be used instead of the destination from the Action Record. + */ + CFA_P70_FULL_ACTION_DEST_OP_METADATA = 2, +}; + +/** + * This field controls the decapsulation function for the action. + */ +#define CFA_P70_FULL_ACTION_DECAP_BITPOS 19 +#define CFA_P70_FULL_ACTION_DECAP_NUM_BITS 5 +/** + * Enumeration definition for field 'decap' + */ +enum cfa_p70_full_action_decap { + /* Do nothing. */ + CFA_P70_FULL_ACTION_DECAP_DISABLE = 0, + /* Decap the outer VLAN tag */ + CFA_P70_FULL_ACTION_DECAP_OVLAN = 1, + /* Decap all the VLAN tags */ + CFA_P70_FULL_ACTION_DECAP_ALL_VLAN = 2, + /* Decap through Tunnel L2 header */ + CFA_P70_FULL_ACTION_DECAP_TO_TL2 = 3, + /* Decap 1 MPLS label (does not delete outer L2) */ + CFA_P70_FULL_ACTION_DECAP_1MPLS = 4, + /* Decap 1 MPLS label and outer L2 */ + CFA_P70_FULL_ACTION_DECAP_1MPLS_OL2 = 5, + /* Decap 2 MPLS labels (does not delete outer L2) */ + CFA_P70_FULL_ACTION_DECAP_2MPLS = 6, + /* Decap 2 MPLS labels and outer L2 */ + CFA_P70_FULL_ACTION_DECAP_2MPLS_OL2 = 7, + /* Decap through Tunnel L3 header */ + CFA_P70_FULL_ACTION_DECAP_TO_TL3 = 8, + /* Decap through Tunnel L4 header */ + CFA_P70_FULL_ACTION_DECAP_TO_TL4 = 9, + /* Decap through Tunnel header */ + CFA_P70_FULL_ACTION_DECAP_TO_T = 10, + /* Decap through Inner L2 */ + CFA_P70_FULL_ACTION_DECAP_TO_L2 = 11, + /* Decap through Inner L3 */ + CFA_P70_FULL_ACTION_DECAP_TO_L3 = 12, + /* Decap through inner L4 */ + CFA_P70_FULL_ACTION_DECAP_TO_L4 = 13, + /* Shift tunnel->inner (single shift) */ + CFA_P70_FULL_ACTION_DECAP_SHIFT_SINGLE = 14, + /* Un-parse (treat header as payload) */ + CFA_P70_FULL_ACTION_DECAP_UNPARSE = 15, + /* Shift outer tunnel->inner (double shift) */ + CFA_P70_FULL_ACTION_DECAP_SHIFT_DOUBLE = 18, + /* Decap through Outer Tunnel L2 header */ + CFA_P70_FULL_ACTION_DECAP_TO_OL2 = 20, + /* Decap through Outer Tunnel L3 header */ + CFA_P70_FULL_ACTION_DECAP_TO_OL3 = 21, + /* Decap through Outer Tunnel L4 header */ + CFA_P70_FULL_ACTION_DECAP_TO_OL4 = 22, + /* Decap through Outer Tunnel header */ + CFA_P70_FULL_ACTION_DECAP_TO_OT = 23, +}; + +/** + * The mirroring value selects one of 31 mirror destinations for the + * packet. A value of zero means that there is not Action Record + * mirroring for the packet. + */ +#define CFA_P70_FULL_ACTION_MIRRORING_BITPOS 24 +#define CFA_P70_FULL_ACTION_MIRRORING_NUM_BITS 5 + +/** + * This value points to one of the 1024 meter entries. If the meter has + * scope verification enabled, then the scope in the meter table entry + * must match the scope of this action record. + */ +#define CFA_P70_FULL_ACTION_METER_PTR_BITPOS 29 +#define CFA_P70_FULL_ACTION_METER_PTR_NUM_BITS 10 + +/** + * This is the pointer to the statistic structure in 8B units A value of + * zero will disable the statistics action. + */ +#define CFA_P70_FULL_ACTION_STAT0_PTR_BITPOS 39 +#define CFA_P70_FULL_ACTION_STAT0_PTR_NUM_BITS 28 + +/** + * This value controls the packet size that is used for counted stats. + */ +#define CFA_P70_FULL_ACTION_STAT0_OP_BITPOS 67 +#define CFA_P70_FULL_ACTION_STAT0_OP_NUM_BITS 1 +/** + * Enumeration definition for field 'stat0_op' + */ +enum cfa_p70_full_action_stat0_op { + /* Statistics count reflects packet at 'ingress' to CFA. */ + CFA_P70_FULL_ACTION_STAT0_OP_INGRESS = 0, + /* Statistics count reflects packet at 'egress' from CFA. */ + CFA_P70_FULL_ACTION_STAT0_OP_EGRESS = 1, +}; + +/** + * Selects counter type. In all cases, fields are packet little endian + * in the action memory. + */ +#define CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_BITPOS 68 +#define CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_NUM_BITS 2 +/** + * Enumeration definition for field 'stat0_ctr_type' + */ +enum cfa_p70_full_action_stat0_ctr_type { + /* Forward packet count(64b)/byte count(64b) */ + CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_B16 = 0, + /* + * Forward packet count(64b)/byte count(64b) timestamp(32b) TCP + * Flags(16b) reserved(23b) + */ + CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_B24 = 1, + /* + * Forward packet count(64b)/byte count(64b) Meter (drop or red) packet + * count(64b)/byte count(64b) + */ + CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_B32A = 2, + /* + * Forward packet count(64b)/byte count(64b) Meter timestamp(32b) TCP + * Flags(16b) reserved(6b) (drop or red) packet count(38b)/byte + * count(42b) + */ + CFA_P70_FULL_ACTION_STAT0_CTR_TYPE_B32B = 3, +}; + +/** + * This is the pointer to the statistic structure in 8B units A value of + * zero will disable the statistics action. + */ +#define CFA_P70_FULL_ACTION_STAT1_PTR_BITPOS 70 +#define CFA_P70_FULL_ACTION_STAT1_PTR_NUM_BITS 28 + +/** + * This value controls the packet size that is used for counted stats. + */ +#define CFA_P70_FULL_ACTION_STAT1_OP_BITPOS 98 +#define CFA_P70_FULL_ACTION_STAT1_OP_NUM_BITS 1 +/** + * Enumeration definition for field 'stat1_op' + */ +enum cfa_p70_full_action_stat1_op { + /* Statistics count reflects packet at 'ingress' to CFA. */ + CFA_P70_FULL_ACTION_STAT1_OP_INGRESS = 0, + /* Statistics count reflects packet at 'egress' from CFA. */ + CFA_P70_FULL_ACTION_STAT1_OP_EGRESS = 1, +}; + +/** + * Selects counter type. In all cases, fields are packet little endian + * in the action memory. + */ +#define CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_BITPOS 99 +#define CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_NUM_BITS 2 +/** + * Enumeration definition for field 'stat1_ctr_type' + */ +enum cfa_p70_full_action_stat1_ctr_type { + /* Forward packet count(64b)/byte count(64b) */ + CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_B16 = 0, + /* + * Forward packet count(64b)/byte count(64b) timestamp(32b) TCP + * Flags(16b) reserved(23b) + */ + CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_B24 = 1, + /* + * Forward packet count(64b)/byte count(64b) Meter (drop or red) packet + * count(64b)/byte count(64b) + */ + CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_B32A = 2, + /* + * Forward packet count(64b)/byte count(64b) Meter timestamp(32b) TCP + * Flags(16b) reserved(6b) (drop or red) packet count(38b)/byte + * count(42b) + */ + CFA_P70_FULL_ACTION_STAT1_CTR_TYPE_B32B = 3, +}; + +/** + * This is a pointer to the modification record. This is a pointer in 8B + * units directly to dependent record data. A value of zero indicates no + * additional actions. + */ +#define CFA_P70_FULL_ACTION_MOD_PTR_BITPOS 101 +#define CFA_P70_FULL_ACTION_MOD_PTR_NUM_BITS 28 + +/** + * This is a pointer to the encapsulation record. This is a pointer in + * 8B units directly to dependent record data. A value of zero indicates + * no additional actions. + */ +#define CFA_P70_FULL_ACTION_ENC_PTR_BITPOS 129 +#define CFA_P70_FULL_ACTION_ENC_PTR_NUM_BITS 28 + +/** + * This is a pointer to the source record. This is a pointer in 8B units + * directly to dependent record data. A value of zero indicates no + * additional actions. + */ +#define CFA_P70_FULL_ACTION_SRC_PTR_BITPOS 157 +#define CFA_P70_FULL_ACTION_SRC_PTR_NUM_BITS 28 +#define CFA_P70_FULL_ACTION_UNUSED_0_BITPOS 185 +#define CFA_P70_FULL_ACTION_UNUSED_0_NUM_BITS 7 + +/** + * Total number of bits for full_action + */ +#define CFA_P70_FULL_ACTION_TOTAL_NUM_BITS 192 + +/** + * The type field identifies the format of the action record to the + * hardware. + */ +#define CFA_P70_MCG_ACTION_TYPE_BITPOS 0 +#define CFA_P70_MCG_ACTION_TYPE_NUM_BITS 3 +/** + * Enumeration definition for field 'type' + */ +enum cfa_p70_mcg_action_type { + /* + * Multicast Group Action Record. This action is used to send the packet + * to multiple destinations. The MGC Action record is 256b. + */ + CFA_P70_MCG_ACTION_TYPE_MCG_ACTION = 4, +}; + +/** + * When this bit is set to '1', source knockout will be supported for + * the MCG record. This value also applies to any chained subsequent MCG + * records. This is applied on the RX CFA only. + */ +#define CFA_P70_MCG_ACTION_SRC_KO_EN_BITPOS 3 +#define CFA_P70_MCG_ACTION_SRC_KO_EN_NUM_BITS 1 +#define CFA_P70_MCG_ACTION_UNUSED_0_BITPOS 4 +#define CFA_P70_MCG_ACTION_UNUSED_0_NUM_BITS 2 + +/** + * This is a pointer to the next MGC Subsequent Entries Record. The + * Subsequent Entries MGC record must be on a 32B boundary. A value of + * zero indicates that there are not additional MGC Subsequent Entries + * record. + */ +#define CFA_P70_MCG_ACTION_NEXT_PTR_BITPOS 6 +#define CFA_P70_MCG_ACTION_NEXT_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_ACTION_PTR0_ACT_HINT_BITPOS 32 +#define CFA_P70_MCG_ACTION_PTR0_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_ACTION_PTR0_ACT_REC_PTR_BITPOS 34 +#define CFA_P70_MCG_ACTION_PTR0_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_ACTION_PTR1_ACT_HINT_BITPOS 60 +#define CFA_P70_MCG_ACTION_PTR1_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_ACTION_PTR1_ACT_REC_PTR_BITPOS 62 +#define CFA_P70_MCG_ACTION_PTR1_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_ACTION_PTR2_ACT_HINT_BITPOS 88 +#define CFA_P70_MCG_ACTION_PTR2_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_ACTION_PTR2_ACT_REC_PTR_BITPOS 90 +#define CFA_P70_MCG_ACTION_PTR2_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_ACTION_PTR3_ACT_HINT_BITPOS 116 +#define CFA_P70_MCG_ACTION_PTR3_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_ACTION_PTR3_ACT_REC_PTR_BITPOS 118 +#define CFA_P70_MCG_ACTION_PTR3_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_ACTION_PTR4_ACT_HINT_BITPOS 144 +#define CFA_P70_MCG_ACTION_PTR4_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_ACTION_PTR4_ACT_REC_PTR_BITPOS 146 +#define CFA_P70_MCG_ACTION_PTR4_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_ACTION_PTR5_ACT_HINT_BITPOS 172 +#define CFA_P70_MCG_ACTION_PTR5_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_ACTION_PTR5_ACT_REC_PTR_BITPOS 174 +#define CFA_P70_MCG_ACTION_PTR5_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_ACTION_PTR6_ACT_HINT_BITPOS 200 +#define CFA_P70_MCG_ACTION_PTR6_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_ACTION_PTR6_ACT_REC_PTR_BITPOS 202 +#define CFA_P70_MCG_ACTION_PTR6_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_ACTION_PTR7_ACT_HINT_BITPOS 228 +#define CFA_P70_MCG_ACTION_PTR7_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_ACTION_PTR7_ACT_REC_PTR_BITPOS 230 +#define CFA_P70_MCG_ACTION_PTR7_ACT_REC_PTR_NUM_BITS 26 + +/** + * Total number of bits for mcg_action + */ +#define CFA_P70_MCG_ACTION_TOTAL_NUM_BITS 256 + +/** + * The type field identifies the format of the action record to the + * hardware. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_TYPE_BITPOS 0 +#define CFA_P70_MCG_SUBSEQ_ACTION_TYPE_NUM_BITS 3 +/** + * Enumeration definition for field 'type' + */ +enum cfa_p70_mcg_subseq_action_type { + /* + * Multicast Group Action Record. This action is used to send the packet + * to multiple destinations. The MGC Action record is 256b. + */ + CFA_P70_MCG_SUBSEQ_ACTION_TYPE_MCG_ACTION = 4, +}; +#define CFA_P70_MCG_SUBSEQ_ACTION_UNUSED_0_BITPOS 3 +#define CFA_P70_MCG_SUBSEQ_ACTION_UNUSED_0_NUM_BITS 3 + +/** + * This is a pointer to the next MGC Subsequent Entries Record. The + * Subsequent Entries MGC record must be on a 32B boundary. A value of + * zero indicates that there are not additional MGC Subsequent Entries + * record. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_NEXT_PTR_BITPOS 6 +#define CFA_P70_MCG_SUBSEQ_ACTION_NEXT_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR0_ACT_HINT_BITPOS 32 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR0_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR0_ACT_REC_PTR_BITPOS 34 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR0_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR1_ACT_HINT_BITPOS 60 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR1_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR1_ACT_REC_PTR_BITPOS 62 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR1_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR2_ACT_HINT_BITPOS 88 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR2_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR2_ACT_REC_PTR_BITPOS 90 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR2_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR3_ACT_HINT_BITPOS 116 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR3_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR3_ACT_REC_PTR_BITPOS 118 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR3_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR4_ACT_HINT_BITPOS 144 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR4_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR4_ACT_REC_PTR_BITPOS 146 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR4_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR5_ACT_HINT_BITPOS 172 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR5_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR5_ACT_REC_PTR_BITPOS 174 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR5_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR6_ACT_HINT_BITPOS 200 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR6_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR6_ACT_REC_PTR_BITPOS 202 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR6_ACT_REC_PTR_NUM_BITS 26 + +/** + * This is the prefetch hint that corresponds to this action record + * pointer. This value will index into the hint table for the current + * scope to determines the actual prefetch size. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR7_ACT_HINT_BITPOS 228 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR7_ACT_HINT_NUM_BITS 2 + +/** + * This is an individual action record pointer for an MGC entry. This + * points to a action record for this particular MGC member. If this + * pointer is zero, then it will not be followed. + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR7_ACT_REC_PTR_BITPOS 230 +#define CFA_P70_MCG_SUBSEQ_ACTION_PTR7_ACT_REC_PTR_NUM_BITS 26 + +/** + * Total number of bits for mcg_subseq_action + */ +#define CFA_P70_MCG_SUBSEQ_ACTION_TOTAL_NUM_BITS 256 + +/** + * Current committed token bucket count. + */ +#define CFA_P70_METERS_BKT_C_BITPOS 0 +#define CFA_P70_METERS_BKT_C_NUM_BITS 27 + +/** + * Current excess token bucket count. + */ +#define CFA_P70_METERS_BKT_E_BITPOS 27 +#define CFA_P70_METERS_BKT_E_NUM_BITS 27 + +/** + * Meter Valid + */ +#define CFA_P70_METERS_FLAGS_MTR_VAL_BITPOS 54 +#define CFA_P70_METERS_FLAGS_MTR_VAL_NUM_BITS 1 + +/** + * ECN Remap Enable + */ +#define CFA_P70_METERS_FLAGS_ECN_RMP_EN_BITPOS 55 +#define CFA_P70_METERS_FLAGS_ECN_RMP_EN_NUM_BITS 1 + +/** + * Coupling Flag. Indicates that tokens being added to the committed + * bucket should be diverted to the excess bucket when the committed + * bucket is full. This bit is ignored when RFC2698=1 + */ +#define CFA_P70_METERS_FLAGS_CF_BITPOS 56 +#define CFA_P70_METERS_FLAGS_CF_NUM_BITS 1 + +/** + * Packet Mode. When set packet length is ignored and a global value is + * used instead. + */ +#define CFA_P70_METERS_FLAGS_PM_BITPOS 57 +#define CFA_P70_METERS_FLAGS_PM_NUM_BITS 1 + +/** + * RFC2698 Enable - Indicates if BOTH buckets must have sufficient + * tokens to color a packet green per RFC2698, as opposed to just the + * committed bucket. + */ +#define CFA_P70_METERS_FLAGS_RFC2698_BITPOS 58 +#define CFA_P70_METERS_FLAGS_RFC2698_NUM_BITS 1 + +/** + * Committed Bucket Strict Mode. If set, a packet conforms to the + * committed bucket only if the number of tokens is greater than or + * equal to the packet length. When not set meter conformance is + * independent of packet size and requires only that the token count is + * non-negative. + */ +#define CFA_P70_METERS_FLAGS_CBSM_BITPOS 59 +#define CFA_P70_METERS_FLAGS_CBSM_NUM_BITS 1 + +/** + * Excess Bucket Strict Mode. If set, a packet conforms to the excess + * bucket only if the number of tokens is greater than or equal to the + * packet length. When not set, meter conformance is independent of + * packet size and requires only that the token count is non-negative. + */ +#define CFA_P70_METERS_FLAGS_EBSM_BITPOS 60 +#define CFA_P70_METERS_FLAGS_EBSM_NUM_BITS 1 + +/** + * Committed Bucket No Decrement. If set, tokens are never decremented + * from the committed bucket, even when the packet is Green. + */ +#define CFA_P70_METERS_FLAGS_CBND_BITPOS 61 +#define CFA_P70_METERS_FLAGS_CBND_NUM_BITS 1 + +/** + * Excess Bucket No Decrement. If set, tokens are never decremented from + * the excess bucket, even when the packet is Green. + */ +#define CFA_P70_METERS_FLAGS_EBND_BITPOS 62 +#define CFA_P70_METERS_FLAGS_EBND_NUM_BITS 1 + +/** + * Committed Burst Size. Expressed in bytes in a normalized floating + * point format. + */ +#define CFA_P70_METERS_CBS_BITPOS 63 +#define CFA_P70_METERS_CBS_NUM_BITS 12 + +/** + * Excess Burst Size. Expressed in bytes in a normalized floating point + * format. + */ +#define CFA_P70_METERS_EBS_BITPOS 75 +#define CFA_P70_METERS_EBS_NUM_BITS 12 + +/** + * Committed Information Rate. A rate expressed in bytes per clock cycle + * in a normalized floating point format. + */ +#define CFA_P70_METERS_CIR_BITPOS 87 +#define CFA_P70_METERS_CIR_NUM_BITS 17 + +/** + * Excess Information Rate. A rate expressed in bytes per clock cycle in + * a normalized floating point format. + */ +#define CFA_P70_METERS_EIR_BITPOS 104 +#define CFA_P70_METERS_EIR_NUM_BITS 17 + +/** + * This is the scope whose action records will be allowed to reference + * this meter if the enable bit is '1'. + */ +#define CFA_P70_METERS_PROTECTION_SCOPE_BITPOS 121 +#define CFA_P70_METERS_PROTECTION_SCOPE_NUM_BITS 5 + +/** + * Reserved. + */ +#define CFA_P70_METERS_PROTECTION_RSVD_BITPOS 126 +#define CFA_P70_METERS_PROTECTION_RSVD_NUM_BITS 1 + +/** + * When this bit is '1', the meter will be protected from any scope + * action other than the one in the scope field. + */ +#define CFA_P70_METERS_PROTECTION_ENABLE_BITPOS 127 +#define CFA_P70_METERS_PROTECTION_ENABLE_NUM_BITS 1 + +/** + * Total number of bits for meters + */ +#define CFA_P70_METERS_TOTAL_NUM_BITS 128 + +/** + * Field length definitions for fkb + */ +#define CFA_P70_FKB_PROF_ID_NUM_BITS 8 +#define CFA_P70_FKB_L2CTXT_NUM_BITS 11 +#define CFA_P70_FKB_L2FUNC_NUM_BITS 8 +#define CFA_P70_FKB_PARIF_NUM_BITS 2 +#define CFA_P70_FKB_SPIF_NUM_BITS 2 +#define CFA_P70_FKB_SVIF_NUM_BITS 6 +#define CFA_P70_FKB_LCOS_NUM_BITS 3 +#define CFA_P70_FKB_META_HI_NUM_BITS 16 +#define CFA_P70_FKB_META_LO_NUM_BITS 16 +#define CFA_P70_FKB_RCYC_CNT_NUM_BITS 4 +#define CFA_P70_FKB_LOOPBACK_NUM_BITS 1 +#define CFA_P70_FKB_OTL2_TYPE_NUM_BITS 2 +#define CFA_P70_FKB_OTL2_DMAC_NUM_BITS 48 +#define CFA_P70_FKB_OTL2_SMAC_NUM_BITS 48 +#define CFA_P70_FKB_OTL2_DT_NUM_BITS 2 +#define CFA_P70_FKB_OTL2_SA_NUM_BITS 1 +#define CFA_P70_FKB_OTL2_NVT_NUM_BITS 2 +#define CFA_P70_FKB_OTL2_OVP_NUM_BITS 3 +#define CFA_P70_FKB_OTL2_OVD_NUM_BITS 1 +#define CFA_P70_FKB_OTL2_OVV_NUM_BITS 12 +#define CFA_P70_FKB_OTL2_OVT_NUM_BITS 3 +#define CFA_P70_FKB_OTL2_IVP_NUM_BITS 3 +#define CFA_P70_FKB_OTL2_IVD_NUM_BITS 1 +#define CFA_P70_FKB_OTL2_IVV_NUM_BITS 12 +#define CFA_P70_FKB_OTL2_IVT_NUM_BITS 3 +#define CFA_P70_FKB_OTL2_ETYPE_NUM_BITS 16 +#define CFA_P70_FKB_OTL3_TYPE_NUM_BITS 4 +#define CFA_P70_FKB_OTL3_SIP3_NUM_BITS 32 +#define CFA_P70_FKB_OTL3_SIP2_NUM_BITS 32 +#define CFA_P70_FKB_OTL3_SIP1_NUM_BITS 32 +#define CFA_P70_FKB_OTL3_SIP0_NUM_BITS 32 +#define CFA_P70_FKB_OTL3_DIP3_NUM_BITS 32 +#define CFA_P70_FKB_OTL3_DIP2_NUM_BITS 32 +#define CFA_P70_FKB_OTL3_DIP1_NUM_BITS 32 +#define CFA_P70_FKB_OTL3_DIP0_NUM_BITS 32 +#define CFA_P70_FKB_OTL3_TTL_NUM_BITS 8 +#define CFA_P70_FKB_OTL3_PROT_NUM_BITS 8 +/** + * CFA_P70_FKB_OTL3_FID bit length is not fixed + * So the CFA_P70_FKB_OTL3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_FKB_OTL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_FKB_OTL3_QOS_NUM_BITS 8 +#define CFA_P70_FKB_OTL3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_FKB_OTL3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_FKB_OTL3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_FKB_OTL3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_FKB_OTL3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_FKB_OTL3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_FKB_OTL3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_FKB_OTL3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_FKB_OTL3_DF_NUM_BITS 1 +#define CFA_P70_FKB_OTL3_L3ERR_NUM_BITS 4 +#define CFA_P70_FKB_OTL4_TYPE_NUM_BITS 4 +#define CFA_P70_FKB_OTL4_SRC_NUM_BITS 16 +#define CFA_P70_FKB_OTL4_DST_NUM_BITS 16 +#define CFA_P70_FKB_OTL4_FLAGS_NUM_BITS 9 +#define CFA_P70_FKB_OTL4_SEQ_NUM_BITS 32 +#define CFA_P70_FKB_OTL4_PA_NUM_BITS 1 +#define CFA_P70_FKB_OTL4_OPT_NUM_BITS 1 +#define CFA_P70_FKB_OTL4_TCPTS_NUM_BITS 1 +#define CFA_P70_FKB_OTL4_ERR_NUM_BITS 4 +#define CFA_P70_FKB_OT_TYPE_NUM_BITS 5 +#define CFA_P70_FKB_OT_FLAGS_NUM_BITS 8 +#define CFA_P70_FKB_OT_IDS_NUM_BITS 24 +#define CFA_P70_FKB_OT_ID_NUM_BITS 32 +#define CFA_P70_FKB_OT_CTXTS_NUM_BITS 24 +#define CFA_P70_FKB_OT_CTXT_NUM_BITS 32 +#define CFA_P70_FKB_OT_QOS_NUM_BITS 3 +#define CFA_P70_FKB_OT_ERR_NUM_BITS 4 +#define CFA_P70_FKB_TL2_TYPE_NUM_BITS 2 +#define CFA_P70_FKB_TL2_DMAC_NUM_BITS 48 +#define CFA_P70_FKB_TL2_SMAC_NUM_BITS 48 +#define CFA_P70_FKB_TL2_DT_NUM_BITS 2 +#define CFA_P70_FKB_TL2_SA_NUM_BITS 1 +#define CFA_P70_FKB_TL2_NVT_NUM_BITS 2 +#define CFA_P70_FKB_TL2_OVP_NUM_BITS 3 +#define CFA_P70_FKB_TL2_OVD_NUM_BITS 1 +#define CFA_P70_FKB_TL2_OVV_NUM_BITS 12 +#define CFA_P70_FKB_TL2_OVT_NUM_BITS 3 +#define CFA_P70_FKB_TL2_IVP_NUM_BITS 3 +#define CFA_P70_FKB_TL2_IVD_NUM_BITS 1 +#define CFA_P70_FKB_TL2_IVV_NUM_BITS 12 +#define CFA_P70_FKB_TL2_IVT_NUM_BITS 3 +#define CFA_P70_FKB_TL2_ETYPE_NUM_BITS 16 +#define CFA_P70_FKB_TL3_TYPE_NUM_BITS 4 +#define CFA_P70_FKB_TL3_SIP3_NUM_BITS 32 +#define CFA_P70_FKB_TL3_SIP2_NUM_BITS 32 +#define CFA_P70_FKB_TL3_SIP1_NUM_BITS 32 +#define CFA_P70_FKB_TL3_SIP0_NUM_BITS 32 +#define CFA_P70_FKB_TL3_DIP3_NUM_BITS 32 +#define CFA_P70_FKB_TL3_DIP2_NUM_BITS 32 +#define CFA_P70_FKB_TL3_DIP1_NUM_BITS 32 +#define CFA_P70_FKB_TL3_DIP0_NUM_BITS 32 +#define CFA_P70_FKB_TL3_TTL_NUM_BITS 8 +#define CFA_P70_FKB_TL3_PROT_NUM_BITS 8 +/** + * CFA_P70_FKB_TL3_FID bit length is not fixed + * So the CFA_P70_FKB_TL3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_FKB_TL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_FKB_TL3_QOS_NUM_BITS 8 +#define CFA_P70_FKB_TL3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_FKB_TL3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_FKB_TL3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_FKB_TL3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_FKB_TL3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_FKB_TL3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_FKB_TL3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_FKB_TL3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_FKB_TL3_DF_NUM_BITS 1 +#define CFA_P70_FKB_TL3_L3ERR_NUM_BITS 4 +#define CFA_P70_FKB_TL4_TYPE_NUM_BITS 4 +#define CFA_P70_FKB_TL4_SRC_NUM_BITS 16 +#define CFA_P70_FKB_TL4_DST_NUM_BITS 16 +#define CFA_P70_FKB_TL4_FLAGS_NUM_BITS 9 +#define CFA_P70_FKB_TL4_SEQ_NUM_BITS 32 +#define CFA_P70_FKB_TL4_PA_NUM_BITS 1 +#define CFA_P70_FKB_TL4_OPT_NUM_BITS 1 +#define CFA_P70_FKB_TL4_TCPTS_NUM_BITS 1 +#define CFA_P70_FKB_TL4_ERR_NUM_BITS 4 +#define CFA_P70_FKB_T_TYPE_NUM_BITS 5 +#define CFA_P70_FKB_T_FLAGS_NUM_BITS 8 +#define CFA_P70_FKB_T_IDS_NUM_BITS 24 +#define CFA_P70_FKB_T_ID_NUM_BITS 32 +#define CFA_P70_FKB_T_CTXTS_NUM_BITS 24 +#define CFA_P70_FKB_T_CTXT_NUM_BITS 32 +#define CFA_P70_FKB_T_QOS_NUM_BITS 3 +#define CFA_P70_FKB_T_ERR_NUM_BITS 4 +#define CFA_P70_FKB_L2_TYPE_NUM_BITS 2 +#define CFA_P70_FKB_L2_DMAC_NUM_BITS 48 +#define CFA_P70_FKB_L2_SMAC_NUM_BITS 48 +#define CFA_P70_FKB_L2_DT_NUM_BITS 2 +#define CFA_P70_FKB_L2_SA_NUM_BITS 1 +#define CFA_P70_FKB_L2_NVT_NUM_BITS 2 +#define CFA_P70_FKB_L2_OVP_NUM_BITS 3 +#define CFA_P70_FKB_L2_OVD_NUM_BITS 1 +#define CFA_P70_FKB_L2_OVV_NUM_BITS 12 +#define CFA_P70_FKB_L2_OVT_NUM_BITS 3 +#define CFA_P70_FKB_L2_IVP_NUM_BITS 3 +#define CFA_P70_FKB_L2_IVD_NUM_BITS 1 +#define CFA_P70_FKB_L2_IVV_NUM_BITS 12 +#define CFA_P70_FKB_L2_IVT_NUM_BITS 3 +#define CFA_P70_FKB_L2_ETYPE_NUM_BITS 16 +#define CFA_P70_FKB_L3_TYPE_NUM_BITS 4 +#define CFA_P70_FKB_L3_SIP3_NUM_BITS 32 +#define CFA_P70_FKB_L3_SIP2_NUM_BITS 32 +#define CFA_P70_FKB_L3_SIP1_NUM_BITS 32 +#define CFA_P70_FKB_L3_SIP0_NUM_BITS 32 +#define CFA_P70_FKB_L3_DIP3_NUM_BITS 32 +#define CFA_P70_FKB_L3_DIP2_NUM_BITS 32 +#define CFA_P70_FKB_L3_DIP1_NUM_BITS 32 +#define CFA_P70_FKB_L3_DIP0_NUM_BITS 32 +#define CFA_P70_FKB_L3_TTL_NUM_BITS 8 +#define CFA_P70_FKB_L3_PROT_NUM_BITS 8 +/** + * CFA_P70_FKB_L3_FID bit length is not fixed + * So the CFA_P70_FKB_L3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_FKB_L3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_FKB_L3_QOS_NUM_BITS 8 +#define CFA_P70_FKB_L3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_FKB_L3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_FKB_L3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_FKB_L3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_FKB_L3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_FKB_L3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_FKB_L3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_FKB_L3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_FKB_L3_DF_NUM_BITS 1 +#define CFA_P70_FKB_L3_L3ERR_NUM_BITS 4 +#define CFA_P70_FKB_L4_TYPE_NUM_BITS 4 +#define CFA_P70_FKB_L4_SRC_NUM_BITS 16 +#define CFA_P70_FKB_L4_DST_NUM_BITS 16 +#define CFA_P70_FKB_L4_FLAGS_NUM_BITS 9 +#define CFA_P70_FKB_L4_SEQ_NUM_BITS 32 +#define CFA_P70_FKB_L4_ACK_NUM_BITS 32 +#define CFA_P70_FKB_L4_WIN_NUM_BITS 16 +#define CFA_P70_FKB_L4_PA_NUM_BITS 1 +#define CFA_P70_FKB_L4_OPT_NUM_BITS 1 +#define CFA_P70_FKB_L4_TCPTS_NUM_BITS 1 +#define CFA_P70_FKB_L4_TSVAL_NUM_BITS 32 +#define CFA_P70_FKB_L4_TXECR_NUM_BITS 32 +#define CFA_P70_FKB_L4_ERR_NUM_BITS 4 + +/** + * Field length definitions for wc tcam fkb + */ +#define CFA_P70_WC_TCAM_FKB_PROF_ID_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_L2CTXT_NUM_BITS 11 +#define CFA_P70_WC_TCAM_FKB_L2FUNC_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_PARIF_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_SPIF_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_SVIF_NUM_BITS 6 +#define CFA_P70_WC_TCAM_FKB_LCOS_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_META_HI_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_META_LO_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_RCYC_CNT_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_LOOPBACK_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL2_TYPE_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_OTL2_DMAC_NUM_BITS 48 +#define CFA_P70_WC_TCAM_FKB_OTL2_SMAC_NUM_BITS 48 +#define CFA_P70_WC_TCAM_FKB_OTL2_DT_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_OTL2_SA_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL2_NVT_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_OTL2_OVP_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_OTL2_OVD_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL2_OVV_NUM_BITS 12 +#define CFA_P70_WC_TCAM_FKB_OTL2_OVT_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_OTL2_IVP_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_OTL2_IVD_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL2_IVV_NUM_BITS 12 +#define CFA_P70_WC_TCAM_FKB_OTL2_IVT_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_OTL2_ETYPE_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_OTL3_TYPE_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_OTL3_SIP3_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OTL3_SIP2_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OTL3_SIP1_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OTL3_SIP0_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OTL3_DIP3_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OTL3_DIP2_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OTL3_DIP1_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OTL3_DIP0_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OTL3_TTL_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_OTL3_PROT_NUM_BITS 8 +/** + * CFA_P70_WC_TCAM_FKB_OTL3_FID bit length is not fixed + * So the CFA_P70_WC_TCAM_FKB_OTL3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_WC_TCAM_FKB_OTL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_WC_TCAM_FKB_OTL3_QOS_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL3_DF_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL3_L3ERR_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_OTL4_TYPE_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_OTL4_SRC_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_OTL4_DST_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_OTL4_FLAGS_NUM_BITS 9 +#define CFA_P70_WC_TCAM_FKB_OTL4_SEQ_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OTL4_PA_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL4_OPT_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL4_TCPTS_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_OTL4_ERR_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_OT_TYPE_NUM_BITS 5 +#define CFA_P70_WC_TCAM_FKB_OT_FLAGS_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_OT_IDS_NUM_BITS 24 +#define CFA_P70_WC_TCAM_FKB_OT_ID_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OT_CTXTS_NUM_BITS 24 +#define CFA_P70_WC_TCAM_FKB_OT_CTXT_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_OT_QOS_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_OT_ERR_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_TL2_TYPE_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_TL2_DMAC_NUM_BITS 48 +#define CFA_P70_WC_TCAM_FKB_TL2_SMAC_NUM_BITS 48 +#define CFA_P70_WC_TCAM_FKB_TL2_DT_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_TL2_SA_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL2_NVT_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_TL2_OVP_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_TL2_OVD_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL2_OVV_NUM_BITS 12 +#define CFA_P70_WC_TCAM_FKB_TL2_OVT_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_TL2_IVP_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_TL2_IVD_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL2_IVV_NUM_BITS 12 +#define CFA_P70_WC_TCAM_FKB_TL2_IVT_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_TL2_ETYPE_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_TL3_TYPE_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_TL3_SIP3_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_TL3_SIP2_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_TL3_SIP1_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_TL3_SIP0_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_TL3_DIP3_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_TL3_DIP2_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_TL3_DIP1_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_TL3_DIP0_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_TL3_TTL_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_TL3_PROT_NUM_BITS 8 +/** + * CFA_P70_WC_TCAM_FKB_TL3_FID bit length is not fixed + * So the CFA_P70_WC_TCAM_FKB_TL3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_WC_TCAM_FKB_TL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_WC_TCAM_FKB_TL3_QOS_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_TL3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL3_DF_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL3_L3ERR_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_TL4_TYPE_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_TL4_SRC_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_TL4_DST_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_TL4_FLAGS_NUM_BITS 9 +#define CFA_P70_WC_TCAM_FKB_TL4_SEQ_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_TL4_PA_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL4_OPT_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL4_TCPTS_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_TL4_ERR_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_T_TYPE_NUM_BITS 5 +#define CFA_P70_WC_TCAM_FKB_T_FLAGS_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_T_IDS_NUM_BITS 24 +#define CFA_P70_WC_TCAM_FKB_T_ID_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_T_CTXTS_NUM_BITS 24 +#define CFA_P70_WC_TCAM_FKB_T_CTXT_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_T_QOS_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_T_ERR_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_L2_TYPE_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_L2_DMAC_NUM_BITS 48 +#define CFA_P70_WC_TCAM_FKB_L2_SMAC_NUM_BITS 48 +#define CFA_P70_WC_TCAM_FKB_L2_DT_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_L2_SA_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L2_NVT_NUM_BITS 2 +#define CFA_P70_WC_TCAM_FKB_L2_OVP_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_L2_OVD_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L2_OVV_NUM_BITS 12 +#define CFA_P70_WC_TCAM_FKB_L2_OVT_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_L2_IVP_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_L2_IVD_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L2_IVV_NUM_BITS 12 +#define CFA_P70_WC_TCAM_FKB_L2_IVT_NUM_BITS 3 +#define CFA_P70_WC_TCAM_FKB_L2_ETYPE_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_L3_TYPE_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_L3_SIP3_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L3_SIP2_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L3_SIP1_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L3_SIP0_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L3_DIP3_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L3_DIP2_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L3_DIP1_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L3_DIP0_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L3_TTL_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_L3_PROT_NUM_BITS 8 +/** + * CFA_P70_WC_TCAM_FKB_L3_FID bit length is not fixed + * So the CFA_P70_WC_TCAM_FKB_L3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_WC_TCAM_FKB_L3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_WC_TCAM_FKB_L3_QOS_NUM_BITS 8 +#define CFA_P70_WC_TCAM_FKB_L3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L3_DF_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L3_L3ERR_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_L4_TYPE_NUM_BITS 4 +#define CFA_P70_WC_TCAM_FKB_L4_SRC_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_L4_DST_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_L4_FLAGS_NUM_BITS 9 +#define CFA_P70_WC_TCAM_FKB_L4_SEQ_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L4_ACK_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L4_WIN_NUM_BITS 16 +#define CFA_P70_WC_TCAM_FKB_L4_PA_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L4_OPT_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L4_TCPTS_NUM_BITS 1 +#define CFA_P70_WC_TCAM_FKB_L4_TSVAL_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L4_TXECR_NUM_BITS 32 +#define CFA_P70_WC_TCAM_FKB_L4_ERR_NUM_BITS 4 + +/** + * Field length definitions for em fkb + */ +#define CFA_P70_EM_FKB_PROF_ID_NUM_BITS 8 +#define CFA_P70_EM_FKB_L2CTXT_NUM_BITS 11 +#define CFA_P70_EM_FKB_L2FUNC_NUM_BITS 8 +#define CFA_P70_EM_FKB_PARIF_NUM_BITS 2 +#define CFA_P70_EM_FKB_SPIF_NUM_BITS 2 +#define CFA_P70_EM_FKB_SVIF_NUM_BITS 6 +#define CFA_P70_EM_FKB_LCOS_NUM_BITS 3 +#define CFA_P70_EM_FKB_META_HI_NUM_BITS 16 +#define CFA_P70_EM_FKB_META_LO_NUM_BITS 16 +#define CFA_P70_EM_FKB_RCYC_CNT_NUM_BITS 4 +#define CFA_P70_EM_FKB_LOOPBACK_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL2_TYPE_NUM_BITS 2 +#define CFA_P70_EM_FKB_OTL2_DMAC_NUM_BITS 48 +#define CFA_P70_EM_FKB_OTL2_SMAC_NUM_BITS 48 +#define CFA_P70_EM_FKB_OTL2_DT_NUM_BITS 2 +#define CFA_P70_EM_FKB_OTL2_SA_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL2_NVT_NUM_BITS 2 +#define CFA_P70_EM_FKB_OTL2_OVP_NUM_BITS 3 +#define CFA_P70_EM_FKB_OTL2_OVD_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL2_OVV_NUM_BITS 12 +#define CFA_P70_EM_FKB_OTL2_OVT_NUM_BITS 3 +#define CFA_P70_EM_FKB_OTL2_IVP_NUM_BITS 3 +#define CFA_P70_EM_FKB_OTL2_IVD_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL2_IVV_NUM_BITS 12 +#define CFA_P70_EM_FKB_OTL2_IVT_NUM_BITS 3 +#define CFA_P70_EM_FKB_OTL2_ETYPE_NUM_BITS 16 +#define CFA_P70_EM_FKB_OTL3_TYPE_NUM_BITS 4 +#define CFA_P70_EM_FKB_OTL3_SIP3_NUM_BITS 32 +#define CFA_P70_EM_FKB_OTL3_SIP2_NUM_BITS 32 +#define CFA_P70_EM_FKB_OTL3_SIP1_NUM_BITS 32 +#define CFA_P70_EM_FKB_OTL3_SIP0_NUM_BITS 32 +#define CFA_P70_EM_FKB_OTL3_DIP3_NUM_BITS 32 +#define CFA_P70_EM_FKB_OTL3_DIP2_NUM_BITS 32 +#define CFA_P70_EM_FKB_OTL3_DIP1_NUM_BITS 32 +#define CFA_P70_EM_FKB_OTL3_DIP0_NUM_BITS 32 +#define CFA_P70_EM_FKB_OTL3_TTL_NUM_BITS 8 +#define CFA_P70_EM_FKB_OTL3_PROT_NUM_BITS 8 +/** + * CFA_P70_EM_FKB_OTL3_FID bit length is not fixed + * So the CFA_P70_EM_FKB_OTL3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_EM_FKB_OTL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_EM_FKB_OTL3_QOS_NUM_BITS 8 +#define CFA_P70_EM_FKB_OTL3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL3_DF_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL3_L3ERR_NUM_BITS 4 +#define CFA_P70_EM_FKB_OTL4_TYPE_NUM_BITS 4 +#define CFA_P70_EM_FKB_OTL4_SRC_NUM_BITS 16 +#define CFA_P70_EM_FKB_OTL4_DST_NUM_BITS 16 +#define CFA_P70_EM_FKB_OTL4_FLAGS_NUM_BITS 9 +#define CFA_P70_EM_FKB_OTL4_SEQ_NUM_BITS 32 +#define CFA_P70_EM_FKB_OTL4_PA_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL4_OPT_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL4_TCPTS_NUM_BITS 1 +#define CFA_P70_EM_FKB_OTL4_ERR_NUM_BITS 4 +#define CFA_P70_EM_FKB_OT_TYPE_NUM_BITS 5 +#define CFA_P70_EM_FKB_OT_FLAGS_NUM_BITS 8 +#define CFA_P70_EM_FKB_OT_IDS_NUM_BITS 24 +#define CFA_P70_EM_FKB_OT_ID_NUM_BITS 32 +#define CFA_P70_EM_FKB_OT_CTXTS_NUM_BITS 24 +#define CFA_P70_EM_FKB_OT_CTXT_NUM_BITS 32 +#define CFA_P70_EM_FKB_OT_QOS_NUM_BITS 3 +#define CFA_P70_EM_FKB_OT_ERR_NUM_BITS 4 +#define CFA_P70_EM_FKB_TL2_TYPE_NUM_BITS 2 +#define CFA_P70_EM_FKB_TL2_DMAC_NUM_BITS 48 +#define CFA_P70_EM_FKB_TL2_SMAC_NUM_BITS 48 +#define CFA_P70_EM_FKB_TL2_DT_NUM_BITS 2 +#define CFA_P70_EM_FKB_TL2_SA_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL2_NVT_NUM_BITS 2 +#define CFA_P70_EM_FKB_TL2_OVP_NUM_BITS 3 +#define CFA_P70_EM_FKB_TL2_OVD_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL2_OVV_NUM_BITS 12 +#define CFA_P70_EM_FKB_TL2_OVT_NUM_BITS 3 +#define CFA_P70_EM_FKB_TL2_IVP_NUM_BITS 3 +#define CFA_P70_EM_FKB_TL2_IVD_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL2_IVV_NUM_BITS 12 +#define CFA_P70_EM_FKB_TL2_IVT_NUM_BITS 3 +#define CFA_P70_EM_FKB_TL2_ETYPE_NUM_BITS 16 +#define CFA_P70_EM_FKB_TL3_TYPE_NUM_BITS 4 +#define CFA_P70_EM_FKB_TL3_SIP3_NUM_BITS 32 +#define CFA_P70_EM_FKB_TL3_SIP2_NUM_BITS 32 +#define CFA_P70_EM_FKB_TL3_SIP1_NUM_BITS 32 +#define CFA_P70_EM_FKB_TL3_SIP0_NUM_BITS 32 +#define CFA_P70_EM_FKB_TL3_DIP3_NUM_BITS 32 +#define CFA_P70_EM_FKB_TL3_DIP2_NUM_BITS 32 +#define CFA_P70_EM_FKB_TL3_DIP1_NUM_BITS 32 +#define CFA_P70_EM_FKB_TL3_DIP0_NUM_BITS 32 +#define CFA_P70_EM_FKB_TL3_TTL_NUM_BITS 8 +#define CFA_P70_EM_FKB_TL3_PROT_NUM_BITS 8 +/** + * CFA_P70_EM_FKB_TL3_FID bit length is not fixed + * So the CFA_P70_EM_FKB_TL3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_EM_FKB_TL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_EM_FKB_TL3_QOS_NUM_BITS 8 +#define CFA_P70_EM_FKB_TL3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL3_DF_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL3_L3ERR_NUM_BITS 4 +#define CFA_P70_EM_FKB_TL4_TYPE_NUM_BITS 4 +#define CFA_P70_EM_FKB_TL4_SRC_NUM_BITS 16 +#define CFA_P70_EM_FKB_TL4_DST_NUM_BITS 16 +#define CFA_P70_EM_FKB_TL4_FLAGS_NUM_BITS 9 +#define CFA_P70_EM_FKB_TL4_SEQ_NUM_BITS 32 +#define CFA_P70_EM_FKB_TL4_PA_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL4_OPT_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL4_TCPTS_NUM_BITS 1 +#define CFA_P70_EM_FKB_TL4_ERR_NUM_BITS 4 +#define CFA_P70_EM_FKB_T_TYPE_NUM_BITS 5 +#define CFA_P70_EM_FKB_T_FLAGS_NUM_BITS 8 +#define CFA_P70_EM_FKB_T_IDS_NUM_BITS 24 +#define CFA_P70_EM_FKB_T_ID_NUM_BITS 32 +#define CFA_P70_EM_FKB_T_CTXTS_NUM_BITS 24 +#define CFA_P70_EM_FKB_T_CTXT_NUM_BITS 32 +#define CFA_P70_EM_FKB_T_QOS_NUM_BITS 3 +#define CFA_P70_EM_FKB_T_ERR_NUM_BITS 4 +#define CFA_P70_EM_FKB_L2_TYPE_NUM_BITS 2 +#define CFA_P70_EM_FKB_L2_DMAC_NUM_BITS 48 +#define CFA_P70_EM_FKB_L2_SMAC_NUM_BITS 48 +#define CFA_P70_EM_FKB_L2_DT_NUM_BITS 2 +#define CFA_P70_EM_FKB_L2_SA_NUM_BITS 1 +#define CFA_P70_EM_FKB_L2_NVT_NUM_BITS 2 +#define CFA_P70_EM_FKB_L2_OVP_NUM_BITS 3 +#define CFA_P70_EM_FKB_L2_OVD_NUM_BITS 1 +#define CFA_P70_EM_FKB_L2_OVV_NUM_BITS 12 +#define CFA_P70_EM_FKB_L2_OVT_NUM_BITS 3 +#define CFA_P70_EM_FKB_L2_IVP_NUM_BITS 3 +#define CFA_P70_EM_FKB_L2_IVD_NUM_BITS 1 +#define CFA_P70_EM_FKB_L2_IVV_NUM_BITS 12 +#define CFA_P70_EM_FKB_L2_IVT_NUM_BITS 3 +#define CFA_P70_EM_FKB_L2_ETYPE_NUM_BITS 16 +#define CFA_P70_EM_FKB_L3_TYPE_NUM_BITS 4 +#define CFA_P70_EM_FKB_L3_SIP3_NUM_BITS 32 +#define CFA_P70_EM_FKB_L3_SIP2_NUM_BITS 32 +#define CFA_P70_EM_FKB_L3_SIP1_NUM_BITS 32 +#define CFA_P70_EM_FKB_L3_SIP0_NUM_BITS 32 +#define CFA_P70_EM_FKB_L3_DIP3_NUM_BITS 32 +#define CFA_P70_EM_FKB_L3_DIP2_NUM_BITS 32 +#define CFA_P70_EM_FKB_L3_DIP1_NUM_BITS 32 +#define CFA_P70_EM_FKB_L3_DIP0_NUM_BITS 32 +#define CFA_P70_EM_FKB_L3_TTL_NUM_BITS 8 +#define CFA_P70_EM_FKB_L3_PROT_NUM_BITS 8 +/** + * CFA_P70_EM_FKB_L3_FID bit length is not fixed + * So the CFA_P70_EM_FKB_L3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_EM_FKB_L3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_EM_FKB_L3_QOS_NUM_BITS 8 +#define CFA_P70_EM_FKB_L3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_EM_FKB_L3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_EM_FKB_L3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_EM_FKB_L3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_EM_FKB_L3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_EM_FKB_L3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_EM_FKB_L3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_EM_FKB_L3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_EM_FKB_L3_DF_NUM_BITS 1 +#define CFA_P70_EM_FKB_L3_L3ERR_NUM_BITS 4 +#define CFA_P70_EM_FKB_L4_TYPE_NUM_BITS 4 +#define CFA_P70_EM_FKB_L4_SRC_NUM_BITS 16 +#define CFA_P70_EM_FKB_L4_DST_NUM_BITS 16 +#define CFA_P70_EM_FKB_L4_FLAGS_NUM_BITS 9 +#define CFA_P70_EM_FKB_L4_SEQ_NUM_BITS 32 +#define CFA_P70_EM_FKB_L4_ACK_NUM_BITS 32 +#define CFA_P70_EM_FKB_L4_WIN_NUM_BITS 16 +#define CFA_P70_EM_FKB_L4_PA_NUM_BITS 1 +#define CFA_P70_EM_FKB_L4_OPT_NUM_BITS 1 +#define CFA_P70_EM_FKB_L4_TCPTS_NUM_BITS 1 +#define CFA_P70_EM_FKB_L4_TSVAL_NUM_BITS 32 +#define CFA_P70_EM_FKB_L4_TXECR_NUM_BITS 32 +#define CFA_P70_EM_FKB_L4_ERR_NUM_BITS 4 + +/** + * Field length definitions for em key layout + */ +#define CFA_P70_EM_KL_RANGE_IDX_NUM_BITS 16 +#define CFA_P70_EM_KL_RANGE_PROFILE_NUM_BITS 4 +#define CFA_P70_EM_KL_CREC_TIMER_VALUE_NUM_BITS 4 +#define CFA_P70_EM_KL_CREC_STATE_NUM_BITS 5 +#define CFA_P70_EM_KL_CREC_TCP_MSB_OPP_INIT_NUM_BITS 1 +#define CFA_P70_EM_KL_CREC_TCP_MSB_OPP_NUM_BITS 18 +#define CFA_P70_EM_KL_CREC_TCP_MSB_LOC_NUM_BITS 18 +#define CFA_P70_EM_KL_CREC_TCP_WIN_NUM_BITS 5 +#define CFA_P70_EM_KL_CREC_TCP_UPDT_EN_NUM_BITS 1 +#define CFA_P70_EM_KL_CREC_TCP_DIR_NUM_BITS 1 +#define CFA_P70_EM_KL_METADATA_NUM_BITS 32 +#define CFA_P70_EM_KL_PROF_FUNC_NUM_BITS 8 +#define CFA_P70_EM_KL_META_PROF_NUM_BITS 3 +#define CFA_P70_EM_KL_RECYCLE_DEST_NUM_BITS 1 +#define CFA_P70_EM_KL_FC_PTR_NUM_BITS 28 +#define CFA_P70_EM_KL_FC_TYPE_NUM_BITS 2 +#define CFA_P70_EM_KL_FC_OP_NUM_BITS 1 +#define CFA_P70_EM_KL_PATHS_M1_NUM_BITS 4 +#define CFA_P70_EM_KL_ACT_REC_SIZE_NUM_BITS 5 +#define CFA_P70_EM_KL_RING_TABLE_IDX_NUM_BITS 9 +#define CFA_P70_EM_KL_DESTINATION_NUM_BITS 17 +#define CFA_P70_EM_KL_ACT_REC_PTR_NUM_BITS 26 +#define CFA_P70_EM_KL_ACT_HINT_NUM_BITS 2 +#define CFA_P70_EM_KL_STRENGTH_NUM_BITS 2 +#define CFA_P70_EM_KL_OPCODE_NUM_BITS 4 +#define CFA_P70_EM_KL_EPOCH1_NUM_BITS 6 +#define CFA_P70_EM_KL_EPOCH0_NUM_BITS 12 +#define CFA_P70_EM_KL_REC_SIZE_NUM_BITS 2 +#define CFA_P70_EM_KL_VALID_NUM_BITS 1 +#define CFA_P70_EM_KL_PROF_ID_NUM_BITS 8 +#define CFA_P70_EM_KL_L2CTXT_NUM_BITS 11 +#define CFA_P70_EM_KL_L2FUNC_NUM_BITS 8 +#define CFA_P70_EM_KL_PARIF_NUM_BITS 2 +#define CFA_P70_EM_KL_SPIF_NUM_BITS 2 +#define CFA_P70_EM_KL_SVIF_NUM_BITS 6 +#define CFA_P70_EM_KL_LCOS_NUM_BITS 3 +#define CFA_P70_EM_KL_META_HI_NUM_BITS 16 +#define CFA_P70_EM_KL_META_LO_NUM_BITS 16 +#define CFA_P70_EM_KL_RCYC_CNT_NUM_BITS 4 +#define CFA_P70_EM_KL_LOOPBACK_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL2_TYPE_NUM_BITS 2 +#define CFA_P70_EM_KL_OTL2_DMAC_NUM_BITS 48 +#define CFA_P70_EM_KL_OTL2_SMAC_NUM_BITS 48 +#define CFA_P70_EM_KL_OTL2_DT_NUM_BITS 2 +#define CFA_P70_EM_KL_OTL2_SA_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL2_NVT_NUM_BITS 2 +#define CFA_P70_EM_KL_OTL2_OVP_NUM_BITS 3 +#define CFA_P70_EM_KL_OTL2_OVD_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL2_OVV_NUM_BITS 12 +#define CFA_P70_EM_KL_OTL2_OVT_NUM_BITS 3 +#define CFA_P70_EM_KL_OTL2_IVP_NUM_BITS 3 +#define CFA_P70_EM_KL_OTL2_IVD_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL2_IVV_NUM_BITS 12 +#define CFA_P70_EM_KL_OTL2_IVT_NUM_BITS 3 +#define CFA_P70_EM_KL_OTL2_ETYPE_NUM_BITS 16 +#define CFA_P70_EM_KL_OTL3_TYPE_NUM_BITS 4 +#define CFA_P70_EM_KL_OTL3_SIP3_NUM_BITS 32 +#define CFA_P70_EM_KL_OTL3_SIP2_NUM_BITS 32 +#define CFA_P70_EM_KL_OTL3_SIP1_NUM_BITS 32 +#define CFA_P70_EM_KL_OTL3_SIP0_NUM_BITS 32 +#define CFA_P70_EM_KL_OTL3_DIP3_NUM_BITS 32 +#define CFA_P70_EM_KL_OTL3_DIP2_NUM_BITS 32 +#define CFA_P70_EM_KL_OTL3_DIP1_NUM_BITS 32 +#define CFA_P70_EM_KL_OTL3_DIP0_NUM_BITS 32 +#define CFA_P70_EM_KL_OTL3_TTL_NUM_BITS 8 +#define CFA_P70_EM_KL_OTL3_PROT_NUM_BITS 8 +/** + * CFA_P70_EM_KL_OTL3_FID bit length is not fixed + * So the CFA_P70_EM_KL_OTL3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_EM_KL_OTL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_EM_KL_OTL3_QOS_NUM_BITS 8 +#define CFA_P70_EM_KL_OTL3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL3_DF_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL3_L3ERR_NUM_BITS 4 +#define CFA_P70_EM_KL_OTL4_TYPE_NUM_BITS 4 +#define CFA_P70_EM_KL_OTL4_SRC_NUM_BITS 16 +#define CFA_P70_EM_KL_OTL4_DST_NUM_BITS 16 +#define CFA_P70_EM_KL_OTL4_FLAGS_NUM_BITS 9 +#define CFA_P70_EM_KL_OTL4_SEQ_NUM_BITS 32 +#define CFA_P70_EM_KL_OTL4_PA_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL4_OPT_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL4_TCPTS_NUM_BITS 1 +#define CFA_P70_EM_KL_OTL4_ERR_NUM_BITS 4 +#define CFA_P70_EM_KL_OT_TYPE_NUM_BITS 5 +#define CFA_P70_EM_KL_OT_FLAGS_NUM_BITS 8 +#define CFA_P70_EM_KL_OT_IDS_NUM_BITS 24 +#define CFA_P70_EM_KL_OT_ID_NUM_BITS 32 +#define CFA_P70_EM_KL_OT_CTXTS_NUM_BITS 24 +#define CFA_P70_EM_KL_OT_CTXT_NUM_BITS 32 +#define CFA_P70_EM_KL_OT_QOS_NUM_BITS 3 +#define CFA_P70_EM_KL_OT_ERR_NUM_BITS 4 +#define CFA_P70_EM_KL_TL2_TYPE_NUM_BITS 2 +#define CFA_P70_EM_KL_TL2_DMAC_NUM_BITS 48 +#define CFA_P70_EM_KL_TL2_SMAC_NUM_BITS 48 +#define CFA_P70_EM_KL_TL2_DT_NUM_BITS 2 +#define CFA_P70_EM_KL_TL2_SA_NUM_BITS 1 +#define CFA_P70_EM_KL_TL2_NVT_NUM_BITS 2 +#define CFA_P70_EM_KL_TL2_OVP_NUM_BITS 3 +#define CFA_P70_EM_KL_TL2_OVD_NUM_BITS 1 +#define CFA_P70_EM_KL_TL2_OVV_NUM_BITS 12 +#define CFA_P70_EM_KL_TL2_OVT_NUM_BITS 3 +#define CFA_P70_EM_KL_TL2_IVP_NUM_BITS 3 +#define CFA_P70_EM_KL_TL2_IVD_NUM_BITS 1 +#define CFA_P70_EM_KL_TL2_IVV_NUM_BITS 12 +#define CFA_P70_EM_KL_TL2_IVT_NUM_BITS 3 +#define CFA_P70_EM_KL_TL2_ETYPE_NUM_BITS 16 +#define CFA_P70_EM_KL_TL3_TYPE_NUM_BITS 4 +#define CFA_P70_EM_KL_TL3_SIP3_NUM_BITS 32 +#define CFA_P70_EM_KL_TL3_SIP2_NUM_BITS 32 +#define CFA_P70_EM_KL_TL3_SIP1_NUM_BITS 32 +#define CFA_P70_EM_KL_TL3_SIP0_NUM_BITS 32 +#define CFA_P70_EM_KL_TL3_DIP3_NUM_BITS 32 +#define CFA_P70_EM_KL_TL3_DIP2_NUM_BITS 32 +#define CFA_P70_EM_KL_TL3_DIP1_NUM_BITS 32 +#define CFA_P70_EM_KL_TL3_DIP0_NUM_BITS 32 +#define CFA_P70_EM_KL_TL3_TTL_NUM_BITS 8 +#define CFA_P70_EM_KL_TL3_PROT_NUM_BITS 8 +/** + * CFA_P70_EM_KL_TL3_FID bit length is not fixed + * So the CFA_P70_EM_KL_TL3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_EM_KL_TL3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_EM_KL_TL3_QOS_NUM_BITS 8 +#define CFA_P70_EM_KL_TL3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_EM_KL_TL3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_EM_KL_TL3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_EM_KL_TL3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_EM_KL_TL3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_EM_KL_TL3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_EM_KL_TL3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_EM_KL_TL3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_EM_KL_TL3_DF_NUM_BITS 1 +#define CFA_P70_EM_KL_TL3_L3ERR_NUM_BITS 4 +#define CFA_P70_EM_KL_TL4_TYPE_NUM_BITS 4 +#define CFA_P70_EM_KL_TL4_SRC_NUM_BITS 16 +#define CFA_P70_EM_KL_TL4_DST_NUM_BITS 16 +#define CFA_P70_EM_KL_TL4_FLAGS_NUM_BITS 9 +#define CFA_P70_EM_KL_TL4_SEQ_NUM_BITS 32 +#define CFA_P70_EM_KL_TL4_PA_NUM_BITS 1 +#define CFA_P70_EM_KL_TL4_OPT_NUM_BITS 1 +#define CFA_P70_EM_KL_TL4_TCPTS_NUM_BITS 1 +#define CFA_P70_EM_KL_TL4_ERR_NUM_BITS 4 +#define CFA_P70_EM_KL_T_TYPE_NUM_BITS 5 +#define CFA_P70_EM_KL_T_FLAGS_NUM_BITS 8 +#define CFA_P70_EM_KL_T_IDS_NUM_BITS 24 +#define CFA_P70_EM_KL_T_ID_NUM_BITS 32 +#define CFA_P70_EM_KL_T_CTXTS_NUM_BITS 24 +#define CFA_P70_EM_KL_T_CTXT_NUM_BITS 32 +#define CFA_P70_EM_KL_T_QOS_NUM_BITS 3 +#define CFA_P70_EM_KL_T_ERR_NUM_BITS 4 +#define CFA_P70_EM_KL_L2_TYPE_NUM_BITS 2 +#define CFA_P70_EM_KL_L2_DMAC_NUM_BITS 48 +#define CFA_P70_EM_KL_L2_SMAC_NUM_BITS 48 +#define CFA_P70_EM_KL_L2_DT_NUM_BITS 2 +#define CFA_P70_EM_KL_L2_SA_NUM_BITS 1 +#define CFA_P70_EM_KL_L2_NVT_NUM_BITS 2 +#define CFA_P70_EM_KL_L2_OVP_NUM_BITS 3 +#define CFA_P70_EM_KL_L2_OVD_NUM_BITS 1 +#define CFA_P70_EM_KL_L2_OVV_NUM_BITS 12 +#define CFA_P70_EM_KL_L2_OVT_NUM_BITS 3 +#define CFA_P70_EM_KL_L2_IVP_NUM_BITS 3 +#define CFA_P70_EM_KL_L2_IVD_NUM_BITS 1 +#define CFA_P70_EM_KL_L2_IVV_NUM_BITS 12 +#define CFA_P70_EM_KL_L2_IVT_NUM_BITS 3 +#define CFA_P70_EM_KL_L2_ETYPE_NUM_BITS 16 +#define CFA_P70_EM_KL_L3_TYPE_NUM_BITS 4 +#define CFA_P70_EM_KL_L3_SIP3_NUM_BITS 32 +#define CFA_P70_EM_KL_L3_SIP2_NUM_BITS 32 +#define CFA_P70_EM_KL_L3_SIP1_NUM_BITS 32 +#define CFA_P70_EM_KL_L3_SIP0_NUM_BITS 32 +#define CFA_P70_EM_KL_L3_DIP3_NUM_BITS 32 +#define CFA_P70_EM_KL_L3_DIP2_NUM_BITS 32 +#define CFA_P70_EM_KL_L3_DIP1_NUM_BITS 32 +#define CFA_P70_EM_KL_L3_DIP0_NUM_BITS 32 +#define CFA_P70_EM_KL_L3_TTL_NUM_BITS 8 +#define CFA_P70_EM_KL_L3_PROT_NUM_BITS 8 +/** + * CFA_P70_EM_KL_L3_FID bit length is not fixed + * So the CFA_P70_EM_KL_L3_FID_NUMBITS macro is defined with arguments + */ +#define CFA_P70_EM_KL_L3_FID_NUM_BITS(COND) ((COND) ? 16 : 20) +#define CFA_P70_EM_KL_L3_QOS_NUM_BITS 8 +#define CFA_P70_EM_KL_L3_IEH_NONEXT_NUM_BITS 1 +#define CFA_P70_EM_KL_L3_IEH_SEP_NUM_BITS 1 +#define CFA_P70_EM_KL_L3_IEH_AUTH_NUM_BITS 1 +#define CFA_P70_EM_KL_L3_IEH_DEST_NUM_BITS 1 +#define CFA_P70_EM_KL_L3_IEH_FRAG_NUM_BITS 1 +#define CFA_P70_EM_KL_L3_IEH_RTHDR_NUM_BITS 1 +#define CFA_P70_EM_KL_L3_IEH_HOP_NUM_BITS 1 +#define CFA_P70_EM_KL_L3_IEH_1FRAG_NUM_BITS 1 +#define CFA_P70_EM_KL_L3_DF_NUM_BITS 1 +#define CFA_P70_EM_KL_L3_L3ERR_NUM_BITS 4 +#define CFA_P70_EM_KL_L4_TYPE_NUM_BITS 4 +#define CFA_P70_EM_KL_L4_SRC_NUM_BITS 16 +#define CFA_P70_EM_KL_L4_DST_NUM_BITS 16 +#define CFA_P70_EM_KL_L4_FLAGS_NUM_BITS 9 +#define CFA_P70_EM_KL_L4_SEQ_NUM_BITS 32 +#define CFA_P70_EM_KL_L4_ACK_NUM_BITS 32 +#define CFA_P70_EM_KL_L4_WIN_NUM_BITS 16 +#define CFA_P70_EM_KL_L4_PA_NUM_BITS 1 +#define CFA_P70_EM_KL_L4_OPT_NUM_BITS 1 +#define CFA_P70_EM_KL_L4_TCPTS_NUM_BITS 1 +#define CFA_P70_EM_KL_L4_TSVAL_NUM_BITS 32 +#define CFA_P70_EM_KL_L4_TXECR_NUM_BITS 32 +#define CFA_P70_EM_KL_L4_ERR_NUM_BITS 4 + +/** + * Field length definitions for action + */ +#define CFA_P70_ACT_TYPE_NUM_BITS 3 +#define CFA_P70_ACT_DROP_NUM_BITS 1 +#define CFA_P70_ACT_VLAN_DELETE_NUM_BITS 2 +#define CFA_P70_ACT_DEST_NUM_BITS 7 +#define CFA_P70_ACT_DEST_OP_NUM_BITS 2 +#define CFA_P70_ACT_DECAP_NUM_BITS 5 +#define CFA_P70_ACT_MIRRORING_NUM_BITS 5 +#define CFA_P70_ACT_METER_PTR_NUM_BITS 10 +#define CFA_P70_ACT_STAT0_OFF_NUM_BITS 3 +#define CFA_P70_ACT_STAT0_OP_NUM_BITS 1 +#define CFA_P70_ACT_STAT0_CTR_TYPE_NUM_BITS 2 +#define CFA_P70_ACT_MOD_OFF_NUM_BITS 5 +#define CFA_P70_ACT_ENC_OFF_NUM_BITS 6 +#define CFA_P70_ACT_SRC_OFF_NUM_BITS 4 +#define CFA_P70_ACT_COMPACT_RSVD_0_NUM_BITS 4 +#define CFA_P70_ACT_STAT0_PTR_NUM_BITS 28 +#define CFA_P70_ACT_STAT1_PTR_NUM_BITS 28 +#define CFA_P70_ACT_STAT1_OP_NUM_BITS 1 +#define CFA_P70_ACT_STAT1_CTR_TYPE_NUM_BITS 2 +#define CFA_P70_ACT_MOD_PTR_NUM_BITS 28 +#define CFA_P70_ACT_ENC_PTR_NUM_BITS 28 +#define CFA_P70_ACT_SRC_PTR_NUM_BITS 28 +#define CFA_P70_ACT_FULL_RSVD_0_NUM_BITS 7 +#define CFA_P70_ACT_SRC_KO_EN_NUM_BITS 1 +#define CFA_P70_ACT_MCG_RSVD_0_NUM_BITS 2 +#define CFA_P70_ACT_NEXT_PTR_NUM_BITS 26 +#define CFA_P70_ACT_PTR0_ACT_HINT_NUM_BITS 2 +#define CFA_P70_ACT_PTR0_ACT_REC_PTR_NUM_BITS 26 +#define CFA_P70_ACT_PTR1_ACT_HINT_NUM_BITS 2 +#define CFA_P70_ACT_PTR1_ACT_REC_PTR_NUM_BITS 26 +#define CFA_P70_ACT_PTR2_ACT_HINT_NUM_BITS 2 +#define CFA_P70_ACT_PTR2_ACT_REC_PTR_NUM_BITS 26 +#define CFA_P70_ACT_PTR3_ACT_HINT_NUM_BITS 2 +#define CFA_P70_ACT_PTR3_ACT_REC_PTR_NUM_BITS 26 +#define CFA_P70_ACT_PTR4_ACT_HINT_NUM_BITS 2 +#define CFA_P70_ACT_PTR4_ACT_REC_PTR_NUM_BITS 26 +#define CFA_P70_ACT_PTR5_ACT_HINT_NUM_BITS 2 +#define CFA_P70_ACT_PTR5_ACT_REC_PTR_NUM_BITS 26 +#define CFA_P70_ACT_PTR6_ACT_HINT_NUM_BITS 2 +#define CFA_P70_ACT_PTR6_ACT_REC_PTR_NUM_BITS 26 +#define CFA_P70_ACT_PTR7_ACT_HINT_NUM_BITS 2 +#define CFA_P70_ACT_PTR7_ACT_REC_PTR_NUM_BITS 26 +#define CFA_P70_ACT_MCG_SUBSEQ_RSVD_0_NUM_BITS 3 +#define CFA_P70_ACT_MOD_MODIFY_ACT_HDR_NUM_BITS 16 +#define CFA_P70_ACT_MOD_MD_UPDT_DATA_NUM_BITS 32 +#define CFA_P70_ACT_MOD_MD_UPDT_PROF_NUM_BITS 4 + +/** + * Enumeration definition for field 'md_op' + */ +enum cfa_p70_md_op { + /* + * Normal Metadata update: ! md = (md & ~md_prof.mask) | (md_prof.mask & + * md_data) + */ + CFA_P70_MD_OP_NORMAL = 0, + /* + * L2 Hash Metadata update: ! md = (md & ~md_prof.mask) | (md_prof.mask + * & hash_l2(seed,packet)) + */ + CFA_P70_MD_OP_L2_HASH = 1, + /* + * L4 Hash Metadata update: ! md = (md & ~ md_prof.mask) | (md_prof.mask + * & hash_l3l4(seed,packet)) + */ + CFA_P70_MD_OP_L4_HASH = 2, + /* + * SVIF insert Metadata update: ! md = (md & ~ md_prof.mask) | + * (md_prof.mask & zero_extend(svif)) + */ + CFA_P70_MD_OP_SVIF = 3, +}; +#define CFA_P70_ACT_MOD_MD_UPDT_OP_NUM_BITS 2 +#define CFA_P70_ACT_MOD_MD_UPDT_RSVD_0_NUM_BITS 10 +#define CFA_P70_ACT_MOD_MD_UPDT_TOP_NUM_BITS 48 +#define CFA_P70_ACT_MOD_RM_OVLAN_NUM_BITS 32 +#define CFA_P70_ACT_MOD_RM_IVLAN_NUM_BITS 32 +#define CFA_P70_ACT_MOD_RPL_IVLAN_NUM_BITS 32 +#define CFA_P70_ACT_MOD_RPL_OVLAN_NUM_BITS 32 +#define CFA_P70_ACT_MOD_TTL_UPDT_OP_NUM_BITS 15 +#define CFA_P70_ACT_MOD_TTL_UPDT_ALT_VID_NUM_BITS 12 +#define CFA_P70_ACT_MOD_TTL_UPDT_ALT_PFID_NUM_BITS 5 +#define CFA_P70_ACT_MOD_TTL_UPDT_TOP_NUM_BITS 32 +#define CFA_P70_ACT_MOD_TNL_MODIFY_DEL_NUM_BITS 16 +#define CFA_P70_ACT_MOD_TNL_MODIFY_8B_NEW_PROT_NUM_BITS 8 +#define CFA_P70_ACT_MOD_TNL_MODIFY_8B_EXIST_PROT_NUM_BITS 8 +#define CFA_P70_ACT_MOD_TNL_MODIFY_8B_VEC_NUM_BITS 16 +#define CFA_P70_ACT_MOD_TNL_MODIFY_8B_TOP_NUM_BITS 32 +#define CFA_P70_ACT_MOD_TNL_MODIFY_16B_NEW_PROT_NUM_BITS 16 +#define CFA_P70_ACT_MOD_TNL_MODIFY_16B_EXIST_PROT_NUM_BITS 16 +#define CFA_P70_ACT_MOD_TNL_MODIFY_16B_VEC_NUM_BITS 16 +#define CFA_P70_ACT_MOD_TNL_MODIFY_16B_TOP_NUM_BITS 48 +#define CFA_P70_ACT_MOD_UPDT_FIELD_DATA0_NUM_BITS 32 +#define CFA_P70_ACT_MOD_UPDT_FIELD_VEC_RSVD_NUM_BITS 15 +#define CFA_P70_ACT_MOD_UPDT_FIELD_VEC_KID_NUM_BITS 1 +#define CFA_P70_ACT_MOD_UPDT_FIELD_TOP_NUM_BITS 48 +#define CFA_P70_ACT_MOD_SMAC_NUM_BITS 48 +#define CFA_P70_ACT_MOD_DMAC_NUM_BITS 48 +#define CFA_P70_ACT_MOD_SIPV6_NUM_BITS 128 +#define CFA_P70_ACT_MOD_DIPV6_NUM_BITS 128 +#define CFA_P70_ACT_MOD_SIPV4_NUM_BITS 32 +#define CFA_P70_ACT_MOD_DIPV4_NUM_BITS 32 +#define CFA_P70_ACT_MOD_SPORT_NUM_BITS 16 +#define CFA_P70_ACT_MOD_DPORT_NUM_BITS 16 + +/** + * Enumeration definition for field 'ecv_tnl' + */ +enum cfa_p70_ecv_tnl { + /* No tunnel header will be added. */ + CFA_P70_ECV_TNL_NOP = 0, + /* + * Generic full header will be added after inserted L2, L3, or L4 + * header. The first byte of the tunnel body will be the length of the + * inserted tunnel. + */ + CFA_P70_ECV_TNL_GENERIC = 1, + /* VXLAN tunnel header will be added. */ + CFA_P70_ECV_TNL_VXLAN = 2, + /* NGE (VXLAN2) Header will be added. */ + CFA_P70_ECV_TNL_NGE = 3, + /* NVGRE Header will be added. */ + CFA_P70_ECV_TNL_NVGRE = 4, + /* GRE Header will be added. */ + CFA_P70_ECV_TNL_GRE = 5, + /* + * Generic header after existing L4 header will be added. The first byte + * of the tunnel body will be the length of the inserted tunnel. + */ + CFA_P70_ECV_TNL_GENERIC_L4 = 6, + /* + * Generic header after existing tunnel will be added. The first byte of + * the tunnel body will be the length of the inserted tunnel. + */ + CFA_P70_ECV_TNL_GENERIC_TUN = 7, +}; +#define CFA_P70_ACT_ENC_ECV_TNL_NUM_BITS 3 + +/** + * Enumeration definition for field 'ecv_l4' + */ +enum cfa_p70_ecv_l4 { + /* No L4 Header */ + CFA_P70_ECV_L4_NOP = 0, + /* No L4 Header */ + CFA_P70_ECV_L4_NOP1 = 1, + /* No L4 Header */ + CFA_P70_ECV_L4_NOP2 = 2, + /* No L4 Header */ + CFA_P70_ECV_L4_NOP3 = 3, + /* Add L4 Header without entropy and with CS=0. */ + CFA_P70_ECV_L4_L4 = 4, + /* Add L4 Header without entropy and with CS=calculated. */ + CFA_P70_ECV_L4_L4_CS = 5, + /* Add L4 Header with entropy and with CS=0. */ + CFA_P70_ECV_L4_L4_ENT = 6, + /* Add L4 Header with entropy and with CS=calculated. */ + CFA_P70_ECV_L4_L4_ENT_CS = 7, +}; +#define CFA_P70_ACT_ENC_ECV_L4_NUM_BITS 3 + +/** + * Enumeration definition for field 'ecv_l3' + */ +enum cfa_p70_ecv_l3 { + /* No L3 Header */ + CFA_P70_ECV_L3_NOP = 0, + /* No L3 Header */ + CFA_P70_ECV_L3_NOP1 = 1, + /* No L3 Header */ + CFA_P70_ECV_L3_NOP2 = 2, + /* No L3 Header */ + CFA_P70_ECV_L3_NOP3 = 3, + /* Add IPV4 Header */ + CFA_P70_ECV_L3_IPV4 = 4, + /* Add IPV4 Header */ + CFA_P70_ECV_L3_IPV6 = 5, + /* Add MPLS (8847) Header */ + CFA_P70_ECV_L3_MPLS8847 = 6, + /* Add MPLS (8848) Header */ + CFA_P70_ECV_L3_MPLS8848 = 7, +}; +#define CFA_P70_ACT_ENC_ECV_L3_NUM_BITS 3 +#define CFA_P70_ACT_ENC_ECV_L2_NUM_BITS 1 + +/** + * Enumeration definition for field 'ecv_vtag' + */ +enum cfa_p70_ecv_vtag { + /* No VLAN tag will be added. */ + CFA_P70_ECV_VTAG_NOP = 0, + /* Add one VLAN tag using the PRI field from the encap record. */ + CFA_P70_ECV_VTAG_ADD1_USE_PRI = 1, + /* Add one VLAN tag remap wit inner VLAN Tag PRI field. */ + CFA_P70_ECV_VTAG_ADD1_REMAP_INNER_PRI = 2, + /* Add one VLAN tag remap with diff serve field. */ + CFA_P70_ECV_VTAG_ADD1_REMAP_DIFF = 3, + /* Add two VLAN tags using the PRI field from the encap record. */ + CFA_P70_ECV_VTAG_ADD2_USE_PRI = 4, + /* Add two VLAN tag remap with diff serve field. */ + CFA_P70_ECV_VTAG_ADD2_REMAP_DIFF = 5, + /* Add zero VLAN tags remap with inner VLAN Tag PRI Field. */ + CFA_P70_ECV_VTAG_ADD0_REMAP_INNER_PRI = 6, + /* Add zero VLAN tags remap with diff serve field. */ + CFA_P70_ECV_VTAG_ADD0_REMAP_DIFF = 7, + /* Add zero VLAG tags remap with immediate PRI=0. */ + CFA_P70_ECV_VTAG_ADD0_IMMED_PRI0 = 8, + /* Add zero VLAG tags remap with immediate PRI=1. */ + CFA_P70_ECV_VTAG_ADD0_IMMED_PRI1 = 9, + /* Add zero VLAG tags remap with immediate PRI=2. */ + CFA_P70_ECV_VTAG_ADD0_IMMED_PRI2 = 10, + /* Add zero VLAG tags remap with immediate PRI=3. */ + CFA_P70_ECV_VTAG_ADD0_IMMED_PRI3 = 11, + /* Add zero VLAG tags remap with immediate PRI=4. */ + CFA_P70_ECV_VTAG_ADD0_IMMED_PRI4 = 12, + /* Add zero VLAG tags remap with immediate PRI=5. */ + CFA_P70_ECV_VTAG_ADD0_IMMED_PRI5 = 13, + /* Add zero VLAG tags remap with immediate PRI=6. */ + CFA_P70_ECV_VTAG_ADD0_IMMED_PRI6 = 14, + /* Add zero VLAG tags remap with immediate PRI=7. */ + CFA_P70_ECV_VTAG_ADD0_IMMED_PRI7 = 15, +}; +#define CFA_P70_ACT_ENC_ECV_VTAG_NUM_BITS 4 +#define CFA_P70_ACT_ENC_ECV_EC_NUM_BITS 1 +#define CFA_P70_ACT_ENC_ECV_VALID_NUM_BITS 1 +#define CFA_P70_ACT_ENC_EC_IP_TTL_IH_NUM_BITS 1 +#define CFA_P70_ACT_ENC_EC_IP_TOS_IH_NUM_BITS 1 +#define CFA_P70_ACT_ENC_EC_TUN_QOS_NUM_BITS 3 +#define CFA_P70_ACT_ENC_EC_GRE_SET_K_NUM_BITS 1 + +/** + * Enumeration definition for field 'enccfg_dmac_ovr' + */ +enum cfa_p70_enccfg_dmac_ovr { + /* use encap record DMAC */ + CFA_P70_ENCCFG_DMAC_OVR_ENCAP = 0, + /* re-use existing inner L2 header DMAC */ + CFA_P70_ENCCFG_DMAC_OVR_INNER_DMAC = 1, + /* re-use existing tunnel L2 header DMAC */ + CFA_P70_ENCCFG_DMAC_OVR_TUNNEL_DMAC = 2, + /* re-use existing outer-most L2 header DMAC */ + CFA_P70_ENCCFG_DMAC_OVR_OUTER_DMAC = 3, +}; +#define CFA_P70_ACT_ENC_EC_DMAC_OVR_NUM_BITS 2 + +/** + * Enumeration definition for field 'enccfg_vlan_ovr' + */ +enum cfa_p70_enccfg_vlan_ovr { + /* use only encap record VLAN tags */ + CFA_P70_ENCCFG_VLAN_OVR_ENCAP = 0, + /* use only existing inner L2 header VLAN tags */ + CFA_P70_ENCCFG_VLAN_OVR_INNER_L2 = 1, + /* use only existing tunnel L2 header VLAN tags */ + CFA_P70_ENCCFG_VLAN_OVR_TUNNEL_L2 = 2, + /* use only existing outer-most L2 header VLAN tags */ + CFA_P70_ENCCFG_VLAN_OVR_OUTER_L2 = 3, + /* include inner VLAN Tag from existing inner L2 header (keeps 1 TAG) */ + CFA_P70_ENCCFG_VLAN_OVR_INNER_INNER = 4, + /* include outer VLAN Tag from existing inner L2 header (keeps 1 TAG) */ + CFA_P70_ENCCFG_VLAN_OVR_INNER_OUTER = 5, + /* + * include inner VLAN Tag from existing outer-most L2 header (keeps 1 + * TAG) + */ + CFA_P70_ENCCFG_VLAN_OVR_OUTER_INNER = 6, + /* + * include outer VLAN Tag from existing outer-most L2 header (keeps 1 + * TAG) + */ + CFA_P70_ENCCFG_VLAN_OVR_OUTER_OUTER = 7, +}; +#define CFA_P70_ACT_ENC_EC_VLAN_OVR_NUM_BITS 3 + +/** + * Enumeration definition for field 'enccfg_smac_ovr' + */ +enum cfa_p70_enccfg_smac_ovr { + /* use only source property record SMAC */ + CFA_P70_ENCCFG_SMAC_OVR_ENCAP = 0, + /* re-use existing inner L2 header SMAC */ + CFA_P70_ENCCFG_SMAC_OVR_INNER_SMAC = 1, + /* re-use existing tunnel L2 header SMAC */ + CFA_P70_ENCCFG_SMAC_OVR_TUNNEL_SMAC = 2, + /* re-use existing outer-most L2 header SMAC */ + CFA_P70_ENCCFG_SMAC_OVR_OUTER_SMAC = 3, + /* re-use existing inner L2 header DMAC */ + CFA_P70_ENCCFG_SMAC_OVR_INNER_DMAC = 5, + /* re-use existing tunnel L2 header DMAC */ + CFA_P70_ENCCFG_SMAC_OVR_TUNNEL_DMAC = 6, + /* re-use existing outer-most L2 header DMAC */ + CFA_P70_ENCCFG_SMAC_OVR_OUTER_DMAC = 7, +}; +#define CFA_P70_ACT_ENC_EC_SMAC_OVR_NUM_BITS 3 + +/** + * Enumeration definition for field 'enccfg_ipv4_id_ctrl' + */ +enum cfa_p70_enccfg_ipv4_id_ctrl { + /* use encap record IPv4 ID field */ + CFA_P70_ENCCFG_IPV4_ID_CTRL_ENCAP = 0, + /* inherit from next existing IPv4 header ID field */ + CFA_P70_ENCCFG_IPV4_ID_CTRL_INHERIT = 2, + /* use CFA incrementing IPv4 ID counter */ + CFA_P70_ENCCFG_IPV4_ID_CTRL_INCREMENT = 3, +}; +#define CFA_P70_ACT_ENC_EC_IPV4_ID_CTRL_NUM_BITS 2 +#define CFA_P70_ACT_ENC_L2_DMAC_NUM_BITS 48 +#define CFA_P70_ACT_ENC_VLAN1_TAG_VID_NUM_BITS 12 +#define CFA_P70_ACT_ENC_VLAN1_TAG_DE_NUM_BITS 1 +#define CFA_P70_ACT_ENC_VLAN1_TAG_PRI_NUM_BITS 3 +#define CFA_P70_ACT_ENC_VLAN1_TAG_TPID_NUM_BITS 16 +#define CFA_P70_ACT_ENC_VLAN2_IT_VID_NUM_BITS 12 +#define CFA_P70_ACT_ENC_VLAN2_IT_DE_NUM_BITS 1 +#define CFA_P70_ACT_ENC_VLAN2_IT_PRI_NUM_BITS 3 +#define CFA_P70_ACT_ENC_VLAN2_IT_TPID_NUM_BITS 16 +#define CFA_P70_ACT_ENC_VLAN2_OT_VID_NUM_BITS 12 +#define CFA_P70_ACT_ENC_VLAN2_OT_DE_NUM_BITS 1 +#define CFA_P70_ACT_ENC_VLAN2_OT_PRI_NUM_BITS 3 +#define CFA_P70_ACT_ENC_VLAN2_OT_TPID_NUM_BITS 16 +#define CFA_P70_ACT_ENC_IPV4_ID_NUM_BITS 16 +#define CFA_P70_ACT_ENC_IPV4_TOS_NUM_BITS 8 +#define CFA_P70_ACT_ENC_IPV4_HLEN_NUM_BITS 4 +#define CFA_P70_ACT_ENC_IPV4_VER_NUM_BITS 4 +#define CFA_P70_ACT_ENC_IPV4_PROT_NUM_BITS 8 +#define CFA_P70_ACT_ENC_IPV4_TTL_NUM_BITS 8 +#define CFA_P70_ACT_ENC_IPV4_FRAG_NUM_BITS 13 +#define CFA_P70_ACT_ENC_IPV4_FLAGS_NUM_BITS 3 +#define CFA_P70_ACT_ENC_IPV4_DEST_NUM_BITS 32 +#define CFA_P70_ACT_ENC_IPV6_FLOW_LABEL_NUM_BITS 20 +#define CFA_P70_ACT_ENC_IPV6_TRAFFIC_CLASS_NUM_BITS 8 +#define CFA_P70_ACT_ENC_IPV6_VER_NUM_BITS 4 +#define CFA_P70_ACT_ENC_IPV6_HOP_LIMIT_NUM_BITS 8 +#define CFA_P70_ACT_ENC_IPV6_NEXT_HEADER_NUM_BITS 8 +#define CFA_P70_ACT_ENC_IPV6_PAYLOAD_LENGTH_NUM_BITS 16 +#define CFA_P70_ACT_ENC_IPV6_DEST_NUM_BITS 128 +#define CFA_P70_ACT_ENC_MPLS_TAG1_NUM_BITS 32 +#define CFA_P70_ACT_ENC_MPLS_TAG2_NUM_BITS 32 +#define CFA_P70_ACT_ENC_MPLS_TAG3_NUM_BITS 32 +#define CFA_P70_ACT_ENC_MPLS_TAG4_NUM_BITS 32 +#define CFA_P70_ACT_ENC_MPLS_TAG5_NUM_BITS 32 +#define CFA_P70_ACT_ENC_MPLS_TAG6_NUM_BITS 32 +#define CFA_P70_ACT_ENC_MPLS_TAG7_NUM_BITS 32 +#define CFA_P70_ACT_ENC_MPLS_TAG8_NUM_BITS 32 +#define CFA_P70_ACT_ENC_L4_DEST_PORT_NUM_BITS 16 +#define CFA_P70_ACT_ENC_L4_SRC_PORT_NUM_BITS 16 +#define CFA_P70_ACT_ENC_TNL_VXLAN_NEXT_PROT_NUM_BITS 8 +#define CFA_P70_ACT_ENC_TNL_VXLAN_RSVD_0_NUM_BITS 16 +#define CFA_P70_ACT_ENC_TNL_VXLAN_FLAGS_NUM_BITS 8 +#define CFA_P70_ACT_ENC_TNL_VXLAN_RSVD_1_NUM_BITS 8 +#define CFA_P70_ACT_ENC_TNL_VXLAN_VNI_NUM_BITS 24 +#define CFA_P70_ACT_ENC_TNL_NGE_PROT_TYPE_NUM_BITS 16 +#define CFA_P70_ACT_ENC_TNL_NGE_RSVD_0_NUM_BITS 6 +#define CFA_P70_ACT_ENC_TNL_NGE_FLAGS_C_NUM_BITS 1 +#define CFA_P70_ACT_ENC_TNL_NGE_FLAGS_O_NUM_BITS 1 +#define CFA_P70_ACT_ENC_TNL_NGE_FLAGS_OPT_LEN_NUM_BITS 6 +#define CFA_P70_ACT_ENC_TNL_NGE_FLAGS_VER_NUM_BITS 2 +#define CFA_P70_ACT_ENC_TNL_NGE_RSVD_1_NUM_BITS 8 +#define CFA_P70_ACT_ENC_TNL_NGE_VNI_NUM_BITS 24 +#define CFA_P70_ACT_ENC_TNL_NGE_OPTIONS_NUM_BITS 64 +#define CFA_P70_ACT_ENC_TNL_NVGRE_FLOW_ID_NUM_BITS 8 +#define CFA_P70_ACT_ENC_TNL_NVGRE_VSID_NUM_BITS 24 +#define CFA_P70_ACT_ENC_TNL_GRE_KEY_NUM_BITS 32 +#define CFA_P70_ACT_ENC_TNL_GENERIC_TID_NUM_BITS 8 +#define CFA_P70_ACT_ENC_TNL_GENERIC_LENGTH_NUM_BITS 8 +#define CFA_P70_ACT_ENC_TNL_GENERIC_HEADER_NUM_BITS 32 +#define CFA_P70_ACT_SRC_MAC_NUM_BITS 48 +#define CFA_P70_ACT_SRC_IPV4_ADDR_NUM_BITS 32 +#define CFA_P70_ACT_SRC_IPV6_ADDR_NUM_BITS 128 +#define CFA_P70_ACT_STAT0_B16_FPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B16_FPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B16_FBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B16_FBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B24_FPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B24_FPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B24_FBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B24_FBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B24_TIMESTAMP_NUM_BITS 32 +#define CFA_P70_ACT_STAT1_B24_TIMESTAMP_NUM_BITS 32 +#define CFA_P70_ACT_STAT0_B24_TCP_FLAGS_NUM_BITS 9 +#define CFA_P70_ACT_STAT1_B24_TCP_FLAGS_NUM_BITS 9 +#define CFA_P70_ACT_STAT0_B24_UNUSED_0_NUM_BITS 23 +#define CFA_P70_ACT_STAT1_B24_UNUSED_0_NUM_BITS 23 +#define CFA_P70_ACT_STAT0_B32A_FPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B32A_FPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B32A_FBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B32A_FBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B32A_MPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B32A_MPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B32A_MBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B32A_MBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B32B_FPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B32B_FPC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B32B_FBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT1_B32B_FBC_NUM_BITS 64 +#define CFA_P70_ACT_STAT0_B32B_TIMESTAMP_NUM_BITS 32 +#define CFA_P70_ACT_STAT1_B32B_TIMESTAMP_NUM_BITS 32 +#define CFA_P70_ACT_STAT0_B32B_TCP_FLAGS_NUM_BITS 9 +#define CFA_P70_ACT_STAT1_B32B_TCP_FLAGS_NUM_BITS 9 +#define CFA_P70_ACT_STAT0_B32B_UNUSED_0_NUM_BITS 7 +#define CFA_P70_ACT_STAT1_B32B_UNUSED_0_NUM_BITS 7 +#define CFA_P70_ACT_STAT0_B32B_MPC15_0_NUM_BITS 16 +#define CFA_P70_ACT_STAT1_B32B_MPC15_0_NUM_BITS 16 +#define CFA_P70_ACT_STAT0_B32B_MPC37_16_NUM_BITS 22 +#define CFA_P70_ACT_STAT1_B32B_MPC37_16_NUM_BITS 22 +#define CFA_P70_ACT_STAT0_B32B_MBC_NUM_BITS 42 +#define CFA_P70_ACT_STAT1_B32B_MBC_NUM_BITS 42 + +#define CFA_P70_CACHE_LINE_BYTES 32 +#define CFA_P70_CACHE_LINE_BITS \ + (CFA_P70_CACHE_LINE_BYTES * BITS_PER_BYTE) + +/* clang-format on */ + +#endif /* _CFA_P70_HW_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70_mpc_structs.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70_mpc_structs.h new file mode 100644 index 0000000000..508e6f1b44 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/include/p70/cfa_p70_mpc_structs.h @@ -0,0 +1,1496 @@ +/**************************************************************************** + * Copyright(c) 2001-2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * Name: cfa_p70_mpc_structs.h + * + * Description: MPC CFA command and completion structure definitions + * + * Date: 09/29/22 11:50:38 + * + * Note: This file is scripted generated by ./cfa_header_gen.py. + * DO NOT modify this file manually !!!! + * + ****************************************************************************/ +#ifndef _CFA_P70_MPC_STRUCTS_H_ +#define _CFA_P70_MPC_STRUCTS_H_ + +/* clang-format off */ + +/** + * READ_CMD: This command reads 1-4 consecutive 32B words from the + * specified address within a table scope. + */ +struct cfa_mpc_read_cmd { + /* + * This value selects the format for the mid-path command for the CFA. + */ + uint32_t opcode:8; + #define READ_CMD_OPCODE_READ 0 + /* This value selects the table type to be acted upon. */ + uint32_t table_type:4; + #define READ_CMD_TABLE_TYPE_ACTION 0 + #define READ_CMD_TABLE_TYPE_EM 1 + /* Unused field [4] */ + uint32_t unused0:4; + /* Table scope to access. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused1:3; + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + uint32_t data_size:3; + /* Unused field [1] */ + uint32_t unused2:1; + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + uint32_t cache_option:4; + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused3:6; + /* + * The 64-bit host address to which to write the DMA data returned in + * the completion. The data will be written to the same function as the + * one that owns the SQ this command is read from. DATA_SIZE determines + * the maximum size of the data written. If HOST_ADDRESS[1:0] is not 0, + * CFA aborts processing and reports FMT_ERR status. + */ + uint32_t host_address_1:32; + uint32_t host_address_2:32; +}; + +/** + * WRITE_CMD: This command writes 1-4 consecutive 32B words to the + * specified address within a table scope. + */ +struct cfa_mpc_write_cmd { + /* + * This value selects the format for the mid-path command for the CFA. + */ + uint32_t opcode:8; + #define WRITE_CMD_OPCODE_WRITE 1 + /* This value selects the table type to be acted upon. */ + uint32_t table_type:4; + #define WRITE_CMD_TABLE_TYPE_ACTION 0 + #define WRITE_CMD_TABLE_TYPE_EM 1 + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + uint32_t write_through:1; + /* Unused field [3] */ + uint32_t unused0:3; + /* Table scope to access. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused1:3; + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + uint32_t data_size:3; + /* Unused field [1] */ + uint32_t unused2:1; + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + uint32_t cache_option:4; + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + uint32_t table_index:26; + /* Unused field [70] */ + uint32_t unused3_1:6; + uint32_t unused3_2:32; + uint32_t unused3_3:32; +}; + +/** + * READ_CLR_CMD: This command performs a read-modify-write to the + * specified 32B address using a 16b mask that specifies up to 16 16b + * words to clear before writing the data back. It returns the 32B data + * word read from cache (not the value written after the clear + * operation). + */ +struct cfa_mpc_read_clr_cmd { + /* + * This value selects the format for the mid-path command for the CFA. + */ + uint32_t opcode:8; + #define READ_CLR_CMD_OPCODE_READ_CLR 2 + /* This value selects the table type to be acted upon. */ + uint32_t table_type:4; + #define READ_CLR_CMD_TABLE_TYPE_ACTION 0 + #define READ_CLR_CMD_TABLE_TYPE_EM 1 + /* Unused field [4] */ + uint32_t unused0:4; + /* Table scope to access. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused1:3; + /* + * This field is no longer used. The READ_CLR command always reads (and + * does a mask-clear) on a single cache line. This field was added for + * SR2 A0 to avoid an ADDR_ERR when TABLE_INDEX=0 and TABLE_TYPE=EM (see + * CUMULUS-17872). That issue was fixed in SR2 B0. + */ + uint32_t data_size:3; + /* Unused field [1] */ + uint32_t unused2:1; + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + uint32_t cache_option:4; + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused3:6; + /* + * The 64-bit host address to which to write the DMA data returned in + * the completion. The data will be written to the same function as the + * one that owns the SQ this command is read from. DATA_SIZE determines + * the maximum size of the data written. If HOST_ADDRESS[1:0] is not 0, + * CFA aborts processing and reports FMT_ERR status. + */ + uint32_t host_address_1:32; + uint32_t host_address_2:32; + /* + * Specifies bits in 32B data word to clear. For x=0..15, when + * clear_mask[x]=1, data[x*16+15:x*16] is set to 0. + */ + uint32_t clear_mask:16; + /* Unused field [16] */ + uint32_t unused4:16; +}; + +/** + * INVALIDATE_CMD: This command forces an explicit evict of 1-4 + * consecutive cache lines such that the next time the structure is used + * it will be re-read from its backing store location. + */ +struct cfa_mpc_invalidate_cmd { + /* + * This value selects the format for the mid-path command for the CFA. + */ + uint32_t opcode:8; + #define INVALIDATE_CMD_OPCODE_INVALIDATE 5 + /* This value selects the table type to be acted upon. */ + uint32_t table_type:4; + #define INVALIDATE_CMD_TABLE_TYPE_ACTION 0 + #define INVALIDATE_CMD_TABLE_TYPE_EM 1 + /* Unused field [4] */ + uint32_t unused0:4; + /* Table scope to access. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused1:3; + /* + * This value identifies the number of cache lines to invalidate. A + * FMT_ERR is reported if the value is not in the range of [1, 4]. + */ + uint32_t data_size:3; + /* Unused field [1] */ + uint32_t unused2:1; + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + uint32_t cache_option:4; + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused3:6; +}; + +/** + * EM_SEARCH_CMD: This command supplies an exact match entry of 1-4 32B + * words to search for in the exact match table. CFA first computes the + * hash value of the key in the entry, and determines the static bucket + * address to search from the hash and the (EM_BUCKETS, EM_SIZE) for + * TABLE_SCOPE. It then searches that static bucket chain for an entry + * with a matching key (the LREC in the command entry is ignored). If a + * matching entry is found, CFA reports OK status in the completion. + * Otherwise, assuming no errors abort the search before it completes, + * it reports EM_MISS status. + */ +struct cfa_mpc_em_search_cmd { + /* + * This value selects the format for the mid-path command for the CFA. + */ + uint32_t opcode:8; + #define EM_SEARCH_CMD_OPCODE_EM_SEARCH 8 + /* Unused field [8] */ + uint32_t unused0:8; + /* Table scope to access. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused1:3; + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + uint32_t data_size:3; + /* Unused field [1] */ + uint32_t unused2:1; + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + uint32_t cache_option:4; + /* Unused field [96] */ + uint32_t unused3_1:32; + uint32_t unused3_2:32; + uint32_t unused3_3:32; +}; + +/** + * EM_INSERT_CMD: This command supplies an exact match entry of 1-4 32B + * words to insert in the exact match table. CFA first computes the hash + * value of the key in the entry, and determines the static bucket + * address to search from the hash and the (EM_BUCKETS, EM_SIZE) for + * TABLE_SCOPE. It then writes the 1-4 32B words of the exact match + * entry starting at the TABLE_INDEX location in the command. When the + * entry write completes, it searches the static bucket chain for an + * existing entry with a key matching the key in the insert entry (the + * LREC does not need to match). If a matching entry is found: * If + * REPLACE=0, the CFA aborts the insert and returns EM_DUPLICATE status. + * * If REPLACE=1, the CFA overwrites the matching entry with the new + * entry. REPLACED_ENTRY=1 in the completion in this case to signal that + * an entry was replaced. The location of the entry is provided in the + * completion. If no match is found, CFA adds the new entry to the + * lowest unused entry in the tail bucket. If the current tail bucket is + * full, this requires adding a new bucket to the tail. Then entry is + * then inserted at entry number 0. TABLE_INDEX2 provides the address of + * the new tail bucket, if needed. If set to 0, the insert is aborted + * and returns EM_ABORT status instead of adding a new bucket to the + * tail. CHAIN_UPD in the completion indicates whether a new bucket was + * added (1) or not (0). For locked scopes, if the read of the static + * bucket gives a locked scope miss error, indicating that the address + * is not in the cache, the static bucket is assumed empty. In this + * case, TAI creates a new bucket, setting entry 0 to the new entry + * fields and initializing all other fields to 0. It writes this new + * bucket to the static bucket address, which installs it in the cache. + */ +struct cfa_mpc_em_insert_cmd { + /* + * This value selects the format for the mid-path command for the CFA. + */ + uint32_t opcode:8; + #define EM_INSERT_CMD_OPCODE_EM_INSERT 9 + /* Unused field [4] */ + uint32_t unused0:4; + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + uint32_t write_through:1; + /* Unused field [3] */ + uint32_t unused1:3; + /* Table scope to access. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused2:3; + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + uint32_t data_size:3; + /* Unused field [1] */ + uint32_t unused3:1; + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + uint32_t cache_option:4; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Starting + * address to write exact match entry being inserted. + */ + uint32_t table_index:26; + /* Unused field [2] */ + uint32_t unused4:2; + /* + * Determines setting of OPTION field for all cache write requests for + * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support + * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0. + */ + uint32_t cache_option2:4; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Only used + * when no duplicate entry is found and the tail bucket in the chain + * searched has no unused entries. In this case, TABLE_INDEX2 provides + * the index to the 32B dynamic bucket to add to the tail of the chain + * (it is the new tail bucket). In this case, the CFA first writes + * TABLE_INDEX2 with a new bucket: * Entry 0 of the bucket sets the + * HASH_MSBS computed from the hash and ENTRY_PTR to TABLE_INDEX. * + * Entries 1-5 of the bucket set HASH_MSBS and ENTRY_PTR to 0. * CHAIN=0 + * and CHAIN_PTR is set to CHAIN_PTR from to original tail bucket to + * maintain the background chaining. CFA then sets CHAIN=1 and + * CHAIN_PTR=TABLE_INDEX2 in the original tail bucket to link the new + * bucket to the chain. CHAIN_UPD=1 in the completion to signal that the + * new bucket at TABLE_INDEX2 was added to the tail of the chain. + */ + uint32_t table_index2:26; + /* Unused field [5] */ + uint32_t unused5:5; + /* + * Only used if an entry is found whose key matches the exact match + * entry key in the command: * REPLACE=0: The insert is aborted and + * EM_DUPLICATE status is returned, signaling that the insert failed. + * The index of the matching entry that blocked the insertion is + * returned in the completion. * REPLACE=1: The matching entry is + * replaced with that from the command (ENTRY_PTR in the bucket is + * overwritten with TABLE_INDEX from the command). HASH_MSBS for the + * entry number never changes in this case since it had to match the new + * entry key HASH_MSBS to match. When an entry is replaced, + * REPLACED_ENTRY=1 in the completion and the index of the matching + * entry is returned in the completion so that software can de-allocate + * the entry. + */ + uint32_t replace:1; + /* Unused field [32] */ + uint32_t unused6:32; +}; + +/** + * EM_DELETE_CMD: This command searches for an exact match entry index + * in the static bucket chain and deletes it if found. TABLE_INDEX give + * the entry index to delete and TABLE_INDEX2 gives the static bucket + * index. If a matching entry is found: * If the matching entry is the + * last valid entry in the tail bucket, its entry fields (HASH_MSBS and + * ENTRY_PTR) are set to 0 to delete the entry. * If the matching entry + * is not the last valid entry in the tail bucket, the entry fields from + * that last entry are moved to the matching entry, and the fields of + * that last entry are set to 0. * If any of the previous processing + * results in the tail bucket not having any valid entries, the tail + * bucket is the static bucket, the scope is a locked scope, and + * CHAIN_PTR=0, hardware evicts the static bucket from the cache and the + * completion signals this case with CHAIN_UPD=1. * If any of the + * previous processing results in the tail bucket not having any valid + * entries, and the tail bucket is not the static bucket, the tail + * bucket is removed from the chain. In this case, the penultimate + * bucket in the chain becomes the tail bucket. It has CHAIN set to 0 to + * unlink the tail bucket, and CHAIN_PTR set to that from the original + * tail bucket to preserve background chaining. The completion signals + * this case with CHAIN_UPD=1 and returns the index to the bucket + * removed so that software can de-allocate it. CFA returns OK status if + * the entry was successfully deleted. Otherwise, it returns EM_MISS + * status assuming there were no errors that caused processing to be + * aborted. + */ +struct cfa_mpc_em_delete_cmd { + /* + * This value selects the format for the mid-path command for the CFA. + */ + uint32_t opcode:8; + #define EM_DELETE_CMD_OPCODE_EM_DELETE 10 + /* Unused field [4] */ + uint32_t unused0:4; + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + uint32_t write_through:1; + /* Unused field [3] */ + uint32_t unused1:3; + /* Table scope to access. */ + uint32_t table_scope:5; + /* Unused field [7] */ + uint32_t unused2:7; + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + uint32_t cache_option:4; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Entry index + * to delete. + */ + uint32_t table_index:26; + /* Unused field [2] */ + uint32_t unused3:2; + /* + * Determines setting of OPTION field for all cache write requests for + * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support + * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0. + */ + uint32_t cache_option2:4; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Static + * bucket address for bucket chain. + */ + uint32_t table_index2:26; + /* Unused field [6] */ + uint32_t unused4:6; +}; + +/** + * EM_CHAIN_CMD: This command updates CHAIN_PTR in the tail bucket of a + * static bucket chain, supplying both the static bucket and the new + * CHAIN_PTR value. TABLE_INDEX is the new CHAIN_PTR value and + * TABLE_INDEX2[23:0] is the static bucket. This command provides + * software a means to update background chaining coherently with other + * bucket updates. The value of CHAIN is unaffected (stays at 0). For + * locked scopes, if the static bucket is the tail bucket, it is empty + * (all of its ENTRY_PTR values are 0), and TABLE_INDEX=0 (the CHAIN_PTR + * is being set to 0), instead of updating the static bucket it is + * evicted from the cache. In this case, CHAIN_UPD=1 in the completion. + */ +struct cfa_mpc_em_chain_cmd { + /* + * This value selects the format for the mid-path command for the CFA. + */ + uint32_t opcode:8; + #define EM_CHAIN_CMD_OPCODE_EM_CHAIN 11 + /* Unused field [4] */ + uint32_t unused0:4; + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + uint32_t write_through:1; + /* Unused field [3] */ + uint32_t unused1:3; + /* Table scope to access. */ + uint32_t table_scope:5; + /* Unused field [7] */ + uint32_t unused2:7; + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + uint32_t cache_option:4; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. New + * CHAIN_PTR to write to tail bucket. + */ + uint32_t table_index:26; + /* Unused field [2] */ + uint32_t unused3:2; + /* + * Determines setting of OPTION field for all cache write requests for + * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support + * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0. + */ + uint32_t cache_option2:4; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Static + * bucket address for bucket chain. + */ + uint32_t table_index2:26; + /* Unused field [6] */ + uint32_t unused4:6; +}; + +/** + * READ_CMP: When no errors, teturns 1-4 consecutive 32B words from the + * TABLE_INDEX within the TABLE_SCOPE specified in the command, writing + * them to HOST_ADDRESS from the command. + */ +struct cfa_mpc_read_cmp { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + uint32_t type:6; + #define READ_CMP_TYPE_MID_PATH_SHORT 30 + /* Unused field [2] */ + uint32_t unused0:2; + /* The command processing status. */ + uint32_t status:4; + #define READ_CMP_STATUS_OK 0 + #define READ_CMP_STATUS_UNSPRT_ERR 1 + #define READ_CMP_STATUS_FMT_ERR 2 + #define READ_CMP_STATUS_SCOPE_ERR 3 + #define READ_CMP_STATUS_ADDR_ERR 4 + #define READ_CMP_STATUS_CACHE_ERR 5 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + uint32_t mp_client:4; + #define READ_CMP_MP_CLIENT_TE_CFA 2 + #define READ_CMP_MP_CLIENT_RE_CFA 3 + /* OPCODE from the command. */ + uint32_t opcode:8; + #define READ_CMP_OPCODE_READ 0 + /* + * The length of the DMA that accompanies the completion in units of + * DWORDs (32b). Valid values are [0, 128]. A value of zero indicates + * that there is no DMA that accompanies the completion. + */ + uint32_t dma_length:8; + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque:32; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v:1; + /* Unused field [3] */ + uint32_t unused1:3; + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + uint32_t hash_msb:12; + /* Unused field [4] */ + uint32_t unused2:4; + /* TABLE_TYPE from the command. */ + uint32_t table_type:4; + #define READ_CMP_TABLE_TYPE_ACTION 0 + #define READ_CMP_TABLE_TYPE_EM 1 + /* TABLE_SCOPE from the command. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused3:3; + /* TABLE_INDEX from the command. */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused4:6; +}; + +/** + * WRITE_CMP: Returns status of the write of 1-4 consecutive 32B words + * starting at TABLE_INDEX in the table specified by (TABLE_TYPE, + * TABLE_SCOPE). + */ +struct cfa_mpc_write_cmp { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + uint32_t type:6; + #define WRITE_CMP_TYPE_MID_PATH_SHORT 30 + /* Unused field [2] */ + uint32_t unused0:2; + /* The command processing status. */ + uint32_t status:4; + #define WRITE_CMP_STATUS_OK 0 + #define WRITE_CMP_STATUS_UNSPRT_ERR 1 + #define WRITE_CMP_STATUS_FMT_ERR 2 + #define WRITE_CMP_STATUS_SCOPE_ERR 3 + #define WRITE_CMP_STATUS_ADDR_ERR 4 + #define WRITE_CMP_STATUS_CACHE_ERR 5 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + uint32_t mp_client:4; + #define WRITE_CMP_MP_CLIENT_TE_CFA 2 + #define WRITE_CMP_MP_CLIENT_RE_CFA 3 + /* OPCODE from the command. */ + uint32_t opcode:8; + #define WRITE_CMP_OPCODE_WRITE 1 + /* Unused field [8] */ + uint32_t unused1:8; + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque:32; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v:1; + /* Unused field [3] */ + uint32_t unused2:3; + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + uint32_t hash_msb:12; + /* Unused field [4] */ + uint32_t unused3:4; + /* TABLE_TYPE from the command. */ + uint32_t table_type:4; + #define WRITE_CMP_TABLE_TYPE_ACTION 0 + #define WRITE_CMP_TABLE_TYPE_EM 1 + /* TABLE_SCOPE from the command. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused4:3; + /* TABLE_INDEX from the command. */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused5:6; +}; + +/** + * READ_CLR_CMP: When no errors, returns 1 32B word from TABLE_INDEX in + * the table specified by (TABLE_TYPE, TABLE_SCOPE). The data returned + * is the value prior to the clear. + */ +struct cfa_mpc_read_clr_cmp { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + uint32_t type:6; + #define READ_CLR_CMP_TYPE_MID_PATH_SHORT 30 + /* Unused field [2] */ + uint32_t unused0:2; + /* The command processing status. */ + uint32_t status:4; + #define READ_CLR_CMP_STATUS_OK 0 + #define READ_CLR_CMP_STATUS_UNSPRT_ERR 1 + #define READ_CLR_CMP_STATUS_FMT_ERR 2 + #define READ_CLR_CMP_STATUS_SCOPE_ERR 3 + #define READ_CLR_CMP_STATUS_ADDR_ERR 4 + #define READ_CLR_CMP_STATUS_CACHE_ERR 5 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + uint32_t mp_client:4; + #define READ_CLR_CMP_MP_CLIENT_TE_CFA 2 + #define READ_CLR_CMP_MP_CLIENT_RE_CFA 3 + /* OPCODE from the command. */ + uint32_t opcode:8; + #define READ_CLR_CMP_OPCODE_READ_CLR 2 + /* + * The length of the DMA that accompanies the completion in units of + * DWORDs (32b). Valid values are [0, 128]. A value of zero indicates + * that there is no DMA that accompanies the completion. + */ + uint32_t dma_length:8; + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque:32; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v:1; + /* Unused field [3] */ + uint32_t unused1:3; + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + uint32_t hash_msb:12; + /* Unused field [4] */ + uint32_t unused2:4; + /* TABLE_TYPE from the command. */ + uint32_t table_type:4; + #define READ_CLR_CMP_TABLE_TYPE_ACTION 0 + #define READ_CLR_CMP_TABLE_TYPE_EM 1 + /* TABLE_SCOPE from the command. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused3:3; + /* TABLE_INDEX from the command. */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused4:6; +}; + +/** + * INVALIDATE_CMP: Returns status for INVALIDATE commands. + */ +struct cfa_mpc_invalidate_cmp { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + uint32_t type:6; + #define INVALIDATE_CMP_TYPE_MID_PATH_SHORT 30 + /* Unused field [2] */ + uint32_t unused0:2; + /* The command processing status. */ + uint32_t status:4; + #define INVALIDATE_CMP_STATUS_OK 0 + #define INVALIDATE_CMP_STATUS_UNSPRT_ERR 1 + #define INVALIDATE_CMP_STATUS_FMT_ERR 2 + #define INVALIDATE_CMP_STATUS_SCOPE_ERR 3 + #define INVALIDATE_CMP_STATUS_ADDR_ERR 4 + #define INVALIDATE_CMP_STATUS_CACHE_ERR 5 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + uint32_t mp_client:4; + #define INVALIDATE_CMP_MP_CLIENT_TE_CFA 2 + #define INVALIDATE_CMP_MP_CLIENT_RE_CFA 3 + /* OPCODE from the command. */ + uint32_t opcode:8; + #define INVALIDATE_CMP_OPCODE_INVALIDATE 5 + /* Unused field [8] */ + uint32_t unused1:8; + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque:32; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v:1; + /* Unused field [3] */ + uint32_t unused2:3; + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + uint32_t hash_msb:12; + /* Unused field [4] */ + uint32_t unused3:4; + /* TABLE_TYPE from the command. */ + uint32_t table_type:4; + #define INVALIDATE_CMP_TABLE_TYPE_ACTION 0 + #define INVALIDATE_CMP_TABLE_TYPE_EM 1 + /* TABLE_SCOPE from the command. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused4:3; + /* TABLE_INDEX from the command. */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused5:6; +}; + +/** + * EM_SEARCH_CMP: For OK status, returns the index of the matching entry + * found for the EM key supplied in the command. Returns EM_MISS status + * if no match was found. + */ +struct cfa_mpc_em_search_cmp { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + uint32_t type:6; + #define EM_SEARCH_CMP_TYPE_MID_PATH_LONG 31 + /* Unused field [2] */ + uint32_t unused0:2; + /* The command processing status. */ + uint32_t status:4; + #define EM_SEARCH_CMP_STATUS_OK 0 + #define EM_SEARCH_CMP_STATUS_UNSPRT_ERR 1 + #define EM_SEARCH_CMP_STATUS_FMT_ERR 2 + #define EM_SEARCH_CMP_STATUS_SCOPE_ERR 3 + #define EM_SEARCH_CMP_STATUS_ADDR_ERR 4 + #define EM_SEARCH_CMP_STATUS_CACHE_ERR 5 + #define EM_SEARCH_CMP_STATUS_EM_MISS 6 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + uint32_t mp_client:4; + #define EM_SEARCH_CMP_MP_CLIENT_TE_CFA 2 + #define EM_SEARCH_CMP_MP_CLIENT_RE_CFA 3 + /* OPCODE from the command. */ + uint32_t opcode:8; + #define EM_SEARCH_CMP_OPCODE_EM_SEARCH 8 + /* Unused field [8] */ + uint32_t unused1:8; + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque:32; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v1:1; + /* Unused field [3] */ + uint32_t unused2:3; + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + uint32_t hash_msb:12; + /* Unused field [8] */ + uint32_t unused3:8; + /* TABLE_SCOPE from the command. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused4:3; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK + * status, gives ENTRY_PTR[25:0] of the matching entry found. Otherwise, + * set to 0. + */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused5:6; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. If the hash + * is computed (no errors during initial processing of the command), + * TABLE_INDEX2[23:0] is the static bucket address determined from the + * hash of the exact match entry key in the command and the (EM_SIZE, + * EM_BUCKETS) configuration for TABLE_SCOPE of the command. Bits 25:24 + * in this case are set to 0. For any other status, it is always 0. + */ + uint32_t table_index2:26; + /* Unused field [38] */ + uint32_t unused6_1:6; + uint32_t unused6_2:32; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v2:1; + /* Unused field [31] */ + uint32_t unused7:31; + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + uint32_t bkt_num:8; + /* See BKT_NUM description. */ + uint32_t num_entries:3; + /* Unused field [21] */ + uint32_t unused8:21; +}; + +/** + * EM_INSERT_CMP: OK status indicates that the exact match entry from + * the command was successfully inserted. EM_DUPLICATE status indicates + * that the insert was aborted because an entry with the same exact + * match key was found and REPLACE=0 in the command. EM_ABORT status + * indicates that no duplicate was found, the tail bucket in the chain + * was full, and TABLE_INDEX2=0. No changes are made to the database in + * this case. TABLE_INDEX is the starting address at which to insert the + * exact match entry (from the command). TABLE_INDEX2 is the address at + * which to insert a new bucket at the tail of the static bucket chain + * if needed (from the command). CHAIN_UPD=1 if a new bucket was added + * at this address. TABLE_INDEX3 is the static bucket address for the + * chain, determined from hashing the exact match entry. Software needs + * this address and TABLE_INDEX in order to delete the entry using an + * EM_DELETE command. TABLE_INDEX4 is the index of an entry found that + * had a matching exact match key to the command entry key. If no + * matching entry was found, it is set to 0. There are two cases when + * there is a matching entry, depending on REPLACE from the command: * + * REPLACE=0: EM_DUPLICATE status is reported and the insert is aborted. + * Software can use the static bucket address (TABLE_INDEX3[23:0]) and + * the matching entry (TABLE_INDEX4) in an EM_DELETE command if it + * wishes to explicity delete the matching entry. * REPLACE=1: + * REPLACED_ENTRY=1 to signal that the entry at TABLE_INDEX4 was + * replaced by the insert entry. REPLACED_ENTRY will only be 1 if + * reporting OK status in this case. Software can de-allocate the entry + * at TABLE_INDEX4. + */ +struct cfa_mpc_em_insert_cmp { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + uint32_t type:6; + #define EM_INSERT_CMP_TYPE_MID_PATH_LONG 31 + /* Unused field [2] */ + uint32_t unused0:2; + /* The command processing status. */ + uint32_t status:4; + #define EM_INSERT_CMP_STATUS_OK 0 + #define EM_INSERT_CMP_STATUS_UNSPRT_ERR 1 + #define EM_INSERT_CMP_STATUS_FMT_ERR 2 + #define EM_INSERT_CMP_STATUS_SCOPE_ERR 3 + #define EM_INSERT_CMP_STATUS_ADDR_ERR 4 + #define EM_INSERT_CMP_STATUS_CACHE_ERR 5 + #define EM_INSERT_CMP_STATUS_EM_DUPLICATE 7 + #define EM_INSERT_CMP_STATUS_EM_ABORT 9 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + uint32_t mp_client:4; + #define EM_INSERT_CMP_MP_CLIENT_TE_CFA 2 + #define EM_INSERT_CMP_MP_CLIENT_RE_CFA 3 + /* OPCODE from the command. */ + uint32_t opcode:8; + #define EM_INSERT_CMP_OPCODE_EM_INSERT 9 + /* Unused field [8] */ + uint32_t unused1:8; + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque:32; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v1:1; + /* Unused field [3] */ + uint32_t unused2:3; + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + uint32_t hash_msb:12; + /* Unused field [8] */ + uint32_t unused3:8; + /* TABLE_SCOPE from the command. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused4:3; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX + * from the command, which is the starting address at which to insert + * the exact match entry. + */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused5:6; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2 + * from the command, which is the index for the new tail bucket to add + * if needed (CHAIN_UPD=1 if it was used). + */ + uint32_t table_index2:26; + /* Unused field [6] */ + uint32_t unused6:6; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. If the hash + * is computed (no errors during initial processing of the command), + * TABLE_INDEX2[23:0] is the static bucket address determined from the + * hash of the exact match entry key in the command and the (EM_SIZE, + * EM_BUCKETS) configuration for TABLE_SCOPE of the command. Bits 25:24 + * in this case are set to 0. For any other status, it is always 0. + */ + uint32_t table_index3:26; + /* Unused field [6] */ + uint32_t unused7:6; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v2:1; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. ENTRY_PTR of + * matching entry found. Set to 0 if no matching entry found. If + * REPLACED_ENTRY=1, that indicates a matching entry was found and + * REPLACE=1 in the command. In this case, the matching entry was + * replaced by the new entry in the command and this index can therefore + * by de-allocated. + */ + uint32_t table_index4:26; + /* Unused field [5] */ + uint32_t unused8:5; + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + uint32_t bkt_num:8; + /* See BKT_NUM description. */ + uint32_t num_entries:3; + /* + * Specifies if the chain was updated while processing the command: Set + * to 1 when a new bucket is added to the tail of the static bucket + * chain at TABLE_INDEX2. This occurs if and only if the insert requires + * adding a new entry and the tail bucket is full. If set to 0, + * TABLE_INDEX2 was not used and is therefore still free. + */ + uint32_t chain_upd:1; + /* + * Set to 1 if a matching entry was found and REPLACE=1 in command. In + * the case, the entry starting at TABLE_INDEX4 was replaced and can + * therefore be de-allocated. Otherwise, this flag is set to 0. + */ + uint32_t replaced_entry:1; + /* Unused field [19] */ + uint32_t unused9:19; +}; + +/** + * EM_DELETE_CMP: OK status indicates that an ENTRY_PTR matching + * TABLE_INDEX was found in the static bucket chain specified and was + * therefore deleted. EM_MISS status indicates that no match was found. + * TABLE_INDEX is from the command. It is the index of the entry to + * delete. TABLE_INDEX2 is from the command. It is the static bucket + * address. TABLE_INDEX3 is the index of the tail bucket of the static + * bucket chain prior to processing the command. TABLE_INDEX4 is the + * index of the tail bucket of the static bucket chain after processing + * the command. If CHAIN_UPD=1 and TABLE_INDEX4==TABLE_INDEX2, the + * static bucket was the tail bucket, it became empty after the delete, + * the scope is a locked scope, and CHAIN_PTR was 0. In this case, the + * static bucket has been evicted from the cache. Otherwise, if + * CHAIN_UPD=1, the original tail bucket given by TABLE_INDEX3 was + * removed from the chain because it went empty. It can therefore be de- + * allocated. + */ +struct cfa_mpc_em_delete_cmp { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + uint32_t type:6; + #define EM_DELETE_CMP_TYPE_MID_PATH_LONG 31 + /* Unused field [2] */ + uint32_t unused0:2; + /* The command processing status. */ + uint32_t status:4; + #define EM_DELETE_CMP_STATUS_OK 0 + #define EM_DELETE_CMP_STATUS_UNSPRT_ERR 1 + #define EM_DELETE_CMP_STATUS_FMT_ERR 2 + #define EM_DELETE_CMP_STATUS_SCOPE_ERR 3 + #define EM_DELETE_CMP_STATUS_ADDR_ERR 4 + #define EM_DELETE_CMP_STATUS_CACHE_ERR 5 + #define EM_DELETE_CMP_STATUS_EM_MISS 6 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + uint32_t mp_client:4; + #define EM_DELETE_CMP_MP_CLIENT_TE_CFA 2 + #define EM_DELETE_CMP_MP_CLIENT_RE_CFA 3 + /* OPCODE from the command. */ + uint32_t opcode:8; + #define EM_DELETE_CMP_OPCODE_EM_DELETE 10 + /* Unused field [8] */ + uint32_t unused1:8; + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque:32; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v1:1; + /* Unused field [3] */ + uint32_t unused2:3; + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + uint32_t hash_msb:12; + /* Unused field [8] */ + uint32_t unused3:8; + /* TABLE_SCOPE from the command. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused4:3; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX + * from the command, which is the index of the entry to delete. + */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused5:6; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2 + * from the command. + */ + uint32_t table_index2:26; + /* Unused field [6] */ + uint32_t unused6:6; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK or + * EM_MISS status, the index of the tail bucket of the chain prior to + * processing the command. If CHAIN_UPD=1, the bucket was removed and + * this index can be de-allocated. For other status values, it is set to + * 0. + */ + uint32_t table_index3:26; + /* Unused field [6] */ + uint32_t unused7:6; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v2:1; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK or + * EM_MISS status, the index of the tail bucket of the chain prior to + * after the command. If CHAIN_UPD=0 (always for EM_MISS status), it is + * always equal to TABLE_INDEX3 as the chain was not updated. For other + * status values, it is set to 0. + */ + uint32_t table_index4:26; + /* Unused field [5] */ + uint32_t unused8:5; + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + uint32_t bkt_num:8; + /* See BKT_NUM description. */ + uint32_t num_entries:3; + /* + * Specifies if the chain was updated while processing the command: Set + * to 1 when a bucket is removed from the static bucket chain. This + * occurs if after the delete, the tail bucket is a dynamic bucket and + * no longer has any valid entries. In this case, software should de- + * allocate the dynamic bucket at TABLE_INDEX3. It is also set to 1 when + * the static bucket is evicted, which only occurs for locked scopes. + * See the EM_DELETE command description for details. + */ + uint32_t chain_upd:1; + /* Unused field [20] */ + uint32_t unused9:20; +}; + +/** + * EM_CHAIN_CMP: OK status indicates that the CHAIN_PTR of the tail + * bucket was successfully updated. TABLE_INDEX is from the command. It + * is the value of the new CHAIN_PTR. TABLE_INDEX2 is from the command. + * TABLE_INDEX3 is the index of the tail bucket of the static bucket + * chain. + */ +struct cfa_mpc_em_chain_cmp { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + uint32_t type:6; + #define EM_CHAIN_CMP_TYPE_MID_PATH_LONG 31 + /* Unused field [2] */ + uint32_t unused0:2; + /* The command processing status. */ + uint32_t status:4; + #define EM_CHAIN_CMP_STATUS_OK 0 + #define EM_CHAIN_CMP_STATUS_UNSPRT_ERR 1 + #define EM_CHAIN_CMP_STATUS_FMT_ERR 2 + #define EM_CHAIN_CMP_STATUS_SCOPE_ERR 3 + #define EM_CHAIN_CMP_STATUS_ADDR_ERR 4 + #define EM_CHAIN_CMP_STATUS_CACHE_ERR 5 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + uint32_t mp_client:4; + #define EM_CHAIN_CMP_MP_CLIENT_TE_CFA 2 + #define EM_CHAIN_CMP_MP_CLIENT_RE_CFA 3 + /* OPCODE from the command. */ + uint32_t opcode:8; + #define EM_CHAIN_CMP_OPCODE_EM_CHAIN 11 + /* Unused field [8] */ + uint32_t unused1:8; + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque:32; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v1:1; + /* Unused field [3] */ + uint32_t unused2:3; + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + uint32_t hash_msb:12; + /* Unused field [8] */ + uint32_t unused3:8; + /* TABLE_SCOPE from the command. */ + uint32_t table_scope:5; + /* Unused field [3] */ + uint32_t unused4:3; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX + * from the command, which is the new CHAIN_PTR for the tail bucket of + * the static bucket chain. + */ + uint32_t table_index:26; + /* Unused field [6] */ + uint32_t unused5:6; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2 + * from the command. + */ + uint32_t table_index2:26; + /* Unused field [6] */ + uint32_t unused6:6; + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK + * status, the index of the tail bucket of the chain. Otherwise, set to + * 0. + */ + uint32_t table_index3:26; + /* Unused field [6] */ + uint32_t unused7:6; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + uint32_t v2:1; + /* Unused field [31] */ + uint32_t unused8:31; + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + uint32_t bkt_num:8; + /* See BKT_NUM description. */ + uint32_t num_entries:3; + /* + * Set to 1 when the scope is a locked scope, the tail bucket is the + * static bucket, the bucket is empty (all of its ENTRY_PTR values are + * 0), and TABLE_INDEX=0 in the command. In this case, the static bucket + * is evicted. For all other cases, it is set to 0. + */ + uint32_t chain_upd:1; + /* Unused field [20] */ + uint32_t unused9:20; +}; + +/* clang-format on */ + +#endif /* _CFA_P70_MPC_STRUCTS_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/cfa_bld_p70_mpc.c b/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/cfa_bld_p70_mpc.c new file mode 100644 index 0000000000..b65c37e86e --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/cfa_bld_p70_mpc.c @@ -0,0 +1,927 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_p70_mpc.c + * + * @brief CFA phase 7.0 api implementation to build CFA Mid-path commands + * and Parse CFA Mid-path Command completions + */ + +#define COMP_ID BLD + +#include +#include +#include "sys_util.h" +#include "cfa_trace.h" +#include "cfa_types.h" +#include "cfa_p70.h" +#include "cfa_bld_p70_mpc.h" +#include "cfa_bld_p70_mpc_defs.h" +#include "cfa_p70_mpc_structs.h" + +/* CFA MPC client ids */ +#define MP_CLIENT_TE_CFA READ_CMP_MP_CLIENT_TE_CFA +#define MP_CLIENT_RE_CFA READ_CMP_MP_CLIENT_RE_CFA + +/* MPC Client id check in CFA completion messages */ +#define ASSERT_CFA_MPC_CLIENT_ID(MPCID) \ + do { \ + if ((MPCID) != MP_CLIENT_TE_CFA && \ + (MPCID) != MP_CLIENT_RE_CFA) { \ + CFA_LOG_WARN( \ + "Unexpected MPC client id in response: %d\n", \ + (MPCID)); \ + } \ + } while (0) + +#ifdef NXT_ENV_DEBUG +#define ASSERT_RETURN(ERRNO) CFA_LOG_ERR("Returning error: %d\n", (ERRNO)) +#else +#define ASSERT_RETURN(ERRNO) +#endif + +/** + * MPC header definition + */ +struct mpc_header { + uint32_t type : 6; + uint32_t flags : 10; + uint32_t len : 16; + uint32_t opaque; + uint64_t unused; +}; + +/* + * For successful completions of read and read-clear MPC CFA + * commands, the responses will contain this dma info structure + * following the cfa_mpc_read(|clr)_cmp structure and preceding + * the actual data read from the cache. + */ +struct mpc_cr_short_dma_data { + uint32_t dma_length : 8; + uint32_t unused0 : 24; + uint32_t dma_addr0; + uint32_t dma_addr1; +}; + +/** Add MPC header information to MPC command message */ +static int fill_mpc_header(uint8_t *cmd, uint32_t size, uint32_t opaque_val) +{ + struct mpc_header hdr = { + .opaque = opaque_val, + }; + + if (size < sizeof(struct mpc_header)) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + memcpy(cmd, &hdr, sizeof(hdr)); + + return 0; +} + +/** Compose Table read-clear message */ +static int compose_mpc_read_clr_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len, + struct cfa_mpc_cache_axs_params *parms) +{ + struct cfa_mpc_read_clr_cmd *cmd; + struct cfa_mpc_cache_read_params *rd_parms = &parms->read; + uint32_t cmd_size = + sizeof(struct mpc_header) + sizeof(struct cfa_mpc_read_clr_cmd); + + if (parms->data_size != 1) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (parms->tbl_type >= CFA_HW_TABLE_MAX) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (*cmd_buff_len < cmd_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + cmd = (struct cfa_mpc_read_clr_cmd *)(cmd_buff + + sizeof(struct mpc_header)); + + /* Populate CFA MPC command header */ + memset(cmd, 0, sizeof(struct cfa_mpc_read_clr_cmd)); + cmd->opcode = READ_CLR_CMD_OPCODE_READ_CLR; + cmd->table_type = parms->tbl_type; + cmd->table_scope = parms->tbl_scope; + cmd->data_size = parms->data_size; + cmd->table_index = parms->tbl_index; + cmd->host_address_1 = (uint32_t)rd_parms->host_address; + cmd->host_address_2 = (uint32_t)(rd_parms->host_address >> 32); + switch (rd_parms->mode) { + case CFA_MPC_RD_EVICT: + cmd->cache_option = CACHE_READ_CLR_OPTION_EVICT; + break; + default: + case CFA_MPC_RD_NORMAL: + cmd->cache_option = CACHE_READ_CLR_OPTION_NORMAL; + break; + } + cmd->clear_mask = rd_parms->clear_mask; + *cmd_buff_len = cmd_size; + + return 0; +} + +/** Compose Table read message */ +static int compose_mpc_read_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len, + struct cfa_mpc_cache_axs_params *parms) +{ + struct cfa_mpc_read_cmd *cmd; + struct cfa_mpc_cache_read_params *rd_parms = &parms->read; + uint32_t cmd_size = + sizeof(struct mpc_header) + sizeof(struct cfa_mpc_read_cmd); + + if (parms->data_size < 1 || parms->data_size > 4) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (parms->tbl_type >= CFA_HW_TABLE_MAX) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (*cmd_buff_len < cmd_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + cmd = (struct cfa_mpc_read_cmd *)(cmd_buff + sizeof(struct mpc_header)); + + /* Populate CFA MPC command header */ + memset(cmd, 0, sizeof(struct cfa_mpc_read_cmd)); + cmd->opcode = READ_CMD_OPCODE_READ; + cmd->table_type = parms->tbl_type; + cmd->table_scope = parms->tbl_scope; + cmd->data_size = parms->data_size; + cmd->table_index = parms->tbl_index; + cmd->host_address_1 = (uint32_t)rd_parms->host_address; + cmd->host_address_2 = (uint32_t)(rd_parms->host_address >> 32); + switch (rd_parms->mode) { + case CFA_MPC_RD_EVICT: + cmd->cache_option = CACHE_READ_OPTION_EVICT; + break; + case CFA_MPC_RD_DEBUG_LINE: + cmd->cache_option = CACHE_READ_OPTION_DEBUG_LINE; + break; + case CFA_MPC_RD_DEBUG_TAG: + cmd->cache_option = CACHE_READ_OPTION_DEBUG_TAG; + break; + default: + case CFA_MPC_RD_NORMAL: + cmd->cache_option = CACHE_READ_OPTION_NORMAL; + break; + } + *cmd_buff_len = cmd_size; + + return 0; +} + +/** Compose Table write message */ +static int compose_mpc_write_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len, + struct cfa_mpc_cache_axs_params *parms) +{ + struct cfa_mpc_write_cmd *cmd; + struct cfa_mpc_cache_write_params *wr_parms = &parms->write; + uint32_t cmd_size = sizeof(struct mpc_header) + + sizeof(struct cfa_mpc_write_cmd) + + parms->data_size * MPC_CFA_CACHE_ACCESS_UNIT_SIZE; + + if (parms->data_size < 1 || parms->data_size > 4) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (parms->tbl_type >= CFA_HW_TABLE_MAX) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (!parms->write.data_ptr) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (*cmd_buff_len < cmd_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + cmd = (struct cfa_mpc_write_cmd *)(cmd_buff + + sizeof(struct mpc_header)); + + /* Populate CFA MPC command header */ + memset(cmd, 0, sizeof(struct cfa_mpc_write_cmd)); + cmd->opcode = WRITE_CMD_OPCODE_WRITE; + cmd->table_type = parms->tbl_type; + cmd->table_scope = parms->tbl_scope; + cmd->data_size = parms->data_size; + cmd->table_index = parms->tbl_index; + switch (wr_parms->mode) { + case CFA_MPC_WR_WRITE_THRU: + cmd->cache_option = CACHE_WRITE_OPTION_WRITE_THRU; + break; + default: + case CFA_MPC_WR_WRITE_BACK: + cmd->cache_option = CACHE_WRITE_OPTION_WRITE_BACK; + break; + } + + /* Populate CFA MPC command payload following the header */ + memcpy(cmd + 1, wr_parms->data_ptr, + parms->data_size * MPC_CFA_CACHE_ACCESS_UNIT_SIZE); + + *cmd_buff_len = cmd_size; + + return 0; +} + +/** Compose Invalidate message */ +static int compose_mpc_evict_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len, + struct cfa_mpc_cache_axs_params *parms) +{ + struct cfa_mpc_invalidate_cmd *cmd; + struct cfa_mpc_cache_evict_params *ev_parms = &parms->evict; + uint32_t cmd_size = sizeof(struct mpc_header) + + sizeof(struct cfa_mpc_invalidate_cmd); + + if (parms->data_size < 1 || parms->data_size > 4) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (parms->tbl_type >= CFA_HW_TABLE_MAX) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (*cmd_buff_len < cmd_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + cmd = (struct cfa_mpc_invalidate_cmd *)(cmd_buff + + sizeof(struct mpc_header)); + + /* Populate CFA MPC command header */ + memset(cmd, 0, sizeof(struct cfa_mpc_invalidate_cmd)); + cmd->opcode = INVALIDATE_CMD_OPCODE_INVALIDATE; + cmd->table_type = parms->tbl_type; + cmd->table_scope = parms->tbl_scope; + cmd->data_size = parms->data_size; + cmd->table_index = parms->tbl_index; + + switch (ev_parms->mode) { + case CFA_MPC_EV_EVICT_LINE: + cmd->cache_option = CACHE_EVICT_OPTION_LINE; + break; + case CFA_MPC_EV_EVICT_CLEAN_LINES: + cmd->cache_option = CACHE_EVICT_OPTION_CLEAN_LINES; + break; + case CFA_MPC_EV_EVICT_CLEAN_FAST_EVICT_LINES: + cmd->cache_option = CACHE_EVICT_OPTION_CLEAN_FAST_LINES; + break; + case CFA_MPC_EV_EVICT_CLEAN_AND_CLEAN_FAST_EVICT_LINES: + cmd->cache_option = + CACHE_EVICT_OPTION_CLEAN_AND_CLEAN_FAST_EVICT_LINES; + break; + case CFA_MPC_EV_EVICT_TABLE_SCOPE: + /* Not supported */ + ASSERT_RETURN(-ENOTSUP); + return -ENOTSUP; + default: + case CFA_MPC_EV_EVICT_SCOPE_ADDRESS: + cmd->cache_option = CACHE_EVICT_OPTION_SCOPE_ADDRESS; + break; + } + *cmd_buff_len = cmd_size; + + return 0; +} + +/** + * Build MPC CFA Cache access command + * + * @param [in] opc MPC opcode + * + * @param [out] cmd_buff Command data buffer to write the command to + * + * @param [in/out] cmd_buff_len Pointer to command buffer size param + * Set by caller to indicate the input cmd_buff size. + * Set to the actual size of the command generated by the api. + * + * @param [in] parms Pointer to MPC cache access command parameters + * + * @return 0 on Success, negative errno on failure + */ +int cfa_mpc_build_cache_axs_cmd(enum cfa_mpc_opcode opc, uint8_t *cmd_buff, + uint32_t *cmd_buff_len, + struct cfa_mpc_cache_axs_params *parms) +{ + int rc; + if (!cmd_buff || !cmd_buff_len || *cmd_buff_len == 0 || !parms) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + rc = fill_mpc_header(cmd_buff, *cmd_buff_len, parms->opaque); + if (rc) + return rc; + + switch (opc) { + case CFA_MPC_READ_CLR: + return compose_mpc_read_clr_msg(cmd_buff, cmd_buff_len, parms); + case CFA_MPC_READ: + return compose_mpc_read_msg(cmd_buff, cmd_buff_len, parms); + case CFA_MPC_WRITE: + return compose_mpc_write_msg(cmd_buff, cmd_buff_len, parms); + case CFA_MPC_INVALIDATE: + return compose_mpc_evict_msg(cmd_buff, cmd_buff_len, parms); + default: + ASSERT_RETURN(-ENOTSUP); + return -ENOTSUP; + } +} + +/** Compose EM Search message */ +static int compose_mpc_em_search_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len, + struct cfa_mpc_em_op_params *parms) +{ + struct cfa_mpc_em_search_cmd *cmd; + struct cfa_mpc_em_search_params *e = &parms->search; + uint32_t cmd_size = sizeof(struct mpc_header) + + sizeof(struct cfa_mpc_em_search_cmd) + + e->data_size * MPC_CFA_CACHE_ACCESS_UNIT_SIZE; + + if (e->data_size < 1 || e->data_size > 4) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (*cmd_buff_len < cmd_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (!e->em_entry) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + cmd = (struct cfa_mpc_em_search_cmd *)(cmd_buff + + sizeof(struct mpc_header)); + + /* Populate CFA MPC command header */ + memset(cmd, 0, sizeof(struct cfa_mpc_em_search_cmd)); + cmd->opcode = EM_SEARCH_CMD_OPCODE_EM_SEARCH; + cmd->table_scope = parms->tbl_scope; + cmd->data_size = e->data_size; + /* Default to normal read cache option for EM search */ + cmd->cache_option = CACHE_READ_OPTION_NORMAL; + + /* Populate CFA MPC command payload following the header */ + memcpy(cmd + 1, e->em_entry, + e->data_size * MPC_CFA_CACHE_ACCESS_UNIT_SIZE); + + *cmd_buff_len = cmd_size; + + return 0; +} + +/** Compose EM Insert message */ +static int compose_mpc_em_insert_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len, + struct cfa_mpc_em_op_params *parms) +{ + struct cfa_mpc_em_insert_cmd *cmd; + struct cfa_mpc_em_insert_params *e = &parms->insert; + uint32_t cmd_size = sizeof(struct mpc_header) + + sizeof(struct cfa_mpc_em_insert_cmd) + + e->data_size * MPC_CFA_CACHE_ACCESS_UNIT_SIZE; + + if (e->data_size < 1 || e->data_size > 4) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (*cmd_buff_len < cmd_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (!e->em_entry) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + cmd = (struct cfa_mpc_em_insert_cmd *)(cmd_buff + + sizeof(struct mpc_header)); + + /* Populate CFA MPC command header */ + memset(cmd, 0, sizeof(struct cfa_mpc_em_insert_cmd)); + cmd->opcode = EM_INSERT_CMD_OPCODE_EM_INSERT; + cmd->write_through = 1; + cmd->table_scope = parms->tbl_scope; + cmd->data_size = e->data_size; + cmd->replace = e->replace; + cmd->table_index = e->entry_idx; + cmd->table_index2 = e->bucket_idx; + /* Default to normal read cache option for EM insert */ + cmd->cache_option = CACHE_READ_OPTION_NORMAL; + /* Default to write through cache write option for EM insert */ + cmd->cache_option2 = CACHE_WRITE_OPTION_WRITE_THRU; + + /* Populate CFA MPC command payload following the header */ + memcpy(cmd + 1, e->em_entry, + e->data_size * MPC_CFA_CACHE_ACCESS_UNIT_SIZE); + + *cmd_buff_len = cmd_size; + + return 0; +} + +/** Compose EM Delete message */ +static int compose_mpc_em_delete_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len, + struct cfa_mpc_em_op_params *parms) +{ + struct cfa_mpc_em_delete_cmd *cmd; + struct cfa_mpc_em_delete_params *e = &parms->del; + uint32_t cmd_size = sizeof(struct mpc_header) + + sizeof(struct cfa_mpc_em_delete_cmd); + + if (*cmd_buff_len < cmd_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + /* Populate CFA MPC command header */ + cmd = (struct cfa_mpc_em_delete_cmd *)(cmd_buff + + sizeof(struct mpc_header)); + memset(cmd, 0, sizeof(struct cfa_mpc_em_delete_cmd)); + cmd->opcode = EM_DELETE_CMD_OPCODE_EM_DELETE; + cmd->table_scope = parms->tbl_scope; + cmd->table_index = e->entry_idx; + cmd->table_index2 = e->bucket_idx; + /* Default to normal read cache option for EM delete */ + cmd->cache_option = CACHE_READ_OPTION_NORMAL; + /* Default to write through cache write option for EM delete */ + cmd->cache_option2 = CACHE_WRITE_OPTION_WRITE_THRU; + + *cmd_buff_len = cmd_size; + + return 0; +} + +/** Compose EM Chain message */ +static int compose_mpc_em_chain_msg(uint8_t *cmd_buff, uint32_t *cmd_buff_len, + struct cfa_mpc_em_op_params *parms) +{ + struct cfa_mpc_em_chain_cmd *cmd; + struct cfa_mpc_em_chain_params *e = &parms->chain; + uint32_t cmd_size = + sizeof(struct mpc_header) + sizeof(struct cfa_mpc_em_chain_cmd); + + if (*cmd_buff_len < cmd_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + /* Populate CFA MPC command header */ + cmd = (struct cfa_mpc_em_chain_cmd *)(cmd_buff + + sizeof(struct mpc_header)); + memset(cmd, 0, sizeof(struct cfa_mpc_em_chain_cmd)); + cmd->opcode = EM_CHAIN_CMD_OPCODE_EM_CHAIN; + cmd->table_scope = parms->tbl_scope; + cmd->table_index = e->entry_idx; + cmd->table_index2 = e->bucket_idx; + /* Default to normal read cache option for EM delete */ + cmd->cache_option = CACHE_READ_OPTION_NORMAL; + /* Default to write through cache write option for EM delete */ + cmd->cache_option2 = CACHE_WRITE_OPTION_WRITE_THRU; + + *cmd_buff_len = cmd_size; + + return 0; +} + +/** + * Build MPC CFA EM operation command + * + * @param [in] opc MPC EM opcode + * + * @param [in] cmd_buff Command data buffer to write the command to + * + * @param [in/out] cmd_buff_len Pointer to command buffer size param + * Set by caller to indicate the input cmd_buff size. + * Set to the actual size of the command generated by the api. + * + * @param [in] parms Pointer to MPC cache access command parameters + * + * @return 0 on Success, negative errno on failure + */ +int cfa_mpc_build_em_op_cmd(enum cfa_mpc_opcode opc, uint8_t *cmd_buff, + uint32_t *cmd_buff_len, + struct cfa_mpc_em_op_params *parms) +{ + int rc; + if (!cmd_buff || !cmd_buff_len || *cmd_buff_len == 0 || !parms) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + rc = fill_mpc_header(cmd_buff, *cmd_buff_len, parms->opaque); + if (rc) + return rc; + + switch (opc) { + case CFA_MPC_EM_SEARCH: + return compose_mpc_em_search_msg(cmd_buff, cmd_buff_len, parms); + case CFA_MPC_EM_INSERT: + return compose_mpc_em_insert_msg(cmd_buff, cmd_buff_len, parms); + case CFA_MPC_EM_DELETE: + return compose_mpc_em_delete_msg(cmd_buff, cmd_buff_len, parms); + case CFA_MPC_EM_CHAIN: + return compose_mpc_em_chain_msg(cmd_buff, cmd_buff_len, parms); + default: + ASSERT_RETURN(-ENOTSUP); + return -ENOTSUP; + } + + return 0; +} + +/** Parse MPC read clear completion */ +static int parse_mpc_read_clr_result(uint8_t *resp_buff, uint32_t resp_buff_len, + struct cfa_mpc_cache_axs_result *result) +{ + uint8_t *rd_data; + uint32_t resp_size, rd_size; + struct cfa_mpc_read_clr_cmp *cmp; + + /* Minimum data size = 1 32B unit */ + rd_size = MPC_CFA_CACHE_ACCESS_UNIT_SIZE; + resp_size = sizeof(struct mpc_header) + + sizeof(struct cfa_mpc_read_clr_cmp) + + sizeof(struct mpc_cr_short_dma_data) + rd_size; + cmp = (struct cfa_mpc_read_clr_cmp *)(resp_buff + + sizeof(struct mpc_header)); + + if (resp_buff_len < resp_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (result->data_len < rd_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (!result->rd_data) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + ASSERT_CFA_MPC_CLIENT_ID(cmp->mp_client); + + result->status = cmp->status; + result->error_data = cmp->hash_msb; + result->opaque = cmp->opaque; + + /* No data to copy if there was an error, return early */ + if (cmp->status != READ_CLR_CMP_STATUS_OK) + return 0; + + /* Copy the read data - starting at the end of the completion header including dma data */ + rd_data = resp_buff + sizeof(struct mpc_header) + + sizeof(struct cfa_mpc_read_clr_cmp) + + sizeof(struct mpc_cr_short_dma_data); + memcpy(result->rd_data, rd_data, rd_size); + + return 0; +} + +/** Parse MPC table read completion */ +static int parse_mpc_read_result(uint8_t *resp_buff, uint32_t resp_buff_len, + struct cfa_mpc_cache_axs_result *result) +{ + uint8_t *rd_data; + uint32_t resp_size, rd_size; + struct cfa_mpc_read_cmp *cmp; + + /* Minimum data size = 1 32B unit */ + rd_size = MPC_CFA_CACHE_ACCESS_UNIT_SIZE; + resp_size = sizeof(struct mpc_header) + + sizeof(struct cfa_mpc_read_cmp) + + sizeof(struct mpc_cr_short_dma_data) + rd_size; + cmp = (struct cfa_mpc_read_cmp *)(resp_buff + + sizeof(struct mpc_header)); + + if (resp_buff_len < resp_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (result->data_len < rd_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (!result->rd_data) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + ASSERT_CFA_MPC_CLIENT_ID(cmp->mp_client); + + result->status = cmp->status; + result->error_data = cmp->hash_msb; + result->opaque = cmp->opaque; + + /* No data to copy if there was an error, return early */ + if (cmp->status != READ_CMP_STATUS_OK) + return 0; + + /* Copy max of 4 32B words that can fit into the return buffer */ + rd_size = MIN(4 * MPC_CFA_CACHE_ACCESS_UNIT_SIZE, result->data_len); + + /* Copy the read data - starting at the end of the completion header */ + rd_data = resp_buff + sizeof(struct mpc_header) + + sizeof(struct cfa_mpc_read_cmp) + + sizeof(struct mpc_cr_short_dma_data); + memcpy(result->rd_data, rd_data, rd_size); + + return 0; +} + +/** Parse MPC table write completion */ +static int parse_mpc_write_result(uint8_t *resp_buff, uint32_t resp_buff_len, + struct cfa_mpc_cache_axs_result *result) +{ + uint32_t resp_size; + struct cfa_mpc_write_cmp *cmp; + + resp_size = + sizeof(struct mpc_header) + sizeof(struct cfa_mpc_write_cmp); + cmp = (struct cfa_mpc_write_cmp *)(resp_buff + + sizeof(struct mpc_header)); + + if (resp_buff_len < resp_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + ASSERT_CFA_MPC_CLIENT_ID(cmp->mp_client); + + result->status = cmp->status; + result->error_data = cmp->hash_msb; + result->opaque = cmp->opaque; + return 0; +} + +/** Parse MPC table evict completion */ +static int parse_mpc_evict_result(uint8_t *resp_buff, uint32_t resp_buff_len, + struct cfa_mpc_cache_axs_result *result) +{ + uint32_t resp_size; + struct cfa_mpc_invalidate_cmp *cmp; + + resp_size = sizeof(struct mpc_header) + + sizeof(struct cfa_mpc_invalidate_cmp); + cmp = (struct cfa_mpc_invalidate_cmp *)(resp_buff + + sizeof(struct mpc_header)); + + if (resp_buff_len < resp_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + ASSERT_CFA_MPC_CLIENT_ID(cmp->mp_client); + + result->status = cmp->status; + result->error_data = cmp->hash_msb; + result->opaque = cmp->opaque; + return 0; +} + +/** + * Parse MPC CFA Cache access command completion result + * + * @param [in] opc MPC cache access opcode + * + * @param [in] resp_buff Data buffer containing the response to parse + * + * @param [in] resp_buff_len Response buffer size + * + * @param [out] result Pointer to MPC cache access result object. This + * object will contain the fields parsed and extracted from the + * response buffer. + * + * @return 0 on Success, negative errno on failure + */ +int cfa_mpc_parse_cache_axs_resp(enum cfa_mpc_opcode opc, uint8_t *resp_buff, + uint32_t resp_buff_len, + struct cfa_mpc_cache_axs_result *result) +{ + if (!resp_buff || resp_buff_len == 0 || !result) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + switch (opc) { + case CFA_MPC_READ_CLR: + return parse_mpc_read_clr_result(resp_buff, resp_buff_len, + result); + case CFA_MPC_READ: + return parse_mpc_read_result(resp_buff, resp_buff_len, result); + case CFA_MPC_WRITE: + return parse_mpc_write_result(resp_buff, resp_buff_len, result); + case CFA_MPC_INVALIDATE: + return parse_mpc_evict_result(resp_buff, resp_buff_len, result); + default: + ASSERT_RETURN(-ENOTSUP); + return -ENOTSUP; + } +} + +/** Parse MPC EM Search completion */ +static int parse_mpc_em_search_result(uint8_t *resp_buff, + uint32_t resp_buff_len, + struct cfa_mpc_em_op_result *result) +{ + uint32_t resp_size; + struct cfa_mpc_em_search_cmp *cmp; + + cmp = (struct cfa_mpc_em_search_cmp *)(resp_buff + + sizeof(struct mpc_header)); + resp_size = sizeof(struct mpc_header) + + sizeof(struct cfa_mpc_em_search_cmp); + + if (resp_buff_len < resp_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + ASSERT_CFA_MPC_CLIENT_ID(cmp->mp_client); + + result->status = cmp->status; + result->error_data = cmp->status != CFA_MPC_OK ? cmp->hash_msb : 0; + result->opaque = cmp->opaque; + result->search.bucket_num = cmp->bkt_num; + result->search.num_entries = cmp->num_entries; + result->search.hash_msb = cmp->hash_msb; + result->search.match_idx = cmp->table_index; + result->search.bucket_idx = cmp->table_index2; + + return 0; +} + +/** Parse MPC EM Insert completion */ +static int parse_mpc_em_insert_result(uint8_t *resp_buff, + uint32_t resp_buff_len, + struct cfa_mpc_em_op_result *result) +{ + uint32_t resp_size; + struct cfa_mpc_em_insert_cmp *cmp; + + cmp = (struct cfa_mpc_em_insert_cmp *)(resp_buff + + sizeof(struct mpc_header)); + resp_size = sizeof(struct mpc_header) + + sizeof(struct cfa_mpc_em_insert_cmp); + + if (resp_buff_len < resp_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + ASSERT_CFA_MPC_CLIENT_ID(cmp->mp_client); + + result->status = cmp->status; + result->error_data = cmp->status != CFA_MPC_OK ? cmp->hash_msb : 0; + result->opaque = cmp->opaque; + result->insert.bucket_num = cmp->bkt_num; + result->insert.num_entries = cmp->num_entries; + result->insert.hash_msb = cmp->hash_msb; + result->insert.match_idx = cmp->table_index4; + result->insert.bucket_idx = cmp->table_index3; + result->insert.replaced = cmp->replaced_entry; + result->insert.chain_update = cmp->chain_upd; + + return 0; +} + +/** Parse MPC EM Delete completion */ +static int parse_mpc_em_delete_result(uint8_t *resp_buff, + uint32_t resp_buff_len, + struct cfa_mpc_em_op_result *result) +{ + uint32_t resp_size; + struct cfa_mpc_em_delete_cmp *cmp; + + cmp = (struct cfa_mpc_em_delete_cmp *)(resp_buff + + sizeof(struct mpc_header)); + resp_size = sizeof(struct mpc_header) + + sizeof(struct cfa_mpc_em_delete_cmp); + + if (resp_buff_len < resp_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + ASSERT_CFA_MPC_CLIENT_ID(cmp->mp_client); + + result->status = cmp->status; + result->error_data = cmp->hash_msb; + result->opaque = cmp->opaque; + result->del.bucket_num = cmp->bkt_num; + result->del.num_entries = cmp->num_entries; + result->del.prev_tail = cmp->table_index3; + result->del.new_tail = cmp->table_index4; + result->del.chain_update = cmp->chain_upd; + + return 0; +} + +/** Parse MPC EM Chain completion */ +static int parse_mpc_em_chain_result(uint8_t *resp_buff, uint32_t resp_buff_len, + struct cfa_mpc_em_op_result *result) +{ + uint32_t resp_size; + struct cfa_mpc_em_chain_cmp *cmp; + + cmp = (struct cfa_mpc_em_chain_cmp *)(resp_buff + + sizeof(struct mpc_header)); + resp_size = + sizeof(struct mpc_header) + sizeof(struct cfa_mpc_em_chain_cmp); + + if (resp_buff_len < resp_size) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + ASSERT_CFA_MPC_CLIENT_ID(cmp->mp_client); + + result->status = cmp->status; + result->error_data = cmp->hash_msb; + result->opaque = cmp->opaque; + result->chain.bucket_num = cmp->bkt_num; + result->chain.num_entries = cmp->num_entries; + + return 0; +} + +/** + * Parse MPC CFA EM operation command completion result + * + * @param [in] opc MPC cache access opcode + * + * @param [in] resp_buff Data buffer containing the response to parse + * + * @param [in] resp_buff_len Response buffer size + * + * @param [out] result Pointer to MPC EM operation result object. This + * object will contain the fields parsed and extracted from the + * response buffer. + * + * @return 0 on Success, negative errno on failure + */ +int cfa_mpc_parse_em_op_resp(enum cfa_mpc_opcode opc, uint8_t *resp_buff, + uint32_t resp_buff_len, + struct cfa_mpc_em_op_result *result) +{ + if (!resp_buff || resp_buff_len == 0 || !result) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + switch (opc) { + case CFA_MPC_EM_SEARCH: + return parse_mpc_em_search_result(resp_buff, resp_buff_len, + result); + case CFA_MPC_EM_INSERT: + return parse_mpc_em_insert_result(resp_buff, resp_buff_len, + result); + case CFA_MPC_EM_DELETE: + return parse_mpc_em_delete_result(resp_buff, resp_buff_len, + result); + case CFA_MPC_EM_CHAIN: + return parse_mpc_em_chain_result(resp_buff, resp_buff_len, + result); + default: + ASSERT_RETURN(-ENOTSUP); + return -ENOTSUP; + } +} diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/cfa_bld_p70_mpc_defs.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/cfa_bld_p70_mpc_defs.h new file mode 100644 index 0000000000..ff0ba7b7cb --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/cfa_bld_p70_mpc_defs.h @@ -0,0 +1,51 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_p70_mpc_defs.h + * + * @brief CFA phase 7.0 spefific MPC CFA command/completion field definitions + */ + +#ifndef _CFA_BLD_P70_MPC_DEFS_H_ +#define _CFA_BLD_P70_MPC_DEFS_H_ + +/* + * CFA phase 7.0 Action/Lookup cache option values for various accesses + * From EAS + */ +#define CACHE_READ_OPTION_NORMAL 0x0 +#define CACHE_READ_OPTION_EVICT 0x1 +#define CACHE_READ_OPTION_FAST_EVICT 0x2 +#define CACHE_READ_OPTION_DEBUG_LINE 0x4 +#define CACHE_READ_OPTION_DEBUG_TAG 0x5 + +/* + * Cache read and clear command expects the cache option bit 3 + * to be set, failing which the clear is not done. + */ +#define CACHE_READ_CLR_MASK (0x1U << 3) +#define CACHE_READ_CLR_OPTION_NORMAL \ + (CACHE_READ_CLR_MASK | CACHE_READ_OPTION_NORMAL) +#define CACHE_READ_CLR_OPTION_EVICT \ + (CACHE_READ_CLR_MASK | CACHE_READ_OPTION_EVICT) +#define CACHE_READ_CLR_OPTION_FAST_EVICT \ + (CACHE_READ_CLR_MASK | CACHE_READ_OPTION_FAST_EVICT) + +#define CACHE_WRITE_OPTION_WRITE_BACK 0x0 +#define CACHE_WRITE_OPTION_WRITE_THRU 0x1 + +#define CACHE_EVICT_OPTION_CLEAN_LINES 0x1 +#define CACHE_EVICT_OPTION_CLEAN_FAST_LINES 0x2 +#define CACHE_EVICT_OPTION_CLEAN_AND_CLEAN_FAST_EVICT_LINES 0x3 +#define CACHE_EVICT_OPTION_LINE 0x4 +#define CACHE_EVICT_OPTION_SCOPE_ADDRESS 0x5 + +/* EM/action cache access unit size in bytes */ +#define MPC_CFA_CACHE_ACCESS_UNIT_SIZE CFA_P70_CACHE_LINE_BYTES + +#endif /* _CFA_BLD_P70_MPC_DEFS_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_host_mpc_wrapper.c b/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_host_mpc_wrapper.c new file mode 100644 index 0000000000..40aa966116 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_host_mpc_wrapper.c @@ -0,0 +1,1127 @@ +/**************************************************************************** + * Copyright(c) 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_p70_host_mpc_wrapper.c + * + * @brief CFA Phase 7.0 specific MPC Builder Wrapper functions + */ + +#define COMP_ID BLD + +#include +#include +#include "sys_util.h" +#include "cfa_trace.h" + +#include "cfa_types.h" +#include "cfa_bld_mpcops.h" + +#include "host/cfa_bld_mpc_field_ids.h" +#include "host/cfa_p70_mpc_field_ids.h" +#include "p70/cfa_p70_mpc_structs.h" +#include "p70/cfa_bld_p70_mpc.h" +#include "cfa_bld_p70_host_mpc_wrapper.h" +#include "host/cfa_p70_mpc_field_mapping.h" + +#ifdef NXT_ENV_DEBUG +#define ASSERT_RETURN(ERRNO) CFA_LOG_ERR("Returning error: %d\n", (ERRNO)) +#else +#define ASSERT_RETURN(ERRNO) +#endif + +/* + * Helper macro to set an input parm field from fields array + */ +#define SET_PARM_VALUE(NAME, TYPE, INDEX, FIELDS) \ + do { \ + if (FIELDS[INDEX].field_id != INVALID_U16) \ + parms.NAME = (TYPE)fields[INDEX].val; \ + } while (0) + +/* + * Helper macro to set an input parm field from fields array thorugh a mapping + * function + */ +#define SET_PARM_MAPPED_VALUE(NAME, TYPE, INDEX, FIELDS, MAP_FUNC) \ + ({ \ + int retcode = 0; \ + if (FIELDS[INDEX].field_id != INVALID_U16) { \ + int retcode; \ + uint64_t mapped_val; \ + retcode = MAP_FUNC(fields[INDEX].val, &mapped_val); \ + if (retcode) \ + ASSERT_RETURN(retcode); \ + else \ + parms.NAME = (TYPE)mapped_val; \ + } \ + retcode; \ + }) + +/* + * Helper macro to set a result field into fields array + */ +#define GET_RESP_VALUE(NAME, INDEX, FIELDS) \ + do { \ + if (FIELDS[INDEX].field_id != INVALID_U16) \ + FIELDS[INDEX].val = (uint64_t)result.NAME; \ + } while (0) + +/* + * Helper macro to set a result field into fields array thorugh a mapping + * function + */ +#define GET_RESP_MAPPED_VALUE(NAME, INDEX, FIELDS, MAP_FUNC) \ + ({ \ + int retcode = 0; \ + if (FIELDS[INDEX].field_id != INVALID_U16) { \ + int retcode; \ + uint64_t mapped_val; \ + retcode = MAP_FUNC(result.NAME, &mapped_val); \ + if (retcode) \ + ASSERT_RETURN(retcode); \ + else \ + fields[INDEX].val = mapped_val; \ + } \ + retcode; \ + }) + +/* + * MPC fields validate routine. + */ +static bool fields_valid(struct cfa_mpc_data_obj *fields, uint16_t len, + struct field_mapping *fld_map) +{ + int i; + + for (i = 0; i < len; i++) { + /* Field not requested to be set by caller, skip it */ + if (fields[i].field_id == INVALID_U16) + continue; + + /* + * Field id should be index value unless + * it is set to UINT16_MAx + */ + if (fields[i].field_id != i) + return false; + + /* Field is valid */ + if (!fld_map[i].valid) + return false; + } + + return true; +} + +/* Map global table type definition to p70 specific value */ +static int table_type_map(uint64_t val, uint64_t *mapped_val) +{ + switch (val) { + case CFA_BLD_MPC_HW_TABLE_TYPE_ACTION: + *mapped_val = CFA_HW_TABLE_ACTION; + break; + case CFA_BLD_MPC_HW_TABLE_TYPE_LOOKUP: + *mapped_val = CFA_HW_TABLE_LOOKUP; + break; + default: + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + return 0; +} + +/* Map global read mode value to p70 specific value */ +static int read_mode_map(uint64_t val, uint64_t *mapped_val) +{ + switch (val) { + case CFA_BLD_MPC_RD_NORMAL: + *mapped_val = CFA_MPC_RD_NORMAL; + break; + case CFA_BLD_MPC_RD_EVICT: + *mapped_val = CFA_MPC_RD_EVICT; + break; + case CFA_BLD_MPC_RD_DEBUG_LINE: + *mapped_val = CFA_MPC_RD_DEBUG_LINE; + break; + case CFA_BLD_MPC_RD_DEBUG_TAG: + *mapped_val = CFA_MPC_RD_DEBUG_TAG; + break; + default: + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + return 0; +} + +/* Map global write mode value to p70 specific value */ +static int write_mode_map(uint64_t val, uint64_t *mapped_val) +{ + switch (val) { + case CFA_BLD_MPC_WR_WRITE_THRU: + *mapped_val = CFA_MPC_WR_WRITE_THRU; + break; + case CFA_BLD_MPC_WR_WRITE_BACK: + *mapped_val = CFA_MPC_WR_WRITE_BACK; + break; + default: + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + return 0; +} + +/* Map global evict mode value to p70 specific value */ +static int evict_mode_map(uint64_t val, uint64_t *mapped_val) +{ + switch (val) { + case CFA_BLD_MPC_EV_EVICT_LINE: + *mapped_val = CFA_MPC_EV_EVICT_LINE; + break; + case CFA_BLD_MPC_EV_EVICT_SCOPE_ADDRESS: + *mapped_val = CFA_MPC_EV_EVICT_SCOPE_ADDRESS; + break; + case CFA_BLD_MPC_EV_EVICT_CLEAN_LINES: + *mapped_val = CFA_MPC_EV_EVICT_CLEAN_LINES; + break; + case CFA_BLD_MPC_EV_EVICT_CLEAN_FAST_EVICT_LINES: + *mapped_val = CFA_MPC_EV_EVICT_CLEAN_FAST_EVICT_LINES; + break; + case CFA_BLD_MPC_EV_EVICT_CLEAN_AND_CLEAN_FAST_EVICT_LINES: + *mapped_val = CFA_MPC_EV_EVICT_CLEAN_AND_CLEAN_FAST_EVICT_LINES; + break; + case CFA_BLD_MPC_EV_EVICT_TABLE_SCOPE: + *mapped_val = CFA_MPC_EV_EVICT_TABLE_SCOPE; + break; + default: + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + return 0; +} + +/* Map device specific response status code to global value */ +static int status_code_map(uint64_t val, uint64_t *mapped_val) +{ + switch (val) { + case CFA_MPC_OK: + *mapped_val = CFA_BLD_MPC_OK; + break; + case CFA_MPC_UNSPRT_ERR: + *mapped_val = CFA_BLD_MPC_UNSPRT_ERR; + break; + case CFA_MPC_FMT_ERR: + *mapped_val = CFA_BLD_MPC_FMT_ERR; + break; + case CFA_MPC_SCOPE_ERR: + *mapped_val = CFA_BLD_MPC_SCOPE_ERR; + break; + case CFA_MPC_ADDR_ERR: + *mapped_val = CFA_BLD_MPC_ADDR_ERR; + break; + case CFA_MPC_CACHE_ERR: + *mapped_val = CFA_BLD_MPC_CACHE_ERR; + break; + case CFA_MPC_EM_MISS: + *mapped_val = CFA_BLD_MPC_EM_MISS; + break; + case CFA_MPC_EM_DUPLICATE: + *mapped_val = CFA_BLD_MPC_EM_DUPLICATE; + break; + case CFA_MPC_EM_EVENT_COLLECTION_FAIL: + *mapped_val = CFA_BLD_MPC_EM_EVENT_COLLECTION_FAIL; + break; + case CFA_MPC_EM_ABORT: + *mapped_val = CFA_BLD_MPC_EM_ABORT; + break; + default: + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + return 0; +} + +static bool has_unsupported_fields(struct cfa_mpc_data_obj *fields, + uint16_t len, uint16_t *unsup_flds, + uint16_t unsup_flds_len) +{ + int i, j; + + for (i = 0; i < len; i++) { + /* Skip invalid fields */ + if (fields[i].field_id == INVALID_U16) + continue; + + for (j = 0; j < unsup_flds_len; j++) { + if (fields[i].field_id == unsup_flds[j]) + return true; + } + } + + return false; +} + +int cfa_bld_p70_mpc_build_cache_read(uint8_t *cmd, uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields) +{ + int rc; + struct cfa_mpc_cache_axs_params parms = { 0 }; + + /* Parameters check */ + if (!cmd || !cmd_buff_len || !fields) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (!fields_valid(fields, CFA_BLD_MPC_READ_CMD_MAX_FLD, + cfa_p70_mpc_read_cmd_gbl_to_dev)) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + /* Prepare parameters structure */ + SET_PARM_VALUE(opaque, uint32_t, CFA_BLD_MPC_READ_CMD_OPAQUE_FLD, + fields); + SET_PARM_VALUE(tbl_scope, uint8_t, CFA_BLD_MPC_READ_CMD_TABLE_SCOPE_FLD, + fields); + SET_PARM_VALUE(tbl_index, uint32_t, + CFA_BLD_MPC_READ_CMD_TABLE_INDEX_FLD, fields); + SET_PARM_VALUE(data_size, uint8_t, CFA_BLD_MPC_READ_CMD_DATA_SIZE_FLD, + fields); + SET_PARM_VALUE(read.host_address, uint64_t, + CFA_BLD_MPC_READ_CMD_HOST_ADDRESS_FLD, fields); + rc = SET_PARM_MAPPED_VALUE(tbl_type, enum cfa_hw_table_type, + CFA_BLD_MPC_READ_CMD_TABLE_TYPE_FLD, fields, + table_type_map); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + rc = SET_PARM_MAPPED_VALUE(read.mode, enum cfa_mpc_read_mode, + CFA_BLD_MPC_READ_CMD_CACHE_OPTION_FLD, + fields, read_mode_map); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + return cfa_mpc_build_cache_axs_cmd(CFA_MPC_READ, cmd, cmd_buff_len, + &parms); +} + +int cfa_bld_p70_mpc_build_cache_write(uint8_t *cmd, uint32_t *cmd_buff_len, + const uint8_t *data, + struct cfa_mpc_data_obj *fields) +{ + int rc; + struct cfa_mpc_cache_axs_params parms = { 0 }; + + /* Parameters check */ + if (!cmd || !cmd_buff_len || !fields) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (!fields_valid(fields, CFA_BLD_MPC_WRITE_CMD_MAX_FLD, + cfa_p70_mpc_write_cmd_gbl_to_dev)) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + /* Prepare parameters structure */ + SET_PARM_VALUE(opaque, uint32_t, CFA_BLD_MPC_WRITE_CMD_OPAQUE_FLD, + fields); + SET_PARM_VALUE(tbl_scope, uint8_t, + CFA_BLD_MPC_WRITE_CMD_TABLE_SCOPE_FLD, fields); + SET_PARM_VALUE(tbl_index, uint32_t, + CFA_BLD_MPC_WRITE_CMD_TABLE_INDEX_FLD, fields); + SET_PARM_VALUE(data_size, uint8_t, CFA_BLD_MPC_WRITE_CMD_DATA_SIZE_FLD, + fields); + rc = SET_PARM_MAPPED_VALUE(tbl_type, enum cfa_hw_table_type, + CFA_BLD_MPC_WRITE_CMD_TABLE_TYPE_FLD, fields, + table_type_map); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + parms.write.data_ptr = data; + rc = SET_PARM_MAPPED_VALUE(write.mode, enum cfa_mpc_write_mode, + CFA_BLD_MPC_WRITE_CMD_CACHE_OPTION_FLD, + fields, write_mode_map); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + return cfa_mpc_build_cache_axs_cmd(CFA_MPC_WRITE, cmd, cmd_buff_len, + &parms); +} + +int cfa_bld_p70_mpc_build_cache_evict(uint8_t *cmd, uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields) +{ + int rc; + struct cfa_mpc_cache_axs_params parms = { 0 }; + + /* Parameters check */ + if (!cmd || !cmd_buff_len || !fields) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (!fields_valid(fields, CFA_BLD_MPC_INVALIDATE_CMD_MAX_FLD, + cfa_p70_mpc_invalidate_cmd_gbl_to_dev)) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + /* Prepare parameters structure */ + SET_PARM_VALUE(opaque, uint32_t, CFA_BLD_MPC_INVALIDATE_CMD_OPAQUE_FLD, + fields); + SET_PARM_VALUE(tbl_scope, uint8_t, + CFA_BLD_MPC_INVALIDATE_CMD_TABLE_SCOPE_FLD, fields); + SET_PARM_VALUE(tbl_index, uint32_t, + CFA_BLD_MPC_INVALIDATE_CMD_TABLE_INDEX_FLD, fields); + SET_PARM_VALUE(data_size, uint8_t, + CFA_BLD_MPC_INVALIDATE_CMD_DATA_SIZE_FLD, fields); + rc = SET_PARM_MAPPED_VALUE(tbl_type, enum cfa_hw_table_type, + CFA_BLD_MPC_INVALIDATE_CMD_TABLE_TYPE_FLD, + fields, table_type_map); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + rc = SET_PARM_MAPPED_VALUE(evict.mode, enum cfa_mpc_evict_mode, + CFA_BLD_MPC_INVALIDATE_CMD_CACHE_OPTION_FLD, + fields, evict_mode_map); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + return cfa_mpc_build_cache_axs_cmd(CFA_MPC_INVALIDATE, cmd, + cmd_buff_len, &parms); +} + +int cfa_bld_p70_mpc_build_cache_rdclr(uint8_t *cmd, uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields) +{ + int rc; + struct cfa_mpc_cache_axs_params parms = { 0 }; + + /* Parameters check */ + if (!cmd || !cmd_buff_len || !fields) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (!fields_valid(fields, CFA_BLD_MPC_READ_CLR_CMD_MAX_FLD, + cfa_p70_mpc_read_clr_cmd_gbl_to_dev)) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + /* Prepare parameters structure */ + SET_PARM_VALUE(opaque, uint32_t, CFA_BLD_MPC_READ_CLR_CMD_OPAQUE_FLD, + fields); + SET_PARM_VALUE(tbl_scope, uint8_t, + CFA_BLD_MPC_READ_CLR_CMD_TABLE_SCOPE_FLD, fields); + SET_PARM_VALUE(tbl_index, uint32_t, + CFA_BLD_MPC_READ_CLR_CMD_TABLE_INDEX_FLD, fields); + SET_PARM_VALUE(data_size, uint8_t, + CFA_BLD_MPC_READ_CLR_CMD_DATA_SIZE_FLD, fields); + SET_PARM_VALUE(read.host_address, uint64_t, + CFA_BLD_MPC_READ_CLR_CMD_HOST_ADDRESS_FLD, fields); + rc = SET_PARM_MAPPED_VALUE(tbl_type, enum cfa_hw_table_type, + CFA_BLD_MPC_READ_CLR_CMD_TABLE_TYPE_FLD, + fields, table_type_map); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + SET_PARM_VALUE(read.clear_mask, uint16_t, + CFA_BLD_MPC_READ_CLR_CMD_CLEAR_MASK_FLD, fields); + rc = SET_PARM_MAPPED_VALUE(read.mode, enum cfa_mpc_read_mode, + CFA_BLD_MPC_READ_CLR_CMD_CACHE_OPTION_FLD, + fields, read_mode_map); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + return cfa_mpc_build_cache_axs_cmd(CFA_MPC_READ_CLR, cmd, cmd_buff_len, + &parms); +} + +int cfa_bld_p70_mpc_build_em_search(uint8_t *cmd, uint32_t *cmd_buff_len, + uint8_t *em_entry, + struct cfa_mpc_data_obj *fields) +{ + struct cfa_mpc_em_op_params parms = { 0 }; + uint16_t unsupported_fields[] = { + CFA_BLD_MPC_EM_SEARCH_CMD_CACHE_OPTION_FLD, + }; + + /* Parameters check */ + if (!cmd || !cmd_buff_len || !fields) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (has_unsupported_fields(fields, CFA_BLD_MPC_EM_SEARCH_CMD_MAX_FLD, + unsupported_fields, + ARRAY_SIZE(unsupported_fields))) { + ASSERT_RETURN(-ENOTSUP); + return -ENOTSUP; + } + + if (!fields_valid(fields, CFA_BLD_MPC_EM_SEARCH_CMD_MAX_FLD, + cfa_p70_mpc_em_search_cmd_gbl_to_dev)) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + /* Prepare parameters structure */ + SET_PARM_VALUE(opaque, uint32_t, CFA_BLD_MPC_EM_SEARCH_CMD_OPAQUE_FLD, + fields); + SET_PARM_VALUE(tbl_scope, uint8_t, + CFA_BLD_MPC_EM_SEARCH_CMD_TABLE_SCOPE_FLD, fields); + + parms.search.em_entry = em_entry; + SET_PARM_VALUE(search.data_size, uint8_t, + CFA_BLD_MPC_EM_SEARCH_CMD_DATA_SIZE_FLD, fields); + + return cfa_mpc_build_em_op_cmd(CFA_MPC_EM_SEARCH, cmd, cmd_buff_len, + &parms); +} + +int cfa_bld_p70_mpc_build_em_insert(uint8_t *cmd, uint32_t *cmd_buff_len, + const uint8_t *em_entry, + struct cfa_mpc_data_obj *fields) +{ + struct cfa_mpc_em_op_params parms = { 0 }; + uint16_t unsupported_fields[] = { + CFA_BLD_MPC_EM_INSERT_CMD_WRITE_THROUGH_FLD, + CFA_BLD_MPC_EM_INSERT_CMD_CACHE_OPTION_FLD, + CFA_BLD_MPC_EM_INSERT_CMD_CACHE_OPTION2_FLD, + }; + + /* Parameters check */ + if (!cmd || !cmd_buff_len || !fields) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (has_unsupported_fields(fields, CFA_BLD_MPC_EM_INSERT_CMD_MAX_FLD, + unsupported_fields, + ARRAY_SIZE(unsupported_fields))) { + ASSERT_RETURN(-ENOTSUP); + return -ENOTSUP; + } + + if (!fields_valid(fields, CFA_BLD_MPC_EM_INSERT_CMD_MAX_FLD, + cfa_p70_mpc_em_insert_cmd_gbl_to_dev)) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + /* Prepare parameters structure */ + SET_PARM_VALUE(opaque, uint32_t, CFA_BLD_MPC_EM_INSERT_CMD_OPAQUE_FLD, + fields); + SET_PARM_VALUE(tbl_scope, uint8_t, + CFA_BLD_MPC_EM_INSERT_CMD_TABLE_SCOPE_FLD, fields); + + parms.insert.em_entry = (const uint8_t *)em_entry; + SET_PARM_VALUE(insert.replace, uint8_t, + CFA_BLD_MPC_EM_INSERT_CMD_REPLACE_FLD, fields); + SET_PARM_VALUE(insert.entry_idx, uint32_t, + CFA_BLD_MPC_EM_INSERT_CMD_TABLE_INDEX_FLD, fields); + SET_PARM_VALUE(insert.bucket_idx, uint32_t, + CFA_BLD_MPC_EM_INSERT_CMD_TABLE_INDEX2_FLD, fields); + SET_PARM_VALUE(insert.data_size, uint8_t, + CFA_BLD_MPC_EM_INSERT_CMD_DATA_SIZE_FLD, fields); + + return cfa_mpc_build_em_op_cmd(CFA_MPC_EM_INSERT, cmd, cmd_buff_len, + &parms); +} + +int cfa_bld_p70_mpc_build_em_delete(uint8_t *cmd, uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields) +{ + struct cfa_mpc_em_op_params parms = { 0 }; + uint16_t unsupported_fields[] = { + CFA_BLD_MPC_EM_DELETE_CMD_WRITE_THROUGH_FLD, + CFA_BLD_MPC_EM_DELETE_CMD_CACHE_OPTION_FLD, + CFA_BLD_MPC_EM_DELETE_CMD_CACHE_OPTION2_FLD, + }; + + /* Parameters check */ + if (!cmd || !cmd_buff_len || !fields) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (has_unsupported_fields(fields, CFA_BLD_MPC_EM_DELETE_CMD_MAX_FLD, + unsupported_fields, + ARRAY_SIZE(unsupported_fields))) { + ASSERT_RETURN(-ENOTSUP); + return -ENOTSUP; + } + + if (!fields_valid(fields, CFA_BLD_MPC_EM_DELETE_CMD_MAX_FLD, + cfa_p70_mpc_em_delete_cmd_gbl_to_dev)) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + /* Prepare parameters structure */ + SET_PARM_VALUE(opaque, uint32_t, CFA_BLD_MPC_EM_DELETE_CMD_OPAQUE_FLD, + fields); + SET_PARM_VALUE(tbl_scope, uint8_t, + CFA_BLD_MPC_EM_DELETE_CMD_TABLE_SCOPE_FLD, fields); + + SET_PARM_VALUE(del.entry_idx, uint32_t, + CFA_BLD_MPC_EM_DELETE_CMD_TABLE_INDEX_FLD, fields); + SET_PARM_VALUE(del.bucket_idx, uint32_t, + CFA_BLD_MPC_EM_DELETE_CMD_TABLE_INDEX2_FLD, fields); + + return cfa_mpc_build_em_op_cmd(CFA_MPC_EM_DELETE, cmd, cmd_buff_len, + &parms); +} + +int cfa_bld_p70_mpc_build_em_chain(uint8_t *cmd, uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields) +{ + struct cfa_mpc_em_op_params parms = { 0 }; + uint16_t unsupported_fields[] = { + CFA_BLD_MPC_EM_CHAIN_CMD_WRITE_THROUGH_FLD, + CFA_BLD_MPC_EM_CHAIN_CMD_CACHE_OPTION_FLD, + CFA_BLD_MPC_EM_CHAIN_CMD_CACHE_OPTION2_FLD, + }; + + /* Parameters check */ + if (!cmd || !cmd_buff_len || !fields) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (has_unsupported_fields(fields, CFA_BLD_MPC_EM_CHAIN_CMD_MAX_FLD, + unsupported_fields, + ARRAY_SIZE(unsupported_fields))) { + ASSERT_RETURN(-ENOTSUP); + return -ENOTSUP; + } + + if (!fields_valid(fields, CFA_BLD_MPC_EM_CHAIN_CMD_MAX_FLD, + cfa_p70_mpc_em_chain_cmd_gbl_to_dev)) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + /* Prepare parameters structure */ + SET_PARM_VALUE(opaque, uint32_t, CFA_BLD_MPC_EM_CHAIN_CMD_OPAQUE_FLD, + fields); + SET_PARM_VALUE(tbl_scope, uint8_t, + CFA_BLD_MPC_EM_CHAIN_CMD_TABLE_SCOPE_FLD, fields); + + SET_PARM_VALUE(chain.entry_idx, uint32_t, + CFA_BLD_MPC_EM_CHAIN_CMD_TABLE_INDEX_FLD, fields); + SET_PARM_VALUE(chain.bucket_idx, uint32_t, + CFA_BLD_MPC_EM_CHAIN_CMD_TABLE_INDEX2_FLD, fields); + + return cfa_mpc_build_em_op_cmd(CFA_MPC_EM_CHAIN, cmd, cmd_buff_len, + &parms); +} + +int cfa_bld_p70_mpc_parse_cache_read(uint8_t *resp, uint32_t resp_buff_len, + uint8_t *rd_data, uint32_t rd_data_len, + struct cfa_mpc_data_obj *fields) +{ + int rc; + struct cfa_mpc_cache_axs_result result = { 0 }; + uint16_t unsupported_fields[] = { + CFA_BLD_MPC_READ_CMP_TYPE_FLD, + CFA_BLD_MPC_READ_CMP_MP_CLIENT_FLD, + CFA_BLD_MPC_READ_CMP_DMA_LENGTH_FLD, + CFA_BLD_MPC_READ_CMP_OPCODE_FLD, + CFA_BLD_MPC_READ_CMP_V_FLD, + CFA_BLD_MPC_READ_CMP_TABLE_TYPE_FLD, + CFA_BLD_MPC_READ_CMP_TABLE_SCOPE_FLD, + CFA_BLD_MPC_READ_CMP_TABLE_INDEX_FLD, + }; + + /* Parameters check */ + if (!resp || !resp_buff_len || !fields || !rd_data) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (has_unsupported_fields(fields, CFA_BLD_MPC_READ_CMP_MAX_FLD, + unsupported_fields, + ARRAY_SIZE(unsupported_fields))) { + ASSERT_RETURN(-ENOTSUP); + return -ENOTSUP; + } + + if (!fields_valid(fields, CFA_BLD_MPC_READ_CMP_MAX_FLD, + cfa_p70_mpc_read_cmp_gbl_to_dev)) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + /* Retrieve response parameters */ + result.rd_data = rd_data; + result.data_len = rd_data_len; + rc = cfa_mpc_parse_cache_axs_resp(CFA_MPC_READ, resp, resp_buff_len, + &result); + if (rc) + return rc; + + GET_RESP_VALUE(opaque, CFA_BLD_MPC_READ_CMP_OPAQUE_FLD, fields); + GET_RESP_VALUE(error_data, CFA_BLD_MPC_READ_CMP_HASH_MSB_FLD, fields); + rc = GET_RESP_MAPPED_VALUE(status, CFA_BLD_MPC_READ_CMP_STATUS_FLD, + fields, status_code_map); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + return 0; +} + +int cfa_bld_p70_mpc_parse_cache_write(uint8_t *resp, uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields) +{ + int rc; + struct cfa_mpc_cache_axs_result result = { 0 }; + uint16_t unsupported_fields[] = { + CFA_BLD_MPC_WRITE_CMP_TYPE_FLD, + CFA_BLD_MPC_WRITE_CMP_MP_CLIENT_FLD, + CFA_BLD_MPC_WRITE_CMP_OPCODE_FLD, + CFA_BLD_MPC_WRITE_CMP_V_FLD, + CFA_BLD_MPC_WRITE_CMP_TABLE_TYPE_FLD, + CFA_BLD_MPC_WRITE_CMP_TABLE_SCOPE_FLD, + CFA_BLD_MPC_WRITE_CMP_TABLE_INDEX_FLD, + }; + + /* Parameters check */ + if (!resp || !resp_buff_len || !fields) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (has_unsupported_fields(fields, CFA_BLD_MPC_WRITE_CMP_MAX_FLD, + unsupported_fields, + ARRAY_SIZE(unsupported_fields))) { + ASSERT_RETURN(-ENOTSUP); + return -ENOTSUP; + } + + if (!fields_valid(fields, CFA_BLD_MPC_WRITE_CMP_MAX_FLD, + cfa_p70_mpc_write_cmp_gbl_to_dev)) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + /* Retrieve response parameters */ + rc = cfa_mpc_parse_cache_axs_resp(CFA_MPC_WRITE, resp, resp_buff_len, + &result); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + GET_RESP_VALUE(opaque, CFA_BLD_MPC_WRITE_CMP_OPAQUE_FLD, fields); + GET_RESP_VALUE(error_data, CFA_BLD_MPC_WRITE_CMP_HASH_MSB_FLD, fields); + rc = GET_RESP_MAPPED_VALUE(status, CFA_BLD_MPC_WRITE_CMP_STATUS_FLD, + fields, status_code_map); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + return 0; +} + +int cfa_bld_p70_mpc_parse_cache_evict(uint8_t *resp, uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields) +{ + int rc; + struct cfa_mpc_cache_axs_result result = { 0 }; + uint16_t unsupported_fields[] = { + CFA_BLD_MPC_INVALIDATE_CMP_TYPE_FLD, + CFA_BLD_MPC_INVALIDATE_CMP_MP_CLIENT_FLD, + CFA_BLD_MPC_INVALIDATE_CMP_OPCODE_FLD, + CFA_BLD_MPC_INVALIDATE_CMP_V_FLD, + CFA_BLD_MPC_INVALIDATE_CMP_TABLE_TYPE_FLD, + CFA_BLD_MPC_INVALIDATE_CMP_TABLE_SCOPE_FLD, + CFA_BLD_MPC_INVALIDATE_CMP_TABLE_INDEX_FLD, + }; + + /* Parameters check */ + if (!resp || !resp_buff_len || !fields) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (has_unsupported_fields(fields, CFA_BLD_MPC_INVALIDATE_CMP_MAX_FLD, + unsupported_fields, + ARRAY_SIZE(unsupported_fields))) { + ASSERT_RETURN(-ENOTSUP); + return -ENOTSUP; + } + + if (!fields_valid(fields, CFA_BLD_MPC_INVALIDATE_CMP_MAX_FLD, + cfa_p70_mpc_invalidate_cmp_gbl_to_dev)) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + /* Retrieve response parameters */ + rc = cfa_mpc_parse_cache_axs_resp(CFA_MPC_INVALIDATE, resp, + resp_buff_len, &result); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + GET_RESP_VALUE(opaque, CFA_BLD_MPC_INVALIDATE_CMP_OPAQUE_FLD, fields); + GET_RESP_VALUE(error_data, CFA_BLD_MPC_INVALIDATE_CMP_HASH_MSB_FLD, + fields); + rc = GET_RESP_MAPPED_VALUE(status, + CFA_BLD_MPC_INVALIDATE_CMP_STATUS_FLD, + fields, status_code_map); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + return 0; +} + +int cfa_bld_p70_mpc_parse_cache_rdclr(uint8_t *resp, uint32_t resp_buff_len, + uint8_t *rd_data, uint32_t rd_data_len, + struct cfa_mpc_data_obj *fields) +{ + int rc; + struct cfa_mpc_cache_axs_result result = { 0 }; + uint16_t unsupported_fields[] = { + CFA_BLD_MPC_READ_CMP_TYPE_FLD, + CFA_BLD_MPC_READ_CMP_MP_CLIENT_FLD, + CFA_BLD_MPC_READ_CMP_DMA_LENGTH_FLD, + CFA_BLD_MPC_READ_CMP_OPCODE_FLD, + CFA_BLD_MPC_READ_CMP_V_FLD, + CFA_BLD_MPC_READ_CMP_TABLE_TYPE_FLD, + CFA_BLD_MPC_READ_CMP_TABLE_SCOPE_FLD, + CFA_BLD_MPC_READ_CMP_TABLE_INDEX_FLD, + }; + + /* Parameters check */ + if (!resp || !resp_buff_len || !fields || !rd_data) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (has_unsupported_fields(fields, CFA_BLD_MPC_READ_CMP_MAX_FLD, + unsupported_fields, + ARRAY_SIZE(unsupported_fields))) { + ASSERT_RETURN(-ENOTSUP); + return -ENOTSUP; + } + + if (!fields_valid(fields, CFA_BLD_MPC_READ_CMP_MAX_FLD, + cfa_p70_mpc_read_cmp_gbl_to_dev)) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + /* Retrieve response parameters */ + result.rd_data = rd_data; + result.data_len = rd_data_len; + rc = cfa_mpc_parse_cache_axs_resp(CFA_MPC_READ_CLR, resp, resp_buff_len, + &result); + if (rc) + return rc; + + GET_RESP_VALUE(opaque, CFA_BLD_MPC_READ_CMP_OPAQUE_FLD, fields); + GET_RESP_VALUE(error_data, CFA_BLD_MPC_READ_CMP_HASH_MSB_FLD, fields); + rc = GET_RESP_MAPPED_VALUE(status, CFA_BLD_MPC_READ_CMP_STATUS_FLD, + fields, status_code_map); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + return 0; +} + +int cfa_bld_p70_mpc_parse_em_search(uint8_t *resp, uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields) +{ + int rc; + struct cfa_mpc_em_op_result result = { 0 }; + uint16_t unsupported_fields[] = { + CFA_BLD_MPC_EM_SEARCH_CMP_TYPE_FLD, + CFA_BLD_MPC_EM_SEARCH_CMP_MP_CLIENT_FLD, + CFA_BLD_MPC_EM_SEARCH_CMP_OPCODE_FLD, + CFA_BLD_MPC_EM_SEARCH_CMP_V1_FLD, + CFA_BLD_MPC_EM_SEARCH_CMP_TABLE_SCOPE_FLD, + CFA_BLD_MPC_EM_SEARCH_CMP_V2_FLD, + }; + + /* Parameters check */ + if (!resp || !resp_buff_len || !fields) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (has_unsupported_fields(fields, CFA_BLD_MPC_EM_SEARCH_CMP_MAX_FLD, + unsupported_fields, + ARRAY_SIZE(unsupported_fields))) { + ASSERT_RETURN(-ENOTSUP); + return -ENOTSUP; + } + + if (!fields_valid(fields, CFA_BLD_MPC_EM_SEARCH_CMP_MAX_FLD, + cfa_p70_mpc_em_search_cmp_gbl_to_dev)) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + /* Retrieve response parameters */ + rc = cfa_mpc_parse_em_op_resp(CFA_MPC_EM_SEARCH, resp, resp_buff_len, + &result); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + GET_RESP_VALUE(opaque, CFA_BLD_MPC_EM_SEARCH_CMP_OPAQUE_FLD, fields); + GET_RESP_VALUE(error_data, CFA_BLD_MPC_EM_SEARCH_CMP_HASH_MSB_FLD, + fields); + rc = GET_RESP_MAPPED_VALUE(status, CFA_BLD_MPC_EM_SEARCH_CMP_STATUS_FLD, + fields, status_code_map); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + GET_RESP_VALUE(search.bucket_num, CFA_BLD_MPC_EM_SEARCH_CMP_BKT_NUM_FLD, + fields); + GET_RESP_VALUE(search.num_entries, + CFA_BLD_MPC_EM_SEARCH_CMP_NUM_ENTRIES_FLD, fields); + GET_RESP_VALUE(search.hash_msb, CFA_BLD_MPC_EM_SEARCH_CMP_HASH_MSB_FLD, + fields); + GET_RESP_VALUE(search.match_idx, + CFA_BLD_MPC_EM_SEARCH_CMP_TABLE_INDEX_FLD, fields); + GET_RESP_VALUE(search.bucket_idx, + CFA_BLD_MPC_EM_SEARCH_CMP_TABLE_INDEX2_FLD, fields); + + return 0; +} + +int cfa_bld_p70_mpc_parse_em_insert(uint8_t *resp, uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields) +{ + int rc; + struct cfa_mpc_em_op_result result = { 0 }; + uint16_t unsupported_fields[] = { + CFA_BLD_MPC_EM_INSERT_CMP_TYPE_FLD, + CFA_BLD_MPC_EM_INSERT_CMP_MP_CLIENT_FLD, + CFA_BLD_MPC_EM_INSERT_CMP_OPCODE_FLD, + CFA_BLD_MPC_EM_INSERT_CMP_V1_FLD, + CFA_BLD_MPC_EM_INSERT_CMP_TABLE_SCOPE_FLD, + CFA_BLD_MPC_EM_INSERT_CMP_V2_FLD, + CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX_FLD, + CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX2_FLD, + }; + + /* Parameters check */ + if (!resp || !resp_buff_len || !fields) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (has_unsupported_fields(fields, CFA_BLD_MPC_EM_INSERT_CMP_MAX_FLD, + unsupported_fields, + ARRAY_SIZE(unsupported_fields))) { + ASSERT_RETURN(-ENOTSUP); + return -ENOTSUP; + } + + if (!fields_valid(fields, CFA_BLD_MPC_EM_INSERT_CMP_MAX_FLD, + cfa_p70_mpc_em_insert_cmp_gbl_to_dev)) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + /* Retrieve response parameters */ + rc = cfa_mpc_parse_em_op_resp(CFA_MPC_EM_INSERT, resp, resp_buff_len, + &result); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + GET_RESP_VALUE(opaque, CFA_BLD_MPC_EM_INSERT_CMP_OPAQUE_FLD, fields); + GET_RESP_VALUE(error_data, CFA_BLD_MPC_EM_INSERT_CMP_HASH_MSB_FLD, + fields); + rc = GET_RESP_MAPPED_VALUE(status, CFA_BLD_MPC_EM_INSERT_CMP_STATUS_FLD, + fields, status_code_map); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + GET_RESP_VALUE(insert.bucket_num, CFA_BLD_MPC_EM_INSERT_CMP_BKT_NUM_FLD, + fields); + GET_RESP_VALUE(insert.num_entries, + CFA_BLD_MPC_EM_INSERT_CMP_NUM_ENTRIES_FLD, fields); + GET_RESP_VALUE(insert.hash_msb, CFA_BLD_MPC_EM_INSERT_CMP_HASH_MSB_FLD, + fields); + GET_RESP_VALUE(insert.match_idx, + CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX4_FLD, fields); + GET_RESP_VALUE(insert.bucket_idx, + CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX3_FLD, fields); + GET_RESP_VALUE(insert.replaced, + CFA_BLD_MPC_EM_INSERT_CMP_REPLACED_ENTRY_FLD, fields); + GET_RESP_VALUE(insert.chain_update, + CFA_BLD_MPC_EM_INSERT_CMP_CHAIN_UPD_FLD, fields); + + return 0; +} + +int cfa_bld_p70_mpc_parse_em_delete(uint8_t *resp, uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields) +{ + int rc; + struct cfa_mpc_em_op_result result = { 0 }; + uint16_t unsupported_fields[] = { + CFA_BLD_MPC_EM_DELETE_CMP_TYPE_FLD, + CFA_BLD_MPC_EM_DELETE_CMP_MP_CLIENT_FLD, + CFA_BLD_MPC_EM_DELETE_CMP_OPCODE_FLD, + CFA_BLD_MPC_EM_DELETE_CMP_V1_FLD, + CFA_BLD_MPC_EM_DELETE_CMP_TABLE_SCOPE_FLD, + CFA_BLD_MPC_EM_DELETE_CMP_V2_FLD, + CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX_FLD, + CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX2_FLD, + }; + + /* Parameters check */ + if (!resp || !resp_buff_len || !fields) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (has_unsupported_fields(fields, CFA_BLD_MPC_EM_DELETE_CMP_MAX_FLD, + unsupported_fields, + ARRAY_SIZE(unsupported_fields))) { + ASSERT_RETURN(-ENOTSUP); + return -ENOTSUP; + } + + if (!fields_valid(fields, CFA_BLD_MPC_EM_DELETE_CMP_MAX_FLD, + cfa_p70_mpc_em_delete_cmp_gbl_to_dev)) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + /* Retrieve response parameters */ + rc = cfa_mpc_parse_em_op_resp(CFA_MPC_EM_DELETE, resp, resp_buff_len, + &result); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + GET_RESP_VALUE(opaque, CFA_BLD_MPC_EM_DELETE_CMP_OPAQUE_FLD, fields); + GET_RESP_VALUE(error_data, CFA_BLD_MPC_EM_DELETE_CMP_HASH_MSB_FLD, + fields); + rc = GET_RESP_MAPPED_VALUE(status, CFA_BLD_MPC_EM_DELETE_CMP_STATUS_FLD, + fields, status_code_map); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + GET_RESP_VALUE(del.new_tail, CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX4_FLD, + fields); + GET_RESP_VALUE(del.prev_tail, + CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX3_FLD, fields); + GET_RESP_VALUE(del.chain_update, + CFA_BLD_MPC_EM_DELETE_CMP_CHAIN_UPD_FLD, fields); + GET_RESP_VALUE(del.bucket_num, CFA_BLD_MPC_EM_DELETE_CMP_BKT_NUM_FLD, + fields); + GET_RESP_VALUE(del.num_entries, + CFA_BLD_MPC_EM_DELETE_CMP_NUM_ENTRIES_FLD, fields); + return 0; +} + +int cfa_bld_p70_mpc_parse_em_chain(uint8_t *resp, uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields) +{ + int rc; + struct cfa_mpc_em_op_result result = { 0 }; + uint16_t unsupported_fields[] = { + CFA_BLD_MPC_EM_CHAIN_CMP_TYPE_FLD, + CFA_BLD_MPC_EM_CHAIN_CMP_MP_CLIENT_FLD, + CFA_BLD_MPC_EM_CHAIN_CMP_OPCODE_FLD, + CFA_BLD_MPC_EM_CHAIN_CMP_V1_FLD, + CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_SCOPE_FLD, + CFA_BLD_MPC_EM_CHAIN_CMP_V2_FLD, + CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_INDEX_FLD, + CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_INDEX2_FLD, + }; + + /* Parameters check */ + if (!resp || !resp_buff_len || !fields) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + if (has_unsupported_fields(fields, CFA_BLD_MPC_EM_CHAIN_CMP_MAX_FLD, + unsupported_fields, + ARRAY_SIZE(unsupported_fields))) { + ASSERT_RETURN(-ENOTSUP); + return -ENOTSUP; + } + + if (!fields_valid(fields, CFA_BLD_MPC_EM_CHAIN_CMP_MAX_FLD, + cfa_p70_mpc_em_chain_cmp_gbl_to_dev)) { + ASSERT_RETURN(-EINVAL); + return -EINVAL; + } + + /* Retrieve response parameters */ + rc = cfa_mpc_parse_em_op_resp(CFA_MPC_EM_CHAIN, resp, resp_buff_len, + &result); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + GET_RESP_VALUE(opaque, CFA_BLD_MPC_EM_CHAIN_CMP_OPAQUE_FLD, fields); + GET_RESP_VALUE(error_data, CFA_BLD_MPC_EM_CHAIN_CMP_HASH_MSB_FLD, + fields); + rc = GET_RESP_MAPPED_VALUE(status, CFA_BLD_MPC_EM_CHAIN_CMP_STATUS_FLD, + fields, status_code_map); + if (rc) { + ASSERT_RETURN(rc); + return rc; + } + + GET_RESP_VALUE(chain.bucket_num, CFA_BLD_MPC_EM_CHAIN_CMP_BKT_NUM_FLD, + fields); + GET_RESP_VALUE(chain.num_entries, + CFA_BLD_MPC_EM_CHAIN_CMP_NUM_ENTRIES_FLD, fields); + return 0; +} diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_host_mpc_wrapper.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_host_mpc_wrapper.h new file mode 100644 index 0000000000..284412d649 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_host_mpc_wrapper.h @@ -0,0 +1,83 @@ +/**************************************************************************** + * Copyright(c) 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_p70_host_mpc_wrapper.c + * + * @brief CFA Phase 7.0 specific MPC Builder Wrapper functions + */ + +#ifndef _CFA_BLD_P70_HOST_MPC_WRAPPER_H_ +#define _CFA_BLD_P70_HOST_MPC_WRAPPER_H_ + +#include "cfa_bld_mpcops.h" +/** + * MPC Cache operation command build apis + */ +int cfa_bld_p70_mpc_build_cache_read(uint8_t *cmd, uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields); + +int cfa_bld_p70_mpc_build_cache_write(uint8_t *cmd, uint32_t *cmd_buff_len, + const uint8_t *data, + struct cfa_mpc_data_obj *fields); + +int cfa_bld_p70_mpc_build_cache_evict(uint8_t *cmd, uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields); + +int cfa_bld_p70_mpc_build_cache_rdclr(uint8_t *cmd, uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields); + +/** + * MPC EM operation command build apis + */ +int cfa_bld_p70_mpc_build_em_search(uint8_t *cmd, uint32_t *cmd_buff_len, + uint8_t *em_entry, + struct cfa_mpc_data_obj *fields); + +int cfa_bld_p70_mpc_build_em_insert(uint8_t *cmd, uint32_t *cmd_buff_len, + const uint8_t *em_entry, + struct cfa_mpc_data_obj *fields); + +int cfa_bld_p70_mpc_build_em_delete(uint8_t *cmd, uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields); + +int cfa_bld_p70_mpc_build_em_chain(uint8_t *cmd, uint32_t *cmd_buff_len, + struct cfa_mpc_data_obj *fields); + +/** + * MPC Cache operation completion parse apis + */ +int cfa_bld_p70_mpc_parse_cache_read(uint8_t *resp, uint32_t resp_buff_len, + uint8_t *rd_data, uint32_t rd_data_len, + struct cfa_mpc_data_obj *fields); + +int cfa_bld_p70_mpc_parse_cache_write(uint8_t *resp, uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields); + +int cfa_bld_p70_mpc_parse_cache_evict(uint8_t *resp, uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields); + +int cfa_bld_p70_mpc_parse_cache_rdclr(uint8_t *resp, uint32_t resp_buff_len, + uint8_t *rd_data, uint32_t rd_data_len, + struct cfa_mpc_data_obj *fields); + +/** + * MPC EM operation completion parse apis + */ +int cfa_bld_p70_mpc_parse_em_search(uint8_t *resp, uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields); + +int cfa_bld_p70_mpc_parse_em_insert(uint8_t *resp, uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields); + +int cfa_bld_p70_mpc_parse_em_delete(uint8_t *resp, uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields); + +int cfa_bld_p70_mpc_parse_em_chain(uint8_t *resp, uint32_t resp_buff_len, + struct cfa_mpc_data_obj *fields); + +#endif /* _CFA_BLD_P70_HOST_MPC_WRAPPER_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_mpcops.c b/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_mpcops.c new file mode 100644 index 0000000000..8efd674650 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_mpcops.c @@ -0,0 +1,56 @@ +/**************************************************************************** + * Copyright(c) 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_p70_mpcops.c + * + * @brief CFA Phase 7.0 specific Builder library MPC ops api + */ + +#define COMP_ID BLD + +#include +#include +#include "cfa_trace.h" +#include "cfa_bld.h" +#include "host/cfa_bld_mpcops.h" +#include "cfa_bld_p70_host_mpc_wrapper.h" +#include "cfa_bld_p70_mpcops.h" + +const struct cfa_bld_mpcops cfa_bld_p70_mpcops = { + /* Build command apis */ + .cfa_bld_mpc_build_cache_read = cfa_bld_p70_mpc_build_cache_read, + .cfa_bld_mpc_build_cache_write = cfa_bld_p70_mpc_build_cache_write, + .cfa_bld_mpc_build_cache_evict = cfa_bld_p70_mpc_build_cache_evict, + .cfa_bld_mpc_build_cache_read_clr = cfa_bld_p70_mpc_build_cache_rdclr, + .cfa_bld_mpc_build_em_search = cfa_bld_p70_mpc_build_em_search, + .cfa_bld_mpc_build_em_insert = cfa_bld_p70_mpc_build_em_insert, + .cfa_bld_mpc_build_em_delete = cfa_bld_p70_mpc_build_em_delete, + .cfa_bld_mpc_build_em_chain = cfa_bld_p70_mpc_build_em_chain, + /* Parse response apis */ + .cfa_bld_mpc_parse_cache_read = cfa_bld_p70_mpc_parse_cache_read, + .cfa_bld_mpc_parse_cache_write = cfa_bld_p70_mpc_parse_cache_write, + .cfa_bld_mpc_parse_cache_evict = cfa_bld_p70_mpc_parse_cache_evict, + .cfa_bld_mpc_parse_cache_read_clr = cfa_bld_p70_mpc_parse_cache_rdclr, + .cfa_bld_mpc_parse_em_search = cfa_bld_p70_mpc_parse_em_search, + .cfa_bld_mpc_parse_em_insert = cfa_bld_p70_mpc_parse_em_insert, + .cfa_bld_mpc_parse_em_delete = cfa_bld_p70_mpc_parse_em_delete, + .cfa_bld_mpc_parse_em_chain = cfa_bld_p70_mpc_parse_em_chain, +}; + +int cfa_bld_p70_mpc_bind(enum cfa_ver hw_ver, struct cfa_bld_mpcinfo *mpcinfo) +{ + if (hw_ver != CFA_P70) + return -EINVAL; + + if (!mpcinfo) + return -EINVAL; + + mpcinfo->mpcops = &cfa_bld_p70_mpcops; + + return 0; +} diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_mpcops.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_mpcops.h new file mode 100644 index 0000000000..67e0ee4ad0 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_bld_p70_mpcops.h @@ -0,0 +1,22 @@ +/**************************************************************************** + * Copyright(c) 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_bld_p70_mpcops.h + * + * @brief CFA Phase 7.0 specific Builder library MPC ops api + */ + +#ifndef _CFA_BLD_P70_MPCOPS_H_ +#define _CFA_BLD_P70_MPCOPS_H_ + +#include "cfa_types.h" +#include "cfa_bld_mpcops.h" + +int cfa_bld_p70_mpc_bind(enum cfa_ver hw_ver, struct cfa_bld_mpcinfo *mpcinfo); + +#endif /* _CFA_BLD_P70_MPCOPS_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_p70_mpc_field_ids.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_p70_mpc_field_ids.h new file mode 100644 index 0000000000..40c6deead8 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_p70_mpc_field_ids.h @@ -0,0 +1,1177 @@ +/**************************************************************************** + * Copyright(c) 2001-2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * Name: cfa_p70_mpc_field_ids.h + * + * Description: MPC CFA command and completion field enumeration definitions + * + * Date: 09/29/22 11:50:38 + * + * Note: This file is scripted generated by ./cfa_header_gen.py. + * DO NOT modify this file manually !!!! + * + ****************************************************************************/ +#ifndef _CFA_P70_MPC_FIELD_IDS_H_ +#define _CFA_P70_MPC_FIELD_IDS_H_ + +/* clang-format off */ + +/** + * Field IDS for READ_CMD: This command reads 1-4 consecutive 32B words + * from the specified address within a table scope. + */ +enum cfa_p70_mpc_read_cmd_fields { + CFA_P70_MPC_READ_CMD_OPAQUE_FLD = 0, + /* This value selects the table type to be acted upon. */ + CFA_P70_MPC_READ_CMD_TABLE_TYPE_FLD = 1, + /* Table scope to access. */ + CFA_P70_MPC_READ_CMD_TABLE_SCOPE_FLD = 2, + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + CFA_P70_MPC_READ_CMD_DATA_SIZE_FLD = 3, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_P70_MPC_READ_CMD_CACHE_OPTION_FLD = 4, + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + CFA_P70_MPC_READ_CMD_TABLE_INDEX_FLD = 5, + /* + * The 64-bit host address to which to write the DMA data returned in + * the completion. The data will be written to the same function as the + * one that owns the SQ this command is read from. DATA_SIZE determines + * the maximum size of the data written. If HOST_ADDRESS[1:0] is not 0, + * CFA aborts processing and reports FMT_ERR status. + */ + CFA_P70_MPC_READ_CMD_HOST_ADDRESS_FLD = 6, + CFA_P70_MPC_READ_CMD_MAX_FLD = 7, +}; + +/** + * Field IDS for WRITE_CMD: This command writes 1-4 consecutive 32B + * words to the specified address within a table scope. + */ +enum cfa_p70_mpc_write_cmd_fields { + CFA_P70_MPC_WRITE_CMD_OPAQUE_FLD = 0, + /* This value selects the table type to be acted upon. */ + CFA_P70_MPC_WRITE_CMD_TABLE_TYPE_FLD = 1, + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + CFA_P70_MPC_WRITE_CMD_WRITE_THROUGH_FLD = 2, + /* Table scope to access. */ + CFA_P70_MPC_WRITE_CMD_TABLE_SCOPE_FLD = 3, + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + CFA_P70_MPC_WRITE_CMD_DATA_SIZE_FLD = 4, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_P70_MPC_WRITE_CMD_CACHE_OPTION_FLD = 5, + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + CFA_P70_MPC_WRITE_CMD_TABLE_INDEX_FLD = 6, + CFA_P70_MPC_WRITE_CMD_MAX_FLD = 7, +}; + +/** + * Field IDS for READ_CLR_CMD: This command performs a read-modify-write + * to the specified 32B address using a 16b mask that specifies up to 16 + * 16b words to clear before writing the data back. It returns the 32B + * data word read from cache (not the value written after the clear + * operation). + */ +enum cfa_p70_mpc_read_clr_cmd_fields { + CFA_P70_MPC_READ_CLR_CMD_OPAQUE_FLD = 0, + /* This value selects the table type to be acted upon. */ + CFA_P70_MPC_READ_CLR_CMD_TABLE_TYPE_FLD = 1, + /* Table scope to access. */ + CFA_P70_MPC_READ_CLR_CMD_TABLE_SCOPE_FLD = 2, + /* + * This field is no longer used. The READ_CLR command always reads (and + * does a mask-clear) on a single cache line. This field was added for + * SR2 A0 to avoid an ADDR_ERR when TABLE_INDEX=0 and TABLE_TYPE=EM (see + * CUMULUS-17872). That issue was fixed in SR2 B0. + */ + CFA_P70_MPC_READ_CLR_CMD_DATA_SIZE_FLD = 3, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_P70_MPC_READ_CLR_CMD_CACHE_OPTION_FLD = 4, + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + CFA_P70_MPC_READ_CLR_CMD_TABLE_INDEX_FLD = 5, + /* + * The 64-bit host address to which to write the DMA data returned in + * the completion. The data will be written to the same function as the + * one that owns the SQ this command is read from. DATA_SIZE determines + * the maximum size of the data written. If HOST_ADDRESS[1:0] is not 0, + * CFA aborts processing and reports FMT_ERR status. + */ + CFA_P70_MPC_READ_CLR_CMD_HOST_ADDRESS_FLD = 6, + /* + * Specifies bits in 32B data word to clear. For x=0..15, when + * clear_mask[x]=1, data[x*16+15:x*16] is set to 0. + */ + CFA_P70_MPC_READ_CLR_CMD_CLEAR_MASK_FLD = 7, + CFA_P70_MPC_READ_CLR_CMD_MAX_FLD = 8, +}; + +/** + * Field IDS for INVALIDATE_CMD: This command forces an explicit evict + * of 1-4 consecutive cache lines such that the next time the structure + * is used it will be re-read from its backing store location. + */ +enum cfa_p70_mpc_invalidate_cmd_fields { + CFA_P70_MPC_INVALIDATE_CMD_OPAQUE_FLD = 0, + /* This value selects the table type to be acted upon. */ + CFA_P70_MPC_INVALIDATE_CMD_TABLE_TYPE_FLD = 1, + /* Table scope to access. */ + CFA_P70_MPC_INVALIDATE_CMD_TABLE_SCOPE_FLD = 2, + /* + * This value identifies the number of cache lines to invalidate. A + * FMT_ERR is reported if the value is not in the range of [1, 4]. + */ + CFA_P70_MPC_INVALIDATE_CMD_DATA_SIZE_FLD = 3, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_P70_MPC_INVALIDATE_CMD_CACHE_OPTION_FLD = 4, + /* + * A 32B index into the table identified by (TABLE_TYPE, TABLE_SCOPE): + */ + CFA_P70_MPC_INVALIDATE_CMD_TABLE_INDEX_FLD = 5, + CFA_P70_MPC_INVALIDATE_CMD_MAX_FLD = 6, +}; + +/** + * Field IDS for EM_SEARCH_CMD: This command supplies an exact match + * entry of 1-4 32B words to search for in the exact match table. CFA + * first computes the hash value of the key in the entry, and determines + * the static bucket address to search from the hash and the + * (EM_BUCKETS, EM_SIZE) for TABLE_SCOPE. It then searches that static + * bucket chain for an entry with a matching key (the LREC in the + * command entry is ignored). If a matching entry is found, CFA reports + * OK status in the completion. Otherwise, assuming no errors abort the + * search before it completes, it reports EM_MISS status. + */ +enum cfa_p70_mpc_em_search_cmd_fields { + CFA_P70_MPC_EM_SEARCH_CMD_OPAQUE_FLD = 0, + /* Table scope to access. */ + CFA_P70_MPC_EM_SEARCH_CMD_TABLE_SCOPE_FLD = 1, + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + CFA_P70_MPC_EM_SEARCH_CMD_DATA_SIZE_FLD = 2, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_P70_MPC_EM_SEARCH_CMD_CACHE_OPTION_FLD = 3, + CFA_P70_MPC_EM_SEARCH_CMD_MAX_FLD = 4, +}; + +/** + * Field IDS for EM_INSERT_CMD: This command supplies an exact match + * entry of 1-4 32B words to insert in the exact match table. CFA first + * computes the hash value of the key in the entry, and determines the + * static bucket address to search from the hash and the (EM_BUCKETS, + * EM_SIZE) for TABLE_SCOPE. It then writes the 1-4 32B words of the + * exact match entry starting at the TABLE_INDEX location in the + * command. When the entry write completes, it searches the static + * bucket chain for an existing entry with a key matching the key in the + * insert entry (the LREC does not need to match). If a matching entry + * is found: * If REPLACE=0, the CFA aborts the insert and returns + * EM_DUPLICATE status. * If REPLACE=1, the CFA overwrites the matching + * entry with the new entry. REPLACED_ENTRY=1 in the completion in this + * case to signal that an entry was replaced. The location of the entry + * is provided in the completion. If no match is found, CFA adds the new + * entry to the lowest unused entry in the tail bucket. If the current + * tail bucket is full, this requires adding a new bucket to the tail. + * Then entry is then inserted at entry number 0. TABLE_INDEX2 provides + * the address of the new tail bucket, if needed. If set to 0, the + * insert is aborted and returns EM_ABORT status instead of adding a new + * bucket to the tail. CHAIN_UPD in the completion indicates whether a + * new bucket was added (1) or not (0). For locked scopes, if the read + * of the static bucket gives a locked scope miss error, indicating that + * the address is not in the cache, the static bucket is assumed empty. + * In this case, TAI creates a new bucket, setting entry 0 to the new + * entry fields and initializing all other fields to 0. It writes this + * new bucket to the static bucket address, which installs it in the + * cache. + */ +enum cfa_p70_mpc_em_insert_cmd_fields { + CFA_P70_MPC_EM_INSERT_CMD_OPAQUE_FLD = 0, + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + CFA_P70_MPC_EM_INSERT_CMD_WRITE_THROUGH_FLD = 1, + /* Table scope to access. */ + CFA_P70_MPC_EM_INSERT_CMD_TABLE_SCOPE_FLD = 2, + /* + * Number of 32B units in access. If value is outside the range [1, 4], + * CFA aborts processing and reports FMT_ERR status. + */ + CFA_P70_MPC_EM_INSERT_CMD_DATA_SIZE_FLD = 3, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_P70_MPC_EM_INSERT_CMD_CACHE_OPTION_FLD = 4, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Starting + * address to write exact match entry being inserted. + */ + CFA_P70_MPC_EM_INSERT_CMD_TABLE_INDEX_FLD = 5, + /* + * Determines setting of OPTION field for all cache write requests for + * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support + * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0. + */ + CFA_P70_MPC_EM_INSERT_CMD_CACHE_OPTION2_FLD = 6, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Only used + * when no duplicate entry is found and the tail bucket in the chain + * searched has no unused entries. In this case, TABLE_INDEX2 provides + * the index to the 32B dynamic bucket to add to the tail of the chain + * (it is the new tail bucket). In this case, the CFA first writes + * TABLE_INDEX2 with a new bucket: * Entry 0 of the bucket sets the + * HASH_MSBS computed from the hash and ENTRY_PTR to TABLE_INDEX. * + * Entries 1-5 of the bucket set HASH_MSBS and ENTRY_PTR to 0. * CHAIN=0 + * and CHAIN_PTR is set to CHAIN_PTR from to original tail bucket to + * maintain the background chaining. CFA then sets CHAIN=1 and + * CHAIN_PTR=TABLE_INDEX2 in the original tail bucket to link the new + * bucket to the chain. CHAIN_UPD=1 in the completion to signal that the + * new bucket at TABLE_INDEX2 was added to the tail of the chain. + */ + CFA_P70_MPC_EM_INSERT_CMD_TABLE_INDEX2_FLD = 7, + /* + * Only used if an entry is found whose key matches the exact match + * entry key in the command: * REPLACE=0: The insert is aborted and + * EM_DUPLICATE status is returned, signaling that the insert failed. + * The index of the matching entry that blocked the insertion is + * returned in the completion. * REPLACE=1: The matching entry is + * replaced with that from the command (ENTRY_PTR in the bucket is + * overwritten with TABLE_INDEX from the command). HASH_MSBS for the + * entry number never changes in this case since it had to match the new + * entry key HASH_MSBS to match. When an entry is replaced, + * REPLACED_ENTRY=1 in the completion and the index of the matching + * entry is returned in the completion so that software can de-allocate + * the entry. + */ + CFA_P70_MPC_EM_INSERT_CMD_REPLACE_FLD = 8, + CFA_P70_MPC_EM_INSERT_CMD_MAX_FLD = 9, +}; + +/** + * Field IDS for EM_DELETE_CMD: This command searches for an exact match + * entry index in the static bucket chain and deletes it if found. + * TABLE_INDEX give the entry index to delete and TABLE_INDEX2 gives the + * static bucket index. If a matching entry is found: * If the matching + * entry is the last valid entry in the tail bucket, its entry fields + * (HASH_MSBS and ENTRY_PTR) are set to 0 to delete the entry. * If the + * matching entry is not the last valid entry in the tail bucket, the + * entry fields from that last entry are moved to the matching entry, + * and the fields of that last entry are set to 0. * If any of the + * previous processing results in the tail bucket not having any valid + * entries, the tail bucket is the static bucket, the scope is a locked + * scope, and CHAIN_PTR=0, hardware evicts the static bucket from the + * cache and the completion signals this case with CHAIN_UPD=1. * If any + * of the previous processing results in the tail bucket not having any + * valid entries, and the tail bucket is not the static bucket, the tail + * bucket is removed from the chain. In this case, the penultimate + * bucket in the chain becomes the tail bucket. It has CHAIN set to 0 to + * unlink the tail bucket, and CHAIN_PTR set to that from the original + * tail bucket to preserve background chaining. The completion signals + * this case with CHAIN_UPD=1 and returns the index to the bucket + * removed so that software can de-allocate it. CFA returns OK status if + * the entry was successfully deleted. Otherwise, it returns EM_MISS + * status assuming there were no errors that caused processing to be + * aborted. + */ +enum cfa_p70_mpc_em_delete_cmd_fields { + CFA_P70_MPC_EM_DELETE_CMD_OPAQUE_FLD = 0, + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + CFA_P70_MPC_EM_DELETE_CMD_WRITE_THROUGH_FLD = 1, + /* Table scope to access. */ + CFA_P70_MPC_EM_DELETE_CMD_TABLE_SCOPE_FLD = 2, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_P70_MPC_EM_DELETE_CMD_CACHE_OPTION_FLD = 3, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Entry index + * to delete. + */ + CFA_P70_MPC_EM_DELETE_CMD_TABLE_INDEX_FLD = 4, + /* + * Determines setting of OPTION field for all cache write requests for + * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support + * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0. + */ + CFA_P70_MPC_EM_DELETE_CMD_CACHE_OPTION2_FLD = 5, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Static + * bucket address for bucket chain. + */ + CFA_P70_MPC_EM_DELETE_CMD_TABLE_INDEX2_FLD = 6, + CFA_P70_MPC_EM_DELETE_CMD_MAX_FLD = 7, +}; + +/** + * Field IDS for EM_CHAIN_CMD: This command updates CHAIN_PTR in the + * tail bucket of a static bucket chain, supplying both the static + * bucket and the new CHAIN_PTR value. TABLE_INDEX is the new CHAIN_PTR + * value and TABLE_INDEX2[23:0] is the static bucket. This command + * provides software a means to update background chaining coherently + * with other bucket updates. The value of CHAIN is unaffected (stays at + * 0). For locked scopes, if the static bucket is the tail bucket, it is + * empty (all of its ENTRY_PTR values are 0), and TABLE_INDEX=0 (the + * CHAIN_PTR is being set to 0), instead of updating the static bucket + * it is evicted from the cache. In this case, CHAIN_UPD=1 in the + * completion. + */ +enum cfa_p70_mpc_em_chain_cmd_fields { + CFA_P70_MPC_EM_CHAIN_CMD_OPAQUE_FLD = 0, + /* + * Sets the OPTION field on the cache interface to use write-through for + * EM entry writes while processing EM_INSERT commands. For all other + * cases (inluding EM_INSERT bucket writes), the OPTION field is set by + * the CACHE_OPTION and CACHE_OPTION2 fields. + */ + CFA_P70_MPC_EM_CHAIN_CMD_WRITE_THROUGH_FLD = 1, + /* Table scope to access. */ + CFA_P70_MPC_EM_CHAIN_CMD_TABLE_SCOPE_FLD = 2, + /* + * Determines setting of OPTION field for all cache requests while + * processing any command other than EM_INSERT, EM_DELETE, or EM_CHAIN. + * For these latter commands, CACHE_OPTION sets the OPTION field for all + * read requests, and CACHE_OPTION2 sets it for all write requests. CFA + * does not support posted write requests. Therefore, for WRITE + * commands, CACHE_OPTION[1] must be set to 0. And for EM commands that + * send write requests (all but EM_SEARCH), CACHE_OPTION2[1] must be set + * to 0. + */ + CFA_P70_MPC_EM_CHAIN_CMD_CACHE_OPTION_FLD = 3, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. New + * CHAIN_PTR to write to tail bucket. + */ + CFA_P70_MPC_EM_CHAIN_CMD_TABLE_INDEX_FLD = 4, + /* + * Determines setting of OPTION field for all cache write requests for + * EM_INSERT, EM_DELETE, and EM_CHAIN commands. CFA does not support + * posted write requests. Therefore, CACHE_OPTION2[1] must be set to 0. + */ + CFA_P70_MPC_EM_CHAIN_CMD_CACHE_OPTION2_FLD = 5, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. Static + * bucket address for bucket chain. + */ + CFA_P70_MPC_EM_CHAIN_CMD_TABLE_INDEX2_FLD = 6, + CFA_P70_MPC_EM_CHAIN_CMD_MAX_FLD = 7, +}; + +/** + * Field IDS for READ_CMP: When no errors, teturns 1-4 consecutive 32B + * words from the TABLE_INDEX within the TABLE_SCOPE specified in the + * command, writing them to HOST_ADDRESS from the command. + */ +enum cfa_p70_mpc_read_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_P70_MPC_READ_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_P70_MPC_READ_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_P70_MPC_READ_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_P70_MPC_READ_CMP_OPCODE_FLD = 3, + /* + * The length of the DMA that accompanies the completion in units of + * DWORDs (32b). Valid values are [0, 128]. A value of zero indicates + * that there is no DMA that accompanies the completion. + */ + CFA_P70_MPC_READ_CMP_DMA_LENGTH_FLD = 4, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_P70_MPC_READ_CMP_OPAQUE_FLD = 5, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_P70_MPC_READ_CMP_V_FLD = 6, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_P70_MPC_READ_CMP_HASH_MSB_FLD = 7, + /* TABLE_TYPE from the command. */ + CFA_P70_MPC_READ_CMP_TABLE_TYPE_FLD = 8, + /* TABLE_SCOPE from the command. */ + CFA_P70_MPC_READ_CMP_TABLE_SCOPE_FLD = 9, + /* TABLE_INDEX from the command. */ + CFA_P70_MPC_READ_CMP_TABLE_INDEX_FLD = 10, + CFA_P70_MPC_READ_CMP_MAX_FLD = 11, +}; + +/** + * Field IDS for WRITE_CMP: Returns status of the write of 1-4 + * consecutive 32B words starting at TABLE_INDEX in the table specified + * by (TABLE_TYPE, TABLE_SCOPE). + */ +enum cfa_p70_mpc_write_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_P70_MPC_WRITE_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_P70_MPC_WRITE_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_P70_MPC_WRITE_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_P70_MPC_WRITE_CMP_OPCODE_FLD = 3, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_P70_MPC_WRITE_CMP_OPAQUE_FLD = 4, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_P70_MPC_WRITE_CMP_V_FLD = 5, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_P70_MPC_WRITE_CMP_HASH_MSB_FLD = 6, + /* TABLE_TYPE from the command. */ + CFA_P70_MPC_WRITE_CMP_TABLE_TYPE_FLD = 7, + /* TABLE_SCOPE from the command. */ + CFA_P70_MPC_WRITE_CMP_TABLE_SCOPE_FLD = 8, + /* TABLE_INDEX from the command. */ + CFA_P70_MPC_WRITE_CMP_TABLE_INDEX_FLD = 9, + CFA_P70_MPC_WRITE_CMP_MAX_FLD = 10, +}; + +/** + * Field IDS for READ_CLR_CMP: When no errors, returns 1 32B word from + * TABLE_INDEX in the table specified by (TABLE_TYPE, TABLE_SCOPE). The + * data returned is the value prior to the clear. + */ +enum cfa_p70_mpc_read_clr_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_P70_MPC_READ_CLR_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_P70_MPC_READ_CLR_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_P70_MPC_READ_CLR_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_P70_MPC_READ_CLR_CMP_OPCODE_FLD = 3, + /* + * The length of the DMA that accompanies the completion in units of + * DWORDs (32b). Valid values are [0, 128]. A value of zero indicates + * that there is no DMA that accompanies the completion. + */ + CFA_P70_MPC_READ_CLR_CMP_DMA_LENGTH_FLD = 4, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_P70_MPC_READ_CLR_CMP_OPAQUE_FLD = 5, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_P70_MPC_READ_CLR_CMP_V_FLD = 6, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_P70_MPC_READ_CLR_CMP_HASH_MSB_FLD = 7, + /* TABLE_TYPE from the command. */ + CFA_P70_MPC_READ_CLR_CMP_TABLE_TYPE_FLD = 8, + /* TABLE_SCOPE from the command. */ + CFA_P70_MPC_READ_CLR_CMP_TABLE_SCOPE_FLD = 9, + /* TABLE_INDEX from the command. */ + CFA_P70_MPC_READ_CLR_CMP_TABLE_INDEX_FLD = 10, + CFA_P70_MPC_READ_CLR_CMP_MAX_FLD = 11, +}; + +/** + * Field IDS for INVALIDATE_CMP: Returns status for INVALIDATE commands. + */ +enum cfa_p70_mpc_invalidate_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_P70_MPC_INVALIDATE_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_P70_MPC_INVALIDATE_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_P70_MPC_INVALIDATE_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_P70_MPC_INVALIDATE_CMP_OPCODE_FLD = 3, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_P70_MPC_INVALIDATE_CMP_OPAQUE_FLD = 4, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_P70_MPC_INVALIDATE_CMP_V_FLD = 5, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_P70_MPC_INVALIDATE_CMP_HASH_MSB_FLD = 6, + /* TABLE_TYPE from the command. */ + CFA_P70_MPC_INVALIDATE_CMP_TABLE_TYPE_FLD = 7, + /* TABLE_SCOPE from the command. */ + CFA_P70_MPC_INVALIDATE_CMP_TABLE_SCOPE_FLD = 8, + /* TABLE_INDEX from the command. */ + CFA_P70_MPC_INVALIDATE_CMP_TABLE_INDEX_FLD = 9, + CFA_P70_MPC_INVALIDATE_CMP_MAX_FLD = 10, +}; + +/** + * Field IDS for EM_SEARCH_CMP: For OK status, returns the index of the + * matching entry found for the EM key supplied in the command. Returns + * EM_MISS status if no match was found. + */ +enum cfa_p70_mpc_em_search_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_P70_MPC_EM_SEARCH_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_P70_MPC_EM_SEARCH_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_P70_MPC_EM_SEARCH_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_P70_MPC_EM_SEARCH_CMP_OPCODE_FLD = 3, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_P70_MPC_EM_SEARCH_CMP_OPAQUE_FLD = 4, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_P70_MPC_EM_SEARCH_CMP_V1_FLD = 5, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_P70_MPC_EM_SEARCH_CMP_HASH_MSB_FLD = 6, + /* TABLE_SCOPE from the command. */ + CFA_P70_MPC_EM_SEARCH_CMP_TABLE_SCOPE_FLD = 7, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK + * status, gives ENTRY_PTR[25:0] of the matching entry found. Otherwise, + * set to 0. + */ + CFA_P70_MPC_EM_SEARCH_CMP_TABLE_INDEX_FLD = 8, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. If the hash + * is computed (no errors during initial processing of the command), + * TABLE_INDEX2[23:0] is the static bucket address determined from the + * hash of the exact match entry key in the command and the (EM_SIZE, + * EM_BUCKETS) configuration for TABLE_SCOPE of the command. Bits 25:24 + * in this case are set to 0. For any other status, it is always 0. + */ + CFA_P70_MPC_EM_SEARCH_CMP_TABLE_INDEX2_FLD = 9, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_P70_MPC_EM_SEARCH_CMP_V2_FLD = 10, + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + CFA_P70_MPC_EM_SEARCH_CMP_BKT_NUM_FLD = 11, + /* See BKT_NUM description. */ + CFA_P70_MPC_EM_SEARCH_CMP_NUM_ENTRIES_FLD = 12, + CFA_P70_MPC_EM_SEARCH_CMP_MAX_FLD = 13, +}; + +/** + * Field IDS for EM_INSERT_CMP: OK status indicates that the exact match + * entry from the command was successfully inserted. EM_DUPLICATE status + * indicates that the insert was aborted because an entry with the same + * exact match key was found and REPLACE=0 in the command. EM_ABORT + * status indicates that no duplicate was found, the tail bucket in the + * chain was full, and TABLE_INDEX2=0. No changes are made to the + * database in this case. TABLE_INDEX is the starting address at which + * to insert the exact match entry (from the command). TABLE_INDEX2 is + * the address at which to insert a new bucket at the tail of the static + * bucket chain if needed (from the command). CHAIN_UPD=1 if a new + * bucket was added at this address. TABLE_INDEX3 is the static bucket + * address for the chain, determined from hashing the exact match entry. + * Software needs this address and TABLE_INDEX in order to delete the + * entry using an EM_DELETE command. TABLE_INDEX4 is the index of an + * entry found that had a matching exact match key to the command entry + * key. If no matching entry was found, it is set to 0. There are two + * cases when there is a matching entry, depending on REPLACE from the + * command: * REPLACE=0: EM_DUPLICATE status is reported and the insert + * is aborted. Software can use the static bucket address + * (TABLE_INDEX3[23:0]) and the matching entry (TABLE_INDEX4) in an + * EM_DELETE command if it wishes to explicity delete the matching + * entry. * REPLACE=1: REPLACED_ENTRY=1 to signal that the entry at + * TABLE_INDEX4 was replaced by the insert entry. REPLACED_ENTRY will + * only be 1 if reporting OK status in this case. Software can de- + * allocate the entry at TABLE_INDEX4. + */ +enum cfa_p70_mpc_em_insert_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_P70_MPC_EM_INSERT_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_P70_MPC_EM_INSERT_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_P70_MPC_EM_INSERT_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_P70_MPC_EM_INSERT_CMP_OPCODE_FLD = 3, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_P70_MPC_EM_INSERT_CMP_OPAQUE_FLD = 4, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_P70_MPC_EM_INSERT_CMP_V1_FLD = 5, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_P70_MPC_EM_INSERT_CMP_HASH_MSB_FLD = 6, + /* TABLE_SCOPE from the command. */ + CFA_P70_MPC_EM_INSERT_CMP_TABLE_SCOPE_FLD = 7, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX + * from the command, which is the starting address at which to insert + * the exact match entry. + */ + CFA_P70_MPC_EM_INSERT_CMP_TABLE_INDEX_FLD = 8, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2 + * from the command, which is the index for the new tail bucket to add + * if needed (CHAIN_UPD=1 if it was used). + */ + CFA_P70_MPC_EM_INSERT_CMP_TABLE_INDEX2_FLD = 9, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. If the hash + * is computed (no errors during initial processing of the command), + * TABLE_INDEX2[23:0] is the static bucket address determined from the + * hash of the exact match entry key in the command and the (EM_SIZE, + * EM_BUCKETS) configuration for TABLE_SCOPE of the command. Bits 25:24 + * in this case are set to 0. For any other status, it is always 0. + */ + CFA_P70_MPC_EM_INSERT_CMP_TABLE_INDEX3_FLD = 10, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_P70_MPC_EM_INSERT_CMP_V2_FLD = 11, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. ENTRY_PTR of + * matching entry found. Set to 0 if no matching entry found. If + * REPLACED_ENTRY=1, that indicates a matching entry was found and + * REPLACE=1 in the command. In this case, the matching entry was + * replaced by the new entry in the command and this index can therefore + * by de-allocated. + */ + CFA_P70_MPC_EM_INSERT_CMP_TABLE_INDEX4_FLD = 12, + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + CFA_P70_MPC_EM_INSERT_CMP_BKT_NUM_FLD = 13, + /* See BKT_NUM description. */ + CFA_P70_MPC_EM_INSERT_CMP_NUM_ENTRIES_FLD = 14, + /* + * Specifies if the chain was updated while processing the command: Set + * to 1 when a new bucket is added to the tail of the static bucket + * chain at TABLE_INDEX2. This occurs if and only if the insert requires + * adding a new entry and the tail bucket is full. If set to 0, + * TABLE_INDEX2 was not used and is therefore still free. + */ + CFA_P70_MPC_EM_INSERT_CMP_CHAIN_UPD_FLD = 15, + /* + * Set to 1 if a matching entry was found and REPLACE=1 in command. In + * the case, the entry starting at TABLE_INDEX4 was replaced and can + * therefore be de-allocated. Otherwise, this flag is set to 0. + */ + CFA_P70_MPC_EM_INSERT_CMP_REPLACED_ENTRY_FLD = 16, + CFA_P70_MPC_EM_INSERT_CMP_MAX_FLD = 17, +}; + +/** + * Field IDS for EM_DELETE_CMP: OK status indicates that an ENTRY_PTR + * matching TABLE_INDEX was found in the static bucket chain specified + * and was therefore deleted. EM_MISS status indicates that no match was + * found. TABLE_INDEX is from the command. It is the index of the entry + * to delete. TABLE_INDEX2 is from the command. It is the static bucket + * address. TABLE_INDEX3 is the index of the tail bucket of the static + * bucket chain prior to processing the command. TABLE_INDEX4 is the + * index of the tail bucket of the static bucket chain after processing + * the command. If CHAIN_UPD=1 and TABLE_INDEX4==TABLE_INDEX2, the + * static bucket was the tail bucket, it became empty after the delete, + * the scope is a locked scope, and CHAIN_PTR was 0. In this case, the + * static bucket has been evicted from the cache. Otherwise, if + * CHAIN_UPD=1, the original tail bucket given by TABLE_INDEX3 was + * removed from the chain because it went empty. It can therefore be de- + * allocated. + */ +enum cfa_p70_mpc_em_delete_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_P70_MPC_EM_DELETE_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_P70_MPC_EM_DELETE_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_P70_MPC_EM_DELETE_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_P70_MPC_EM_DELETE_CMP_OPCODE_FLD = 3, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_P70_MPC_EM_DELETE_CMP_OPAQUE_FLD = 4, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_P70_MPC_EM_DELETE_CMP_V1_FLD = 5, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_P70_MPC_EM_DELETE_CMP_HASH_MSB_FLD = 6, + /* TABLE_SCOPE from the command. */ + CFA_P70_MPC_EM_DELETE_CMP_TABLE_SCOPE_FLD = 7, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX + * from the command, which is the index of the entry to delete. + */ + CFA_P70_MPC_EM_DELETE_CMP_TABLE_INDEX_FLD = 8, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2 + * from the command. + */ + CFA_P70_MPC_EM_DELETE_CMP_TABLE_INDEX2_FLD = 9, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK or + * EM_MISS status, the index of the tail bucket of the chain prior to + * processing the command. If CHAIN_UPD=1, the bucket was removed and + * this index can be de-allocated. For other status values, it is set to + * 0. + */ + CFA_P70_MPC_EM_DELETE_CMP_TABLE_INDEX3_FLD = 10, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_P70_MPC_EM_DELETE_CMP_V2_FLD = 11, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK or + * EM_MISS status, the index of the tail bucket of the chain prior to + * after the command. If CHAIN_UPD=0 (always for EM_MISS status), it is + * always equal to TABLE_INDEX3 as the chain was not updated. For other + * status values, it is set to 0. + */ + CFA_P70_MPC_EM_DELETE_CMP_TABLE_INDEX4_FLD = 12, + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + CFA_P70_MPC_EM_DELETE_CMP_BKT_NUM_FLD = 13, + /* See BKT_NUM description. */ + CFA_P70_MPC_EM_DELETE_CMP_NUM_ENTRIES_FLD = 14, + /* + * Specifies if the chain was updated while processing the command: Set + * to 1 when a bucket is removed from the static bucket chain. This + * occurs if after the delete, the tail bucket is a dynamic bucket and + * no longer has any valid entries. In this case, software should de- + * allocate the dynamic bucket at TABLE_INDEX3. It is also set to 1 when + * the static bucket is evicted, which only occurs for locked scopes. + * See the EM_DELETE command description for details. + */ + CFA_P70_MPC_EM_DELETE_CMP_CHAIN_UPD_FLD = 15, + CFA_P70_MPC_EM_DELETE_CMP_MAX_FLD = 16, +}; + +/** + * Field IDS for EM_CHAIN_CMP: OK status indicates that the CHAIN_PTR of + * the tail bucket was successfully updated. TABLE_INDEX is from the + * command. It is the value of the new CHAIN_PTR. TABLE_INDEX2 is from + * the command. TABLE_INDEX3 is the index of the tail bucket of the + * static bucket chain. + */ +enum cfa_p70_mpc_em_chain_cmp_fields { + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records **(EXCEPT + * no_op!!!!)** . + */ + CFA_P70_MPC_EM_CHAIN_CMP_TYPE_FLD = 0, + /* The command processing status. */ + CFA_P70_MPC_EM_CHAIN_CMP_STATUS_FLD = 1, + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + CFA_P70_MPC_EM_CHAIN_CMP_MP_CLIENT_FLD = 2, + /* OPCODE from the command. */ + CFA_P70_MPC_EM_CHAIN_CMP_OPCODE_FLD = 3, + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + CFA_P70_MPC_EM_CHAIN_CMP_OPAQUE_FLD = 4, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_P70_MPC_EM_CHAIN_CMP_V1_FLD = 5, + /* + * For EM_SEARCH and EM_INSERT commands without errors that abort the + * command processing prior to the hash computation, set to HASH[35:24] + * of the hash computed from the exact match entry key in the command. + * For all other cases, set to 0 except for the following error + * conditions, which carry debug information in this field as shown by + * error status below: * FMT_ERR: - Set to {7'd0, HOST_ADDRESS[1:0], + * DATA_SIZE[2:0]}. - If HOST_ADDRESS or DATA_SIZE field not present + * they are set to 0. * SCOPE_ERR: - Set to {1'b0, SVIF[10:0]}. * + * ADDR_ERR: - Only possible when TABLE_TYPE=EM or for EM* commands - + * Set to {1'b0, TABLE_INDEX[2:0], 5'd0, DATA_SIZE[2:0]} - + * TABLE_INDEX[2]=1 if TABLE_INDEX3 had an error - TABLE_INDEX[1]=1 if + * TABLE_INDEX2 had an error - TABLE_INDEX[0]=1 if TABLE_INDEX had an + * error - TABLE_INDEX[n]=0 if the completion does not have the + * corresponding TABLE_INDEX field above. * CACHE_ERR: - Set to {9'd0, + * DATA_SIZE[2:0]} + */ + CFA_P70_MPC_EM_CHAIN_CMP_HASH_MSB_FLD = 6, + /* TABLE_SCOPE from the command. */ + CFA_P70_MPC_EM_CHAIN_CMP_TABLE_SCOPE_FLD = 7, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX + * from the command, which is the new CHAIN_PTR for the tail bucket of + * the static bucket chain. + */ + CFA_P70_MPC_EM_CHAIN_CMP_TABLE_INDEX_FLD = 8, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. TABLE_INDEX2 + * from the command. + */ + CFA_P70_MPC_EM_CHAIN_CMP_TABLE_INDEX2_FLD = 9, + /* + * A 32B index into the EM table identified by TABLE_SCOPE. For OK + * status, the index of the tail bucket of the chain. Otherwise, set to + * 0. + */ + CFA_P70_MPC_EM_CHAIN_CMP_TABLE_INDEX3_FLD = 10, + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + CFA_P70_MPC_EM_CHAIN_CMP_V2_FLD = 11, + /* + * BKT_NUM is the bucket number in chain of the tail bucket after + * finishing processing the command, except when the command stops + * processing before the tail bucket. NUM_ENTRIES is the number of valid + * entries in the BKT_NUM bucket. The following describes the cases + * where BKT_NUM and NUM_ENTRIES are not for the tail bucket after + * finishing processing of the command: * For UNSPRT_ERR, FMT_ERR, + * SCOPE_ERR, or ADDR_ERR completion status, BKT_NUM will be set to 0. * + * For CACHE_ERR completion status, BKT_NUM will be set to the bucket + * number that was last read without error. If ERR=1 in the response to + * the static bucket read, BKT_NUM and NUM_ENTRIES are set to 0. The + * static bucket is number 0, BKT_NUM increments for each new bucket in + * the chain, and saturates at 255. Therefore, if the value is 255, + * BKT_NUM may or may not be accurate. In this case, though, NUM_ENTRIES + * will still be the correct value as described above for the bucket. + */ + CFA_P70_MPC_EM_CHAIN_CMP_BKT_NUM_FLD = 12, + /* See BKT_NUM description. */ + CFA_P70_MPC_EM_CHAIN_CMP_NUM_ENTRIES_FLD = 13, + /* + * Set to 1 when the scope is a locked scope, the tail bucket is the + * static bucket, the bucket is empty (all of its ENTRY_PTR values are + * 0), and TABLE_INDEX=0 in the command. In this case, the static bucket + * is evicted. For all other cases, it is set to 0. + */ + CFA_P70_MPC_EM_CHAIN_CMP_CHAIN_UPD_FLD = 14, + CFA_P70_MPC_EM_CHAIN_CMP_MAX_FLD = 15, +}; + +/* clang-format on */ + +#endif /* _CFA_P70_MPC_FIELD_IDS_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_p70_mpc_field_mapping.h b/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_p70_mpc_field_mapping.h new file mode 100644 index 0000000000..2bb44d31dc --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/bld/p70/host/cfa_p70_mpc_field_mapping.h @@ -0,0 +1,775 @@ +/**************************************************************************** + * Copyright(c) 2001-2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * Name: cfa_p70_mpc_field_mapping.h + * + * Description: MPC CFA command and completion field mapping (Global to Device) + * + * Date: 09/29/22 11:50:38 + * + * Note: This file is scripted generated by ./cfa_header_gen.py. + * DO NOT modify this file manually !!!! + * + ****************************************************************************/ +#ifndef _CFA_P70_MPC_FIELD_MAPPING_H_ +#define _CFA_P70_MPC_FIELD_MAPPING_H_ + +/* clang-format off */ +/** Device specific Field ID mapping structure */ +struct field_mapping { + bool valid; + uint16_t mapping; +}; + +/** + * Global to device field id mapping for READ_CMD + */ +struct field_mapping cfa_p70_mpc_read_cmd_gbl_to_dev + [CFA_BLD_MPC_READ_CMD_MAX_FLD] = { + [CFA_BLD_MPC_READ_CMD_OPAQUE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CMD_OPAQUE_FLD, + }, + [CFA_BLD_MPC_READ_CMD_TABLE_TYPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CMD_TABLE_TYPE_FLD, + }, + [CFA_BLD_MPC_READ_CMD_TABLE_SCOPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CMD_TABLE_SCOPE_FLD, + }, + [CFA_BLD_MPC_READ_CMD_DATA_SIZE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CMD_DATA_SIZE_FLD, + }, + [CFA_BLD_MPC_READ_CMD_CACHE_OPTION_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CMD_CACHE_OPTION_FLD, + }, + [CFA_BLD_MPC_READ_CMD_TABLE_INDEX_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CMD_TABLE_INDEX_FLD, + }, + [CFA_BLD_MPC_READ_CMD_HOST_ADDRESS_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CMD_HOST_ADDRESS_FLD, + }, +}; + +/** + * Global to device field id mapping for WRITE_CMD + */ +struct field_mapping cfa_p70_mpc_write_cmd_gbl_to_dev + [CFA_BLD_MPC_WRITE_CMD_MAX_FLD] = { + [CFA_BLD_MPC_WRITE_CMD_OPAQUE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_WRITE_CMD_OPAQUE_FLD, + }, + [CFA_BLD_MPC_WRITE_CMD_TABLE_TYPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_WRITE_CMD_TABLE_TYPE_FLD, + }, + [CFA_BLD_MPC_WRITE_CMD_WRITE_THROUGH_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_WRITE_CMD_WRITE_THROUGH_FLD, + }, + [CFA_BLD_MPC_WRITE_CMD_TABLE_SCOPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_WRITE_CMD_TABLE_SCOPE_FLD, + }, + [CFA_BLD_MPC_WRITE_CMD_DATA_SIZE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_WRITE_CMD_DATA_SIZE_FLD, + }, + [CFA_BLD_MPC_WRITE_CMD_CACHE_OPTION_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_WRITE_CMD_CACHE_OPTION_FLD, + }, + [CFA_BLD_MPC_WRITE_CMD_TABLE_INDEX_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_WRITE_CMD_TABLE_INDEX_FLD, + }, +}; + +/** + * Global to device field id mapping for READ_CLR_CMD + */ +struct field_mapping cfa_p70_mpc_read_clr_cmd_gbl_to_dev + [CFA_BLD_MPC_READ_CLR_CMD_MAX_FLD] = { + [CFA_BLD_MPC_READ_CLR_CMD_OPAQUE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMD_OPAQUE_FLD, + }, + [CFA_BLD_MPC_READ_CLR_CMD_TABLE_TYPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMD_TABLE_TYPE_FLD, + }, + [CFA_BLD_MPC_READ_CLR_CMD_TABLE_SCOPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMD_TABLE_SCOPE_FLD, + }, + [CFA_BLD_MPC_READ_CLR_CMD_DATA_SIZE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMD_DATA_SIZE_FLD, + }, + [CFA_BLD_MPC_READ_CLR_CMD_CACHE_OPTION_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMD_CACHE_OPTION_FLD, + }, + [CFA_BLD_MPC_READ_CLR_CMD_TABLE_INDEX_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMD_TABLE_INDEX_FLD, + }, + [CFA_BLD_MPC_READ_CLR_CMD_HOST_ADDRESS_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMD_HOST_ADDRESS_FLD, + }, + [CFA_BLD_MPC_READ_CLR_CMD_CLEAR_MASK_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMD_CLEAR_MASK_FLD, + }, +}; + +/** + * Global to device field id mapping for INVALIDATE_CMD + */ +struct field_mapping cfa_p70_mpc_invalidate_cmd_gbl_to_dev + [CFA_BLD_MPC_INVALIDATE_CMD_MAX_FLD] = { + [CFA_BLD_MPC_INVALIDATE_CMD_OPAQUE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_INVALIDATE_CMD_OPAQUE_FLD, + }, + [CFA_BLD_MPC_INVALIDATE_CMD_TABLE_TYPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_INVALIDATE_CMD_TABLE_TYPE_FLD, + }, + [CFA_BLD_MPC_INVALIDATE_CMD_TABLE_SCOPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_INVALIDATE_CMD_TABLE_SCOPE_FLD, + }, + [CFA_BLD_MPC_INVALIDATE_CMD_DATA_SIZE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_INVALIDATE_CMD_DATA_SIZE_FLD, + }, + [CFA_BLD_MPC_INVALIDATE_CMD_CACHE_OPTION_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_INVALIDATE_CMD_CACHE_OPTION_FLD, + }, + [CFA_BLD_MPC_INVALIDATE_CMD_TABLE_INDEX_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_INVALIDATE_CMD_TABLE_INDEX_FLD, + }, +}; + +/** + * Global to device field id mapping for EM_SEARCH_CMD + */ +struct field_mapping cfa_p70_mpc_em_search_cmd_gbl_to_dev + [CFA_BLD_MPC_EM_SEARCH_CMD_MAX_FLD] = { + [CFA_BLD_MPC_EM_SEARCH_CMD_OPAQUE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_SEARCH_CMD_OPAQUE_FLD, + }, + [CFA_BLD_MPC_EM_SEARCH_CMD_TABLE_SCOPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_SEARCH_CMD_TABLE_SCOPE_FLD, + }, + [CFA_BLD_MPC_EM_SEARCH_CMD_DATA_SIZE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_SEARCH_CMD_DATA_SIZE_FLD, + }, + [CFA_BLD_MPC_EM_SEARCH_CMD_CACHE_OPTION_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_SEARCH_CMD_CACHE_OPTION_FLD, + }, +}; + +/** + * Global to device field id mapping for EM_INSERT_CMD + */ +struct field_mapping cfa_p70_mpc_em_insert_cmd_gbl_to_dev + [CFA_BLD_MPC_EM_INSERT_CMD_MAX_FLD] = { + [CFA_BLD_MPC_EM_INSERT_CMD_OPAQUE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMD_OPAQUE_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMD_WRITE_THROUGH_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMD_WRITE_THROUGH_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMD_TABLE_SCOPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMD_TABLE_SCOPE_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMD_DATA_SIZE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMD_DATA_SIZE_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMD_CACHE_OPTION_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMD_CACHE_OPTION_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMD_TABLE_INDEX_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMD_TABLE_INDEX_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMD_CACHE_OPTION2_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMD_CACHE_OPTION2_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMD_TABLE_INDEX2_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMD_TABLE_INDEX2_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMD_REPLACE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMD_REPLACE_FLD, + }, +}; + +/** + * Global to device field id mapping for EM_DELETE_CMD + */ +struct field_mapping cfa_p70_mpc_em_delete_cmd_gbl_to_dev + [CFA_BLD_MPC_EM_DELETE_CMD_MAX_FLD] = { + [CFA_BLD_MPC_EM_DELETE_CMD_OPAQUE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMD_OPAQUE_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMD_WRITE_THROUGH_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMD_WRITE_THROUGH_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMD_TABLE_SCOPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMD_TABLE_SCOPE_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMD_CACHE_OPTION_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMD_CACHE_OPTION_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMD_TABLE_INDEX_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMD_TABLE_INDEX_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMD_CACHE_OPTION2_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMD_CACHE_OPTION2_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMD_TABLE_INDEX2_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMD_TABLE_INDEX2_FLD, + }, +}; + +/** + * Global to device field id mapping for EM_CHAIN_CMD + */ +struct field_mapping cfa_p70_mpc_em_chain_cmd_gbl_to_dev + [CFA_BLD_MPC_EM_CHAIN_CMD_MAX_FLD] = { + [CFA_BLD_MPC_EM_CHAIN_CMD_OPAQUE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMD_OPAQUE_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMD_WRITE_THROUGH_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMD_WRITE_THROUGH_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMD_TABLE_SCOPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMD_TABLE_SCOPE_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMD_CACHE_OPTION_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMD_CACHE_OPTION_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMD_TABLE_INDEX_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMD_TABLE_INDEX_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMD_CACHE_OPTION2_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMD_CACHE_OPTION2_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMD_TABLE_INDEX2_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMD_TABLE_INDEX2_FLD, + }, +}; + +/** + * Global to device field id mapping for READ_CMP + */ +struct field_mapping cfa_p70_mpc_read_cmp_gbl_to_dev + [CFA_BLD_MPC_READ_CMP_MAX_FLD] = { + [CFA_BLD_MPC_READ_CMP_TYPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CMP_TYPE_FLD, + }, + [CFA_BLD_MPC_READ_CMP_STATUS_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CMP_STATUS_FLD, + }, + [CFA_BLD_MPC_READ_CMP_MP_CLIENT_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CMP_MP_CLIENT_FLD, + }, + [CFA_BLD_MPC_READ_CMP_OPCODE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CMP_OPCODE_FLD, + }, + [CFA_BLD_MPC_READ_CMP_DMA_LENGTH_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CMP_DMA_LENGTH_FLD, + }, + [CFA_BLD_MPC_READ_CMP_OPAQUE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CMP_OPAQUE_FLD, + }, + [CFA_BLD_MPC_READ_CMP_V_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CMP_V_FLD, + }, + [CFA_BLD_MPC_READ_CMP_HASH_MSB_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CMP_HASH_MSB_FLD, + }, + [CFA_BLD_MPC_READ_CMP_TABLE_TYPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CMP_TABLE_TYPE_FLD, + }, + [CFA_BLD_MPC_READ_CMP_TABLE_SCOPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CMP_TABLE_SCOPE_FLD, + }, + [CFA_BLD_MPC_READ_CMP_TABLE_INDEX_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CMP_TABLE_INDEX_FLD, + }, +}; + +/** + * Global to device field id mapping for WRITE_CMP + */ +struct field_mapping cfa_p70_mpc_write_cmp_gbl_to_dev + [CFA_BLD_MPC_WRITE_CMP_MAX_FLD] = { + [CFA_BLD_MPC_WRITE_CMP_TYPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_WRITE_CMP_TYPE_FLD, + }, + [CFA_BLD_MPC_WRITE_CMP_STATUS_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_WRITE_CMP_STATUS_FLD, + }, + [CFA_BLD_MPC_WRITE_CMP_MP_CLIENT_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_WRITE_CMP_MP_CLIENT_FLD, + }, + [CFA_BLD_MPC_WRITE_CMP_OPCODE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_WRITE_CMP_OPCODE_FLD, + }, + [CFA_BLD_MPC_WRITE_CMP_OPAQUE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_WRITE_CMP_OPAQUE_FLD, + }, + [CFA_BLD_MPC_WRITE_CMP_V_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_WRITE_CMP_V_FLD, + }, + [CFA_BLD_MPC_WRITE_CMP_HASH_MSB_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_WRITE_CMP_HASH_MSB_FLD, + }, + [CFA_BLD_MPC_WRITE_CMP_TABLE_TYPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_WRITE_CMP_TABLE_TYPE_FLD, + }, + [CFA_BLD_MPC_WRITE_CMP_TABLE_SCOPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_WRITE_CMP_TABLE_SCOPE_FLD, + }, + [CFA_BLD_MPC_WRITE_CMP_TABLE_INDEX_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_WRITE_CMP_TABLE_INDEX_FLD, + }, +}; + +/** + * Global to device field id mapping for READ_CLR_CMP + */ +struct field_mapping cfa_p70_mpc_read_clr_cmp_gbl_to_dev + [CFA_BLD_MPC_READ_CLR_CMP_MAX_FLD] = { + [CFA_BLD_MPC_READ_CLR_CMP_TYPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMP_TYPE_FLD, + }, + [CFA_BLD_MPC_READ_CLR_CMP_STATUS_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMP_STATUS_FLD, + }, + [CFA_BLD_MPC_READ_CLR_CMP_MP_CLIENT_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMP_MP_CLIENT_FLD, + }, + [CFA_BLD_MPC_READ_CLR_CMP_OPCODE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMP_OPCODE_FLD, + }, + [CFA_BLD_MPC_READ_CLR_CMP_DMA_LENGTH_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMP_DMA_LENGTH_FLD, + }, + [CFA_BLD_MPC_READ_CLR_CMP_OPAQUE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMP_OPAQUE_FLD, + }, + [CFA_BLD_MPC_READ_CLR_CMP_V_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMP_V_FLD, + }, + [CFA_BLD_MPC_READ_CLR_CMP_HASH_MSB_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMP_HASH_MSB_FLD, + }, + [CFA_BLD_MPC_READ_CLR_CMP_TABLE_TYPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMP_TABLE_TYPE_FLD, + }, + [CFA_BLD_MPC_READ_CLR_CMP_TABLE_SCOPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMP_TABLE_SCOPE_FLD, + }, + [CFA_BLD_MPC_READ_CLR_CMP_TABLE_INDEX_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_READ_CLR_CMP_TABLE_INDEX_FLD, + }, +}; + +/** + * Global to device field id mapping for INVALIDATE_CMP + */ +struct field_mapping cfa_p70_mpc_invalidate_cmp_gbl_to_dev + [CFA_BLD_MPC_INVALIDATE_CMP_MAX_FLD] = { + [CFA_BLD_MPC_INVALIDATE_CMP_TYPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_INVALIDATE_CMP_TYPE_FLD, + }, + [CFA_BLD_MPC_INVALIDATE_CMP_STATUS_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_INVALIDATE_CMP_STATUS_FLD, + }, + [CFA_BLD_MPC_INVALIDATE_CMP_MP_CLIENT_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_INVALIDATE_CMP_MP_CLIENT_FLD, + }, + [CFA_BLD_MPC_INVALIDATE_CMP_OPCODE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_INVALIDATE_CMP_OPCODE_FLD, + }, + [CFA_BLD_MPC_INVALIDATE_CMP_OPAQUE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_INVALIDATE_CMP_OPAQUE_FLD, + }, + [CFA_BLD_MPC_INVALIDATE_CMP_V_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_INVALIDATE_CMP_V_FLD, + }, + [CFA_BLD_MPC_INVALIDATE_CMP_HASH_MSB_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_INVALIDATE_CMP_HASH_MSB_FLD, + }, + [CFA_BLD_MPC_INVALIDATE_CMP_TABLE_TYPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_INVALIDATE_CMP_TABLE_TYPE_FLD, + }, + [CFA_BLD_MPC_INVALIDATE_CMP_TABLE_SCOPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_INVALIDATE_CMP_TABLE_SCOPE_FLD, + }, + [CFA_BLD_MPC_INVALIDATE_CMP_TABLE_INDEX_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_INVALIDATE_CMP_TABLE_INDEX_FLD, + }, +}; + +/** + * Global to device field id mapping for EM_SEARCH_CMP + */ +struct field_mapping cfa_p70_mpc_em_search_cmp_gbl_to_dev + [CFA_BLD_MPC_EM_SEARCH_CMP_MAX_FLD] = { + [CFA_BLD_MPC_EM_SEARCH_CMP_TYPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_SEARCH_CMP_TYPE_FLD, + }, + [CFA_BLD_MPC_EM_SEARCH_CMP_STATUS_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_SEARCH_CMP_STATUS_FLD, + }, + [CFA_BLD_MPC_EM_SEARCH_CMP_MP_CLIENT_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_SEARCH_CMP_MP_CLIENT_FLD, + }, + [CFA_BLD_MPC_EM_SEARCH_CMP_OPCODE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_SEARCH_CMP_OPCODE_FLD, + }, + [CFA_BLD_MPC_EM_SEARCH_CMP_OPAQUE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_SEARCH_CMP_OPAQUE_FLD, + }, + [CFA_BLD_MPC_EM_SEARCH_CMP_V1_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_SEARCH_CMP_V1_FLD, + }, + [CFA_BLD_MPC_EM_SEARCH_CMP_HASH_MSB_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_SEARCH_CMP_HASH_MSB_FLD, + }, + [CFA_BLD_MPC_EM_SEARCH_CMP_TABLE_SCOPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_SEARCH_CMP_TABLE_SCOPE_FLD, + }, + [CFA_BLD_MPC_EM_SEARCH_CMP_TABLE_INDEX_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_SEARCH_CMP_TABLE_INDEX_FLD, + }, + [CFA_BLD_MPC_EM_SEARCH_CMP_TABLE_INDEX2_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_SEARCH_CMP_TABLE_INDEX2_FLD, + }, + [CFA_BLD_MPC_EM_SEARCH_CMP_V2_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_SEARCH_CMP_V2_FLD, + }, + [CFA_BLD_MPC_EM_SEARCH_CMP_BKT_NUM_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_SEARCH_CMP_BKT_NUM_FLD, + }, + [CFA_BLD_MPC_EM_SEARCH_CMP_NUM_ENTRIES_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_SEARCH_CMP_NUM_ENTRIES_FLD, + }, +}; + +/** + * Global to device field id mapping for EM_INSERT_CMP + */ +struct field_mapping cfa_p70_mpc_em_insert_cmp_gbl_to_dev + [CFA_BLD_MPC_EM_INSERT_CMP_MAX_FLD] = { + [CFA_BLD_MPC_EM_INSERT_CMP_TYPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMP_TYPE_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMP_STATUS_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMP_STATUS_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMP_MP_CLIENT_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMP_MP_CLIENT_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMP_OPCODE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMP_OPCODE_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMP_OPAQUE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMP_OPAQUE_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMP_V1_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMP_V1_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMP_HASH_MSB_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMP_HASH_MSB_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMP_TABLE_SCOPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMP_TABLE_SCOPE_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMP_TABLE_INDEX_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX2_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMP_TABLE_INDEX2_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX3_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMP_TABLE_INDEX3_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMP_V2_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMP_V2_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMP_TABLE_INDEX4_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMP_TABLE_INDEX4_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMP_BKT_NUM_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMP_BKT_NUM_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMP_NUM_ENTRIES_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMP_NUM_ENTRIES_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMP_CHAIN_UPD_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMP_CHAIN_UPD_FLD, + }, + [CFA_BLD_MPC_EM_INSERT_CMP_REPLACED_ENTRY_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_INSERT_CMP_REPLACED_ENTRY_FLD, + }, +}; + +/** + * Global to device field id mapping for EM_DELETE_CMP + */ +struct field_mapping cfa_p70_mpc_em_delete_cmp_gbl_to_dev + [CFA_BLD_MPC_EM_DELETE_CMP_MAX_FLD] = { + [CFA_BLD_MPC_EM_DELETE_CMP_TYPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMP_TYPE_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMP_STATUS_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMP_STATUS_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMP_MP_CLIENT_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMP_MP_CLIENT_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMP_OPCODE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMP_OPCODE_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMP_OPAQUE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMP_OPAQUE_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMP_V1_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMP_V1_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMP_HASH_MSB_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMP_HASH_MSB_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMP_TABLE_SCOPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMP_TABLE_SCOPE_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMP_TABLE_INDEX_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX2_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMP_TABLE_INDEX2_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX3_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMP_TABLE_INDEX3_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMP_V2_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMP_V2_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMP_TABLE_INDEX4_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMP_TABLE_INDEX4_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMP_BKT_NUM_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMP_BKT_NUM_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMP_NUM_ENTRIES_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMP_NUM_ENTRIES_FLD, + }, + [CFA_BLD_MPC_EM_DELETE_CMP_CHAIN_UPD_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_DELETE_CMP_CHAIN_UPD_FLD, + }, +}; + +/** + * Global to device field id mapping for EM_CHAIN_CMP + */ +struct field_mapping cfa_p70_mpc_em_chain_cmp_gbl_to_dev + [CFA_BLD_MPC_EM_CHAIN_CMP_MAX_FLD] = { + [CFA_BLD_MPC_EM_CHAIN_CMP_TYPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMP_TYPE_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMP_STATUS_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMP_STATUS_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMP_MP_CLIENT_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMP_MP_CLIENT_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMP_OPCODE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMP_OPCODE_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMP_OPAQUE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMP_OPAQUE_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMP_V1_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMP_V1_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMP_HASH_MSB_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMP_HASH_MSB_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_SCOPE_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMP_TABLE_SCOPE_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_INDEX_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMP_TABLE_INDEX_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_INDEX2_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMP_TABLE_INDEX2_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMP_TABLE_INDEX3_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMP_TABLE_INDEX3_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMP_V2_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMP_V2_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMP_BKT_NUM_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMP_BKT_NUM_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMP_NUM_ENTRIES_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMP_NUM_ENTRIES_FLD, + }, + [CFA_BLD_MPC_EM_CHAIN_CMP_CHAIN_UPD_FLD] = { + .valid = true, + .mapping = CFA_P70_MPC_EM_CHAIN_CMP_CHAIN_UPD_FLD, + }, +}; + +/* clang-format on */ + +#endif /* _CFA_P70_MPC_FIELD_MAPPING_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/include/cfa_resources.h b/drivers/net/bnxt/hcapi/cfa_v3/include/cfa_resources.h new file mode 100644 index 0000000000..a639ee93d6 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/include/cfa_resources.h @@ -0,0 +1,185 @@ +/**************************************************************************** + * Copyright(c) 2021 - 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_resources.h + * + * @brief CFA Resource type definitions + */ +#ifndef _CFA_RESOURCES_H_ +#define _CFA_RESOURCES_H_ + +/** + * @addtogroup CFA_RESC_TYPES CFA Resource Types + * \ingroup CFA_V3 + * CFA HW resource types and sub types definition + * @{ + */ + +/** + * CFA hardware Resource Type + * + * Depending on the type of CFA hardware resource, the resources are divided + * into multiple groups. This group is identified by resource type. The + * following enum defines all the CFA resource types + */ +enum cfa_resource_type { + /** CFA resources using fixed identifiers (IDM) + */ + CFA_RTYPE_IDENT = 0, + /** CFA resources accessed by fixed indices (TBM) + */ + CFA_RTYPE_IDX_TBL, + /** CFA TCAM resources + */ + CFA_RTYPE_TCAM, + /** CFA interface tables (IFM) + */ + CFA_RTYPE_IF_TBL, + /** CFA resources accessed using CFA memory manager index + */ + CFA_RTYPE_CMM, + /** CFA Global fields (e.g. registers which configure global settings) + */ + CFA_RTYPE_GLB_FLD, + + CFA_RTYPE_HW_MAX = 12, + + /** FIrmware only types + */ + /** CFA Firmware Session Manager + */ + CFA_RTYPE_SM = CFA_RTYPE_HW_MAX, + /** CFA Firmware Table Scope Manager + */ + CFA_RTYPE_TSM, + /** CFA Firmware Table Scope Instance Manager + */ + CFA_RTYPE_TIM, + /** CFA Firmware Global Id Manager + */ + CFA_RTYPE_GIM, + + CFA_RTYPE_MAX +}; + +/** + * Resource sub-types for CFA_RTYPE_IDENT + */ +enum cfa_resource_subtype_ident { + CFA_RSUBTYPE_IDENT_L2CTX = 0, /**< Remapped L2 contexts */ + CFA_RSUBTYPE_IDENT_PROF_FUNC, /**< Profile functions */ + CFA_RSUBTYPE_IDENT_WC_PROF, /**< WC TCAM profile IDs */ + CFA_RSUBTYPE_IDENT_EM_PROF, /**< EM profile IDs */ + CFA_RSUBTYPE_IDENT_L2_FUNC, /**< L2 functions */ + CFA_RSUBTYPE_IDENT_LAG_ID, /**< LAG IDs */ + CFA_RSUBTYPE_IDENT_MAX +}; + +/** + * Resource sub-types for CFA_RTYPE_IDX + */ +enum cfa_resource_subtype_idx_tbl { + CFA_RSUBTYPE_IDX_TBL_STAT64 = 0, /**< Statistics */ + CFA_RSUBTYPE_IDX_TBL_METER_PROF, /**< Meter profile */ + CFA_RSUBTYPE_IDX_TBL_METER_INST, /**< Meter instances */ + CFA_RSUBTYPE_IDX_TBL_METER_DROP_CNT, /**< Meter Drop Count */ + CFA_RSUBTYPE_IDX_TBL_MIRROR, /**< Mirror table */ + /* Metadata mask for profiler block */ + CFA_RSUBTYPE_IDX_TBL_METADATA_PROF, + /* Metadata mask for lookup block (for recycling) */ + CFA_RSUBTYPE_IDX_TBL_METADATA_LKUP, + /* Metadata mask for action block */ + CFA_RSUBTYPE_IDX_TBL_METADATA_ACT, + CFA_RSUBTYPE_IDX_TBL_CT_STATE, /**< Connection tracking */ + CFA_RSUBTYPE_IDX_TBL_RANGE_PROF, /**< Range profile */ + CFA_RSUBTYPE_IDX_TBL_RANGE_ENTRY, /**< Range entry */ + CFA_RSUBTYPE_IDX_TBL_EM_FKB, /**< EM FKB table */ + CFA_RSUBTYPE_IDX_TBL_WC_FKB, /**< WC TCAM FKB table */ + CFA_RSUBTYPE_IDX_TBL_EM_FKB_MASK, /**< EM FKB Mask table */ + CFA_RSUBTYPE_IDX_TBL_MAX +}; + +/** + * Resource sub-types for CFA_RTYPE_TCAM + */ +enum cfa_resource_subtype_tcam { + CFA_RSUBTYPE_TCAM_L2CTX = 0, /**< L2 contexts TCAM */ + CFA_RSUBTYPE_TCAM_PROF_TCAM, /**< Profile TCAM */ + CFA_RSUBTYPE_TCAM_WC, /**< WC lookup TCAM */ + CFA_RSUBTYPE_TCAM_CT_RULE, /**< Connection tracking TCAM */ + CFA_RSUBTYPE_TCAM_VEB, /**< VEB TCAM */ + CFA_RSUBTYPE_TCAM_FEATURE_CHAIN, /**< Feature chain TCAM */ + CFA_RSUBTYPE_TCAM_MAX +}; + +/** + * Resource sub-types for CFA_RTYPE_IF_TBL + */ +enum cfa_resource_subtype_if_tbl { + /** ILT table indexed by SVIF + */ + CFA_RSUBTYPE_IF_TBL_ILT = 0, + /** VSPT table + */ + CFA_RSUBTYPE_IF_TBL_VSPT, + /** Profiler partition default action record pointer + */ + CFA_RSUBTYPE_IF_TBL_PROF_PARIF_DFLT_ACT_PTR, + /** Profiler partition error action record pointer + */ + CFA_RSUBTYPE_IF_TBL_PROF_PARIF_ERR_ACT_PTR, + CFA_RSUBTYPE_IF_TBL_EPOCH0, /**< Epoch0 mask table */ + CFA_RSUBTYPE_IF_TBL_EPOCH1, /**< Epoch1 mask table */ + CFA_RSUBTYPE_IF_TBL_LAG, /**< LAG Table */ + CFA_RSUBTYPE_IF_TBL_MAX +}; + +/** + * Resource sub-types for CFA_RTYPE_CMM + */ +enum cfa_resource_subtype_cmm { + CFA_RSUBTYPE_CMM_INT_ACT_B0 = 0, /**< SRAM Bank 0 */ + CFA_RSUBTYPE_CMM_INT_ACT_B1, /**< SRAM Bank 0 */ + CFA_RSUBTYPE_CMM_INT_ACT_B2, /**< SRAM Bank 0 */ + CFA_RSUBTYPE_CMM_INT_ACT_B3, /**< SRAM Bank 0 */ + CFA_RSUBTYPE_CMM_ACT, /**< Action table */ + CFA_RSUBTYPE_CMM_LKUP, /**< EM lookup table */ + CFA_RSUBTYPE_CMM_MAX +}; + +#define CFA_RSUBTYPE_GLB_FLD_MAX 1 +#define CFA_RSUBTYPE_SM_MAX 1 +#define CFA_RSUBTYPE_TSM_MAX 1 +#define CFA_RSUBTYPE_TIM_MAX 1 + +/** + * Resource sub-types for CFA_RTYPE_GIM + */ +enum cfa_resource_subtype_gim { + CFA_RSUBTYPE_GIM_DOMAIN_0 = 0, /**< Domain 0 */ + CFA_RSUBTYPE_GIM_DOMAIN_1, /**< Domain 1 */ + CFA_RSUBTYPE_GIM_DOMAIN_2, /**< Domain 2 */ + CFA_RSUBTYPE_GIM_DOMAIN_3, /**< Domain 3 */ + CFA_RSUBTYPE_GIM_MAX +}; + +/** + * Total number of resource subtypes + */ +#define CFA_NUM_RSUBTYPES \ + (CFA_RSUBTYPE_IDENT_MAX + CFA_RSUBTYPE_IDX_TBL_MAX + \ + CFA_RSUBTYPE_TCAM_MAX + CFA_RSUBTYPE_IF_TBL_MAX + \ + CFA_RSUBTYPE_CMM_MAX + CFA_RSUBTYPE_GLB_FLD_MAX + \ + CFA_RSUBTYPE_SM_MAX + CFA_RSUBTYPE_TSM_MAX + CFA_RSUBTYPE_TIM_MAX + \ + CFA_RSUBTYPE_GIM_MAX) + +/** + * @} + */ + +#endif /* _CFA_RESOURCES_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/include/cfa_trace.h b/drivers/net/bnxt/hcapi/cfa_v3/include/cfa_trace.h new file mode 100644 index 0000000000..1079ee57d3 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/include/cfa_trace.h @@ -0,0 +1,273 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_trace.h + * + * @brief CFA logging macros + */ + +#ifndef __CFA_TRACE_H_ +#define __CFA_TRACE_H_ + +/*! + * \file + * \brief CFA logging macros and functions + * @{ + */ + +#ifndef COMP_ID +#error COMP_ID must be defined in the module including this file. +#endif + +/* These must be defined before the platform specific header is included. */ +#ifndef CFA_DEBUG_LEVEL_DBG +#define CFA_DEBUG_LEVEL_DBG 0x0 +#define CFA_DEBUG_LEVEL_INFO 0x1 +#define CFA_DEBUG_LEVEL_WARN 0x2 +#define CFA_DEBUG_LEVEL_CRITICAL 0x3 +#define CFA_DEBUG_LEVEL_FATAL 0x4 +#endif + +/* Include platform specific CFA logging api header */ +#include "cfa_debug_defs.h" + +/* #define CFA_DYNAMIC_TRACE_FILTERING */ + +/** @name Default Log Levels + * Default log level for each component. If not defined for a component, the + * log level for that component defaults to 0 (CFA_DEBUG_LEVEL_DBG). + * @{ + */ +#define CFA_BLD_DEBUG_LEVEL CFA_DEBUG_LEVEL_INFO +#define CFA_CMM_DEBUG_LEVEL CFA_DEBUG_LEVEL_INFO +#define CFA_GIM_DEBUG_LEVEL CFA_DEBUG_LEVEL_INFO +#define CFA_HOSTIF_DEBUG_LEVEL CFA_DEBUG_LEVEL_INFO +#define CFA_IDM_DEBUG_LEVEL CFA_DEBUG_LEVEL_INFO +#define CFA_OIM_DEBUG_LEVEL CFA_DEBUG_LEVEL_INFO +#define CFA_RM_DEBUG_LEVEL CFA_DEBUG_LEVEL_INFO +#define CFA_SM_DEBUG_LEVEL CFA_DEBUG_LEVEL_INFO +#define CFA_TBM_DEBUG_LEVEL CFA_DEBUG_LEVEL_INFO +#define CFA_TCM_DEBUG_LEVEL CFA_DEBUG_LEVEL_INFO +#define CFA_TIM_DEBUG_LEVEL CFA_DEBUG_LEVEL_INFO +#define CFA_TPM_DEBUG_LEVEL CFA_DEBUG_LEVEL_INFO +#define CFA_TSM_DEBUG_LEVEL CFA_DEBUG_LEVEL_INFO +/** @} */ + +/* Do not use these macros directly */ + +/* \cond DO_NOT_DOCUMENT */ +#define JOIN(a, b) a##b +#define JOIN3(a, b, c) a##b##c +#define CFA_COMP_NAME(ID) JOIN(CFA_COMP_, ID) +#define CFA_COMP_DBG_LEVEL(ID) JOIN3(CFA_, ID, _DEBUG_LEVEL) +#define CFA_TRACE_STRINGIFY(x) #x +#define CFA_TRACE_LINE_STRING(line) CFA_TRACE_STRINGIFY(line) +#define CFA_TRACE_LINE() CFA_TRACE_LINE_STRING(__LINE__) +#define CFA_LOG(level, format, ...) \ + CFA_TRACE(level, "%s:" CFA_TRACE_LINE() ": " format, __func__, \ + ##__VA_ARGS__) + +#define CFA_LOG_FL(function, line, level, format, ...) \ + CFA_TRACE(level, "%s: %s: " format, function, line, ##__VA_ARGS__) + +#ifdef CFA_DYNAMIC_TRACE_FILTERING +#define CFA_TRACE_FILTERED(component, level, format, ...) \ + do { \ + int local_level = level; \ + if (cfa_trace_enabled(component, local_level)) \ + CFA_LOG(local_level, format, ##__VA_ARGS__); \ + } while (0) + +#define CFA_TRACE_FILTERED_FL(function, line, component, level, format, ...) \ + do { \ + int local_level = level; \ + if (cfa_trace_enabled(component, local_level)) \ + CFA_LOG_FL(function, line, local_level, format, \ + ##__VA_ARGS__); \ + } while (0) + +#else +/* Static log filtering */ +#if CFA_COMP_DBG_LEVEL(COMP_ID) <= CFA_DEBUG_LEVEL_DBG +#define CFA_TRACE_DBG(format, ...) \ + CFA_LOG(CFA_DEBUG_LEVEL_DBG, format, ##__VA_ARGS__) +#define CFA_TRACE_DBG_FL(function, line, format, ...) \ + CFA_LOG_FL(function, line, CFA_DEBUG_LEVEL_DBG, format, ##__VA_ARGS__) +#else +#define CFA_TRACE_DBG(format, ...) +#define CFA_TRACE_DBG_FL(format, ...) +#endif +#if CFA_COMP_DBG_LEVEL(COMP_ID) <= CFA_DEBUG_LEVEL_INFO +#define CFA_TRACE_INFO(format, ...) \ + CFA_LOG(CFA_DEBUG_LEVEL_INFO, format, ##__VA_ARGS__) +#define CFA_TRACE_INFO_FL(function, line, format, ...) \ + CFA_LOG_FL(function, line, CFA_DEBUG_LEVEL_INFO, format, ##__VA_ARGS__) +#else +#define CFA_TRACE_INFO(format, ...) +#define CFA_TRACE_INFO_FL(function, line, format, ...) +#endif +#if CFA_COMP_DBG_LEVEL(COMP_ID) <= CFA_DEBUG_LEVEL_WARN +#define CFA_TRACE_WARN(format, ...) \ + CFA_LOG(CFA_DEBUG_LEVEL_WARN, format, ##__VA_ARGS__) +#define CFA_TRACE_WARN_FL(function, line, format, ...) \ + CFA_LOG_FL(function, line, CFA_DEBUG_LEVEL_WARN, format, ##__VA_ARGS__) +#else +#define CFA_TRACE_WARN(format, ...) +#define CFA_TRACE_WARN_FL(function, line, format, ...) +#endif +#if CFA_COMP_DBG_LEVEL(COMP_ID) <= CFA_DEBUG_LEVEL_CRITICAL +#define CFA_TRACE_ERR(format, ...) \ + CFA_LOG(CFA_DEBUG_LEVEL_CRITICAL, format, ##__VA_ARGS__) +#define CFA_TRACE_ERR_FL(function, line, format, ...) \ + CFA_LOG_FL(function, line, CFA_DEBUG_LEVEL_CRITICAL, format, \ + ##__VA_ARGS__) +#else +#define CFA_TRACE_ERR(format, ...) +#define CFA_TRACE_ERR_FL(function, line, format, ...) +#endif +#define CFA_TRACE_FATAL(format, ...) \ + CFA_LOG(CFA_DEBUG_LEVEL_FATAL, format, ##__VA_ARGS__) + +#endif +/* \endcond */ + +/** @name Logging Macros + * These macros log with the function and line number of the location invoking + * the macro. + * @{ + */ +#ifdef CFA_DYNAMIC_TRACE_FILTERING +#define CFA_LOG_DBG(format, ...) \ + CFA_TRACE_FILTERED(CFA_COMP_NAME(COMP_ID), CFA_DEBUG_LEVEL_DBG, \ + format, ##__VA_ARGS__) +#define CFA_LOG_INFO(COMP_ID, format, ...) \ + CFA_TRACE_FILTERED(CFA_COMP_NAME(COMP_ID), CFA_DEBUG_LEVEL_INFO, \ + format, ##__VA_ARGS__) +#define CFA_LOG_WARN(format, ...) \ + CFA_TRACE_FILTERED(CFA_COMP_NAME(COMP_ID), CFA_DEBUG_LEVEL_WARN, \ + format, ##__VA_ARGS__) +#define CFA_LOG_ERR(format, ...) \ + CFA_TRACE_FILTERED(CFA_COMP_NAME(COMP_ID), CFA_DEBUG_LEVEL_CRITICAL, \ + format, ##__VA_ARGS__) +#define CFA_LOG_FATAL(format, ...) \ + CFA_TRACE_FILTERED(CFA_COMP_NAME(COMP_ID), CFA_DEBUG_LEVEL_FATAL, \ + format, ##__VA_ARGS__) +#else +#define CFA_LOG_DBG(format, ...) CFA_TRACE_DBG(format, ##__VA_ARGS__) +#define CFA_LOG_INFO(format, ...) CFA_TRACE_INFO(format, ##__VA_ARGS__) +#define CFA_LOG_WARN(format, ...) CFA_TRACE_WARN(format, ##__VA_ARGS__) +#define CFA_LOG_ERR(format, ...) CFA_TRACE_ERR(format, ##__VA_ARGS__) +#define CFA_LOG_FATAL(format, ...) CFA_TRACE_FATAL(format, ##__VA_ARGS__) +#endif +/** @} */ + +/** @name Logging Macros with Function + * These macros log with the function and line number passed into + * the macro. + * @{ + */ +#ifdef CFA_DYNAMIC_TRACE_FILTERING +#define CFA_LOG_DBG_FL(function, line, format, ...) \ + CFA_TRACE_FILTERED_FL(function, line, CFA_COMP_NAME(COMP_ID), \ + CFA_DEBUG_LEVEL_DBG, format, ##__VA_ARGS__) +#define CFA_LOG_INFO_FL(function, line, format, ...) \ + CFA_TRACE_FILTERED_FL(function, line, CFA_COMP_NAME(COMP_ID), \ + CFA_DEBUG_LEVEL_INFO, format, ##__VA_ARGS__) +#define CFA_LOG_WARN_FL(function, line, format, ...) \ + CFA_TRACE_FILTERED_FL(function, line, CFA_COMP_NAME(COMP_ID), \ + CFA_DEBUG_LEVEL_WARN, format, ##__VA_ARGS__) +#define CFA_LOG_ERR_FL(function, line, format, ...) \ + CFA_TRACE_FILTERED_FL(function, line, CFA_COMP_NAME(COMP_ID), \ + CFA_DEBUG_LEVEL_CRITICAL, format, ##__VA_ARGS__) +#define CFA_LOG_FATAL_FL(function, line, format, ...) \ + CFA_TRACE_FILTERED_FL(function, line, CFA_COMP_NAME(COMP_ID), \ + CFA_DEBUG_LEVEL_FATAL, format, ##__VA_ARGS__) +#else +#define CFA_LOG_DBG_FL(function, line, format, ...) \ + CFA_TRACE_DBG_FL(function, line, format, ##__VA_ARGS__) +#define CFA_LOG_INFO_FL(function, line, format, ...) \ + CFA_TRACE_INFO_FL(function, line, format, ##__VA_ARGS__) +#define CFA_LOG_WARN_FL(function, line, format, ...) \ + CFA_TRACE_WARN_FL(function, line, format, ##__VA_ARGS__) +#define CFA_LOG_ERR_FL(function, line, format, ...) \ + CFA_TRACE_ERR_FL(function, line, format, ##__VA_ARGS__) +#define CFA_LOG_FATAL_FL(function, line, format, ...) \ + CFA_TRACE_FATAL_FL(function, line, format, ##__VA_ARGS__) +#endif +/** @} */ + +/** + * CFA components + */ +enum cfa_components { + CFA_COMP_BLD = 0, + CFA_COMP_FIRST = CFA_COMP_BLD, + CFA_COMP_CMM, + CFA_COMP_GIM, + CFA_COMP_HOSTIF, + CFA_COMP_IDM, + CFA_COMP_OIM, + CFA_COMP_RM, + CFA_COMP_SM, + CFA_COMP_TBM, + CFA_COMP_TCM, + CFA_COMP_TIM, + CFA_COMP_TPM, + CFA_COMP_TSM, + CFA_COMP_MAX +}; + +#ifdef CFA_DYNAMIC_TRACE_FILTERING +/** + * CFA logging system initialization + * + * This API initializes the CFA logging infrastructure + * + * @return + * 0 for SUCCESS, negative error value for FAILURE + */ +int cfa_trace_init(void); + +/** + * CFA logging check if message permitted + * + * This API indicates if a log message for a component at a given level should + * be issued + * + * @param[in] component + * The CFA component + * + * @param[in] level + * The logging level to check for the component + * + * @return + * 0 if message not permitted, non-zero if the message is permitted + */ +int cfa_trace_enabled(enum cfa_components component, int level); + +/** + * CFA logging level set + * + * This API set the minimum level of log messages to be issued for a component + * + * @param[in] component + * The CFA component + * + * @param[in] level + * The logging level to set for the component + * + * @return + * 0 for SUCCESS, negative error value for FAILURE + */ +int cfa_trace_level_set(enum cfa_components component, int level); + +#endif /* CFA_DYNAMIC_TRACE_FILTERING */ + +/** @} */ + +#endif /* __CFA_TRACE_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/include/cfa_types.h b/drivers/net/bnxt/hcapi/cfa_v3/include/cfa_types.h new file mode 100644 index 0000000000..4b3f5379cb --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/include/cfa_types.h @@ -0,0 +1,122 @@ +/**************************************************************************** + * Copyright(c) 2021 - 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_types.h + * + * @brief Basic CFA type definitions + */ +#ifndef _CFA_TYPES_H_ +#define _CFA_TYPES_H_ + +/*! + * \file + * \brief Exported CFA data structures shared between host and firmware + * @{ + */ + +/** \defgroup CFA_V3 Common CFA Access Framework + * + * The primary goal of the CFA common HW access framework is to unify the CFA + * resource management and hardware programming design for different CFA + * applications so the CFA hardware can be properly shared with different + * entities. This framework is collection of the following CFA resource + * managers and Libraries listed below: + * + * 1. CFA Memory Manager + * 2. CFA Object Instance Manager + * 3. CFA Session Manager + * 4. CFA TCAM Manager + * 5. CFA Table Scope Manager + * 6. CFA Hardware Access Library + * 7. CFA Builder Library + * 8. CFA Index table manager + * 9. CFA Utilities Library + * + **/ + +/** + * CFA HW version definition + */ +enum cfa_ver { + CFA_P40 = 0, /**< CFA phase 4.0 */ + CFA_P45 = 1, /**< CFA phase 4.5 */ + CFA_P58 = 2, /**< CFA phase 5.8 */ + CFA_P59 = 3, /**< CFA phase 5.9 */ + CFA_P70 = 4, /**< CFA phase 7.0 */ + CFA_PMAX = 5 +}; + +/** + * CFA direction definition + */ +enum cfa_dir { + CFA_DIR_RX = 0, /**< Receive */ + CFA_DIR_TX = 1, /**< Transmit */ + CFA_DIR_MAX = 2 +}; + +/** + * CFA Remap Table Type + */ +enum cfa_remap_tbl_type { + CFA_REMAP_TBL_TYPE_NORMAL = 0, + CFA_REMAP_TBL_TYPE_BYPASS, + CFA_REMAP_TBL_TYPE_MAX +}; + +/** + * CFA tracker types + */ +enum cfa_track_type { + CFA_TRACK_TYPE_INVALID = 0, /** !< Invalid */ + CFA_TRACK_TYPE_SID, /** !< Tracked by session id */ + CFA_TRACK_TYPE_FIRST = CFA_TRACK_TYPE_SID, + CFA_TRACK_TYPE_FID, /** !< Tracked by function id */ + CFA_TRACK_TYPE_MAX +}; + +/** + * CFA Region Type + */ +enum cfa_region_type { + CFA_REGION_TYPE_LKUP = 0, + CFA_REGION_TYPE_ACT, + CFA_REGION_TYPE_MAX +}; + +/** + * CFA application type + */ +enum cfa_app_type { + CFA_APP_TYPE_AFM = 0, /** !< AFM firmware */ + CFA_APP_TYPE_TF = 1, /** !< TruFlow firmware */ + CFA_APP_TYPE_MAX = 2, + CFA_APP_TYPE_INVALID = CFA_APP_TYPE_MAX, +}; + +/** + * CFA FID types + */ +enum cfa_fid_type { + CFA_FID_TYPE_FID = 0, /**< General */ + CFA_FID_TYPE_RFID = 1, /**< Representor */ + CFA_FID_TYPE_EFID = 2 /**< Endpoint */ +}; + +/** + * CFA srchm modes + */ +enum cfa_srch_mode { + CFA_SRCH_MODE_FIRST = 0, /** !< Start new iteration */ + CFA_SRCH_MODE_NEXT, /** !< Next item in iteration */ + CFA_SRCH_MODE_MAX +}; + +/** @} */ + +#endif /* _CFA_TYPES_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/include/cfa_util.h b/drivers/net/bnxt/hcapi/cfa_v3/include/cfa_util.h new file mode 100644 index 0000000000..17506017be --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/include/cfa_util.h @@ -0,0 +1,44 @@ +/**************************************************************************** + * Copyright(c) 2021 - 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_util.h + * + * @brief CFA specific utility macros used by cfa libraries and manager + * sources. + */ + +#ifndef _CFA_UTIL_H_ +#define _CFA_UTIL_H_ + +/*! + * \file + * \brief CFA specific utility macros + * \ingroup CFA_V3 + * @{ + */ + +/* Bounds (closed interval) check helper macro */ +#define CFA_CHECK_BOUNDS(x, l, h) (((x) >= (l)) && ((x) <= (h))) +#define CFA_CHECK_UPPER_BOUNDS(x, h) ((x) <= (h)) + +/* + * Join macros to generate device specific object/function names for use by + * firmware + */ +#define CFA_JOIN2(A, B) A##_##B +#define CFA_JOIN3(A, B, C) A##B##_##C +#define CFA_OBJ_NAME(PREFIX, VER, NAME) CFA_JOIN3(PREFIX, VER, NAME) +#define CFA_FUNC_NAME(PREFIX, VER, NAME) CFA_OBJ_NAME(PREFIX, VER, NAME) + +/* clang-format off */ +#define CFA_ALIGN_LN2(x) (((x) < 3U) ? (x) : 32U - __builtin_clz((x) - 1U) + 1U) +/* clang-format on */ + +/** @} */ + +#endif /* _CFA_UTIL_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/include/platform/dpdk/cfa_debug_defs.h b/drivers/net/bnxt/hcapi/cfa_v3/include/platform/dpdk/cfa_debug_defs.h new file mode 100644 index 0000000000..86f95f1cf4 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/include/platform/dpdk/cfa_debug_defs.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_debug_defs.h + * + * @brief Platform specific CFA Debug log api definitions + */ + +#ifndef __CFA_DEBUG_DEFS_H_ +#define __CFA_DEBUG_DEFS_H_ + +#include + +extern int bnxt_logtype_driver; + +/* + * The cfa_trace infrastructure assumes that log level debug is the lowest + * numerically. This is true for firmware, but the RTE log levels have debug as + * the highest level. Need to provide a conversion for calling rte_log. We + * don't want to simply use the RTE log levels since there are checks such as: + * + * #if CFA_COMP_DBG_LEVEL(COMP_ID) <= CFA_DEBUG_LEVEL_DBG + * + * Those checks would not have the desired effect if the RTE log levels are + * substituted for the CFA log levels like this: + * + * #define CFA_DEBUG_LEVEL_DBG RTE_LOG_DEBUG + * #define CFA_DEBUG_LEVEL_INFO RTE_LOG_INFO + * #define CFA_DEBUG_LEVEL_WARN RTE_LOG_WARNING + * #define CFA_DEBUG_LEVEL_CRITICAL RTE_LOG_CRIT + * #define CFA_DEBUG_LEVEL_FATAL RTE_LOG_EMERG + */ + +#define CFA_TO_RTE_LOG(level) \ + ((level) == CFA_DEBUG_LEVEL_DBG ? \ + RTE_LOG_DEBUG : \ + (level) == CFA_DEBUG_LEVEL_INFO ? \ + RTE_LOG_INFO : \ + (level) == CFA_DEBUG_LEVEL_WARN ? \ + RTE_LOG_WARNING : \ + (level) == CFA_DEBUG_LEVEL_CRITICAL ? RTE_LOG_CRIT : \ + RTE_LOG_EMERG) + +#define CFA_TRACE(level, ...) \ + rte_log(CFA_TO_RTE_LOG(level), bnxt_logtype_driver, ##__VA_ARGS__) + +#endif /* __CFA_DEBUG_DEFS_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/include/sys_util.h b/drivers/net/bnxt/hcapi/cfa_v3/include/sys_util.h new file mode 100644 index 0000000000..9f5fa8fe98 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/include/sys_util.h @@ -0,0 +1,101 @@ +/**************************************************************************** + * Copyright(c) 2021 - 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file sys_util.h + * + * @brief Utility macros for bit manipulation, alignments and other + * commonly used helper functions. This file should be moved out + * of cfa v3 folder to a common utilities folder + */ + +#ifndef _SYS_UTIL_H_ +#define _SYS_UTIL_H_ + +#include + +#define INVALID_U64 UINT64_MAX +#define INVALID_U32 UINT32_MAX +#define INVALID_U16 UINT16_MAX +#define INVALID_U8 UINT8_MAX + +#ifndef ALIGN +#define ALIGN(x, a) (((x) + (a) - (1)) & ~((a) - (1))) +#endif + +#define ALIGN_256(x) ALIGN(x, 256) +#define ALIGN_128(x) ALIGN(x, 128) +#define ALIGN_64(x) ALIGN(x, 64) +#define ALIGN_32(x) ALIGN(x, 32) +#define ALIGN_16(x) ALIGN(x, 16) +#define ALIGN_8(x) ALIGN(x, 8) +#define ALIGN_4(x) ALIGN(x, 4) + +#define NUM_ALIGN_UNITS(x, unit) (((x) + (unit) - (1)) / (unit)) +#define IS_POWER_2(x) (((x) != 0) && (((x) & ((x) - (1))) == 0)) + +#define NUM_WORDS_ALIGN_32BIT(x) (ALIGN_32(x) / BITS_PER_WORD) +#define NUM_WORDS_ALIGN_64BIT(x) (ALIGN_64(x) / BITS_PER_WORD) +#define NUM_WORDS_ALIGN_128BIT(x) (ALIGN_128(x) / BITS_PER_WORD) +#define NUM_WORDS_ALIGN_256BIT(x) (ALIGN_256(x) / BITS_PER_WORD) + +#ifndef MAX +#define MAX(A, B) ((A) > (B) ? (A) : (B)) +#endif + +#ifndef MIN +#define MIN(A, B) ((A) < (B) ? (A) : (B)) +#endif + +#ifndef STRINGIFY +#define STRINGIFY(X) #X +#endif + +#ifndef ARRAY_SIZE +#define ELEM_SIZE(ARRAY) sizeof((ARRAY)[0]) +#define ARRAY_SIZE(ARRAY) (sizeof(ARRAY) / ELEM_SIZE(ARRAY)) +#endif + +#ifndef BITS_PER_BYTE +#define BITS_PER_BYTE (8) +#endif + +#ifndef BITS_PER_WORD +#define BITS_PER_WORD (sizeof(uint32_t) * BITS_PER_BYTE) +#endif + +#ifndef BITS_PER_DWORD +#define BITS_PER_DWORD (sizeof(uint64_t) * BITS_PER_BYTE) +#endif + +/* Helper macros to get/set/clear Nth bit in a uint8_t bitmap */ +#define BMP_GETBIT(BMP, N) \ + ((*((uint8_t *)(BMP) + ((N) / 8)) >> ((N) % 8)) & 0x1) +#define BMP_SETBIT(BMP, N) \ + do { \ + uint32_t n = (N); \ + *((uint8_t *)(BMP) + (n / 8)) |= (0x1U << (n % 8)); \ + } while (0) +#define BMP_CLRBIT(BMP, N) \ + do { \ + uint32_t n = (N); \ + *((uint8_t *)(BMP) + (n / 8)) &= \ + (uint8_t)(~(0x1U << (n % 8))); \ + } while (0) + +#ifndef STATIC_ASSERT +#ifndef NETXTREME_UT_SUPPORT +#define STATIC_ASSERT_TYPE_DEFINE(cntr) STATIC_ASSERT_TYPE##cntr +#define STATIC_ASSERT(x) \ + typedef int STATIC_ASSERT_TYPE_DEFINE(__COUNTER__)[(x) ? 1 : -1] +#else +#define STATIC_ASSERT_TYPE_DEFINE(cntr) +#define STATIC_ASSERT(x) +#endif +#endif + +#endif /* _SYS_UTIL_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/meson.build b/drivers/net/bnxt/hcapi/cfa_v3/meson.build new file mode 100644 index 0000000000..23ac33443c --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/meson.build @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Intel Corporation +# Copyright(c) 2020 Broadcom + +cflags_options = [ + '-DCFA_BLD_PRINT_OBJ=1', +] + +foreach option:cflags_options + if cc.has_argument(option) + cflags += option + endif +endforeach + +#Include the folder for headers +includes += include_directories('./') +includes += include_directories('./include') +includes += include_directories('./include/platform/dpdk/') +includes += include_directories('./bld/p70') +includes += include_directories('./bld/p70/host') +includes += include_directories('./bld/include') +includes += include_directories('./bld/include/host') +includes += include_directories('./bld/include/p70') +includes += include_directories('./mm/include') +includes += include_directories('./tim/include') +includes += include_directories('./tpm/include') + +#Add the source files +sources += files( + 'bld/host/cfa_bld_mpc.c', + 'bld/p70/cfa_bld_p70_mpc.c', + 'bld/p70/host/cfa_bld_p70_host_mpc_wrapper.c', + 'bld/p70/host/cfa_bld_p70_mpcops.c', + 'mm/cfa_mm.c', + 'tim/cfa_tim.c', + 'tpm/cfa_tpm.c') diff --git a/drivers/net/bnxt/hcapi/cfa_v3/mm/CMakeLists.txt b/drivers/net/bnxt/hcapi/cfa_v3/mm/CMakeLists.txt new file mode 100644 index 0000000000..6d4e746619 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/mm/CMakeLists.txt @@ -0,0 +1,42 @@ +# +# Copyright(c) 2021 Broadcom Limited, all rights reserved +# Contains proprietary and confidential information. +# +# This source file is the property of Broadcom Limited, and +# may not be copied or distributed in any isomorphic form without +# the prior written consent of Broadcom Limited. +# + +add_library(cfa-mm-lib-common INTERFACE) +target_include_directories(cfa-mm-lib-common INTERFACE include + ../include + ../../include) + +set (CFA_MM_SRCS cfa_mm.c) + +# Production version +add_library(cfa-mm-lib STATIC EXCLUDE_FROM_ALL ${CFA_MM_SRCS}) +set_property(TARGET cfa-mm-lib PROPERTY POSITION_INDEPENDENT_CODE 1) +target_link_libraries(cfa-mm-lib PUBLIC cfa-mm-lib-common nxt-platform nxt-arch) +target_include_directories(cfa-mm-lib PUBLIC ../include/platform/fw) + +# UT version +add_library(cfa-mm-lib-ut STATIC EXCLUDE_FROM_ALL ${CFA_MM_SRCS}) +set_property(TARGET cfa-mm-lib-ut PROPERTY POSITION_INDEPENDENT_CODE 1) +target_link_libraries(cfa-mm-lib-ut PUBLIC cfa-mm-lib-common nxt-ut nxt-platform nxt-arch nxt-env-ut) +target_include_directories(cfa-mm-lib-ut PUBLIC ../include/platform/ut) + +set(ignoreMe "${SKIP_MM_UT}") +if(NOT DEFINED SKIP_MM_UT) +add_subdirectory(ut) +endif() + +# Update Doxygen Path for mm api documentation +set(CFA_API_DOC_DIRS ${CFA_API_DOC_DIRS} + ${CMAKE_CURRENT_SOURCE_DIR}/include # Public api + CACHE INTERNAL "") + +# Update Doxygen Path for mm design documentation +set(CFA_DESIGN_DOC_DIRS ${CFA_DESIGN_DOC_DIRS} + ${CMAKE_CURRENT_SOURCE_DIR} # mm implementation + CACHE INTERNAL "") diff --git a/drivers/net/bnxt/hcapi/cfa_v3/mm/cfa_mm.c b/drivers/net/bnxt/hcapi/cfa_v3/mm/cfa_mm.c new file mode 100644 index 0000000000..149bea3401 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/mm/cfa_mm.c @@ -0,0 +1,624 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_mm.c + * + * @brief CFA Memory Manager apis + */ +#define COMP_ID CMM +#include +#include +#include +#include +#include +#include +#include "sys_util.h" +#include "cfa_util.h" +#include "cfa_types.h" +#include "cfa_mm.h" +#include "cfa_mm_priv.h" +#include "cfa_trace.h" + +static void cfa_mm_db_info(uint32_t max_records, uint16_t max_contig_records, + uint16_t *records_per_block, uint32_t *num_blocks, + uint16_t *num_lists, uint32_t *db_size) +{ + *records_per_block = + MAX(CFA_MM_MIN_RECORDS_PER_BLOCK, max_contig_records); + + *num_blocks = (max_records / (*records_per_block)); + + *num_lists = CFA_ALIGN_LN2(max_contig_records) + 1; + + *db_size = sizeof(struct cfa_mm) + + ((*num_blocks) * NUM_ALIGN_UNITS(*records_per_block, + CFA_MM_RECORDS_PER_BYTE)) + + ((*num_blocks) * sizeof(struct cfa_mm_blk)) + + ((*num_lists) * sizeof(struct cfa_mm_blk_list)); +} + +int cfa_mm_query(struct cfa_mm_query_parms *parms) +{ + uint32_t max_records, num_blocks; + uint16_t max_contig_records, num_lists, records_per_block; + + if (unlikely(parms == NULL)) { + CFA_LOG_ERR("parms = %p\n", parms); + return -EINVAL; + } + + max_records = parms->max_records; + max_contig_records = (uint16_t)parms->max_contig_records; + + if (unlikely(!(CFA_CHECK_BOUNDS(max_records, 1, CFA_MM_MAX_RECORDS) && + IS_POWER_2(max_contig_records) && + CFA_CHECK_BOUNDS(max_contig_records, 1, + CFA_MM_MAX_CONTIG_RECORDS)))) { + CFA_LOG_ERR("parms = %p, max_records = %d, " + "max_contig_records = %d\n", + parms, parms->max_records, + parms->max_contig_records); + return -EINVAL; + } + + cfa_mm_db_info(max_records, max_contig_records, &records_per_block, + &num_blocks, &num_lists, &parms->db_size); + + return 0; +} + +int cfa_mm_open(void *cmm, struct cfa_mm_open_parms *parms) +{ + uint32_t max_records, num_blocks, db_size, i; + uint16_t max_contig_records, num_lists, records_per_block; + struct cfa_mm *context = (struct cfa_mm *)cmm; + + if (unlikely(cmm == NULL || parms == NULL)) { + CFA_LOG_ERR("cmm = %p, parms = %p\n", cmm, parms); + return -EINVAL; + } + + max_records = parms->max_records; + max_contig_records = (uint16_t)parms->max_contig_records; + + if (unlikely(!(CFA_CHECK_BOUNDS(max_records, 1, CFA_MM_MAX_RECORDS) && + IS_POWER_2(max_contig_records) && + CFA_CHECK_BOUNDS(max_contig_records, 1, + CFA_MM_MAX_CONTIG_RECORDS)))) { + CFA_LOG_ERR("cmm = %p, parms = %p, db_mem_size = %d, " + "max_records = %d max_contig_records = %d\n", + cmm, parms, parms->db_mem_size, max_records, + max_contig_records); + return -EINVAL; + } + + cfa_mm_db_info(max_records, max_contig_records, &records_per_block, + &num_blocks, &num_lists, &db_size); + + if (unlikely(parms->db_mem_size < db_size)) { + CFA_LOG_ERR("cmm = %p, parms = %p, db_mem_size = %d, " + "max_records = %d max_contig_records = %d\n", + cmm, parms, parms->db_mem_size, max_records, + max_contig_records); + return -EINVAL; + } + + memset(context, 0, parms->db_mem_size); + + context->signature = CFA_MM_SIGNATURE; + context->max_records = max_records; + context->records_in_use = 0; + context->records_per_block = records_per_block; + context->max_contig_records = max_contig_records; + + context->blk_list_tbl = (struct cfa_mm_blk_list *)(context + 1); + context->blk_tbl = + (struct cfa_mm_blk *)(context->blk_list_tbl + num_lists); + context->blk_bmap_tbl = (uint8_t *)(context->blk_tbl + num_blocks); + + context->blk_list_tbl[0].first_blk_idx = 0; + context->blk_list_tbl[0].current_blk_idx = 0; + + for (i = 1; i < num_lists; i++) { + context->blk_list_tbl[i].first_blk_idx = CFA_MM_INVALID32; + context->blk_list_tbl[i].current_blk_idx = CFA_MM_INVALID32; + } + + for (i = 0; i < num_blocks; i++) { + context->blk_tbl[i].prev_blk_idx = i - 1; + context->blk_tbl[i].next_blk_idx = i + 1; + context->blk_tbl[i].num_free_records = records_per_block; + context->blk_tbl[i].first_free_record = 0; + context->blk_tbl[i].num_contig_records = 0; + } + + context->blk_tbl[num_blocks - 1].next_blk_idx = CFA_MM_INVALID32; + + memset(context->blk_bmap_tbl, 0, + num_blocks * NUM_ALIGN_UNITS(records_per_block, + CFA_MM_RECORDS_PER_BYTE)); + + return 0; +} + +int cfa_mm_close(void *cmm) +{ + uint32_t db_size, num_blocks; + uint16_t num_lists, records_per_block; + struct cfa_mm *context = (struct cfa_mm *)cmm; + + if (unlikely(cmm == NULL || context->signature != CFA_MM_SIGNATURE)) { + CFA_LOG_ERR("cmm = %p\n", cmm); + return -EINVAL; + } + + cfa_mm_db_info(context->max_records, context->max_contig_records, + &records_per_block, &num_blocks, &num_lists, &db_size); + + memset(cmm, 0, db_size); + + return 0; +} + +static uint32_t cfa_mm_blk_alloc(struct cfa_mm *context) +{ + uint32_t blk_idx; + struct cfa_mm_blk_list *free_list; + + free_list = context->blk_list_tbl; + + blk_idx = free_list->first_blk_idx; + + if (unlikely(blk_idx == CFA_MM_INVALID32)) { + CFA_LOG_ERR("Out of record blocks\n"); + return CFA_MM_INVALID32; + } + + free_list->first_blk_idx = + context->blk_tbl[free_list->first_blk_idx].next_blk_idx; + + free_list->current_blk_idx = free_list->first_blk_idx; + + if (free_list->first_blk_idx != CFA_MM_INVALID32) { + context->blk_tbl[free_list->first_blk_idx].prev_blk_idx = + CFA_MM_INVALID32; + } + + context->blk_tbl[blk_idx].prev_blk_idx = CFA_MM_INVALID32; + context->blk_tbl[blk_idx].next_blk_idx = CFA_MM_INVALID32; + + return blk_idx; +} + +static void cfa_mm_blk_free(struct cfa_mm *context, uint32_t blk_idx) +{ + struct cfa_mm_blk_list *free_list = context->blk_list_tbl; + + context->blk_tbl[blk_idx].prev_blk_idx = CFA_MM_INVALID32; + context->blk_tbl[blk_idx].next_blk_idx = free_list->first_blk_idx; + context->blk_tbl[blk_idx].num_free_records = context->records_per_block; + context->blk_tbl[blk_idx].first_free_record = 0; + context->blk_tbl[blk_idx].num_contig_records = 0; + + if (free_list->first_blk_idx != CFA_MM_INVALID32) { + context->blk_tbl[free_list->first_blk_idx].prev_blk_idx = + blk_idx; + } + + free_list->first_blk_idx = blk_idx; + free_list->current_blk_idx = blk_idx; +} + +static void cfa_mm_blk_insert(struct cfa_mm *context, + struct cfa_mm_blk_list *blk_list, + uint32_t blk_idx) +{ + if (blk_list->first_blk_idx == CFA_MM_INVALID32) { + blk_list->first_blk_idx = blk_idx; + blk_list->current_blk_idx = blk_idx; + } else { + struct cfa_mm_blk *blk_info = &context->blk_tbl[blk_idx]; + + blk_info->prev_blk_idx = CFA_MM_INVALID32; + blk_info->next_blk_idx = blk_list->first_blk_idx; + context->blk_tbl[blk_list->first_blk_idx].prev_blk_idx = + blk_idx; + blk_list->first_blk_idx = blk_idx; + blk_list->current_blk_idx = blk_idx; + } +} + +static void cfa_mm_blk_delete(struct cfa_mm *context, + struct cfa_mm_blk_list *blk_list, + uint32_t blk_idx) +{ + struct cfa_mm_blk *blk_info = &context->blk_tbl[blk_idx]; + + if (blk_list->first_blk_idx == CFA_MM_INVALID32) + return; + + if (blk_list->first_blk_idx == blk_idx) { + blk_list->first_blk_idx = blk_info->next_blk_idx; + if (blk_list->first_blk_idx != CFA_MM_INVALID32) { + context->blk_tbl[blk_list->first_blk_idx].prev_blk_idx = + CFA_MM_INVALID32; + } + if (blk_list->current_blk_idx == blk_idx) + blk_list->current_blk_idx = blk_list->first_blk_idx; + + return; + } + + if (blk_info->prev_blk_idx != CFA_MM_INVALID32) { + context->blk_tbl[blk_info->prev_blk_idx].next_blk_idx = + blk_info->next_blk_idx; + } + + if (blk_info->next_blk_idx != CFA_MM_INVALID32) { + context->blk_tbl[blk_info->next_blk_idx].prev_blk_idx = + blk_info->prev_blk_idx; + } + + if (blk_list->current_blk_idx == blk_idx) { + if (blk_info->next_blk_idx != CFA_MM_INVALID32) { + blk_list->current_blk_idx = blk_info->next_blk_idx; + } else { + if (blk_info->prev_blk_idx != CFA_MM_INVALID32) { + blk_list->current_blk_idx = + blk_info->prev_blk_idx; + } else { + blk_list->current_blk_idx = + blk_list->first_blk_idx; + } + } + } +} + +/* Returns true if the bit in the bitmap is set to 'val' else returns false */ +static bool cfa_mm_test_bit(uint8_t *bmap, uint16_t index, uint8_t val) +{ + uint8_t shift; + + bmap += index / CFA_MM_RECORDS_PER_BYTE; + index %= CFA_MM_RECORDS_PER_BYTE; + + shift = CFA_MM_RECORDS_PER_BYTE - (index + 1); + if (val) { + if ((*bmap >> shift) & 0x1) + return true; + } else { + if (!((*bmap >> shift) & 0x1)) + return true; + } + + return false; +} + +static int cfa_mm_test_and_set_bits(uint8_t *bmap, uint16_t start, + uint16_t count, uint8_t val) +{ + uint8_t mask[NUM_ALIGN_UNITS(CFA_MM_MAX_CONTIG_RECORDS, + CFA_MM_RECORDS_PER_BYTE) + + 1]; + uint16_t i, j, nbits; + + bmap += start / CFA_MM_RECORDS_PER_BYTE; + start %= CFA_MM_RECORDS_PER_BYTE; + + if ((start + count - 1) < CFA_MM_RECORDS_PER_BYTE) { + nbits = CFA_MM_RECORDS_PER_BYTE - (start + count); + mask[0] = (uint8_t)(((uint16_t)1 << count) - 1); + mask[0] <<= nbits; + if (val) { + if (*bmap & mask[0]) + return -EINVAL; + *bmap |= mask[0]; + } else { + if ((*bmap & mask[0]) != mask[0]) + return -EINVAL; + *bmap &= ~(mask[0]); + } + return 0; + } + + i = 0; + + nbits = CFA_MM_RECORDS_PER_BYTE - start; + mask[i++] = (uint8_t)(((uint16_t)1 << nbits) - 1); + + count -= nbits; + + while (count > CFA_MM_RECORDS_PER_BYTE && i < sizeof(mask)) { + count -= CFA_MM_RECORDS_PER_BYTE; + mask[i++] = 0xff; + } + + if (i < sizeof(mask)) { + mask[i] = (uint8_t)(((uint16_t)1 << count) - 1); + mask[i++] <<= (CFA_MM_RECORDS_PER_BYTE - count); + } else { + CFA_LOG_ERR("Mask array out of bounds; index:%d.\n", i); + return -ENOMEM; + } + + for (j = 0; j < i; j++) { + if (val) { + if (bmap[j] & mask[j]) + return -EINVAL; + } else { + if ((bmap[j] & mask[j]) != mask[j]) + return -EINVAL; + } + } + + for (j = 0; j < i; j++) { + if (val) + bmap[j] |= mask[j]; + else + bmap[j] &= ~(mask[j]); + } + + return 0; +} + +int cfa_mm_alloc(void *cmm, struct cfa_mm_alloc_parms *parms) +{ + int ret = 0; + uint16_t list_idx, num_records; + uint32_t i, cnt, blk_idx, record_idx; + struct cfa_mm_blk_list *blk_list; + struct cfa_mm_blk *blk_info; + uint8_t *blk_bmap; + struct cfa_mm *context = (struct cfa_mm *)cmm; + + if (unlikely(cmm == NULL || parms == NULL || + context->signature != CFA_MM_SIGNATURE)) { + CFA_LOG_ERR("cmm = %p parms = %p\n", cmm, parms); + return -EINVAL; + } + + if (unlikely(!(CFA_CHECK_BOUNDS(parms->num_contig_records, 1, + context->max_contig_records) && + IS_POWER_2(parms->num_contig_records)))) { + CFA_LOG_ERR("cmm = %p parms = %p num_records = %d\n", cmm, + parms, parms->num_contig_records); + return -EINVAL; + } + + list_idx = CFA_ALIGN_LN2(parms->num_contig_records); + + blk_list = context->blk_list_tbl + list_idx; + + num_records = 1 << (list_idx - 1); + + if (unlikely(context->records_in_use + num_records > context->max_records)) { + CFA_LOG_ERR("Requested number (%d) of records not available\n", + num_records); + ret = -ENOMEM; + goto cfa_mm_alloc_exit; + } + + if (blk_list->first_blk_idx == CFA_MM_INVALID32) { + blk_idx = cfa_mm_blk_alloc(context); + if (unlikely(blk_idx == CFA_MM_INVALID32)) { + ret = -ENOMEM; + goto cfa_mm_alloc_exit; + } + + cfa_mm_blk_insert(context, blk_list, blk_idx); + + blk_info = &context->blk_tbl[blk_idx]; + + blk_info->num_contig_records = num_records; + } else { + blk_idx = blk_list->current_blk_idx; + blk_info = &context->blk_tbl[blk_idx]; + } + + while (blk_info->num_free_records < num_records) { + if (blk_info->next_blk_idx == CFA_MM_INVALID32 || !blk_info->num_free_records) { + blk_idx = cfa_mm_blk_alloc(context); + if (unlikely(blk_idx == CFA_MM_INVALID32)) { + ret = -ENOMEM; + goto cfa_mm_alloc_exit; + } + + cfa_mm_blk_insert(context, blk_list, blk_idx); + + blk_info = &context->blk_tbl[blk_idx]; + + blk_info->num_contig_records = num_records; + } else { + blk_idx = blk_info->next_blk_idx; + blk_info = &context->blk_tbl[blk_idx]; + + blk_list->current_blk_idx = blk_idx; + } + } + + blk_bmap = context->blk_bmap_tbl + blk_idx * + context->records_per_block / + CFA_MM_RECORDS_PER_BYTE; + + record_idx = blk_info->first_free_record; + + if (unlikely(cfa_mm_test_and_set_bits(blk_bmap, record_idx, num_records, 1))) { + CFA_LOG_ERR("Records are already allocated. record_idx = %d, " + "num_records = %d\n", + record_idx, num_records); + return -EINVAL; + } + + parms->record_offset = + (blk_idx * context->records_per_block) + record_idx; + + parms->num_contig_records = num_records; + + blk_info->num_free_records -= num_records; + + if (!blk_info->num_free_records) { + blk_info->first_free_record = context->records_per_block; + } else { + cnt = NUM_ALIGN_UNITS(context->records_per_block, + CFA_MM_RECORDS_PER_BYTE); + + for (i = (record_idx + num_records) / CFA_MM_RECORDS_PER_BYTE; + i < cnt; i++) { + if (blk_bmap[i] != 0xff) { + uint8_t bmap = blk_bmap[i]; + blk_info->first_free_record = + i * CFA_MM_RECORDS_PER_BYTE; + while (bmap & 0x80) { + bmap <<= 1; + blk_info->first_free_record++; + } + break; + } + } + } + + context->records_in_use += num_records; + + ret = 0; + +cfa_mm_alloc_exit: + + parms->used_count = context->records_in_use; + + parms->all_used = (context->records_in_use >= context->max_records); + + return ret; +} + +int cfa_mm_free(void *cmm, struct cfa_mm_free_parms *parms) +{ + uint16_t list_idx, num_records; + uint32_t blk_idx, record_idx; + struct cfa_mm_blk *blk_info; + struct cfa_mm_blk_list *blk_list; + uint8_t *blk_bmap; + struct cfa_mm *context = (struct cfa_mm *)cmm; + + if (unlikely(cmm == NULL || parms == NULL || + context->signature != CFA_MM_SIGNATURE)) { + CFA_LOG_ERR("cmm = %p parms = %p\n", cmm, parms); + return -EINVAL; + } + + if (unlikely(!(parms->record_offset < context->max_records && + CFA_CHECK_BOUNDS(parms->num_contig_records, 1, + context->max_contig_records) && + IS_POWER_2(parms->num_contig_records)))) { + CFA_LOG_ERR("cmm = %p, parms = %p, record_offset = %d, " + "num_contig_records = %d\n", + cmm, parms, parms->record_offset, + parms->num_contig_records); + return -EINVAL; + } + + record_idx = parms->record_offset % context->records_per_block; + blk_idx = parms->record_offset / context->records_per_block; + + list_idx = CFA_ALIGN_LN2(parms->num_contig_records); + + blk_list = &context->blk_list_tbl[list_idx]; + + if (unlikely(blk_list->first_blk_idx == CFA_MM_INVALID32)) { + CFA_LOG_ERR("Records were not allocated\n"); + return -EINVAL; + } + + num_records = 1 << (list_idx - 1); + + blk_info = &context->blk_tbl[blk_idx]; + + if (unlikely(blk_info->num_contig_records != num_records)) { + CFA_LOG_ERR("num_contig_records (%d) doesn't match the " + "num_contig_records (%d) of the allocation\n", + num_records, blk_info->num_contig_records); + return -EINVAL; + } + + blk_bmap = context->blk_bmap_tbl + blk_idx * + context->records_per_block / + CFA_MM_RECORDS_PER_BYTE; + + if (unlikely(cfa_mm_test_and_set_bits(blk_bmap, record_idx, num_records, 0))) { + CFA_LOG_ERR("Records are not allocated. record_idx = %d, " + "num_records = %d\n", + record_idx, num_records); + return -EINVAL; + } + + blk_info->num_free_records += num_records; + + if (blk_info->num_free_records >= context->records_per_block) { + cfa_mm_blk_delete(context, blk_list, blk_idx); + cfa_mm_blk_free(context, blk_idx); + } else { + if (blk_info->num_free_records == num_records) { + cfa_mm_blk_delete(context, blk_list, blk_idx); + cfa_mm_blk_insert(context, blk_list, blk_idx); + blk_info->first_free_record = record_idx; + } else { + if (record_idx < blk_info->first_free_record) + blk_info->first_free_record = record_idx; + } + } + + context->records_in_use -= num_records; + + parms->used_count = context->records_in_use; + + return 0; +} + +int cfa_mm_entry_size_get(void *cmm, uint32_t entry_id, uint8_t *size) +{ + uint8_t *blk_bmap; + struct cfa_mm_blk *blk_info; + struct cfa_mm *context = (struct cfa_mm *)cmm; + uint32_t blk_idx, record_idx; + + if (unlikely(cmm == NULL || size == NULL || + context->signature != CFA_MM_SIGNATURE)) { + CFA_LOG_ERR("%s: cmm = %p size = %p\n", __func__, cmm, size); + return -EINVAL; + } + + if (unlikely(!(entry_id < context->max_records))) { + CFA_LOG_ERR("cmm = %p, entry_id = %d\n", cmm, entry_id); + return -EINVAL; + } + + blk_idx = entry_id / context->records_per_block; + blk_info = &context->blk_tbl[blk_idx]; + record_idx = entry_id % context->records_per_block; + + /* + * Block is unused if num contig records is 0 and + * there are no allocated entries in the block + */ + if (unlikely(blk_info->num_contig_records == 0)) + return -ENOENT; + + /* + * Check the entry is indeed allocated. Suffices to check if + * the first bit in the bitmap is set. + */ + blk_bmap = context->blk_bmap_tbl + blk_idx * + context->records_per_block / + CFA_MM_RECORDS_PER_BYTE; + + if (cfa_mm_test_bit(blk_bmap, record_idx, 1)) { + *size = blk_info->num_contig_records; + return 0; + } else { + return -ENOENT; + } +} diff --git a/drivers/net/bnxt/hcapi/cfa_v3/mm/cfa_mm_priv.h b/drivers/net/bnxt/hcapi/cfa_v3/mm/cfa_mm_priv.h new file mode 100644 index 0000000000..c6fe2fb8a8 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/mm/cfa_mm_priv.h @@ -0,0 +1,92 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_mm_priv.h + * + * @brief CFA Memory Manager private API definitions + */ + +#ifndef _CFA_MM_PRIV_H_ +#define _CFA_MM_PRIV_H_ + +#define CFA_MM_SIGNATURE 0xCFA66C89 + +#define CFA_MM_INVALID8 0xFF +#define CFA_MM_INVALID16 0xFFFF +#define CFA_MM_INVALID32 0xFFFFFFFF +#define CFA_MM_INVALID64 0xFFFFFFFFFFFFFFFFULL + +#define CFA_MM_MAX_RECORDS (64 * 1024 * 1024) +#define CFA_MM_MAX_CONTIG_RECORDS 8 +#define CFA_MM_RECORDS_PER_BYTE 8 +#define CFA_MM_MIN_RECORDS_PER_BLOCK 8 + +/** + * CFA Records block + * + * Structure used to store the CFA record block info + */ +struct cfa_mm_blk { + /* Index of the previous block in the list */ + uint32_t prev_blk_idx; + /* Index of the next block in the list */ + uint32_t next_blk_idx; + /* Number of free records available in the block */ + uint16_t num_free_records; + /* Location of first free record in the block */ + uint16_t first_free_record; + /* Number of contiguous records */ + uint16_t num_contig_records; + /* Reserved for future use */ + uint16_t reserved; +}; + +/** + * CFA Record block list + * + * Structure used to store CFA Record block list info + */ +struct cfa_mm_blk_list { + /* Index of the first block in the list */ + uint32_t first_blk_idx; + /* Index of the current block having free records */ + uint32_t current_blk_idx; +}; + +/** + * CFA memory manager Database + * + * Structure used to store CFA memory manager database info + */ +struct cfa_mm { + /* Signature of the CFA Memory Manager Database */ + uint32_t signature; + /* Maximum number of CFA Records */ + uint32_t max_records; + /* Number of CFA Records in use*/ + uint32_t records_in_use; + /* Number of Records per block */ + uint16_t records_per_block; + /* Maximum number of contiguous records */ + uint16_t max_contig_records; + /** + * Block list table stores the info of lists of blocks + * for various numbers of contiguous records + */ + struct cfa_mm_blk_list *blk_list_tbl; + /** + * Block table stores the info about the blocks of CFA Records + */ + struct cfa_mm_blk *blk_tbl; + /** + * Block bitmap table stores bit maps for the blocks of CFA Records + */ + uint8_t *blk_bmap_tbl; +}; + +#endif /* _CFA_MM_PRIV_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/mm/include/cfa_mm.h b/drivers/net/bnxt/hcapi/cfa_v3/mm/include/cfa_mm.h new file mode 100644 index 0000000000..bd71fa1cf8 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/mm/include/cfa_mm.h @@ -0,0 +1,173 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_mm.h + * + * @brief CFA Memory Manager Public API definitions + */ +#ifndef _CFA_MM_H_ +#define _CFA_MM_H_ + +/** + * @addtogroup CFA_MM CFA Memory Manager + * \ingroup CFA_V3 + * A CFA memory manager (Document Control:DCSG00988445) is a object instance + * within the CFA service module that is responsible for managing CFA related + * memories such as Thor2 CFA backings stores, Thor CFA action SRAM, etc. It + * is designed to operate in firmware or as part of the host Truflow stack. + * Each manager instance consists of a number of bank databases with each + * database managing a pool of CFA memory. + * + * @{ + */ + +/** CFA Memory Manager database query params structure + * + * Structure of database params + */ +struct cfa_mm_query_parms { + /** [in] Maximum number of CFA records */ + uint32_t max_records; + /** [in] Max contiguous CFA records per Alloc (Must be a power of 2). */ + uint32_t max_contig_records; + /** [out] Memory required for Database */ + uint32_t db_size; +}; + +/** CFA Memory Manager open parameters + * + * Structure to store CFA MM open parameters + */ +struct cfa_mm_open_parms { + /** [in] Size of memory allocated for CFA MM database */ + uint32_t db_mem_size; + /** [in] Max number of CFA records */ + uint32_t max_records; + /** [in] Maximum number of contiguous CFA records */ + uint16_t max_contig_records; +}; + +/** CFA Memory Manager record alloc parameters + * + * Structure to contain parameters for record alloc + */ +struct cfa_mm_alloc_parms { + /** [in] Number of contiguous CFA records */ + uint32_t num_contig_records; + /** [out] Offset of the first of the records allocated */ + uint32_t record_offset; + /** [out] Total number of records already allocated */ + uint32_t used_count; + /** [out] Flag to indicate if all the records are allocated */ + uint32_t all_used; +}; + +/** CFA Memory Manager record free parameters + * + * Structure to contain parameters for record free + */ +struct cfa_mm_free_parms { + /** [in] Offset of the first of the records allocated */ + uint32_t record_offset; + /** [in] Number of contiguous CFA records */ + uint32_t num_contig_records; + /** [out] Total number of records already allocated */ + uint32_t used_count; +}; + +/** CFA Memory Manager query API + * + * This API returns the size of memory required for internal data structures to + * manage the pool of CFA Records with given parameters. + * + * @param[in,out] parms + * CFA Memory manager query data base parameters. + * + * @return + * Returns 0 if the query is successful, Error Code otherwise + */ +int cfa_mm_query(struct cfa_mm_query_parms *parms); + +/** CFA Memory Manager open API + * + * This API initializes the CFA Memory Manager database + * + * @param[in] cmm + * Pointer to the memory used for the CFA Mmeory Manager Database + * + * @param[in] parms + * CFA Memory manager data base parameters. + * + * @return + * Returns 0 if the initialization is successful, Error Code otherwise + */ +int cfa_mm_open(void *cmm, struct cfa_mm_open_parms *parms); + +/** CFA Memory Manager close API + * + * This API frees the CFA Memory NManager database + * + * @param[in] cmm + * Pointer to the database memory for the record pool + * + * @return + * Returns 0 if the initialization is successful, Error Code otherwise + */ +int cfa_mm_close(void *cmm); + +/** CFA Memory Manager Allocate CFA Records API + * + * This API allocates the request number of contiguous CFA Records + * + * @param[in] cmm + * Pointer to the database from which to allocate CFA Records + * + * @param[in,out] parms + * CFA MM alloc records parameters + * + * @return + * Returns 0 if the initialization is successful, Error Code otherwise + */ +int cfa_mm_alloc(void *cmm, struct cfa_mm_alloc_parms *parms); + +/** CFA MemoryManager Free CFA Records API + * + * This API frees the requested number of contiguous CFA Records + * + * @param[in] cmm + * Pointer to the database from which to free CFA Records + * + * @param[in,out] parms + * CFA MM free records parameters + * + * @return + * Returns 0 if the initialization is successful, Error Code otherwise + */ +int cfa_mm_free(void *cmm, struct cfa_mm_free_parms *parms); + +/** CFA Memory Manager Get Entry Size API + * + * This API retrieves the size of an allocated CMM entry. + * + * @param[in] cmm + * Pointer to the database from which to allocate CFA Records + * + * @param[in] entry_id + * Index of the allocated entry. + * + * @param[out] size + * Number of contiguous records in the entry. + * + * @return + * Returns 0 if successful, negative errno otherwise + */ +int cfa_mm_entry_size_get(void *cmm, uint32_t entry_id, uint8_t *size); + +/**@}*/ + +#endif /* _CFA_MM_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/tim/CMakeLists.txt b/drivers/net/bnxt/hcapi/cfa_v3/tim/CMakeLists.txt new file mode 100644 index 0000000000..518004c592 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/tim/CMakeLists.txt @@ -0,0 +1,43 @@ +# +# Copyright(c) 2021 Broadcom Limited, all rights reserved +# Contains proprietary and confidential information. +# +# This source file is the property of Broadcom Limited, and +# may not be copied or distributed in any isomorphic form without +# the prior written consent of Broadcom Limited. +# + +add_library(cfa-tim-lib-common INTERFACE) +target_include_directories(cfa-tim-lib-common INTERFACE include + ../include + ../../include + ../../../tf_core) + +set (CFA_TIM_SRCS cfa_tim.c) + +# Production version +add_library(cfa-tim-lib STATIC EXCLUDE_FROM_ALL ${CFA_TIM_SRCS}) +set_property(TARGET cfa-tim-lib PROPERTY POSITION_INDEPENDENT_CODE 1) +target_link_libraries(cfa-tim-lib PUBLIC cfa-tim-lib-common nxt-platform nxt-arch) +target_include_directories(cfa-tim-lib PUBLIC ../include/platform/fw) + +# UT version +add_library(cfa-tim-lib-ut STATIC EXCLUDE_FROM_ALL ${CFA_TIM_SRCS}) +set_property(TARGET cfa-tim-lib-ut PROPERTY POSITION_INDEPENDENT_CODE 1) +target_link_libraries(cfa-tim-lib-ut PUBLIC cfa-tim-lib-common nxt-ut nxt-platform nxt-arch nxt-env-ut) +target_include_directories(cfa-tim-lib-ut PUBLIC ../include/platform/ut) + +set(ignoreMe "${SKIP_TIM_UT}") +if(NOT DEFINED SKIP_TIM_UT) +add_subdirectory(ut) +endif() + +# Update Doxygen Path for tim api documentation +set(CFA_API_DOC_DIRS ${CFA_API_DOC_DIRS} + ${CMAKE_CURRENT_SOURCE_DIR}/include # Public api + CACHE INTERNAL "") + +# Update Doxygen Path for tim design documentation +set(CFA_DESIGN_DOC_DIRS ${CFA_DESIGN_DOC_DIRS} + ${CMAKE_CURRENT_SOURCE_DIR} # tim implementation + CACHE INTERNAL "") diff --git a/drivers/net/bnxt/hcapi/cfa_v3/tim/cfa_tim.c b/drivers/net/bnxt/hcapi/cfa_v3/tim/cfa_tim.c new file mode 100644 index 0000000000..0c62eddf6c --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/tim/cfa_tim.c @@ -0,0 +1,124 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_tim.c + * + * @brief CFA Table Scope Instance Manager apis + */ +#define COMP_ID TIM + +#include +#include +#include +#include +#include "cfa_util.h" +#include "cfa_types.h" +#include "cfa_tim.h" +#include "cfa_tim_priv.h" +#include "cfa_trace.h" + +static uint32_t cfa_tim_size(uint8_t max_tbl_scopes, uint8_t max_regions) +{ + return (sizeof(struct cfa_tim) + + (max_tbl_scopes * max_regions * CFA_DIR_MAX) * sizeof(void *)); +} + +int cfa_tim_query(uint8_t max_tbl_scopes, uint8_t max_regions, + uint32_t *tim_db_size) +{ + if (tim_db_size == NULL) { + CFA_LOG_ERR("tim_db_size = %p\n", tim_db_size); + return -EINVAL; + } + + *tim_db_size = cfa_tim_size(max_tbl_scopes, max_regions); + + return 0; +} + +int cfa_tim_open(void *tim, uint32_t tim_db_size, uint8_t max_tbl_scopes, + uint8_t max_regions) +{ + struct cfa_tim *ctx = (struct cfa_tim *)tim; + + if (tim == NULL) { + CFA_LOG_ERR("tim = %p\n", tim); + return -EINVAL; + } + if (tim_db_size < cfa_tim_size(max_tbl_scopes, max_regions)) { + CFA_LOG_ERR("max_tbl_scopes = %d, max_regions = %d\n", + max_tbl_scopes, max_regions); + return -EINVAL; + } + + memset(tim, 0, tim_db_size); + + ctx->signature = CFA_TIM_SIGNATURE; + ctx->max_tsid = max_tbl_scopes; + ctx->max_regions = max_regions; + ctx->tpm_tbl = (void **)(ctx + 1); + + return 0; +} + +int cfa_tim_close(void *tim) +{ + struct cfa_tim *ctx = (struct cfa_tim *)tim; + + if (tim == NULL || ctx->signature != CFA_TIM_SIGNATURE) { + CFA_LOG_ERR("tim = %p\n", tim); + return -EINVAL; + } + + memset(tim, 0, cfa_tim_size(ctx->max_tsid, ctx->max_regions)); + + return 0; +} + +int cfa_tim_tpm_inst_set(void *tim, uint8_t tsid, uint8_t region_id, + int dir, void *tpm_inst) +{ + struct cfa_tim *ctx = (struct cfa_tim *)tim; + + if (tim == NULL || ctx->signature != CFA_TIM_SIGNATURE) { + CFA_LOG_ERR("tim = %p\n", tim); + return -EINVAL; + } + + if (!(CFA_CHECK_UPPER_BOUNDS(tsid, ctx->max_tsid - 1) && + CFA_CHECK_UPPER_BOUNDS(region_id, ctx->max_regions - 1))) { + CFA_LOG_ERR("tsid = %d, region_id = %d\n", tsid, region_id); + return -EINVAL; + } + + ctx->tpm_tbl[CFA_TIM_MAKE_INDEX(tsid, region_id, dir, ctx->max_regions, ctx->max_tsid)] = + tpm_inst; + return 0; +} + +int cfa_tim_tpm_inst_get(void *tim, uint8_t tsid, uint8_t region_id, + int dir, void **tpm_inst) +{ + struct cfa_tim *ctx = (struct cfa_tim *)tim; + + if (tim == NULL || tpm_inst == NULL || + ctx->signature != CFA_TIM_SIGNATURE) { + CFA_LOG_ERR("tim = %p\n", tim); + return -EINVAL; + } + + if (!(CFA_CHECK_UPPER_BOUNDS(tsid, ctx->max_tsid - 1) && + CFA_CHECK_UPPER_BOUNDS(region_id, ctx->max_regions - 1))) { + CFA_LOG_ERR("tsid = %d, region_id = %d\n", tsid, region_id); + return -EINVAL; + } + + *tpm_inst = ctx->tpm_tbl[CFA_TIM_MAKE_INDEX(tsid, region_id, dir, + ctx->max_regions, ctx->max_tsid)]; + return 0; +} diff --git a/drivers/net/bnxt/hcapi/cfa_v3/tim/cfa_tim_priv.h b/drivers/net/bnxt/hcapi/cfa_v3/tim/cfa_tim_priv.h new file mode 100644 index 0000000000..e4fb796f85 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/tim/cfa_tim_priv.h @@ -0,0 +1,85 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_tim.h + * + * @brief CFA Table Scope Instance Manager private API definitions + */ + +#ifndef _CFA_TIM_PRIV_H_ +#define _CFA_TIM_PRIV_H_ + +#include + +#define CFA_TIM_SIGNATURE 0xCFACEE11 + +/* + * + * Total index space is (MaxDir * MaxRegion * MaxTableScope), the + * following macro satisfies that: + * + * (Dir# * (MaxRegionSpace + MaxTableScope)) + + * (TableScope# * (MaxRegionSpace)) + + * Region# + * + * Examples: + * + * MaxD MaxR MaxT Total + * 2 1 1 2 + * + * Dir Region TableScope Index + * 0 0 0 0 + * 1 0 0 1 + * + * MaxD MaxR MaxT Total + * 2 2 1 4 + * + * Dir Region TableScope Index + * 0 0 0 0 + * 1 0 0 2 + * 0 1 0 1 + * 1 1 0 3 + * + * MaxD MaxR MaxT Total + * 2 2 3 12 + * + * Dir Region TableScope Index + * 0 0 0 0 + * 1 0 0 6 + * 0 1 0 1 + * 1 1 0 7 + * 0 0 1 2 + * 1 0 1 8 + * 0 1 1 3 + * 1 1 1 9 + * 0 0 2 4 + * 1 0 2 10 + * 0 1 2 5 + * 1 1 2 11 + * + */ +#define CFA_TIM_MAKE_INDEX(tsid, region, dir, max_regions, max_tsid) \ + (((dir) * (max_regions) * (max_tsid)) + ((tsid) * (max_regions)) + (region)) + +/** + * CFA Table Scope Instance Manager Database + * + * Structure used to store CFA Table Scope Instance Manager database info + */ +struct cfa_tim { + /* Signature of the CFA Table Scope Instance Manager Database */ + uint32_t signature; + /* Maximum number of Table Scope Ids */ + uint8_t max_tsid; + /* Maximum number of regions per Table Scope */ + uint8_t max_regions; + /* TPM instance table */ + void **tpm_tbl; +}; + +#endif /* _CFA_TIM_PRIV_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/tim/include/cfa_tim.h b/drivers/net/bnxt/hcapi/cfa_v3/tim/include/cfa_tim.h new file mode 100644 index 0000000000..35151363b4 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/tim/include/cfa_tim.h @@ -0,0 +1,133 @@ +/**************************************************************************** + * Copyright(c) 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_tim.h + * + * @brief CFA Table Scope Instance Manager Public API definitions + */ +#ifndef _CFA_TIM_H_ +#define _CFA_TIM_H_ + +/** + * @addtogroup CFA_TIM CFA Table Scope Instance Manager + * \ingroup CFA_V3 + * The purpose of the CFA Table Scope Instance manager is to provide a + * centralized management of Table Scope Pool Manager instances. Each instance + * is identified by the Table Scope id and Region id. A caller can set and + * retrieve the instance handle using the Table Scope Id and Region Id. + * @{ + */ + +/** CFA Table Scope Instance Manager query DB size API + * + * This API returns the size of memory required for internal data structures to + * manage the table scope instances. + * + * @param[in] max_tbl_scopes + * Maximum number of table scope ids available to manage. + * + * @param[in] max_regions + * Maximum number of regions per table scope. + * + * @param[out] tim_db_size + * Pointer to 32 bit integer to return the amount of memory required. + * + * @return + * Returns 0 if successful, Error Code otherwise + */ +int cfa_tim_query(uint8_t max_tbl_scopes, uint8_t max_regions, + uint32_t *tim_db_size); + +/** CFA Table Scope Instance Manager open API + * + * This API initializes the CFA Table Scope Instance Manager database + * + * @param[in] tim + * Pointer to the memory used for the CFA Table Scope Instance Manager + * Database. + * + * @param[in] tim_db_size + * The size of memory block pointed to by tim parameter. + * + * @param[in] max_tbl_scopes + * Maximum number of table scope ids available to manage. + * + * @param[in] max_regions + * Maximum number of regions per table scope. + * + * @return + * Returns 0 if successful, Error Code otherwise + */ +int cfa_tim_open(void *tim, uint32_t tim_db_size, uint8_t max_tbl_scopes, + uint8_t max_regions); + +/** CFA Table Scope Instance Manager close API + * + * This API resets the CFA Table Scope Instance Manager database + * + * @param[in] tim + * Pointer to the database memory for the Table Scope Instance Manager. + * + * @return + * Returns 0 if successful, Error Code otherwise + */ +int cfa_tim_close(void *tim); + +/** CFA Table Scope Instance Manager set instance API + * + * This API sets the TPM instance handle into TIM. + * + * @param[in] tim + * Pointer to the database memory for the Table Scope Instance Manager. + * + * @param[in] tsid + * The Table scope id of the instance. + * + * @param[in] region_id + * The region id of the instance. + * + * @param[in] dir + * The direction of the instance. + * + * @param[in] tpm_inst + * The handle of TPM instance. + * + * @return + * Returns 0 if successful, Error Code otherwise + */ +int cfa_tim_tpm_inst_set(void *tim, uint8_t tsid, uint8_t region_id, + int dir, void *tpm_inst); + +/** CFA Table Scope Instance Manager get instance API + * + * This API gets the TPM instance handle from TIM. + * + * @param[in] tim + * Pointer to the database memory for the Table Scope Instance Manager. + * + * @param[in] tsid + * The Table scope id of the instance. + * + * @param[in] region_id + * The region id of the instance. + * + * @param[in] dir + * The direction of the instance. + * + * @param[out] tpm_inst + * Pointer to memory location to return the handle of TPM instance. + * + * @return + * Returns 0 if successful, Error Code otherwise + */ +int cfa_tim_tpm_inst_get(void *tim, uint8_t tsid, uint8_t region_id, + int dir, void **tpm_inst); + +/**@}*/ + +#endif /* _CFA_TIM_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/tpm/CMakeLists.txt b/drivers/net/bnxt/hcapi/cfa_v3/tpm/CMakeLists.txt new file mode 100644 index 0000000000..0af86b8432 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/tpm/CMakeLists.txt @@ -0,0 +1,44 @@ +# +# Copyright(c) 2021 Broadcom Limited, all rights reserved +# Contains proprietary and confidential information. +# +# This source file is the property of Broadcom Limited, and +# may not be copied or distributed in any isomorphic form without +# the prior written consent of Broadcom Limited. +# + +add_library(cfa-tpm-lib-common INTERFACE) +target_include_directories(cfa-tpm-lib-common INTERFACE include + ../include + ../../include + ../../generic-common/include + ../../../tf_core) + +set (CFA_TPM_SRCS cfa_tpm.c) + +# Production version +add_library(cfa-tpm-lib STATIC EXCLUDE_FROM_ALL ${CFA_TPM_SRCS}) +set_property(TARGET cfa-tpm-lib PROPERTY POSITION_INDEPENDENT_CODE 1) +target_link_libraries(cfa-tpm-lib PUBLIC cfa-tpm-lib-common nxt-platform nxt-arch) +target_include_directories(cfa-tpm-lib PUBLIC ../include/platform/fw) + +# UT version +add_library(cfa-tpm-lib-ut STATIC EXCLUDE_FROM_ALL ${CFA_TPM_SRCS}) +set_property(TARGET cfa-tpm-lib-ut PROPERTY POSITION_INDEPENDENT_CODE 1) +target_link_libraries(cfa-tpm-lib-ut PUBLIC cfa-tpm-lib-common nxt-ut nxt-platform nxt-arch nxt-env-ut) +target_include_directories(cfa-tpm-lib-ut PUBLIC ../include/platform/ut) + +set(ignoreMe "${SKIP_TPM_UT}") +if(NOT DEFINED SKIP_TPM_UT) +add_subdirectory(ut) +endif() + +# Update Doxygen Path for tpm api documentation +set(CFA_API_DOC_DIRS ${CFA_API_DOC_DIRS} + ${CMAKE_CURRENT_SOURCE_DIR}/include # Public api + CACHE INTERNAL "") + +# Update Doxygen Path for tpm design documentation +set(CFA_DESIGN_DOC_DIRS ${CFA_DESIGN_DOC_DIRS} + ${CMAKE_CURRENT_SOURCE_DIR} # tpm implementation + CACHE INTERNAL "") diff --git a/drivers/net/bnxt/hcapi/cfa_v3/tpm/cfa_tpm.c b/drivers/net/bnxt/hcapi/cfa_v3/tpm/cfa_tpm.c new file mode 100644 index 0000000000..8b34e1939f --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/tpm/cfa_tpm.c @@ -0,0 +1,273 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_tpm.c + * + * @brief CFA Table Scope Pool Manager apis + */ +#define COMP_ID TPM + +#include +#include +#include +#include +#include "cfa_util.h" +#include "cfa_tpm_priv.h" +#include "cfa_tpm.h" +#include "cfa_trace.h" + +static uint32_t cfa_tpm_size(uint16_t max_pools) +{ + return (sizeof(struct cfa_tpm) + BITALLOC_SIZEOF(max_pools) + + max_pools * sizeof(uint16_t)); +} + +int cfa_tpm_query(uint16_t max_pools, uint32_t *tpm_db_size) +{ + if (tpm_db_size == NULL) { + CFA_LOG_ERR("tpm_db_size = %p\n", tpm_db_size); + return -EINVAL; + } + + if (!CFA_CHECK_BOUNDS(max_pools, CFA_TPM_MIN_POOLS, + CFA_TPM_MAX_POOLS)) { + CFA_LOG_ERR("max_pools = %d\n", max_pools); + return -EINVAL; + } + + *tpm_db_size = cfa_tpm_size(max_pools); + + return 0; +} + +int cfa_tpm_open(void *tpm, uint32_t tpm_db_size, uint16_t max_pools) +{ + int i; + struct cfa_tpm *ctx = (struct cfa_tpm *)tpm; + + if (tpm == NULL) { + CFA_LOG_ERR("tpm = %p\n", tpm); + return -EINVAL; + } + + if (!(CFA_CHECK_BOUNDS(max_pools, CFA_TPM_MIN_POOLS, + CFA_TPM_MAX_POOLS) && + tpm_db_size >= cfa_tpm_size(max_pools))) { + CFA_LOG_ERR("max_pools = %d tpm_db_size = %d\n", max_pools, + tpm_db_size); + return -EINVAL; + } + + memset(tpm, 0, tpm_db_size); + + ctx->signature = CFA_TPM_SIGNATURE; + ctx->max_pools = max_pools; + ctx->pool_ba = (struct bitalloc *)(ctx + 1); + ctx->fid_tbl = (uint16_t *)((uint8_t *)ctx->pool_ba + + BITALLOC_SIZEOF(max_pools)); + + if (ba_init(ctx->pool_ba, max_pools, true)) + return -EINVAL; + + for (i = 0; i < max_pools; i++) + ctx->fid_tbl[i] = CFA_INVALID_FID; + + return 0; +} + +int cfa_tpm_close(void *tpm) +{ + struct cfa_tpm *ctx = (struct cfa_tpm *)tpm; + + if (tpm == NULL || ctx->signature != CFA_TPM_SIGNATURE) { + CFA_LOG_ERR("tpm = %p\n", tpm); + return -EINVAL; + } + + memset(tpm, 0, cfa_tpm_size(ctx->max_pools)); + + return 0; +} + +int cfa_tpm_alloc(void *tpm, uint16_t *pool_id) +{ + int rc; + struct cfa_tpm *ctx = (struct cfa_tpm *)tpm; + + if (tpm == NULL || pool_id == NULL || + ctx->signature != CFA_TPM_SIGNATURE) { + CFA_LOG_ERR("tpm = %p, pool_id = %p\n", tpm, pool_id); + return -EINVAL; + } + + rc = ba_alloc(ctx->pool_ba); + + if (rc < 0) + return -ENOMEM; + + *pool_id = rc; + + ctx->fid_tbl[rc] = CFA_INVALID_FID; + + return 0; +} + +int cfa_tpm_free(void *tpm, uint16_t pool_id) +{ + struct cfa_tpm *ctx = (struct cfa_tpm *)tpm; + + if (tpm == NULL || ctx->signature != CFA_TPM_SIGNATURE) { + CFA_LOG_ERR("tpm = %p, pool_id = %d\n", tpm, pool_id); + return -EINVAL; + } + + if (ctx->fid_tbl[pool_id] != CFA_INVALID_FID) { + CFA_LOG_ERR("A function (%d) is still using the pool (%d)\n", + ctx->fid_tbl[pool_id], pool_id); + return -EINVAL; + } + + return ba_free(ctx->pool_ba, pool_id); +} + +int cfa_tpm_fid_add(void *tpm, uint16_t pool_id, uint16_t fid) +{ + struct cfa_tpm *ctx = (struct cfa_tpm *)tpm; + + if (tpm == NULL || ctx->signature != CFA_TPM_SIGNATURE) { + CFA_LOG_ERR("tpm = %p, pool_id = %d\n", tpm, pool_id); + return -EINVAL; + } + + if (!ba_inuse(ctx->pool_ba, pool_id)) { + CFA_LOG_ERR("Pool id (%d) was not allocated\n", pool_id); + return -EINVAL; + } + + if (ctx->fid_tbl[pool_id] != CFA_INVALID_FID && + ctx->fid_tbl[pool_id] != fid) { + CFA_LOG_ERR("A function id %d was already set to the pool %d\n", + fid, ctx->fid_tbl[pool_id]); + return -EINVAL; + } + + ctx->fid_tbl[pool_id] = fid; + + return 0; +} + +int cfa_tpm_fid_rem(void *tpm, uint16_t pool_id, uint16_t fid) +{ + struct cfa_tpm *ctx = (struct cfa_tpm *)tpm; + + if (tpm == NULL || ctx->signature != CFA_TPM_SIGNATURE) { + CFA_LOG_ERR("tpm = %p, pool_id = %d\n", tpm, pool_id); + return -EINVAL; + } + + if (!ba_inuse(ctx->pool_ba, pool_id)) { + CFA_LOG_ERR("Pool id (%d) was not allocated\n", pool_id); + return -EINVAL; + } + + if (ctx->fid_tbl[pool_id] == CFA_INVALID_FID || + ctx->fid_tbl[pool_id] != fid) { + CFA_LOG_ERR("The function id %d was not set to the pool %d\n", + fid, pool_id); + return -EINVAL; + } + + ctx->fid_tbl[pool_id] = CFA_INVALID_FID; + + return 0; +} + +int cfa_tpm_srch_by_pool(void *tpm, uint16_t pool_id, uint16_t *fid) +{ + struct cfa_tpm *ctx = (struct cfa_tpm *)tpm; + + if (tpm == NULL || ctx->signature != CFA_TPM_SIGNATURE || fid == NULL || + pool_id >= ctx->max_pools) { + CFA_LOG_ERR("tpm = %p, pool_id = %d, fid = %p\n", tpm, pool_id, + fid); + return -EINVAL; + } + + if (!ba_inuse(ctx->pool_ba, pool_id)) { + CFA_LOG_ERR("Pool id (%d) was not allocated\n", pool_id); + return -EINVAL; + } + + if (ctx->fid_tbl[pool_id] == CFA_INVALID_FID) { + CFA_LOG_ERR("A function id was not set to the pool (%d)\n", + pool_id); + return -EINVAL; + } + + *fid = ctx->fid_tbl[pool_id]; + + return 0; +} + +int cfa_tpm_srchm_by_fid(void *tpm, enum cfa_srch_mode srch_mode, uint16_t fid, + uint16_t *pool_id) +{ + uint16_t i; + struct cfa_tpm *ctx = (struct cfa_tpm *)tpm; + + if (tpm == NULL || ctx->signature != CFA_TPM_SIGNATURE || + pool_id == NULL) { + CFA_LOG_ERR("tpm = %p, pool_id = %p fid = %d\n", tpm, pool_id, + fid); + return -EINVAL; + } + + if (srch_mode == CFA_SRCH_MODE_FIRST) + ctx->next_index = 0; + + for (i = ctx->next_index; i < ctx->max_pools; i++) { + if (ctx->fid_tbl[i] == fid) { + ctx->next_index = i + 1; + *pool_id = i; + return 0; + } + } + + ctx->next_index = ctx->max_pools; + + return -ENOENT; +} + +int cfa_tpm_pool_size_set(void *tpm, uint8_t pool_sz_exp) +{ + struct cfa_tpm *ctx = (struct cfa_tpm *)tpm; + + if (tpm == NULL || ctx->signature != CFA_TPM_SIGNATURE) { + CFA_LOG_ERR("tpm = %p\n", tpm); + return -EINVAL; + } + + ctx->pool_sz_exp = pool_sz_exp; + + return 0; +} + +int cfa_tpm_pool_size_get(void *tpm, uint8_t *pool_sz_exp) +{ + struct cfa_tpm *ctx = (struct cfa_tpm *)tpm; + + if (tpm == NULL || ctx->signature != CFA_TPM_SIGNATURE || + pool_sz_exp == NULL) { + CFA_LOG_ERR("tpm = %p, pool_sz_exp = %p\n", tpm, pool_sz_exp); + return -EINVAL; + } + + *pool_sz_exp = ctx->pool_sz_exp; + + return 0; +} diff --git a/drivers/net/bnxt/hcapi/cfa_v3/tpm/cfa_tpm_priv.h b/drivers/net/bnxt/hcapi/cfa_v3/tpm/cfa_tpm_priv.h new file mode 100644 index 0000000000..506039d376 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/tpm/cfa_tpm_priv.h @@ -0,0 +1,47 @@ +/**************************************************************************** + * Copyright(c) 2021 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_tpm.h + * + * @brief CFA Table Scope Pool Manager private API definitions + */ + +#ifndef _CFA_TPM_PRIV_H_ +#define _CFA_TPM_PRIV_H_ + +#include "cfa_types.h" +#include "bitalloc.h" + +#define CFA_TPM_SIGNATURE 0xCFACF0CD + +#define CFA_TPM_MAX_POOLS 1040 +#define CFA_TPM_MIN_POOLS 1 + +#define CFA_INVALID_FID UINT16_MAX + +/** + * CFA Table Scope Manager Pool Database + * + * Structure used to store CFA Table Scope Pool Manager database info + */ +struct cfa_tpm { + /* Signature of the CFA Table Scope Pool Manager Database */ + uint32_t signature; + /* Maximum number of pools */ + uint16_t max_pools; + /* Size of each pool, in powers of 2 */ + uint8_t pool_sz_exp; + /* Next index for search multiple by fid */ + uint16_t next_index; + /* Bitmap to keep track of pool usage */ + struct bitalloc *pool_ba; + /* Fid table */ + uint16_t *fid_tbl; +}; + +#endif /* _CFA_TPM_PRIV_H_ */ diff --git a/drivers/net/bnxt/hcapi/cfa_v3/tpm/include/cfa_tpm.h b/drivers/net/bnxt/hcapi/cfa_v3/tpm/include/cfa_tpm.h new file mode 100644 index 0000000000..3c381a3db2 --- /dev/null +++ b/drivers/net/bnxt/hcapi/cfa_v3/tpm/include/cfa_tpm.h @@ -0,0 +1,215 @@ +/**************************************************************************** + * Copyright(c) 2022 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * @file cfa_tpm.h + * + * @brief CFA Table Scope Pool Manager Public API definitions + */ +#ifndef _CFA_TPM_H_ +#define _CFA_TPM_H_ + +#include "cfa_types.h" + +/** + * @addtogroup CFA_TPM CFA Table Scope Pool Manager + * \ingroup CFA_V3 + * The purpose of the CFA Table Scope pool manager is to provide a centralized + * management of Table Scope region pools. Each CFA TPM instance manages the + * pools belonging to one region. The Table Scope Pool Manager(TPM) keeps + * track of fids that are using the pools. + * @{ + */ + +/** CFA Table Scope Pool Manager query DB size API + * + * This API returns the size of memory required for internal data structures to + * manage the table scope pool ids, and user fids. + * + * @param[in] max_pools + * Maximum number of pool ids available to manage. + * + * @param[out] tpm_db_size + * Pointer to 32 bit integer to return the amount of memory required. + * + * @return + * Returns 0 if successful, Error Code otherwise + */ +int cfa_tpm_query(uint16_t max_pools, uint32_t *tpm_db_size); + +/** CFA Table Scope Pool Manager open API + * + * This API initializes the CFA Table Scope Pool Manager database + * + * @param[in] tpm + * Pointer to the memory used for the CFA Table Scope Pool Manager Database. + * + * @param[in] tpm_db_size + * The size of memory block pointed to by tpm parameter. + * + * @param[in] max_pools + * Maximum number of pool ids to manage. + * + * @return + * Returns 0 if successful, Error Code otherwise + */ +int cfa_tpm_open(void *tpm, uint32_t tpm_db_size, uint16_t max_pools); + +/** CFA Table Scope Pool Manager close API + * + * This API resets the CFA Table Scope Pool Manager database + * + * @param[in] tpm + * Pointer to the database memory for the Table Scope Pool Manager. + * + * @return + * Returns 0 if successful, Error Code otherwise + */ +int cfa_tpm_close(void *tpm); + +/** CFA Table Scope pool Manager alloc API + * + * This API allocates a pool Id. + * + * @param[in] tpm + * Pointer to the database memory for the Table Scope Pool Manager. + * + * @param[out] pool_id + * Pointer to memory location to return the allocated Pool Id. + * + * @return + * Returns 0 if successful, Error Code otherwise + */ +int cfa_tpm_alloc(void *tpm, uint16_t *pool_id); + +/** CFA Table Scope Pool Manager free API + * + * This API frees a previously allocated Pool Id. + * + * @param[in] tpm + * Pointer to the database memory for the Table Scope Pool Manager. + * + * @param[in] pool_id + * Pool Id to be freed. + * + * @return + * Returns 0 if successful, Error Code otherwise + */ +int cfa_tpm_free(void *tpm, uint16_t pool_id); + +/** CFA Table Scope Pool Manager add fid API + * + * This API adds an fid to a Pool Id. + * + * @param[in] tpm + * Pointer to the database memory for the Table Scope Pool Manager. + * + * @param[in] pool_id + * Pool Id to which the fid has to be added. + * + * @param[in] fid + * Function id to be added. + * + * @return + * Returns 0 if successful, Error Code otherwise + */ +int cfa_tpm_fid_add(void *tpm, uint16_t pool_id, uint16_t fid); + +/** CFA Table Scope Pool Manager remove fid API + * + * This API removes a previously added fid from a Pool Id. + * + * @param[in] tpm + * Pointer to the database memory for the Table Scope Pool Manager. + * + * @param[in] pool_id + * Pool Id from which the fid has to be removed. + * + * @param[in] fid + * Function id to be removed. + * + * @return + * Returns 0 if successful, Error Code otherwise + */ +int cfa_tpm_fid_rem(void *tpm, uint16_t pool_id, uint16_t fid); + +/** CFA Table Scope Pool Manager search by pool id API + * + * This API searches for the fid that is added to the pool id. + * + * @param[in] tpm + * Pointer to the database memory for the Table Scope Pool Manager. + * + * @param[in] pool_id + * Pool id to be searched for. + * + * @param[out] fid + * Pointer to memory location to return the fid that is added + * to the Pool id.. + * + * @return + * Returns 0 if successful, Error Code otherwise + */ +int cfa_tpm_srch_by_pool(void *tpm, uint16_t pool_id, uint16_t *fid); + +/** CFA Table Scope Pool Manager search by fid API + * + * This API searches for the Pool ids to which fid is added. + * + * @param[in] tpm + * Pointer to the database memory for the Table Scope Pool Manager. + * + * @param[in] srch_mode + * srch_mode indicates if the iteration is for the first match, which + * indicates the start of new iteration or for the next match. + * + * @param[in] fid + * Function id to be searched for. + * + * @param[out] pool_id + * Pointer to memory location to return the Pool Id to which fid is + * added. + * + * @return + * Returns 0 if successful, Error Code otherwise + */ +int cfa_tpm_srchm_by_fid(void *tpm, enum cfa_srch_mode srch_mode, uint16_t fid, + uint16_t *pool_id); + +/** CFA Table Scope Pool Manager set pool size API + * + * This API sets the pool size into TPM. + * + * @param[in] tpm + * Pointer to the database memory for the Table Scope Pool Manager. + * + * @param[in] pool_sz_exp + * The size of each pool in power of 2. + * + * @return + * Returns 0 if successful, Error Code otherwise + */ +int cfa_tpm_pool_size_set(void *tpm, uint8_t pool_sz_exp); + +/** CFA Table Scope Pool Manager get pool size API + * + * This API returns the pool size from TPM. + * + * @param[in] tpm + * Pointer to the database memory for the Table Scope Pool Manager. + * + * @param[out] pool_sz_exp + * Pointer to memory location to return the pool size in power of 2. + * + * @return + * Returns 0 if successful, Error Code otherwise + */ +int cfa_tpm_pool_size_get(void *tpm, uint8_t *pool_sz_exp); + +/**@}*/ + +#endif /* _CFA_TPM_H_ */ diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index cec4b59d1a..aac3474c40 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -72,6 +72,10 @@ struct hwrm_resp_hdr { #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4) /* RoCE slow path command to modify CC Gen1 support. */ #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5) +/* RoCE slow path command to query CC Gen2 support. */ +#define TLV_TYPE_QUERY_ROCE_CC_GEN2 UINT32_C(0x6) +/* RoCE slow path command to modify CC Gen2 support. */ +#define TLV_TYPE_MODIFY_ROCE_CC_GEN2 UINT32_C(0x7) /* Engine CKV - The Alias key EC curve and ECC public key information. */ #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001) /* Engine CKV - Initialization vector. */ @@ -153,14 +157,14 @@ struct tlv { /* input (size:128b/16B) */ struct input { /* - * This value indicates what type of request this is. The format + * This value indicates what type of request this is. The format * for the rest of the command is determined by this field. */ uint16_t req_type; /* * This value indicates the what completion ring the request will - * be optionally completed on. If the value is -1, then no - * CR completion will be generated. Any other value must be a + * be optionally completed on. If the value is -1, then no + * CR completion will be generated. Any other value must be a * valid CR ring_id value for this function. */ uint16_t cmpl_ring; @@ -176,7 +180,7 @@ struct input { uint16_t target_id; /* * This is the host address where the response will be written - * when the request is complete. This area must be 16B aligned + * when the request is complete. This area must be 16B aligned * and must be cleared to zero before the request is made. */ uint64_t resp_addr; @@ -197,7 +201,7 @@ struct output { /* This field provides original sequence number of the command. */ uint16_t seq_id; /* - * This field is the length of the response in bytes. The + * This field is the length of the response in bytes. The * last byte of the response is a valid flag that will read * as '1' when the command has been completely written to * memory. @@ -366,6 +370,14 @@ struct cmd_nums { #define HWRM_QUEUE_VLANPRI2PRI_CFG UINT32_C(0x85) #define HWRM_QUEUE_GLOBAL_CFG UINT32_C(0x86) #define HWRM_QUEUE_GLOBAL_QCFG UINT32_C(0x87) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG UINT32_C(0x88) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG UINT32_C(0x89) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG UINT32_C(0x8a) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG UINT32_C(0x8b) + #define HWRM_QUEUE_QCAPS UINT32_C(0x8c) + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG UINT32_C(0x8d) + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG UINT32_C(0x8e) + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG UINT32_C(0x8f) #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90) #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91) #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92) @@ -389,6 +401,7 @@ struct cmd_nums { #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0) #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1) #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2) + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG UINT32_C(0xa3) #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf) #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0) #define HWRM_STAT_CTX_FREE UINT32_C(0xb1) @@ -444,6 +457,8 @@ struct cmd_nums { #define HWRM_PORT_EP_TX_CFG UINT32_C(0xdb) #define HWRM_PORT_CFG UINT32_C(0xdc) #define HWRM_PORT_QCFG UINT32_C(0xdd) + /* Queries MAC capabilities for the specified port */ + #define HWRM_PORT_MAC_QCAPS UINT32_C(0xdf) #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0) #define HWRM_REG_POWER_QUERY UINT32_C(0xe1) #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2) @@ -547,7 +562,12 @@ struct cmd_nums { #define HWRM_CFA_TLS_FILTER_ALLOC UINT32_C(0x128) /* Experimental */ #define HWRM_CFA_TLS_FILTER_FREE UINT32_C(0x129) - /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */ + /* Release an AFM function for TF control */ + #define HWRM_CFA_RELEASE_AFM_FUNC UINT32_C(0x12a) + /* + * Engine CKV - Get the current allocation status of keys provisioned in + * the key vault. + */ #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e) /* Engine CKV - Add a new CKEK used to encrypt keys. */ #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f) @@ -607,7 +627,10 @@ struct cmd_nums { #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156) /* Engine - Query the statistics accumulator for an Engine. */ #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157) - /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */ + /* + * Engine - Query statistics counters for continuous errors from all CDDIP + * Engines. + */ #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158) /* Engine - Allocate an Engine RQ. */ #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e) @@ -689,6 +712,20 @@ struct cmd_nums { #define HWRM_FUNC_SYNCE_CFG UINT32_C(0x1ab) /* Queries SyncE configurations. */ #define HWRM_FUNC_SYNCE_QCFG UINT32_C(0x1ac) + /* The command is used to deallocate KTLS or QUIC key contexts. */ + #define HWRM_FUNC_KEY_CTX_FREE UINT32_C(0x1ad) + /* The command is used to configure link aggr group mode. */ + #define HWRM_FUNC_LAG_MODE_CFG UINT32_C(0x1ae) + /* The command is used to query link aggr group mode. */ + #define HWRM_FUNC_LAG_MODE_QCFG UINT32_C(0x1af) + /* The command is used to create a link aggr group. */ + #define HWRM_FUNC_LAG_CREATE UINT32_C(0x1b0) + /* The command is used to update a link aggr group. */ + #define HWRM_FUNC_LAG_UPDATE UINT32_C(0x1b1) + /* The command is used to free a link aggr group. */ + #define HWRM_FUNC_LAG_FREE UINT32_C(0x1b2) + /* The command is used to query a link aggr group. */ + #define HWRM_FUNC_LAG_QCFG UINT32_C(0x1b3) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -720,12 +757,12 @@ struct cmd_nums { #define HWRM_MFG_SOC_IMAGE UINT32_C(0x20c) /* Retrieves the SoC status and image provisioning information */ #define HWRM_MFG_SOC_QSTATUS UINT32_C(0x20d) - /* Tells the fw to program the seeprom memory */ - #define HWRM_MFG_PARAM_SEEPROM_SYNC UINT32_C(0x20e) - /* Tells the fw to read the seeprom memory */ - #define HWRM_MFG_PARAM_SEEPROM_READ UINT32_C(0x20f) - /* Tells the fw to get the health of seeprom data */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH UINT32_C(0x210) + /* Tells the fw to finalize the critical data (store and lock it) */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE UINT32_C(0x20e) + /* Tells the fw to read the critical data */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_READ UINT32_C(0x20f) + /* Tells the fw to get the health of critical data */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH UINT32_C(0x210) /* * The command is used for certificate provisioning to export a * Certificate Signing Request (CSR) from the device. @@ -760,6 +797,37 @@ struct cmd_nums { #define HWRM_MFG_SELFTEST_EXEC UINT32_C(0x217) /* Queries the generic stats */ #define HWRM_STAT_GENERIC_QSTATS UINT32_C(0x218) + /* + * The command is used for certificate provisioning to export a + * certificate chain from the device. + */ + #define HWRM_MFG_PRVSN_EXPORT_CERT UINT32_C(0x219) + /* Query the statistics for doorbell drops due to various error conditions. */ + #define HWRM_STAT_DB_ERROR_QSTATS UINT32_C(0x21a) + /* + * This command returns the capabilities related to User Defined + * Congestion Control on a function. + */ + #define HWRM_UDCC_QCAPS UINT32_C(0x258) + /* This command configures User Defined Congestion Control on a function. */ + #define HWRM_UDCC_CFG UINT32_C(0x259) + /* + * This command queries the configuration of User Defined Congestion + * Control on a function. + */ + #define HWRM_UDCC_QCFG UINT32_C(0x25a) + /* This command configures an existing UDCC session. */ + #define HWRM_UDCC_SESSION_CFG UINT32_C(0x25b) + /* This command queries the configuration of a UDCC session. */ + #define HWRM_UDCC_SESSION_QCFG UINT32_C(0x25c) + /* This command queries the UDCC session. */ + #define HWRM_UDCC_SESSION_QUERY UINT32_C(0x25d) + /* This command configures the computation unit. */ + #define HWRM_UDCC_COMP_CFG UINT32_C(0x25e) + /* This command queries the configuration of the computation unit. */ + #define HWRM_UDCC_COMP_QCFG UINT32_C(0x25f) + /* This command queries the status and statistics of the computation unit. */ + #define HWRM_UDCC_COMP_QUERY UINT32_C(0x260) /* Experimental */ #define HWRM_TF UINT32_C(0x2bc) /* Experimental */ @@ -767,8 +835,6 @@ struct cmd_nums { /* Experimental */ #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6) /* Experimental */ - #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7) - /* Experimental */ #define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8) /* Experimental */ #define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9) @@ -797,22 +863,6 @@ struct cmd_nums { /* Experimental */ #define HWRM_TF_TBL_TYPE_BULK_GET UINT32_C(0x2dc) /* Experimental */ - #define HWRM_TF_CTXT_MEM_ALLOC UINT32_C(0x2e2) - /* Experimental */ - #define HWRM_TF_CTXT_MEM_FREE UINT32_C(0x2e3) - /* Experimental */ - #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4) - /* Experimental */ - #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5) - /* Experimental */ - #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2e6) - /* Experimental */ - #define HWRM_TF_EXT_EM_OP UINT32_C(0x2e7) - /* Experimental */ - #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2e8) - /* Experimental */ - #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2e9) - /* Experimental */ #define HWRM_TF_EM_INSERT UINT32_C(0x2ea) /* Experimental */ #define HWRM_TF_EM_DELETE UINT32_C(0x2eb) @@ -840,6 +890,10 @@ struct cmd_nums { #define HWRM_TF_RESC_USAGE_SET UINT32_C(0x300) /* Experimental */ #define HWRM_TF_RESC_USAGE_QUERY UINT32_C(0x301) + /* Truflow command to allocate a table */ + #define HWRM_TF_TBL_TYPE_ALLOC UINT32_C(0x302) + /* Truflow command to free a table */ + #define HWRM_TF_TBL_TYPE_FREE UINT32_C(0x303) /* TruFlow command to check firmware table scope capabilities. */ #define HWRM_TFC_TBL_SCOPE_QCAPS UINT32_C(0x380) /* TruFlow command to allocate a table scope ID and create the pools. */ @@ -852,9 +906,9 @@ struct cmd_nums { #define HWRM_TFC_TBL_SCOPE_FID_ADD UINT32_C(0x384) /* TruFlow command to remove a FID from a table scope. */ #define HWRM_TFC_TBL_SCOPE_FID_REM UINT32_C(0x385) - /* TruFlow command to allocate a table scope pool. */ + /* DEPRECATED */ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC UINT32_C(0x386) - /* TruFlow command to free a table scope pool. */ + /* DEPRECATED */ #define HWRM_TFC_TBL_SCOPE_POOL_FREE UINT32_C(0x387) /* Experimental */ #define HWRM_TFC_SESSION_ID_ALLOC UINT32_C(0x388) @@ -888,8 +942,30 @@ struct cmd_nums { #define HWRM_TFC_TCAM_ALLOC_SET UINT32_C(0x396) /* TruFlow command to free a TCAM entry. */ #define HWRM_TFC_TCAM_FREE UINT32_C(0x397) + /* Truflow command to set an interface table entry */ + #define HWRM_TFC_IF_TBL_SET UINT32_C(0x398) + /* Truflow command to get an interface table entry */ + #define HWRM_TFC_IF_TBL_GET UINT32_C(0x399) + /* TruFlow command to get configured info about a table scope. */ + #define HWRM_TFC_TBL_SCOPE_CONFIG_GET UINT32_C(0x39a) + /* TruFlow command to query the resource usage state. */ + #define HWRM_TFC_RESC_USAGE_QUERY UINT32_C(0x39b) + /* + * This command is used to query the pfc watchdog max configurable + * timeout value. + */ + #define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS UINT32_C(0x39c) + /* This command is used to set the PFC watchdog timeout value. */ + #define HWRM_QUEUE_PFCWD_TIMEOUT_CFG UINT32_C(0x39d) + /* + * This command is used to query the current configured pfc watchdog + * timeout value. + */ + #define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG UINT32_C(0x39e) /* Experimental */ #define HWRM_SV UINT32_C(0x400) + /* Flush any trace buffer data that has not been sent to the host. */ + #define HWRM_DBG_LOG_BUFFER_FLUSH UINT32_C(0xff0f) /* Experimental */ #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10) /* Experimental */ @@ -945,6 +1021,8 @@ struct cmd_nums { #define HWRM_DBG_USEQ_DELIVERY_REQ UINT32_C(0xff2a) /* Experimental */ #define HWRM_DBG_USEQ_RESP_HDR UINT32_C(0xff2b) + #define HWRM_NVM_GET_VPD_FIELD_INFO UINT32_C(0xffea) + #define HWRM_NVM_SET_VPD_FIELD_INFO UINT32_C(0xffeb) #define HWRM_NVM_DEFRAG UINT32_C(0xffec) #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed) /* Experimental */ @@ -1039,14 +1117,14 @@ struct ret_codes { #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc) /* * This error code is only reported by firmware when the registered - * driver instances requested to offloaded a flow but was unable to because - * the requested key's hash collides with the installed keys. + * driver instances requested to offloaded a flow but was unable to + * because the requested key's hash collides with the installed keys. */ #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd) /* * This error code is only reported by firmware when the registered - * driver instances requested to offloaded a flow but was unable to because - * the same key has already been installed. + * driver instances requested to offloaded a flow but was unable to + * because the same key has already been installed. */ #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe) /* @@ -1055,8 +1133,8 @@ struct ret_codes { */ #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf) /* - * Firmware is unable to service the request at the present time. Caller - * may try again later. + * Firmware is unable to service the request at the present time. + * Caller may try again later. */ #define HWRM_ERR_CODE_BUSY UINT32_C(0x10) /* @@ -1071,6 +1149,11 @@ struct ret_codes { * async completion ring or associated forwarding buffers configured. */ #define HWRM_ERR_CODE_PF_UNAVAILABLE UINT32_C(0x12) + /* + * This error code is reported by Firmware when the specific entity + * requested by the host is not present or does not exist. + */ + #define HWRM_ERR_CODE_ENTITY_NOT_PRESENT UINT32_C(0x13) /* * This value indicates that the HWRM response is in TLV format and * should be interpreted as one or more TLVs starting with the @@ -1103,7 +1186,7 @@ struct hwrm_err_output { /* This field provides original sequence number of the command. */ uint16_t seq_id; /* - * This field is the length of the response in bytes. The + * This field is the length of the response in bytes. The * last byte of the response is a valid flag that will read * as '1' when the command has been completely written to * memory. @@ -1120,9 +1203,9 @@ struct hwrm_err_output { uint8_t cmd_err; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -1132,7 +1215,12 @@ struct hwrm_err_output { * applicable (All F's). Need to cast it the size of the field if needed. */ #define HWRM_NA_SIGNATURE ((uint32_t)(-1)) -/* hwrm_func_buf_rgtr */ +/* + * This is reflecting the size of the PF mailbox and not the maximum + * command size for any of the HWRM command structures. To determine + * the maximum size of an HWRM command supported by the firmware, see + * the max_ext_req_len field in the response of the HWRM_VER_GET command. + */ #define HWRM_MAX_REQ_LEN 128 /* hwrm_cfa_flow_info */ #define HWRM_MAX_RESP_LEN 704 @@ -1156,10 +1244,10 @@ struct hwrm_err_output { #define HWRM_TARGET_ID_TOOLS 0xFFFD #define HWRM_VERSION_MAJOR 1 #define HWRM_VERSION_MINOR 10 -#define HWRM_VERSION_UPDATE 2 +#define HWRM_VERSION_UPDATE 3 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 158 -#define HWRM_VERSION_STR "1.10.2.158" +#define HWRM_VERSION_RSVD 40 +#define HWRM_VERSION_STR "1.10.3.40" /**************** * hwrm_ver_get * @@ -1377,53 +1465,58 @@ struct hwrm_ver_get_output { /* * If set to 1, then the KONG host mailbox channel is supported. * If set to 0, then the KONG host mailbox channel is not supported. - * By default, this flag should be 0 for older version of core firmware. + * By default, this flag should be 0 for older version of core + * firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \ UINT32_C(0x10) /* - * If set to 1, then the 64bit flow handle is supported in addition to the - * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not - * supported. By default, this flag should be 0 for older version of core firmware. + * If set to 1, then the 64bit flow handle is supported in addition + * to the legacy 16bit flow handle. If set to 0, then the 64bit flow + * handle is not supported. By default, this flag should be 0 for + * older version of core firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \ UINT32_C(0x20) /* - * If set to 1, then filter type can be provided in filter_alloc or filter_cfg - * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic. - * If set to 0, then filter types not supported. - * By default, this flag should be 0 for older version of core firmware. + * If set to 1, then filter type can be provided in filter_alloc or + * filter_cfg filter types like L2 for l2 traffic and ROCE for roce & + * l2 traffic. If set to 0, then filter types not supported. By + * default, this flag should be 0 for older version of core firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \ UINT32_C(0x40) /* - * If set to 1, firmware is capable to support virtio vSwitch offload model. - * If set to 0, firmware can't supported virtio vSwitch offload model. - * By default, this flag should be 0 for older version of core firmware. + * If set to 1, firmware is capable to support virtio vSwitch offload + * model. If set to 0, firmware can't supported virtio vSwitch + * offload model. + * By default, this flag should be 0 for older version of core + * firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \ UINT32_C(0x80) /* * If set to 1, firmware is capable to support trusted VF. * If set to 0, firmware is not capable to support trusted VF. - * By default, this flag should be 0 for older version of core firmware. + * By default, this flag should be 0 for older version of core + * firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \ UINT32_C(0x100) /* * If set to 1, firmware is capable to support flow aging. * If set to 0, firmware is not capable to support flow aging. - * By default, this flag should be 0 for older version of core firmware. - * (deprecated) + * By default, this flag should be 0 for older version of core + * firmware. (deprecated) */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \ UINT32_C(0x200) /* - * If set to 1, firmware is capable to support advanced flow counters like, - * Meter drop counters and EEM counters. - * If set to 0, firmware is not capable to support advanced flow counters. - * By default, this flag should be 0 for older version of core firmware. - * (deprecated) + * If set to 1, firmware is capable to support advanced flow counters + * like, Meter drop counters and EEM counters. + * If set to 0, firmware is not capable to support advanced flow + * counters. By default, this flag should be 0 for older version of + * core firmware. (deprecated) */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \ UINT32_C(0x400) @@ -1432,31 +1525,33 @@ struct hwrm_ver_get_output { * Extended Exact Match(EEM) feature. * If set to 0, firmware is not capable to support the use of the * CFA EEM feature. - * By default, this flag should be 0 for older version of core firmware. - * (deprecated) + * By default, this flag should be 0 for older version of core + * firmware. (deprecated) */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \ UINT32_C(0x800) /* - * If set to 1, the firmware is able to support advance CFA flow management - * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS. - * If set to 0, then the firmware doesn’t support the advance CFA flow management - * features. - * By default, this flag should be 0 for older version of core firmware. + * If set to 1, the firmware is able to support advance CFA flow + * management features reported in the HWRM_CFA_FLOW_MGNT_QCAPS. + * If set to 0, then the firmware doesn't support the advance CFA + * flow management features. + * By default, this flag should be 0 for older version of core + * firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \ UINT32_C(0x1000) /* * Deprecated and replaced with cfa_truflow_supported. * If set to 1, the firmware is able to support TFLIB features. - * If set to 0, then the firmware doesn’t support TFLIB features. - * By default, this flag should be 0 for older version of core firmware. + * If set to 0, then the firmware doesn't support TFLIB features. + * By default, this flag should be 0 for older version of core + * firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \ UINT32_C(0x2000) /* * If set to 1, the firmware is able to support TruFlow features. - * If set to 0, then the firmware doesn’t support TruFlow features. + * If set to 0, then the firmware doesn't support TruFlow features. * By default, this flag should be 0 for older version of * core firmware. */ @@ -1520,7 +1615,10 @@ struct hwrm_ver_get_output { uint8_t chip_metal; /* This field returns the bond id of the chip. */ uint8_t chip_bond_id; - /* This value indicates the type of platform used for chip implementation. */ + /* + * This value indicates the type of platform used for chip + * implementation. + */ uint8_t chip_platform_type; /* ASIC */ #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0) @@ -1576,8 +1674,8 @@ struct hwrm_ver_get_output { * host drivers that it has not completed resource initialization * required for data path operations. Host drivers should not send * any HWRM command that requires data path resources. Firmware will - * fail those commands with HWRM_ERR_CODE_BUSY. Host drivers can retry - * those commands once both the flags are cleared. + * fail those commands with HWRM_ERR_CODE_BUSY. Host drivers can + * retry those commands once both the flags are cleared. * If this flag and dev_not_rdy flag are set to 0, device is ready * to accept all HWRM commands. */ @@ -1738,9 +1836,9 @@ struct hwrm_ver_get_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -2334,11 +2432,11 @@ struct crypto_presync_bd_cmd { * Typically, presync BDs are used for packet retransmissions. Source * port sends all the packets in order over the network to destination * port and packets get dropped in the network. The destination port - * will request retranmission of dropped packets and source port driver - * will send presync BD to setup the transmitter appropriately. It will - * provide the start and end TCP sequence number of the data to be - * transmitted. HW keeps two sets of context variable, one for in order - * traffic and one for retransmission traffic. HW is designed to + * will request retransmission of dropped packets and source port + * driver will send presync BD to setup the transmitter appropriately. + * It will provide the start and end TCP sequence number of the data to + * be transmitted. HW keeps two sets of context variable, one for in + * order traffic and one for retransmission traffic. HW is designed to * transmit everything posted in the presync BD and return to in order * mode after that. No inorder context variables are updated in the * process. There is a special case where packets can be dropped @@ -2506,22 +2604,22 @@ struct ce_bds_quic_add_data_msg { * exchanged as part of sessions setup between the two end * points for QUIC operations. */ - uint64_t quic_iv_lo; + uint8_t quic_iv_lo[8]; /* * Most-significant 32 bits (of 96) of additional IV that is * exchanged as part of sessions setup between the two end * points for QUIC operations. */ - uint32_t quic_iv_hi; + uint8_t quic_iv_hi[4]; uint32_t unused_1; /* * Key used for encrypting or decrypting records. The Key is exchanged * as part of sessions setup between the two end points through this * mid-path BD. */ - uint32_t session_key[8]; + uint8_t session_key[32]; /* Header protection key. */ - uint32_t hp_key[8]; + uint8_t hp_key[32]; /* Packet number associated with the QUIC connection. */ uint64_t pkt_number; } __rte_packed; @@ -2907,7 +3005,7 @@ struct tx_bd_long_hi { * 0xffff. * * If set to one when LSO is '1', then the IPID will be treated - * as a 15b number and will be wrapped if it exceeds a value 0f + * as a 15b number and will be wrapped if it exceeds a value of * 0x7fff. */ #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40) @@ -2961,7 +3059,7 @@ struct tx_bd_long_hi { * will be the following behavior for all cases independent of * settings of inner LSO and checksum offload BD flags. * If outer UDP checksum is 0, then do not update it. - * If outer UDP checksum is non zero, then the hardware should + * If outer UDP checksum is non zero, then the hardware should * compute and update it. */ #define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000) @@ -3091,7 +3189,7 @@ struct tx_bd_long_hi { * - Wh+/SR - this option is not supported. * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta * is set in the Lookup Table. - * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if + * - SR2 - {4'd0, cfa_meta[27:0]} is used for metadata output if * en_bd_meta is set in the Lookup Table. */ #define TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER \ @@ -3387,7 +3485,7 @@ struct tx_bd_long_inline { * - Wh+/SR - this option is not supported. * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta * is set in the Lookup Table. - * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if + * - SR2 - {4'd0, cfa_meta[27:0]} is used for metadata output if * en_bd_meta is set in the Lookup Table. */ #define TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER \ @@ -3505,6 +3603,91 @@ struct tx_bd_presync_cmd { uint32_t unused_1; } __rte_packed; +/* + * This structure is used to send additional information for transmitting + * packets using timed transmit scheduling. It must only to be applied as + * the second BD of a BD chain that represents a packet. Any subsequent + * BDs will follow the timed transmit BD. + */ +/* tx_bd_timedtx (size:128b/16B) */ +struct tx_bd_timedtx { + uint16_t flags_type; + /* This value identifies the type of buffer descriptor. */ + #define TX_BD_TIMEDTX_TYPE_MASK UINT32_C(0x3f) + #define TX_BD_TIMEDTX_TYPE_SFT 0 + /* + * Indicates a timed transmit BD. This is a 16b BD that is inserted + * into a packet BD chain immediately after the first BD. It is used + * to control the flow in a timed transmit operation. + */ + #define TX_BD_TIMEDTX_TYPE_TX_BD_TIMEDTX UINT32_C(0xa) + #define TX_BD_TIMEDTX_TYPE_LAST \ + TX_BD_TIMEDTX_TYPE_TX_BD_TIMEDTX + /* Unless otherwise stated, sub-fields of this field are always valid. */ + #define TX_BD_TIMEDTX_FLAGS_MASK UINT32_C(0xffc0) + #define TX_BD_TIMEDTX_FLAGS_SFT 6 + /* + * This value identifies the kind of buffer timed transmit mode that + * is to be enabled for the packet. + */ + #define TX_BD_TIMEDTX_FLAGS_KIND_MASK UINT32_C(0x1c0) + #define TX_BD_TIMEDTX_FLAGS_KIND_SFT 6 + /* + * This timed transmit mode indicates that the packet will be + * scheduled and send immediately (or as soon as possible), once + * it is scheduled in the transmitter. + * Note: This mode is similar to regular (non-timed transmit) + * operation. Its main purpose is to cancel pace mode timed + * transmit. + */ + #define TX_BD_TIMEDTX_FLAGS_KIND_ASAP (UINT32_C(0x0) << 6) + /* + * This timed transmit mode is used to schedule transmission of + * the packet no earlier than the time given in the tx_time + * field of the BD. + * Note: In case subsequent packets don't include a timed transmit + * BD, they will be scheduled subsequently for transmission + * without any timed transmit constraint. + */ + #define TX_BD_TIMEDTX_FLAGS_KIND_SO_TXTIME (UINT32_C(0x1) << 6) + /* + * This timed transmit mode is used to enable rate control for the + * flow (QP) at a rate as defined by the rate field of this BD. + * Note: In case subsequent, adjacent packets on the same flow + * don't include a timed transmit BD, they will continue to be + * paced by the transmitter at the same rate as given in this BD. + */ + #define TX_BD_TIMEDTX_FLAGS_KIND_PACE (UINT32_C(0x2) << 6) + #define TX_BD_TIMEDTX_FLAGS_KIND_LAST \ + TX_BD_TIMEDTX_FLAGS_KIND_PACE + /* + * This field exists in all Tx BDs. It doesn't apply to this particular + * BD type since the BD never represents an SGL or inline data; i.e. it + * is only a command. This field must be zero. + */ + uint16_t len; + /* + * This field represents the rate of the flow (QP) in terms of KB/s. + * This applies to pace mode timed transmit. + */ + uint32_t rate; + /* + * Applying this rate to a QP will result in this and all subsequent + * packets of the flow being paced at the given rate, until such time + * that the timed transmit mode is either changed or the rate is + * updated in a future packet on the flow. + * This field is applicable only if flags.kind is pace. + */ + #define TX_BD_TIMEDTX_RATE_VAL_MASK UINT32_C(0x1ffffff) + #define TX_BD_TIMEDTX_RATE_VAL_SFT 0 + /* + * This field represents the nano-second time to transmit the + * corresponding packet using SO_TXTIME mode of timed transmit. + * This field is applicable only if flags.kind is so_txtime. + */ + uint64_t tx_time; +} __rte_packed; + /* rx_prod_pkt_bd (size:128b/16B) */ struct rx_prod_pkt_bd { /* This value identifies the type of buffer descriptor. */ @@ -6017,8 +6200,20 @@ struct rx_pkt_v3_cmpl { * is not applicable. */ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_11 (UINT32_C(0xb) << 7) + /* The RSS hash was computed over tunnel context and tunnel ID field. */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_12 (UINT32_C(0xc) << 7) + /* + * The RSS hash was computed over tunnel source IP address, tunnel + * destination IP address, and tunnel ID field. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_13 (UINT32_C(0xd) << 7) + /* + * The RSS hash was computed over tunnel source IP address, tunnel + * destination IP address, tunnel context, and tunnel ID field. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_14 (UINT32_C(0xe) << 7) #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_LAST \ - RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_11 + RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_14 uint16_t metadata1_payload_offset; /* * If truncation placement is not used, this value indicates the offset @@ -7454,7 +7649,7 @@ struct rx_tpa_start_v2_cmpl_hi { UINT32_C(0x100) /* * This indicates that the complete 1's complement checksum was - * calculated for the packet in the affregation. + * calculated for the packet in the aggregation. */ #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \ UINT32_C(0x200) @@ -8526,7 +8721,7 @@ struct rx_tpa_v2_start_cmpl_hi { #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \ UINT32_C(0xf0) #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4 - /* No metadata informtaion. Value is zero. */ + /* No metadata information. Value is zero. */ #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \ (UINT32_C(0x0) << 4) /* @@ -8545,7 +8740,7 @@ struct rx_tpa_v2_start_cmpl_hi { * - VXLAN = VNI[23:0] -> VXLAN Network ID * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier. * - NVGRE = TNI[23:0] -> Tenant Network ID - * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0 + * - GRE = KEY[31:0] -> key field with bit mask. Zero if K = 0 * - IPV4 = 0 (not populated) * - IPV6 = Flow Label[19:0] * - PPPoE = sessionID[15:0] @@ -9534,9 +9729,31 @@ struct hwrm_async_event_cmpl { */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR \ UINT32_C(0x49) + /* + * An event from firmware indicating that the XID partition was not + * allocated/freed by the FW successfully for the request that is + * encapsulated in the HWRM_EXEC_FWD_RESP by the PF driver for VF. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_CTX_ERROR \ + UINT32_C(0x4a) + /* + * A UDCC session has been modified in the FW. The session_id can be + * used by the driver to retrieve information related to the UDCC + * session. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_UDCC_SESSION_CHANGE \ + UINT32_C(0x4b) + /* + * Used to notify the host that the firmware has DMA-ed additional + * debug data to the host buffer. This is effectively a producer index + * update. The host driver can utilize this information to determine + * how much of its host buffer has been populated by the firmware. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DBG_BUF_PRODUCER \ + UINT32_C(0x4c) /* Maximum Registrable event id. */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \ - UINT32_C(0x4a) + UINT32_C(0x4d) /* * A trace log message. This contains firmware trace logs string * embedded in the asynchronous message. This is an experimental @@ -10210,7 +10427,7 @@ struct hwrm_async_event_cmpl_reset_notify { * 16-lsb timestamp (100-msec resolution) * The Maximum Firmware Reset bail out value in the order of 100 * milliseconds. The driver instances will use this value to reinitiate - * the registration process again if the core firmware didn’t set the + * the registration process again if the core firmware didn't set the * state bit. */ uint16_t timestamp_hi; @@ -10920,6 +11137,14 @@ struct hwrm_async_event_cmpl_vf_cfg_change { */ #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \ UINT32_C(0x10) + /* + * If this bit is set to 1, then the control of VF was relinquished + * back to the firmware flow manager following the function takeover + * by TruFlow. + * If set to 0, then this bit should be ignored. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TF_OWNERSHIP_RELEASE \ + UINT32_C(0x20) } __rte_packed; /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */ @@ -11518,8 +11743,8 @@ struct hwrm_async_event_cmpl_quiesce_done { 8 /* * Additional information about internal hardware state related to - * idle/quiesce state. QUIESCE may succeed per quiesce_status - * regardless of idle_state_flags. If QUIESCE fails, the host may + * idle/quiesce state. QUIESCE may succeed per quiesce_status + * regardless of idle_state_flags. If QUIESCE fails, the host may * inspect idle_state_flags to determine whether a retry is warranted. */ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \ @@ -12237,6 +12462,236 @@ struct hwrm_async_event_cmpl_hw_doorbell_recovery_read_error { UINT32_C(0x8) } __rte_packed; +/* hwrm_async_event_cmpl_ctx_error (size:128b/16B) */ +struct hwrm_async_event_cmpl_ctx_error { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform the PF driver + * that firmware fails to allocate/free the contexts requested. This + * message is only valid in the XID partition scheme. Given the start + * xid and the number of contexts in error, the PF driver will figure + * out the corresponding XID partition(s) in error. + */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_ID_CTX_ERROR \ + UINT32_C(0x4a) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_ID_CTX_ERROR + /* Event specific data */ + uint32_t event_data2; + /* Context operation code */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE \ + UINT32_C(0x1) + /* Context alloc failure */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE_ALLOC \ + UINT32_C(0x0) + /* Context free failure */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE_FREE \ + UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE_LAST \ + HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE_FREE + /* Number of contexts in error */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_NUM_CTXS_MASK \ + UINT32_C(0xfffe) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_NUM_CTXS_SFT 1 + /* Function ID which the XID partitions are associated with */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_FID_MASK \ + UINT32_C(0xffff0000) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_FID_SFT 16 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Starting XID that has error */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA1_START_XID_MASK \ + UINT32_C(0xffffffff) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA1_START_XID_SFT 0 +} __rte_packed; + +/* hwrm_async_event_udcc_session_change (size:128b/16B) */ +struct hwrm_async_event_udcc_session_change { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform the PF driver + * that firmware has modified a UDCC session. + */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_ID_UDCC_SESSION_CHANGE \ + UINT32_C(0x4b) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_ID_UDCC_SESSION_CHANGE + /* Event specific data */ + uint32_t event_data2; + /* UDCC Session id operation code */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_SFT \ + 0 + /* session_id has been created */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_CREATED \ + UINT32_C(0x0) + /* session_id has been freed */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_FREED \ + UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_LAST \ + HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_FREED + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* UDCC session id which was modified */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA1_UDCC_SESSION_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA1_UDCC_SESSION_ID_SFT \ + 0 +} __rte_packed; + +/* hwrm_async_event_cmpl_dbg_buf_producer (size:128b/16B) */ +struct hwrm_async_event_cmpl_dbg_buf_producer { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * Used to notify the host that the firmware has DMA-ed additional + * debug data to the host buffer. This is effectively a producer index + * update. The host driver can utilize this information to determine + * how much of its host buffer has been populated by the firmware. + */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER \ + UINT32_C(0x4c) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER + /* Event specific data */ + uint32_t event_data2; + /* + * Specifies the current host buffer offset. Data up to this offset + * has been populated by the firmware. For example, if the firmware + * has DMA-ed 8192 bytes to the host buffer, then this field has a + * value of 8192. This field rolls over to zero once the firmware + * writes the last page of the host buffer + */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURRENT_BUFFER_OFFSET_MASK \ + UINT32_C(0xffffffff) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURRENT_BUFFER_OFFSET_SFT \ + 0 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Type of trace buffer that has been updated. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SFT \ + 0 + /* SRT trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT_TRACE \ + UINT32_C(0x0) + /* SRT2 trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT2_TRACE \ + UINT32_C(0x1) + /* CRT trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT_TRACE \ + UINT32_C(0x2) + /* CRT2 trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT2_TRACE \ + UINT32_C(0x3) + /* RIGP0 trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP0_TRACE \ + UINT32_C(0x4) + /* L2 HWRM trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_L2_HWRM_TRACE \ + UINT32_C(0x5) + /* RoCE HWRM trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE \ + UINT32_C(0x6) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE +} __rte_packed; + /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */ struct hwrm_async_event_cmpl_fw_trace_msg { uint16_t type; @@ -12842,7 +13297,7 @@ struct hwrm_async_event_cmpl_error_report_thermal { HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT /* Event specific data. */ uint32_t event_data2; - /* Current temperature. In Celsius */ + /* Current temperature. In Celsius */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK \ UINT32_C(0xff) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_SFT \ @@ -12929,6 +13384,72 @@ struct hwrm_async_event_cmpl_error_report_thermal { HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING } __rte_packed; +/* hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_SFT \ + 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * Speed change not supported with dual rate transceivers + * on this board. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED \ + UINT32_C(0x6) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED +} __rte_packed; + /* metadata_base_msg (size:64b/8B) */ struct metadata_base_msg { uint16_t md_type_link; @@ -13524,8 +14045,8 @@ struct hwrm_func_reset_input { * The ID of the VF that this PF is trying to reset. * Only the parent PF shall be allowed to reset a child VF. * - * A parent PF driver shall use this field only when a specific child VF - * is requested to be reset. + * A parent PF driver shall use this field only when a specific child + * VF is requested to be reset. */ uint16_t vf_id; /* This value indicates the level of a function reset. */ @@ -13575,9 +14096,9 @@ struct hwrm_func_reset_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -13645,16 +14166,16 @@ struct hwrm_func_getfid_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * FID value. This value is used to identify operations on the PCI + * FID value. This value is used to identify operations on the PCI * bus as belonging to a particular PCI function. */ uint16_t fid; uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -13725,9 +14246,9 @@ struct hwrm_func_vf_alloc_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -13799,9 +14320,9 @@ struct hwrm_func_vf_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -13812,7 +14333,7 @@ struct hwrm_func_vf_free_output { ********************/ -/* hwrm_func_vf_cfg_input (size:512b/64B) */ +/* hwrm_func_vf_cfg_input (size:576b/72B) */ struct hwrm_func_vf_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -13916,17 +14437,29 @@ struct hwrm_func_vf_cfg_input { #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ UINT32_C(0x800) /* - * This bit must be '1' for the num_tx_key_ctxs field to be - * configured. + * This bit must be '1' for the num_ktls_tx_key_ctxs field to + * be configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_KEY_CTXS \ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_KTLS_TX_KEY_CTXS \ UINT32_C(0x1000) /* - * This bit must be '1' for the num_rx_key_ctxs field to be - * configured. + * This bit must be '1' for the num_ktls_rx_key_ctxs field to + * be configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_KEY_CTXS \ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_KTLS_RX_KEY_CTXS \ UINT32_C(0x2000) + /* + * This bit must be '1' for the num_quic_tx_key_ctxs field to + * be configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_QUIC_TX_KEY_CTXS \ + UINT32_C(0x4000) + /* + * This bit must be '1' for the num_quic_rx_key_ctxs field to + * be configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_QUIC_RX_KEY_CTXS \ + UINT32_C(0x8000) /* * The maximum transmission unit requested on the function. * The HWRM should make sure that the mtu of @@ -13991,10 +14524,10 @@ struct hwrm_func_vf_cfg_input { UINT32_C(0x2) /* * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of CMPL rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firmware will NOT reserve the assets if they - * are available. + * requested in this command (i.e. number of CMPL rings) are + * available. The firmware will return an error if the requested + * assets are not available. The firmware will NOT reserve the assets + * if they are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \ UINT32_C(0x4) @@ -14009,10 +14542,10 @@ struct hwrm_func_vf_cfg_input { UINT32_C(0x8) /* * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of ring groups) are available. - * The firmware will return an error if the requested assets are - * not available. The firmware will NOT reserve the assets if they - * are available. + * requested in this command (i.e. number of ring groups) are + * available. The firmware will return an error if the requested + * assets are not available. The firmware will NOT reserve the assets + * if they are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \ UINT32_C(0x10) @@ -14076,11 +14609,17 @@ struct hwrm_func_vf_cfg_input { uint16_t num_stat_ctxs; /* The number of HW ring groups requested for the VF. */ uint16_t num_hw_ring_grps; - /* Number of Tx Key Contexts requested. */ - uint32_t num_tx_key_ctxs; - /* Number of Rx Key Contexts requested. */ - uint32_t num_rx_key_ctxs; - uint8_t unused[4]; + /* Number of KTLS Tx Key Contexts requested. */ + uint32_t num_ktls_tx_key_ctxs; + /* Number of KTLS Rx Key Contexts requested. */ + uint32_t num_ktls_rx_key_ctxs; + /* The number of MSI-X vectors requested for the VF. */ + uint16_t num_msix; + uint8_t unused[2]; + /* Number of QUIC Tx Key Contexts requested. */ + uint32_t num_quic_tx_key_ctxs; + /* Number of QUIC Rx Key Contexts requested. */ + uint32_t num_quic_rx_key_ctxs; } __rte_packed; /* hwrm_func_vf_cfg_output (size:128b/16B) */ @@ -14096,9 +14635,9 @@ struct hwrm_func_vf_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -14161,7 +14700,7 @@ struct hwrm_func_qcaps_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * FID value. This value is used to identify operations on the PCI + * FID value. This value is used to identify operations on the PCI * bus as belonging to a particular PCI function. */ uint16_t fid; @@ -14310,7 +14849,8 @@ struct hwrm_func_qcaps_output { /* * If the query is for a VF, then this flag shall be ignored, * If this query is for a PF and this flag is set to 1, - * then the PF has the administrative privilege to configure another PF + * then the PF has the administrative privilege to configure another + * PF. */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \ UINT32_C(0x40000) @@ -14770,7 +15310,7 @@ struct hwrm_func_qcaps_output { UINT32_C(0x2) /* * When this bit is '1', it indicates that KDNet mode is - * supported on the port for this function. This bit is + * supported on the port for this function. This bit is * never set for a VF. */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KDNET_SUPPORTED \ @@ -14872,11 +15412,11 @@ struct hwrm_func_qcaps_output { UINT32_C(0x4000) /* * This bit is only valid on the condition that both - * “ktls_supported” and “quic_supported” flags are set. When this + * 'ktls_supported' and 'quic_supported' flags are set. When this * bit is valid, it conveys information below: - * 1. If it is set to ‘1’, it indicates that the firmware allows the + * 1. If it is set to '1', it indicates that the firmware allows the * driver to run KTLS and QUIC concurrently; - * 2. If it is cleared to ‘0’, it indicates that the driver has to + * 2. If it is cleared to '0', it indicates that the driver has to * make sure all crypto connections on all functions are of the * same type, i.e., either KTLS or QUIC. */ @@ -14912,6 +15452,51 @@ struct hwrm_func_qcaps_output { */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ROCE_VF_RESOURCE_MGMT_SUPPORTED \ UINT32_C(0x100000) + /* + * When this bit is '1', it indicates that the device supports + * UDCC management. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_UDCC_SUPPORTED \ + UINT32_C(0x200000) + /* + * When this bit is '1', it indicates that the device supports Timed + * Transmit TxTime scheduling; this is applicable to L2 flows only. + * It is expected that host software assigns each packet a transmit + * time and posts packets for transmit in time order. NIC hardware + * transmits the packet at time assigned by software. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TIMED_TX_SO_TXTIME_SUPPORTED \ + UINT32_C(0x400000) + /* + * This bit indicates the method used for the advertisement of the + * max resource limit for the PF and its VFs. + * When this bit is '1', it indicates that the maximum resource + * limits for both RoCE and L2 are software defined. These limits + * are queried using the HWRM backing store qcaps v1 + * and v2(max_num_entries). For RoCE, the resource limits are + * derived from nvm options. For L2, the resources will continue + * to use FW enforced SW limits based on chip config and per PF + * function NVM resource parameters. + * If this bit is '0', the FW will use to legacy behavior. + * For RoCE, the maximum resource values supported by the chip will + * be returned. For L2, the maximum resource values returned will + * be the FW enforced SW limits based on chip config and per PF + * function NVM resource parameters. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SW_MAX_RESOURCE_LIMITS_SUPPORTED \ + UINT32_C(0x800000) + /* + * When this bit is '1', it indicates that the device supports + * migrating ingress NIC flows to Truflow. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TF_INGRESS_NIC_FLOW_SUPPORTED \ + UINT32_C(0x1000000) + /* + * When this bit is '1', it indicates that the Firmware supports + * query and clear of the port loopback statistics. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_LPBK_STATS_SUPPORTED \ + UINT32_C(0x2000000) uint16_t tunnel_disable_flag; /* * When this bit is '1', it indicates that the VXLAN parsing @@ -15035,7 +15620,7 @@ struct hwrm_func_qcaps_output { uint8_t unused_3[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -15101,7 +15686,7 @@ struct hwrm_func_qcfg_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * FID value. This value is used to identify operations on the PCI + * FID value. This value is used to identify operations on the PCI * bus as belonging to a particular PCI function. */ uint16_t fid; @@ -15174,15 +15759,15 @@ struct hwrm_func_qcfg_output { * If the function that is being queried is a PF, then the HWRM shall * set this field to 0 and the HWRM client shall ignore this field. * If the function that is being queried is a VF, then the HWRM shall - * set this field to 1 if the queried VF is trusted, otherwise the HWRM - * shall set this field to 0. + * set this field to 1 if the queried VF is trusted, otherwise the + * HWRM shall set this field to 0. */ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \ UINT32_C(0x40) /* - * If set to 1, then secure mode is enabled for this function or device. - * If set to 0, then secure mode is disabled (or normal mode) for this - * function or device. + * If set to 1, then secure mode is enabled for this function or + * device. If set to 0, then secure mode is disabled (or normal mode) + * for this function or device. */ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \ UINT32_C(0x80) @@ -15244,6 +15829,13 @@ struct hwrm_func_qcfg_output { */ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ENABLE_RDMA_SRIOV \ UINT32_C(0x4000) + /* + * When set to 1, indicates the field roce_vnic_id in the structure + * is valid. If this bit is 0, the driver should not use the + * 'roce_vnic_id' field. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ROCE_VNIC_ID_VALID \ + UINT32_C(0x8000) /* * This value is current MAC address configured for this * function. A value of 00-00-00-00-00-00 indicates no @@ -15327,10 +15919,10 @@ struct hwrm_func_qcfg_output { #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \ HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN /* - * This field will indicate number of physical functions on this port_partition. - * HWRM shall return unavail (i.e. value of 0) for this field - * when this command is used to query VF's configuration or - * from older firmware that doesn't support this field. + * This field will indicate number of physical functions on this + * port_partition. HWRM shall return unavail (i.e. value of 0) for this + * field when this command is used to query VF's configuration or from + * older firmware that doesn't support this field. */ uint8_t port_pf_cnt; /* number of PFs is not available */ @@ -15473,7 +16065,10 @@ struct hwrm_func_qcfg_output { /* Admin link state is in forced up mode. */ #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \ (UINT32_C(0x1) << 2) - /* Admin link state is in auto mode - follows the physical link state. */ + /* + * Admin link state is in auto mode - follows the physical link + * state. + */ #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \ (UINT32_C(0x2) << 2) #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \ @@ -15518,7 +16113,7 @@ struct hwrm_func_qcfg_output { */ uint16_t alloc_msix; /* - * The number of registered VF’s associated with the PF. This field + * The number of registered VF's associated with the PF. This field * should be ignored when the request received on the VF interface. * This field will be updated on the PF interface to initiate * the unregister request on PF in the HOT Reset Process. @@ -15526,14 +16121,22 @@ struct hwrm_func_qcfg_output { uint16_t registered_vfs; /* * The size of the doorbell BAR in KBytes reserved for L2 including - * any area that is shared between L2 and RoCE. The L2 driver - * should only map the L2 portion of the doorbell BAR. Any rounding + * any area that is shared between L2 and RoCE. The L2 driver + * should only map the L2 portion of the doorbell BAR. Any rounding * of the BAR size to the native CPU page size should be performed - * by the driver. If the value is zero, no special partitioning + * by the driver. If the value is zero, no special partitioning * of the doorbell BAR between L2 and RoCE is required. */ uint16_t l2_doorbell_bar_size_kb; - uint8_t unused_1; + /* + * A bitmask indicating the active endpoints. Each bit represents a + * specific endpoint, with bit 0 indicating EP 0 and bit 3 indicating + * EP 3. For example: + * - a single root system would return 0x1 + * - a 2x8 system (where EPs 0 and 2 are active) would return 0x5 + * - a 4x4 system (where EPs 0-3 are active) would return 0xF + */ + uint8_t active_endpoints; /* * For backward compatibility this field must be set to 1. * Older drivers might look for this field to be 1 before @@ -15541,21 +16144,22 @@ struct hwrm_func_qcfg_output { */ uint8_t always_1; /* - * This GRC address location is used by the Host driver interfaces to poll - * the adapter ready state to re-initiate the registration process again - * after receiving the RESET Notify event. + * This GRC address location is used by the Host driver interfaces to + * poll the adapter ready state to re-initiate the registration process + * again after receiving the RESET Notify event. */ uint32_t reset_addr_poll; /* - * This field specifies legacy L2 doorbell size in KBytes. Drivers should use - * this value to find out the doorbell page offset from the BAR. + * This field specifies legacy L2 doorbell size in KBytes. Drivers + * should use this value to find out the doorbell page offset from the + * BAR. */ uint16_t legacy_l2_db_size_kb; uint16_t svif_info; /* - * This field specifies the source virtual interface of the function being - * queried. Drivers can use this to program svif field in the L2 context - * table + * This field specifies the source virtual interface of the function + * being queried. Drivers can use this to program svif field in the + * L2 context table */ #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff) #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0 @@ -15623,7 +16227,11 @@ struct hwrm_func_qcfg_output { #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa) #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_LAST \ HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB - uint8_t unused_2[2]; + /* + * RoCE VNIC ID for the function. If the function does not have a valid + * RoCE vnic id, then the roce_vnic_id_valid bit in flags is set to 0. + */ + uint16_t roce_vnic_id; /* * Minimum guaranteed bandwidth for the network partition made up * of the caller physical function and all its child virtual @@ -15713,7 +16321,7 @@ struct hwrm_func_qcfg_output { uint8_t unused_3[2]; uint8_t unused_4[2]; /* - * KDNet mode for the port for this function. If a VF, KDNet + * KDNet mode for the port for this function. If a VF, KDNet * mode is always disabled. */ uint8_t port_kdnet_mode; @@ -15729,7 +16337,7 @@ struct hwrm_func_qcfg_output { */ uint8_t kdnet_pcie_function; /* - * Function ID of the KDNET function on this port. If the + * Function ID of the KDNET function on this port. If the * KDNET partition does not exist and the FW supports this * feature, 0xffff will be returned. */ @@ -15750,8 +16358,8 @@ struct hwrm_func_qcfg_output { uint8_t parif; /* * The LAG ID of a hardware link aggregation group (LAG) whose - * member ports include the port of this function. The LAG was - * previously created using HWRM_FUNC_LAG_CREATE. If the port of this + * member ports include the port of this function. The LAG was + * previously created using HWRM_FUNC_LAG_CREATE. If the port of this * function is not a member of any LAG, the fw_lag_id will be 0xff. */ uint8_t fw_lag_id; @@ -15812,9 +16420,9 @@ struct hwrm_func_qcfg_output { uint8_t unused_7; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -15923,9 +16531,10 @@ struct hwrm_func_cfg_input { UINT32_C(0x800) /* * This bit only applies to the VF. If this bit is set, the statistic - * context counters will not be cleared when the statistic context is freed - * or a function reset is called on VF. This bit will be cleared when the PF - * is unloaded or a function reset is called on the PF. + * context counters will not be cleared when the statistic context is + * freed or a function reset is called on VF. This bit will be + * cleared when the PF is unloaded or a function reset is called on + * the PF. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \ UINT32_C(0x1000) @@ -15949,10 +16558,10 @@ struct hwrm_func_cfg_input { UINT32_C(0x4000) /* * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of CMPL rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firmware will NOT reserve the assets if they - * are available. + * requested in this command (i.e. number of CMPL rings) are + * available. The firmware will return an error if the requested + * assets are not available. The firmware will NOT reserve the assets + * if they are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \ UINT32_C(0x8000) @@ -15967,10 +16576,10 @@ struct hwrm_func_cfg_input { UINT32_C(0x10000) /* * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of ring groups) are available. - * The firmware will return an error if the requested assets are - * not available. The firmware will NOT reserve the assets if they - * are available. + * requested in this command (i.e. number of ring groups) are + * available. The firmware will return an error if the requested + * assets are not available. The firmware will NOT reserve the assets + * if they are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \ UINT32_C(0x20000) @@ -16505,7 +17114,7 @@ struct hwrm_func_cfg_input { * to configure the EVB mode, it sets the evb_mode_cfg_not_supported * flag in HWRM_FUNC_QCAPS command response for the function. * The HWRM takes into account the switching of EVB mode from one to - * another and reconfigure hardware resources as reqiured. The + * another and reconfigure hardware resources as required. The * switching from VEB to VEPA mode requires the disabling of the * loopback traffic. Additionally, source knockouts are handled * differently in VEB and VEPA modes. @@ -16546,7 +17155,10 @@ struct hwrm_func_cfg_input { /* Admin state is forced up. */ #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \ (UINT32_C(0x1) << 2) - /* Admin state is in auto mode - is to follow the physical link state. */ + /* + * Admin state is in auto mode - is to follow the physical link + * state. + */ #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \ (UINT32_C(0x2) << 2) #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \ @@ -16566,66 +17178,66 @@ struct hwrm_func_cfg_input { /* * When this bit is '1', the caller requests to enable a MPC * channel with destination to the TX crypto engine block. - * When this bit is ‘0’, this flag has no effect. + * When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE UINT32_C(0x1) /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the TX crypto engine block. - * When this bit is ‘0’, this flag has no effect. + * When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE UINT32_C(0x2) /* * When this bit is '1', the caller requests to enable a MPC * channel with destination to the RX crypto engine block. - * When this bit is ‘0’, this flag has no effect. + * When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE UINT32_C(0x4) /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the RX crypto engine block. - * When this bit is ‘0’, this flag has no effect. + * When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE UINT32_C(0x8) /* * When this bit is '1', the caller requests to enable a MPC * channel with destination to the TX configurable flow processing - * block. When this bit is ‘0’, this flag has no effect. + * block. When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE \ UINT32_C(0x10) /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the TX configurable flow processing - * block. When this bit is ‘0’, this flag has no effect. + * block. When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE \ UINT32_C(0x20) /* * When this bit is '1', the caller requests to enable a MPC * channel with destination to the RX configurable flow processing - * block. When this bit is ‘0’, this flag has no effect. + * block. When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE \ UINT32_C(0x40) /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the RX configurable flow processing - * block. When this bit is ‘0’, this flag has no effect. + * block. When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE \ UINT32_C(0x80) /* * When this bit is '1', the caller requests to enable a MPC * channel with destination to the primate processor block. - * When this bit is ‘0’, this flag has no effect. + * When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE \ UINT32_C(0x100) /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the primate processor block. - * When this bit is ‘0’, this flag has no effect. + * When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE \ UINT32_C(0x200) @@ -16822,8 +17434,8 @@ struct hwrm_func_cfg_input { #define HWRM_FUNC_CFG_INPUT_ENABLES2_XID_PARTITION_CFG \ UINT32_C(0x400) /* - * KDNet mode for the port for this function. If NPAR is - * also configured on this port, it takes precedence. KDNet + * KDNet mode for the port for this function. If NPAR is + * also configured on this port, it takes precedence. KDNet * mode is ignored for a VF. */ uint8_t port_kdnet_mode; @@ -16919,9 +17531,9 @@ struct hwrm_func_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17038,7 +17650,7 @@ struct hwrm_func_qstats_output { uint64_t tx_bcast_pkts; /* * Number of transmitted packets that were discarded due to - * internal NIC resource problems. For transmit, this + * internal NIC resource problems. For transmit, this * can only happen if TMP is configured to allow dropping * in HOL blocking conditions, which is not a normal * configuration. @@ -17065,7 +17677,7 @@ struct hwrm_func_qstats_output { uint64_t rx_bcast_pkts; /* * Number of received packets that were discarded on the function - * due to resource limitations. This can happen for 3 reasons. + * due to resource limitations. This can happen for 3 reasons. * # The BD used for the packet has a bad format. * # There were no BDs available in the ring for the packet. * # There were no BDs available on-chip for the packet. @@ -17105,9 +17717,9 @@ struct hwrm_func_qstats_output { uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17244,9 +17856,9 @@ struct hwrm_func_qstats_ext_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17309,9 +17921,9 @@ struct hwrm_func_clr_stats_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17373,9 +17985,9 @@ struct hwrm_func_vf_resc_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17449,14 +18061,15 @@ struct hwrm_func_drv_rgtr_input { UINT32_C(0x4) /* * When this bit is '1', the function is indicating support of - * 64bit flow handle. The firmware that only supports 64bit flow + * 64bit flow handle. The firmware that only supports 64bit flow * handle should check this bit before allowing processing of - * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware - * with 64bit flow handle support can only be compatible with drivers - * that support 64bit flow handle. The legacy drivers that don't support - * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when - * running with new firmware that only supports 64bit flow handle. The new - * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED + * HWRM_CFA_FLOW_XXX commands from the requesting function as + * firmware with 64bit flow handle support can only be compatible + * with drivers that support 64bit flow handle. The legacy drivers + * that don't support 64bit flow handle won't be able to use + * HWRM_CFA_FLOW_XXX commands when running with new firmware that + * only supports 64bit flow handle. The new firmware support 64bit + * flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED * status to the legacy driver when encounters these commands. */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \ @@ -17487,11 +18100,12 @@ struct hwrm_func_drv_rgtr_input { UINT32_C(0x20) /* * When this bit is 1, the function is indicating the support of the - * Master capability. The Firmware will use this capability to select the - * Master function. The master function will be used to initiate - * designated functionality like error recovery etc… If none of the - * registered PF’s or trusted VF’s indicate this support, then - * firmware will select the 1st registered PF as Master capable instance. + * Master capability. The Firmware will use this capability to select + * the Master function. The master function will be used to initiate + * designated functionality like error recovery etc. If none of the + * registered PF's or trusted VF's indicate this support, then + * firmware will select the 1st registered PF as Master capable + * instance. */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \ UINT32_C(0x40) @@ -17532,6 +18146,15 @@ struct hwrm_func_drv_rgtr_input { */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ASYM_QUEUE_CFG_SUPPORT \ UINT32_C(0x400) + /* + * When this bit is 1, the function's driver is indicating to the + * firmware that the Ingress NIC flows will be programmed by the + * TruFlow application and the firmware flow manager should reject + * flow-create commands that programs ingress lookup flows for this + * function. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_TF_INGRESS_NIC_FLOW_MODE \ + UINT32_C(0x800) uint32_t enables; /* * This bit must be '1' for the os_type field to be @@ -17563,7 +18186,10 @@ struct hwrm_func_drv_rgtr_input { */ #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \ UINT32_C(0x10) - /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */ + /* + * This value indicates the type of OS. The values are based on + * CIM_OperatingSystem.mof file as published by the DMTF. + */ uint16_t os_type; /* Unknown */ #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) @@ -17662,9 +18288,9 @@ struct hwrm_func_drv_rgtr_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17728,9 +18354,9 @@ struct hwrm_func_drv_unrgtr_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17863,9 +18489,9 @@ struct hwrm_func_buf_rgtr_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17933,9 +18559,9 @@ struct hwrm_func_buf_unrgtr_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17984,7 +18610,18 @@ struct hwrm_func_drv_qver_input { * function. */ uint16_t fid; - uint8_t unused_0[2]; + /* + * This field is used to indicate the driver type. + * L2 or RoCE + */ + uint8_t driver_type; + /* L2 driver version */ + #define HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_L2 UINT32_C(0x0) + /* RoCE driver version */ + #define HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_ROCE UINT32_C(0x1) + #define HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_LAST \ + HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_ROCE + uint8_t unused_0; } __rte_packed; /* hwrm_func_drv_qver_output (size:256b/32B) */ @@ -17997,7 +18634,10 @@ struct hwrm_func_drv_qver_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */ + /* + * This value indicates the type of OS. The values are based on + * CIM_OperatingSystem.mof file as published by the DMTF. + */ uint16_t os_type; /* Unknown */ #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) @@ -18041,9 +18681,9 @@ struct hwrm_func_drv_qver_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -18093,7 +18733,7 @@ struct hwrm_func_resource_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_resource_qcaps_output (size:576b/72B) */ +/* hwrm_func_resource_qcaps_output (size:704b/88B) */ struct hwrm_func_resource_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -18103,13 +18743,22 @@ struct hwrm_func_resource_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */ + /* + * Maximum guaranteed number of VFs supported by PF. Not applicable for + * VFs. + */ uint16_t max_vfs; - /* Maximum guaranteed number of MSI-X vectors supported by function */ + /* Maximum guaranteed number of MSI-X vectors supported by function. */ uint16_t max_msix; - /* Hint of strategy to be used by PF driver to reserve resources for its VF */ + /* + * Hint of strategy to be used by PF driver to reserve resources for + * its VF. + */ uint16_t vf_reservation_strategy; - /* The PF driver should evenly divide its remaining resources among all VFs. */ + /* + * The PF driver should evenly divide its remaining resources among + * all VFs. + */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \ UINT32_C(0x0) /* The PF driver should only reserve minimal resources for each VF. */ @@ -18123,7 +18772,7 @@ struct hwrm_func_resource_qcaps_output { UINT32_C(0x2) #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \ HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC - /* Minimum guaranteed number of RSS/COS contexts */ + /* Minimum guaranteed number of RSS/COS contexts. */ uint16_t min_rsscos_ctx; /* Maximum non-guaranteed number of RSS/COS contexts */ uint16_t max_rsscos_ctx; @@ -18156,33 +18805,43 @@ struct hwrm_func_resource_qcaps_output { /* Maximum non-guaranteed number of ring groups */ uint16_t max_hw_ring_grps; /* - * Maximum number of inputs into the transmit scheduler for this function. - * The number of TX rings assigned to the function cannot exceed this value. + * Maximum number of inputs into the transmit scheduler for this + * function. The number of TX rings assigned to the function cannot + * exceed this value. */ uint16_t max_tx_scheduler_inputs; uint16_t flags; /* * When this bit is '1', it indicates that VF_RESOURCE_CFG supports - * feature to reserve all minimum resources when minimum >= 1, otherwise - * returns an error. + * feature to reserve all minimum resources when minimum >= 1, + * otherwise returns an error. */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) - uint8_t unused_0[2]; - /* Minimum guaranteed number of Tx Key Contexts */ - uint32_t min_tx_key_ctxs; - /* Maximum non-guaranteed number of Tx Key Contexts */ - uint32_t max_tx_key_ctxs; - /* Minimum guaranteed number of Rx Key Contexts */ - uint32_t min_rx_key_ctxs; - /* Maximum non-guaranteed number of Rx Key Contexts */ - uint32_t max_rx_key_ctxs; - uint8_t unused_1[3]; + /* Minimum guaranteed number of MSI-X vectors supported by function */ + uint16_t min_msix; + /* Minimum guaranteed number of KTLS Tx Key Contexts */ + uint32_t min_ktls_tx_key_ctxs; + /* Maximum non-guaranteed number of KTLS Tx Key Contexts */ + uint32_t max_ktls_tx_key_ctxs; + /* Minimum guaranteed number of KTLS Rx Key Contexts */ + uint32_t min_ktls_rx_key_ctxs; + /* Maximum non-guaranteed number of KTLS Rx Key Contexts */ + uint32_t max_ktls_rx_key_ctxs; + /* Minimum guaranteed number of QUIC Tx Key Contexts */ + uint32_t min_quic_tx_key_ctxs; + /* Maximum non-guaranteed number of QUIC Tx Key Contexts */ + uint32_t max_quic_tx_key_ctxs; + /* Minimum guaranteed number of QUIC Rx Key Contexts */ + uint32_t min_quic_rx_key_ctxs; + /* Maximum non-guaranteed number of QUIC Rx Key Contexts */ + uint32_t max_quic_rx_key_ctxs; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -18193,7 +18852,7 @@ struct hwrm_func_resource_qcaps_output { *****************************/ -/* hwrm_func_vf_resource_cfg_input (size:576b/72B) */ +/* hwrm_func_vf_resource_cfg_input (size:704b/88B) */ struct hwrm_func_vf_resource_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -18267,18 +18926,27 @@ struct hwrm_func_vf_resource_cfg_input { */ #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) - uint8_t unused_0[2]; - /* Minimum guaranteed number of Tx Key Contexts */ - uint32_t min_tx_key_ctxs; - /* Maximum non-guaranteed number of Tx Key Contexts */ - uint32_t max_tx_key_ctxs; - /* Minimum guaranteed number of Rx Key Contexts */ - uint32_t min_rx_key_ctxs; - /* Maximum non-guaranteed number of Rx Key Contexts */ - uint32_t max_rx_key_ctxs; -} __rte_packed; - -/* hwrm_func_vf_resource_cfg_output (size:320b/40B) */ + /* Minimum guaranteed number of MSI-X vectors for the function */ + uint16_t min_msix; + /* Minimum guaranteed number of KTLS Tx Key Contexts */ + uint32_t min_ktls_tx_key_ctxs; + /* Maximum non-guaranteed number of KTLS Tx Key Contexts */ + uint32_t max_ktls_tx_key_ctxs; + /* Minimum guaranteed number of KTLS Rx Key Contexts */ + uint32_t min_ktls_rx_key_ctxs; + /* Maximum non-guaranteed number of KTLS Rx Key Contexts */ + uint32_t max_ktls_rx_key_ctxs; + /* Minimum guaranteed number of QUIC Tx Key Contexts */ + uint32_t min_quic_tx_key_ctxs; + /* Maximum non-guaranteed number of QUIC Tx Key Contexts */ + uint32_t max_quic_tx_key_ctxs; + /* Minimum guaranteed number of QUIC Rx Key Contexts */ + uint32_t min_quic_rx_key_ctxs; + /* Maximum non-guaranteed number of QUIC Rx Key Contexts */ + uint32_t max_quic_rx_key_ctxs; +} __rte_packed; + +/* hwrm_func_vf_resource_cfg_output (size:384b/48B) */ struct hwrm_func_vf_resource_cfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -18304,16 +18972,20 @@ struct hwrm_func_vf_resource_cfg_output { uint16_t reserved_stat_ctx; /* Reserved number of ring groups */ uint16_t reserved_hw_ring_grps; - /* Actual number of Tx Key Contexts reserved */ - uint32_t reserved_tx_key_ctxs; - /* Actual number of Rx Key Contexts reserved */ - uint32_t reserved_rx_key_ctxs; + /* Actual number of KTLS Tx Key Contexts reserved */ + uint32_t reserved_ktls_tx_key_ctxs; + /* Actual number of KTLS Rx Key Contexts reserved */ + uint32_t reserved_ktls_rx_key_ctxs; + /* Actual number of QUIC Tx Key Contexts reserved */ + uint32_t reserved_quic_tx_key_ctxs; + /* Actual number of QUIC Rx Key Contexts reserved */ + uint32_t reserved_quic_rx_key_ctxs; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -18395,11 +19067,17 @@ struct hwrm_func_backing_store_qcaps_output { uint16_t cq_entry_size; /* Maximum number of VNIC context entries supported for this function. */ uint16_t vnic_max_vnic_entries; - /* Maximum number of Ring table context entries supported for this function. */ + /* + * Maximum number of Ring table context entries supported for this + * function. + */ uint16_t vnic_max_ring_table_entries; /* Number of bytes that must be allocated for each context entry. */ uint16_t vnic_entry_size; - /* Maximum number of statistic context entries supported for this function. */ + /* + * Maximum number of statistic context entries supported for this + * function. + */ uint32_t stat_max_entries; /* Number of bytes that must be allocated for each context entry. */ uint16_t stat_entry_size; @@ -18421,7 +19099,8 @@ struct hwrm_func_backing_store_qcaps_output { * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size * * Where: - * num_vnics is the number of VNICs allocated in the VNIC backing store + * num_vnics is the number of VNICs allocated in the VNIC backing + * store * num_l2_tx_rings is the number of L2 rings in the QP backing store * num_roce_qps is the number of RoCE QPs in the QP backing store * tqm_min_size is tqm_min_entries_per_ring reported by @@ -18603,9 +19282,9 @@ struct hwrm_func_backing_store_qcaps_output { uint8_t rsvd1[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -18841,6 +19520,12 @@ struct hwrm_func_backing_store_cfg_input { */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_RKC \ UINT32_C(0x100000) + /* + * This bit must be '1' for the number of QPs reserved for fast + * qp modify destroy feature to be configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP_FAST_QPMD \ + UINT32_C(0x200000) /* QPC page size and level. */ uint8_t qpc_pg_size_qpc_lvl; /* QPC PBL indirect levels. */ @@ -18853,7 +19538,10 @@ struct hwrm_func_backing_store_cfg_input { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \ @@ -18894,7 +19582,10 @@ struct hwrm_func_backing_store_cfg_input { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \ @@ -18935,7 +19626,10 @@ struct hwrm_func_backing_store_cfg_input { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \ @@ -18976,7 +19670,10 @@ struct hwrm_func_backing_store_cfg_input { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \ @@ -19017,7 +19714,10 @@ struct hwrm_func_backing_store_cfg_input { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \ @@ -19058,7 +19758,10 @@ struct hwrm_func_backing_store_cfg_input { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \ @@ -19099,7 +19802,10 @@ struct hwrm_func_backing_store_cfg_input { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \ @@ -19140,7 +19846,10 @@ struct hwrm_func_backing_store_cfg_input { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \ @@ -19181,7 +19890,10 @@ struct hwrm_func_backing_store_cfg_input { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \ @@ -19222,7 +19934,10 @@ struct hwrm_func_backing_store_cfg_input { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \ @@ -19263,7 +19978,10 @@ struct hwrm_func_backing_store_cfg_input { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \ @@ -19304,7 +20022,10 @@ struct hwrm_func_backing_store_cfg_input { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \ @@ -19345,7 +20066,10 @@ struct hwrm_func_backing_store_cfg_input { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \ @@ -19386,7 +20110,10 @@ struct hwrm_func_backing_store_cfg_input { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \ @@ -19427,7 +20154,10 @@ struct hwrm_func_backing_store_cfg_input { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \ @@ -19468,7 +20198,10 @@ struct hwrm_func_backing_store_cfg_input { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \ @@ -19545,11 +20278,11 @@ struct hwrm_func_backing_store_cfg_input { * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size * * Where: - * num_vnics is the number of VNICs allocated in the VNIC backing store - * num_l2_tx_rings is the number of L2 rings in the QP backing store - * num_roce_qps is the number of RoCE QPs in the QP backing store - * tqm_min_size is tqm_min_entries_per_ring reported by - * HWRM_FUNC_BACKING_STORE_QCAPS + * num_vnics is the number of VNICs allocated in the VNIC backing + * store num_l2_tx_rings is the number of L2 rings in the QP backing + * store num_roce_qps is the number of RoCE QPs in the QP backing + * store tqm_min_size is tqm_min_entries_per_ring reported by + * HWRM_FUNC_BACKING_STORE_QCAPS * * Note that TQM ring sizes cannot be extended while the system is * operational. If a PF driver needs to extend a TQM ring, it needs @@ -19883,7 +20616,10 @@ struct hwrm_func_backing_store_cfg_input { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LAST \ @@ -19956,8 +20692,11 @@ struct hwrm_func_backing_store_cfg_input { (UINT32_C(0x5) << 4) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_LAST \ HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G - /* Reserved for future. */ - uint8_t rsvd[2]; + /* + * Number of RoCE QP context entries reserved for this + * function to support fast QP modify destroy feature. + */ + uint16_t qp_num_fast_qpmd_entries; } __rte_packed; /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ @@ -19973,9 +20712,9 @@ struct hwrm_func_backing_store_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -20170,6 +20909,12 @@ struct hwrm_func_backing_store_qcfg_output { */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_RKC \ UINT32_C(0x100000) + /* + * This bit must be '1' for the number of QPs reserved for fast + * qp modify destroy feature to be configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP_FAST_QPMD \ + UINT32_C(0x200000) /* QPC page size and level. */ uint8_t qpc_pg_size_qpc_lvl; /* QPC PBL indirect levels. */ @@ -20182,7 +20927,10 @@ struct hwrm_func_backing_store_qcfg_output { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \ @@ -20223,7 +20971,10 @@ struct hwrm_func_backing_store_qcfg_output { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \ @@ -20264,7 +21015,10 @@ struct hwrm_func_backing_store_qcfg_output { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \ @@ -20305,7 +21059,10 @@ struct hwrm_func_backing_store_qcfg_output { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \ @@ -20346,7 +21103,10 @@ struct hwrm_func_backing_store_qcfg_output { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \ @@ -20387,7 +21147,10 @@ struct hwrm_func_backing_store_qcfg_output { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \ @@ -20428,7 +21191,10 @@ struct hwrm_func_backing_store_qcfg_output { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \ @@ -20469,7 +21235,10 @@ struct hwrm_func_backing_store_qcfg_output { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \ @@ -20510,7 +21279,10 @@ struct hwrm_func_backing_store_qcfg_output { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \ @@ -20551,7 +21323,10 @@ struct hwrm_func_backing_store_qcfg_output { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \ @@ -20592,7 +21367,10 @@ struct hwrm_func_backing_store_qcfg_output { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \ @@ -20633,7 +21411,10 @@ struct hwrm_func_backing_store_qcfg_output { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \ @@ -20674,7 +21455,10 @@ struct hwrm_func_backing_store_qcfg_output { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \ @@ -20715,7 +21499,10 @@ struct hwrm_func_backing_store_qcfg_output { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \ @@ -20756,7 +21543,10 @@ struct hwrm_func_backing_store_qcfg_output { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \ @@ -20797,7 +21587,10 @@ struct hwrm_func_backing_store_qcfg_output { /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \ UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \ @@ -21162,10 +21955,15 @@ struct hwrm_func_backing_store_qcfg_output { (UINT32_C(0x5) << 4) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_LAST \ HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G - uint8_t unused_1[5]; + /* + * Number of RoCE QP context entries required for this + * function to support fast QP modify destroy feature. + */ + uint16_t qp_num_fast_qpmd_entries; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as 1 + * is completely written to RAM. This field should be read as 1 * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field @@ -21579,7 +22377,7 @@ struct hwrm_error_recovery_qcfg_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field @@ -21640,9 +22438,9 @@ struct hwrm_func_echo_response_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -21808,9 +22606,9 @@ struct hwrm_func_ptp_pin_qcfg_output { uint8_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -22026,9 +22824,9 @@ struct hwrm_func_ptp_pin_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -22179,8 +22977,11 @@ struct hwrm_func_ptp_cfg_input { /* 10Mhz sync in frequency. */ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M \ UINT32_C(0x3) + /* 25Mhz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_25M \ + UINT32_C(0x4) #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_LAST \ - HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M + HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_25M uint8_t unused_0[3]; /* * Period in nanoseconds (ns) for external signal @@ -22231,9 +23032,9 @@ struct hwrm_func_ptp_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -22316,9 +23117,9 @@ struct hwrm_func_ptp_ts_query_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -22463,9 +23264,9 @@ struct hwrm_func_ptp_ext_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -22558,9 +23359,9 @@ struct hwrm_func_ptp_ext_qcfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -22571,7 +23372,7 @@ struct hwrm_func_ptp_ext_qcfg_output { ***************************/ -/* hwrm_func_key_ctx_alloc_input (size:320b/40B) */ +/* hwrm_func_key_ctx_alloc_input (size:384b/48B) */ struct hwrm_func_key_ctx_alloc_input { /* The HWRM command request type. */ uint16_t req_type; @@ -22603,9 +23404,26 @@ struct hwrm_func_key_ctx_alloc_input { uint64_t resp_addr; /* Function ID. */ uint16_t fid; - /* Number of Key Contexts to be allocated. */ + /* + * Number of Key Contexts to be allocated. + * When running in the XID partition mode, if the call is made by + * a VF driver, this field specifies the number of XIDs requested + * by the VF driver. The XID partitions are managed by the PF + * driver in XID partition mode and the VF command will be + * redirected to the PF driver. The PF driver may reduce this + * number if it cannot allocate a big enough block of XID + * partitions to satisfy the request. + * This field must not exceed the maximum batch size specified in + * the max_key_ctxs_alloc field of the HWRM_FUNC_QCAPS response, + * must not be zero, and must be integer multiples of the + * partition size specified in the ctxs_per_partition field of + * the HWRM_FUNC_QCAPS response. + */ uint16_t num_key_ctxs; - /* DMA buffer size in bytes. */ + /* + * DMA buffer size in bytes. This field in invalid in the XID + * partition mode. + */ uint32_t dma_bufr_size_bytes; /* Key Context type. */ uint8_t key_ctx_type; @@ -22624,11 +23442,24 @@ struct hwrm_func_key_ctx_alloc_input { #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_LAST \ HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_RX uint8_t unused_0[7]; - /* Host DMA address to send back KTLS context IDs. */ + /* + * Host DMA address to send back KTLS context IDs. This field is + * invalid in the XID partition mode. + */ uint64_t host_dma_addr; + /* + * This field is only used by the PF driver that manages the XID + * partitions. This field specifies the starting XID of one or + * more contiguous XID partitions allocated by the PF driver. + * This field is not used by the VF driver. + * If the call is successful, this starting XID value will be + * returned in the partition_start_xid field of the response. + */ + uint32_t partition_start_xid; + uint8_t unused_1[4]; } __rte_packed; -/* hwrm_func_key_ctx_alloc_output (size:128b/16B) */ +/* hwrm_func_key_ctx_alloc_output (size:192b/24B) */ struct hwrm_func_key_ctx_alloc_output { /* The specific error status for the command. */ uint16_t error_code; @@ -22638,7 +23469,7 @@ struct hwrm_func_key_ctx_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Actual number of Key Contexts allocated. */ + /* Number of Key Contexts that have been allocated. */ uint16_t num_key_ctxs_allocated; /* Control flags. */ uint8_t flags; @@ -22646,22 +23477,116 @@ struct hwrm_func_key_ctx_alloc_output { * When set, it indicates that all key contexts allocated by this * command are contiguous. As a result, the driver has to read the * start context ID from the first entry of the DMA data buffer - * and figures out the end context ID by “start context ID + - * num_key_ctxs_allocated - 1”. + * and figures out the end context ID by 'start context ID + + * num_key_ctxs_allocated - 1'. In XID partition mode, + * this bit should always be set. */ #define HWRM_FUNC_KEY_CTX_ALLOC_OUTPUT_FLAGS_KEY_CTXS_CONTIGUOUS \ UINT32_C(0x1) - uint8_t unused_0[4]; + uint8_t unused_0; + /* + * This field is only valid in the XID partition mode. It indicates + * the starting XID that has been allocated. + */ + uint32_t partition_start_xid; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; } __rte_packed; +/************************** + * hwrm_func_key_ctx_free * + **************************/ + + +/* hwrm_func_key_ctx_free_input (size:256b/32B) */ +struct hwrm_func_key_ctx_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Function ID. */ + uint16_t fid; + /* Key Context type. */ + uint8_t key_ctx_type; + /* KTLS Tx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_TX UINT32_C(0x0) + /* KTLS Rx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_RX UINT32_C(0x1) + /* QUIC Tx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_QUIC_TX UINT32_C(0x2) + /* QUIC Rx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_QUIC_RX UINT32_C(0x3) + #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_LAST \ + HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_QUIC_RX + uint8_t unused_0; + /* Starting XID of the partition that needs to be freed. */ + uint32_t partition_start_xid; + /* + * Number of entries to be freed. + * When running in the XID partition mode, this field is only + * used by the PF driver that manages the XID partitions. + * The PF driver specifies the number of XIDs to be freed and + * this number is always equal to the number of XIDs previously + * allocated successfully using HWRM_FUNC_KEY_CTX_ALLOC. + * This field is not used by the VF driver. + */ + uint16_t num_entries; + uint8_t unused_1[6]; +} __rte_packed; + +/* hwrm_func_key_ctx_free_output (size:128b/16B) */ +struct hwrm_func_key_ctx_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t rsvd0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been completely + * written. When writing a command completion or response to + * an internal processor, the order of writes has to be such + * that this field is written last. + */ + uint8_t valid; +} __rte_packed; + /********************************** * hwrm_func_backing_store_cfg_v2 * **********************************/ @@ -22747,12 +23672,33 @@ struct hwrm_func_backing_store_cfg_v2_input { /* CQ Doorbell shadow region. */ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW \ UINT32_C(0x19) - /* QUIC Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_TKC \ - UINT32_C(0x1a) - /* QUIC Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_RKC \ - UINT32_C(0x1b) + /* CFA table scope context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TBL_SCOPE \ + UINT32_C(0x1c) + /* XID partition context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_XID_PARTITION \ + UINT32_C(0x1d) + /* SRT trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRT_TRACE \ + UINT32_C(0x1e) + /* SRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRT2_TRACE \ + UINT32_C(0x1f) + /* CRT trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CRT_TRACE \ + UINT32_C(0x20) + /* CRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CRT2_TRACE \ + UINT32_C(0x21) + /* RIGP0 trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RIGP0_TRACE \ + UINT32_C(0x22) + /* L2 HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_L2_HWRM_TRACE \ + UINT32_C(0x23) + /* RoCE HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_ROCE_HWRM_TRACE \ + UINT32_C(0x24) /* Invalid type. */ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_INVALID \ UINT32_C(0xffff) @@ -22799,10 +23745,10 @@ struct hwrm_func_backing_store_cfg_v2_input { * The size specified in the command will be the new size to be * configured. The operation is only valid when the specific backing * store has been configured before. Otherwise, the firmware will - * return an error. The driver needs to zero out the “entry_size”, - * “flags”, “page_dir”, and “page_size_pbl_level” fields, and the + * return an error. The driver needs to zero out the 'entry_size', + * 'flags', 'page_dir', and 'page_size_pbl_level' fields, and the * firmware will ignore these inputs. Further, the firmware expects - * the “num_entries” and any valid split entries to be no less than + * the 'num_entries' and any valid split entries to be no less than * the initial value that has been configured. If not, it will * return an error code. */ @@ -22883,6 +23829,7 @@ struct hwrm_func_backing_store_cfg_v2_input { * | VINC | vnic_split_entries | * | MRAV | mrav_split_entries | * | TS | ts_split_entries | + * | CK | ck_split_entries | */ uint32_t split_entry_0; /* Split entry #1. */ @@ -22906,7 +23853,7 @@ struct hwrm_func_backing_store_cfg_v2_output { uint8_t rsvd0[7]; /* * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be + * output is completely written to RAM. This field should be * read as '1' to indicate that the output has been completely * written. When writing a command completion or response to * an internal processor, the order of writes has to be such @@ -23000,12 +23947,33 @@ struct hwrm_func_backing_store_qcfg_v2_input { /* CQ Doorbell shadow region. */ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ_DB_SHADOW \ UINT32_C(0x19) - /* QUIC Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QUIC_TKC \ - UINT32_C(0x1a) - /* QUIC Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QUIC_RKC \ - UINT32_C(0x1b) + /* CFA table scope context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TBL_SCOPE \ + UINT32_C(0x1c) + /* VF XID partition in-use table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_XID_PARTITION_TABLE \ + UINT32_C(0x1d) + /* SRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRT_TRACE \ + UINT32_C(0x1e) + /* SRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRT2_TRACE \ + UINT32_C(0x1f) + /* CRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CRT_TRACE \ + UINT32_C(0x20) + /* CRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CRT2_TRACE \ + UINT32_C(0x21) + /* RIGP0 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RIGP0_TRACE \ + UINT32_C(0x22) + /* L2 HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_L2_HWRM_TRACE \ + UINT32_C(0x23) + /* RoCE HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_ROCE_HWRM_TRACE \ + UINT32_C(0x24) /* Invalid type. */ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_INVALID \ UINT32_C(0xffff) @@ -23068,21 +24036,42 @@ struct hwrm_func_backing_store_qcfg_v2_output { /* TIM. */ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TIM \ UINT32_C(0xf) - /* Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TKC \ + /* Tx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TX_CK \ UINT32_C(0x13) - /* Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RKC \ + /* Rx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RX_CK \ UINT32_C(0x14) /* Mid-path TQM ring. */ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING \ UINT32_C(0x15) - /* QUIC Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QUIC_TKC \ - UINT32_C(0x1a) - /* QUIC Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QUIC_RKC \ - UINT32_C(0x1b) + /* CFA table scope context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TBL_SCOPE \ + UINT32_C(0x1c) + /* XID partition context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_XID_PARTITION \ + UINT32_C(0x1d) + /* SRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRT_TRACE \ + UINT32_C(0x1e) + /* SRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRT2_TRACE \ + UINT32_C(0x1f) + /* CRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CRT_TRACE \ + UINT32_C(0x20) + /* CRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CRT2_TRACE \ + UINT32_C(0x21) + /* RIGP0 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RIGP0_TRACE \ + UINT32_C(0x22) + /* L2 HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_L2_HWRM_TRACE \ + UINT32_C(0x23) + /* RoCE HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_ROCE_HWRM_TRACE \ + UINT32_C(0x24) /* Invalid type. */ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_INVALID \ UINT32_C(0xffff) @@ -23191,7 +24180,7 @@ struct hwrm_func_backing_store_qcfg_v2_output { uint8_t rsvd2[7]; /* * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be + * output is completely written to RAM. This field should be * read as '1' to indicate that the output has been completely * written. When writing a command completion or response to * an internal processor, the order of writes has to be such @@ -23200,6 +24189,7 @@ struct hwrm_func_backing_store_qcfg_v2_output { uint8_t valid; } __rte_packed; +/* Common structure to cast QPC split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is QPC. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ /* qpc_split_entries (size:128b/16B) */ struct qpc_split_entries { /* Number of L2 QP backing store entries. */ @@ -23214,6 +24204,7 @@ struct qpc_split_entries { uint32_t rsvd; } __rte_packed; +/* Common structure to cast SRQ split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is SRQ. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ /* srq_split_entries (size:128b/16B) */ struct srq_split_entries { /* Number of L2 SRQ backing store entries. */ @@ -23222,6 +24213,7 @@ struct srq_split_entries { uint32_t rsvd2[2]; } __rte_packed; +/* Common structure to cast CQ split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is CQ. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ /* cq_split_entries (size:128b/16B) */ struct cq_split_entries { /* Number of L2 CQ backing store entries. */ @@ -23230,6 +24222,7 @@ struct cq_split_entries { uint32_t rsvd2[2]; } __rte_packed; +/* Common structure to cast VNIC split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is VNIC. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ /* vnic_split_entries (size:128b/16B) */ struct vnic_split_entries { /* Number of VNIC backing store entries. */ @@ -23238,6 +24231,7 @@ struct vnic_split_entries { uint32_t rsvd2[2]; } __rte_packed; +/* Common structure to cast MRAV split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is MRAV. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ /* mrav_split_entries (size:128b/16B) */ struct mrav_split_entries { /* Number of AV backing store entries. */ @@ -23246,6 +24240,7 @@ struct mrav_split_entries { uint32_t rsvd2[2]; } __rte_packed; +/* Common structure to cast TBL_SCOPE split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is TBL_SCOPE. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ /* ts_split_entries (size:128b/16B) */ struct ts_split_entries { /* Max number of TBL_SCOPE region entries (QCAPS). */ @@ -23338,11 +24333,11 @@ struct hwrm_func_backing_store_qcaps_v2_input { /* TIM. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TIM \ UINT32_C(0xf) - /* Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TKC \ + /* Tx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TX_CK \ UINT32_C(0x13) - /* Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RKC \ + /* Rx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RX_CK \ UINT32_C(0x14) /* Mid-path TQM ring. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MP_TQM_RING \ @@ -23359,12 +24354,33 @@ struct hwrm_func_backing_store_qcaps_v2_input { /* CQ Doorbell shadow region. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ_DB_SHADOW \ UINT32_C(0x19) - /* QUIC Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QUIC_TKC \ - UINT32_C(0x1a) - /* QUIC Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QUIC_RKC \ - UINT32_C(0x1b) + /* CFA table scope context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TBL_SCOPE \ + UINT32_C(0x1c) + /* XID partition context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_XID_PARTITION \ + UINT32_C(0x1d) + /* SRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRT_TRACE \ + UINT32_C(0x1e) + /* SRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRT2_TRACE \ + UINT32_C(0x1f) + /* CRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CRT_TRACE \ + UINT32_C(0x20) + /* CRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CRT2_TRACE \ + UINT32_C(0x21) + /* RIGP0 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RIGP0_TRACE \ + UINT32_C(0x22) + /* L2 HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_L2_HWRM_TRACE \ + UINT32_C(0x23) + /* RoCE HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_ROCE_HWRM_TRACE \ + UINT32_C(0x24) /* Invalid type. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_INVALID \ UINT32_C(0xffff) @@ -23412,11 +24428,11 @@ struct hwrm_func_backing_store_qcaps_v2_output { /* TIM. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TIM \ UINT32_C(0xf) - /* KTLS Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TKC \ + /* Tx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TX_CK \ UINT32_C(0x13) - /* KTLS Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RKC \ + /* Rx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RX_CK \ UINT32_C(0x14) /* Mid-path TQM ring. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MP_TQM_RING \ @@ -23433,12 +24449,33 @@ struct hwrm_func_backing_store_qcaps_v2_output { /* CQ Doorbell shadow region. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ_DB_SHADOW \ UINT32_C(0x19) - /* QUIC Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QUIC_TKC \ - UINT32_C(0x1a) - /* QUIC Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QUIC_RKC \ - UINT32_C(0x1b) + /* CFA table scope context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TBL_SCOPE \ + UINT32_C(0x1c) + /* XID partition context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_XID_PARTITION \ + UINT32_C(0x1d) + /* SRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRT_TRACE \ + UINT32_C(0x1e) + /* SRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRT2_TRACE \ + UINT32_C(0x1f) + /* CRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CRT_TRACE \ + UINT32_C(0x20) + /* CRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CRT2_TRACE \ + UINT32_C(0x21) + /* RIGP0 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RIGP0_TRACE \ + UINT32_C(0x22) + /* L2 HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_L2_HWRM_TRACE \ + UINT32_C(0x23) + /* RoCE HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_ROCE_HWRM_TRACE \ + UINT32_C(0x24) /* Invalid type. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_INVALID \ UINT32_C(0xffff) @@ -23450,7 +24487,7 @@ struct hwrm_func_backing_store_qcaps_v2_output { uint32_t flags; /* * When set, it indicates the context type should be initialized - * with the “ctx_init_value” at the specified offset. + * with the 'ctx_init_value' at the specified offset. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ENABLE_CTX_KIND_INIT \ UINT32_C(0x1) @@ -23590,7 +24627,6 @@ struct hwrm_func_backing_store_qcaps_v2_output { * | VINC | vnic_split_entries | * | MRAV | mrav_split_entries | * | TS | ts_split_entries | - * | CK | ck_split_entries | */ uint32_t split_entry_0; /* Split entry #1. */ @@ -23602,7 +24638,7 @@ struct hwrm_func_backing_store_qcaps_v2_output { uint8_t rsvd3[3]; /* * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be + * output is completely written to RAM. This field should be * read as '1' to indicate that the output has been completely * written. When writing a command completion or response to * an internal processor, the order of writes has to be such @@ -23672,7 +24708,7 @@ struct hwrm_func_dbr_pacing_cfg_input { #define HWRM_FUNC_DBR_PACING_CFG_INPUT_ENABLES_PACING_THRESHOLD_VALID \ UINT32_C(0x2) /* - * Specify primary function’s NQ ID to receive the doorbell pacing + * Specify primary function's NQ ID to receive the doorbell pacing * threshold crossing events. */ uint32_t primary_nq_id; @@ -23697,7 +24733,7 @@ struct hwrm_func_dbr_pacing_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -23889,7 +24925,7 @@ struct hwrm_func_dbr_pacing_qcfg_output { /* This field indicates the maximum depth of the doorbell FIFO. */ uint32_t dbr_stat_db_max_fifo_depth; /* - * Specifies primary function’s NQ ID. + * Specifies primary function's NQ ID. * A value of 0xFFFF FFFF indicates NQ ID is invalid. */ uint32_t primary_nq_id; @@ -23901,7 +24937,7 @@ struct hwrm_func_dbr_pacing_qcfg_output { uint8_t unused_4[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -23960,7 +24996,7 @@ struct hwrm_func_dbr_pacing_broadcast_event_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -24053,9 +25089,9 @@ struct hwrm_func_dbr_pacing_nqlist_query_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -24122,7 +25158,7 @@ struct hwrm_func_dbr_recovery_completed_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -24235,9 +25271,9 @@ struct hwrm_func_synce_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -24318,112 +25354,21 @@ struct hwrm_func_synce_qcfg_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __rte_packed; - -/*********************** - * hwrm_func_vlan_qcfg * - ***********************/ - - -/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ -struct hwrm_func_vlan_qcfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. - */ - uint16_t fid; - uint8_t unused_0[6]; -} __rte_packed; - -/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ -struct hwrm_func_vlan_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint64_t unused_0; - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; - /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. - */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; - /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. - */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd2; - /* Future use. */ - uint32_t rsvd3; - uint8_t unused_3[3]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/********************** - * hwrm_func_vlan_cfg * - **********************/ +/************************ + * hwrm_func_lag_create * + ************************/ -/* hwrm_func_vlan_cfg_input (size:384b/48B) */ -struct hwrm_func_vlan_cfg_input { +/* hwrm_func_lag_create_input (size:192b/24B) */ +struct hwrm_func_lag_create_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24452,74 +25397,114 @@ struct hwrm_func_vlan_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint8_t enables; /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. - */ - uint16_t fid; - uint8_t unused_0[2]; - uint32_t enables; - /* - * This bit must be '1' for the stag_vid field to be - * configured. - */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1) - /* - * This bit must be '1' for the ctag_vid field to be - * configured. - */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2) - /* - * This bit must be '1' for the stag_pcp field to be - * configured. - */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4) - /* - * This bit must be '1' for the ctag_pcp field to be + * This bit must be '1' for the active_port_map field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8) - /* - * This bit must be '1' for the stag_tpid field to be - * configured. - */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10) + #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_ACTIVE_PORT_MAP \ + UINT32_C(0x1) /* - * This bit must be '1' for the ctag_tpid field to be + * This bit must be '1' for the member_port_map field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20) - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; - /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. - */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; - /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. - */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd1; - /* Future use. */ - uint32_t rsvd2; - uint8_t unused_3[4]; + #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_MEMBER_PORT_MAP \ + UINT32_C(0x2) + /* This bit must be '1' for the aggr_mode field to be configured. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_AGGR_MODE \ + UINT32_C(0x4) + /* rsvd1 is 5 b */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_RSVD1_MASK \ + UINT32_C(0xf8) + #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_RSVD1_SFT 3 + /* + * This is the bitmap of all active ports in the LAG. Each bit + * represents a front panel port of the device. Ports are numbered + * from 0 to n - 1 on a device with n ports. The number of front panel + * ports is specified in the port_cnt field of the HWRM_PORT_PHY_QCAPS + * response. The active_port_map must always be a subset of the + * member_port_map. An active port is eligible to send and receive + * traffic. + * + * If the LAG mode is active-backup, only one port can be an active + * port at a given time. All other ports in the member_port_map that + * are not the active port are backup port. When the active port + * fails, another member port takes over to become the active port. + * The driver should use HWRM_FUNC_LAG_UPDATE to update + * the active_port_map by only setting the port bit of the new active + * port. + * + * In active-active, balance_xor or 802_3_ad mode, all member ports + * can be active ports. If the driver determines that an active + * port is down or unable to function, it should use + * HWRM_FUNC_LAG_UPDATE to update the active_port_map by clearing + * the port bit that has failed. + */ + uint8_t active_port_map; + /* If this bit is set to '1', the port0 is a lag active port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_0 \ + UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag active port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_1 \ + UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag active port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_2 \ + UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag active port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_3 \ + UINT32_C(0x8) + /* rsvd3 is 4 b */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_RSVD3_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_RSVD3_SFT 4 + /* + * This is the bitmap of all member ports in the LAG. Each bit + * represents a front panel port of the device. Ports are numbered + * from 0 to n - 1 on a device with n ports. The number of front panel + * ports is specified in the port_cnt field of the HWRM_PORT_PHY_QCAPS + * response. There must be at least 2 ports in the member ports and + * each must not be a member of another LAG. Note that on a 4-port + * device, there can be either 2 ports or 4 ports in the member ports. + * Using 3 member ports is not supported. + */ + uint8_t member_port_map; + /* If this bit is set to '1', the port0 is a lag member port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_0 \ + UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag member port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_1 \ + UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag member port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_2 \ + UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag member port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_3 \ + UINT32_C(0x8) + /* rsvd4 is 4 b */ + #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_RSVD4_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_RSVD4_SFT 4 + /* Link aggregation mode being used. */ + uint8_t link_aggr_mode; + /* active active mode. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_ACTIVE_ACTIVE \ + UINT32_C(0x1) + /* active backup mode. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_ACTIVE_BACKUP \ + UINT32_C(0x2) + /* Balance XOR mode. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_BALANCE_XOR \ + UINT32_C(0x3) + /* 802.3AD mode. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_802_3_AD \ + UINT32_C(0x4) + #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_LAST \ + HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_802_3_AD + uint8_t unused_0[4]; } __rte_packed; -/* hwrm_func_vlan_cfg_output (size:128b/16B) */ -struct hwrm_func_vlan_cfg_output { +/* hwrm_func_lag_create_output (size:128b/16B) */ +struct hwrm_func_lag_create_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24528,24 +25513,29 @@ struct hwrm_func_vlan_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* + * LAG ID of the created LAG. This LAG ID will also be returned + * in the HWRM_FUNC_QCFG response of all member ports. + */ + uint8_t fw_lag_id; + uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/******************************* - * hwrm_func_vf_vnic_ids_query * - *******************************/ +/************************ + * hwrm_func_lag_update * + ************************/ -/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ -struct hwrm_func_vf_vnic_ids_query_input { +/* hwrm_func_lag_update_input (size:192b/24B) */ +struct hwrm_func_lag_update_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24574,20 +25564,116 @@ struct hwrm_func_vf_vnic_ids_query_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Link aggregation group ID of the LAG to be updated. */ + uint8_t fw_lag_id; + uint8_t enables; /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. + * This bit must be '1' for the active_port_map field to be + * updated. */ - uint16_t vf_id; - uint8_t unused_0[2]; - /* Max number of vnic ids in vnic id table */ - uint32_t max_vnic_id_cnt; - /* This is the address for VF VNIC ID table */ - uint64_t vnic_id_tbl_addr; + #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_ACTIVE_PORT_MAP \ + UINT32_C(0x1) + /* + * This bit must be '1' for the member_port_map field to be + * updated. + */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_MEMBER_PORT_MAP \ + UINT32_C(0x2) + /* This bit must be '1' for the aggr_mode field to be updated. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_AGGR_MODE \ + UINT32_C(0x4) + /* rsvd1 is 5 b */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_RSVD1_MASK \ + UINT32_C(0xf8) + #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_RSVD1_SFT 3 + /* + * This is the bitmap of all active ports in the LAG. Each bit + * represents a front panel port of the device. Ports are numbered + * from 0 to n - 1 on a device with n ports. The number of front panel + * ports is specified in the port_cnt field of the HWRM_PORT_PHY_QCAPS + * response. The active_port_map must always be a subset of the + * member_port_map. An active port is eligible to send and receive + * traffic. + * + * If the LAG mode is active-backup, only one port can be an active + * port at a given time. All other ports in the member_port_map that + * are not the active port are backup port. When the active port + * fails, another member port takes over to become the active port. + * The driver should use HWRM_FUNC_LAG_UPDATE to update + * the active_port_map by only setting the port bit of the new active + * port. + * + * In active-active, balance_xor or 802_3_ad mode, all member ports + * can be active ports. If the driver determines that an active + * port is down or unable to function, it should use + * HWRM_FUNC_LAG_UPDATE to update the active_port_map by clearing + * the port bit that has failed. + */ + uint8_t active_port_map; + /* If this bit is set to '1', the port0 is a lag active port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_0 \ + UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag active port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_1 \ + UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag active port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_2 \ + UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag active port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_3 \ + UINT32_C(0x8) + /* rsvd3 is 4 b */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_RSVD3_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_RSVD3_SFT 4 + /* + * This is the bitmap of all member ports in the LAG. Each bit + * represents a front panel port of the device. Ports are numbered + * from 0 to n - 1 on a device with n ports. The number of front panel + * ports is specified in the port_cnt field of the HWRM_PORT_PHY_QCAPS + * response. There must be at least 2 ports in the member ports and + * each must not be a member of another LAG. Note that on a 4-port + * device, there can be either 2 ports or 4 ports in the member ports. + * Using 3 member ports is not supported. + */ + uint8_t member_port_map; + /* If this bit is set to '1', the port0 is a lag member port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_0 \ + UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag member port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_1 \ + UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag member port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_2 \ + UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag member port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_3 \ + UINT32_C(0x8) + /* rsvd4 is 4 b */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_RSVD4_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_RSVD4_SFT 4 + /* Link aggregation mode being used. */ + uint8_t link_aggr_mode; + /* active active mode. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_ACTIVE_ACTIVE \ + UINT32_C(0x1) + /* active backup mode. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_ACTIVE_BACKUP \ + UINT32_C(0x2) + /* Balance XOR mode. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_BALANCE_XOR \ + UINT32_C(0x3) + /* 802.3AD mode. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_802_3_AD \ + UINT32_C(0x4) + #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_LAST \ + HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_802_3_AD + uint8_t unused_0[3]; } __rte_packed; -/* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */ -struct hwrm_func_vf_vnic_ids_query_output { +/* hwrm_func_lag_update_output (size:128b/16B) */ +struct hwrm_func_lag_update_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24596,30 +25682,24 @@ struct hwrm_func_vf_vnic_ids_query_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * Actual number of vnic ids - * - * Each VNIC ID is written as a 32-bit number. - */ - uint32_t vnic_id_cnt; - uint8_t unused_0[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/*********************** - * hwrm_func_vf_bw_cfg * - ***********************/ +/********************** + * hwrm_func_lag_free * + **********************/ -/* hwrm_func_vf_bw_cfg_input (size:960b/120B) */ -struct hwrm_func_vf_bw_cfg_input { +/* hwrm_func_lag_free_input (size:192b/24B) */ +struct hwrm_func_lag_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24648,77 +25728,13 @@ struct hwrm_func_vf_bw_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * The number of VF functions that are being configured. - * The cmd space allows up to 50 VFs' BW to be configured with one cmd. - */ - uint16_t num_vfs; - uint16_t unused[3]; - /* These 16-bit fields contain the VF fid and the rate scale percentage. */ - uint16_t vfn[48]; - /* The physical VF id the adjustment will be made to. */ - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff) - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0 - /* - * This field configures the rate scale percentage of the VF as specified - * by the physical VF id. - */ - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000) - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12 - /* 0% of the max tx rate */ - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \ - (UINT32_C(0x0) << 12) - /* 6.66% of the max tx rate */ - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \ - (UINT32_C(0x1) << 12) - /* 13.33% of the max tx rate */ - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \ - (UINT32_C(0x2) << 12) - /* 20% of the max tx rate */ - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \ - (UINT32_C(0x3) << 12) - /* 26.66% of the max tx rate */ - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \ - (UINT32_C(0x4) << 12) - /* 33% of the max tx rate */ - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \ - (UINT32_C(0x5) << 12) - /* 40% of the max tx rate */ - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \ - (UINT32_C(0x6) << 12) - /* 46.66% of the max tx rate */ - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \ - (UINT32_C(0x7) << 12) - /* 53.33% of the max tx rate */ - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \ - (UINT32_C(0x8) << 12) - /* 60% of the max tx rate */ - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \ - (UINT32_C(0x9) << 12) - /* 66.66% of the max tx rate */ - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \ - (UINT32_C(0xa) << 12) - /* 53.33% of the max tx rate */ - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \ - (UINT32_C(0xb) << 12) - /* 80% of the max tx rate */ - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \ - (UINT32_C(0xc) << 12) - /* 86.66% of the max tx rate */ - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \ - (UINT32_C(0xd) << 12) - /* 93.33% of the max tx rate */ - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \ - (UINT32_C(0xe) << 12) - /* 100% of the max tx rate */ - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \ - (UINT32_C(0xf) << 12) - #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \ - HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 + /* Link aggregation group ID of the LAG to be freed. */ + uint8_t fw_lag_id; + uint8_t unused_0[7]; } __rte_packed; -/* hwrm_func_vf_bw_cfg_output (size:128b/16B) */ -struct hwrm_func_vf_bw_cfg_output { +/* hwrm_func_lag_free_output (size:128b/16B) */ +struct hwrm_func_lag_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24730,21 +25746,21 @@ struct hwrm_func_vf_bw_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/************************ - * hwrm_func_vf_bw_qcfg * - ************************/ +/********************** + * hwrm_func_lag_qcfg * + **********************/ -/* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */ -struct hwrm_func_vf_bw_qcfg_input { +/* hwrm_func_lag_qcfg_input (size:192b/24B) */ +struct hwrm_func_lag_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24773,22 +25789,13 @@ struct hwrm_func_vf_bw_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * The number of VF functions that are being queried. - * The inline response space allows the host to query up to 50 VFs' - * rate scale percentage - */ - uint16_t num_vfs; - uint16_t unused[3]; - /* These 16-bit fields contain the VF fid */ - uint16_t vfn[48]; - /* The physical VF id of interest */ - #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff) - #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0 + /* Link aggregation group ID of the LAG to be queried. */ + uint8_t fw_lag_id; + uint8_t unused_0[7]; } __rte_packed; -/* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */ -struct hwrm_func_vf_bw_qcfg_output { +/* hwrm_func_lag_qcfg_output (size:128b/16B) */ +struct hwrm_func_lag_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24798,91 +25805,102 @@ struct hwrm_func_vf_bw_qcfg_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * The number of VF functions that are being queried. - * The inline response space allows the host to query up to 50 VFs' rate - * scale percentage - */ - uint16_t num_vfs; - uint16_t unused[3]; - /* These 16-bit fields contain the VF fid and the rate scale percentage. */ - uint16_t vfn[48]; - /* The physical VF id the adjustment will be made to. */ - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff) - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0 - /* - * This field configures the rate scale percentage of the VF as specified - * by the physical VF id. - */ - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000) - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12 - /* 0% of the max tx rate */ - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \ - (UINT32_C(0x0) << 12) - /* 6.66% of the max tx rate */ - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \ - (UINT32_C(0x1) << 12) - /* 13.33% of the max tx rate */ - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \ - (UINT32_C(0x2) << 12) - /* 20% of the max tx rate */ - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \ - (UINT32_C(0x3) << 12) - /* 26.66% of the max tx rate */ - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \ - (UINT32_C(0x4) << 12) - /* 33% of the max tx rate */ - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \ - (UINT32_C(0x5) << 12) - /* 40% of the max tx rate */ - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \ - (UINT32_C(0x6) << 12) - /* 46.66% of the max tx rate */ - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \ - (UINT32_C(0x7) << 12) - /* 53.33% of the max tx rate */ - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \ - (UINT32_C(0x8) << 12) - /* 60% of the max tx rate */ - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \ - (UINT32_C(0x9) << 12) - /* 66.66% of the max tx rate */ - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \ - (UINT32_C(0xa) << 12) - /* 53.33% of the max tx rate */ - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \ - (UINT32_C(0xb) << 12) - /* 80% of the max tx rate */ - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \ - (UINT32_C(0xc) << 12) - /* 86.66% of the max tx rate */ - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \ - (UINT32_C(0xd) << 12) - /* 93.33% of the max tx rate */ - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \ - (UINT32_C(0xe) << 12) - /* 100% of the max tx rate */ - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \ - (UINT32_C(0xf) << 12) - #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \ - HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 - uint8_t unused_0[7]; + * This is the bitmap of all active ports in the LAG. Each bit + * represents a front panel port of the device. Ports are numbered + * from 0 to n - 1 on a device with n ports. The number of front panel + * ports is specified in the port_cnt field of the HWRM_PORT_PHY_QCAPS + * response. The active_port_map must always be a subset of the + * member_port_map. An active port is eligible to send and receive + * traffic. + * + * If the LAG mode is active-backup, only one port can be an active + * port at a given time. All other ports in the member_port_map that + * are not the active port are backup port. When the active port + * fails, another member port takes over to become the active port. + * The driver should use HWRM_FUNC_LAG_UPDATE to update + * the active_port_map by only setting the port bit of the new active + * port. + * + * In active-active, balance_xor or 802_3_ad mode, all member ports + * can be active ports. If the driver determines that an active + * port is down or unable to function, it should use + * HWRM_FUNC_LAG_UPDATE to update the active_port_map by clearing + * the port bit that has failed. + */ + uint8_t active_port_map; + /* If this bit is set to '1', the port0 is a lag active port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_0 \ + UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag active port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_1 \ + UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag active port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_2 \ + UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag active port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_3 \ + UINT32_C(0x8) + /* rsvd3 is 4 b */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_RSVD3_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_RSVD3_SFT 4 + /* + * This is the bitmap of all member ports in the LAG. Each bit + * represents a front panel port of the device. Ports are numbered + * from 0 to n - 1 on a device with n ports. The number of front panel + * ports is specified in the port_cnt field of the HWRM_PORT_PHY_QCAPS + * response. There must be at least 2 ports in the member ports and + * each must not be a member of another LAG. Note that on a 4-port + * device, there can be either 2 ports or 4 ports in the member ports. + * Using 3 member ports is not supported. + */ + uint8_t member_port_map; + /* If this bit is set to '1', the port0 is a lag member port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_0 \ + UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag member port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_1 \ + UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag member port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_2 \ + UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag member port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_3 \ + UINT32_C(0x8) + /* rsvd4 is 4 b */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_RSVD4_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_RSVD4_SFT 4 + /* Link aggregation mode being used. */ + uint8_t link_aggr_mode; + /* active active mode. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1) + /* active backup mode. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2) + /* Balance XOR mode. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3) + /* 802.3AD mode. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_802_3_AD UINT32_C(0x4) + #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_LAST \ + HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_802_3_AD + uint8_t unused_0[4]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/*************************** - * hwrm_func_drv_if_change * - ***************************/ +/************************** + * hwrm_func_lag_mode_cfg * + **************************/ -/* hwrm_func_drv_if_change_input (size:192b/24B) */ -struct hwrm_func_drv_if_change_input { +/* hwrm_func_lag_mode_cfg_input (size:192b/24B) */ +struct hwrm_func_lag_mode_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24911,26 +25929,144 @@ struct hwrm_func_drv_if_change_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; + uint8_t enables; /* - * When this bit is '1', the function driver is indicating - * that the IF state is changing to UP state. The call should - * be made at the beginning of the driver's open call before - * resources are allocated. After making the call, the driver - * should check the response to see if any resources may have - * changed (see the response below). If the driver fails - * the open call, the driver should make this call again with - * this bit cleared to indicate that the IF state is not UP. - * During the driver's close call when the IF state is changing - * to DOWN, the driver should make this call with the bit cleared - * after all resources have been freed. + * This bit must be '1' for the link aggregation enable or + * disable flags to be configured. */ - #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1) - uint32_t unused; + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_FLAGS \ + UINT32_C(0x1) + /* + * This bit must be '1' for the active_port_map field to be + * configured. + */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_ACTIVE_PORT_MAP \ + UINT32_C(0x2) + /* + * This bit must be '1' for the member_port_map field to be + * configured. + */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_MEMBER_PORT_MAP \ + UINT32_C(0x4) + /* This bit must be '1' for the aggr_mode field to be configured. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_AGGR_MODE \ + UINT32_C(0x8) + /* This bit must be '1' for the lag id field to be configured. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_LAG_ID \ + UINT32_C(0x10) + /* rsvd1 is 3 b */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_RSVD1_MASK \ + UINT32_C(0xe0) + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_RSVD1_SFT 5 + uint8_t flags; + /* + * If this bit is set to 1, the driver is requesting FW to disable + * link aggregation feature during run time. + */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_AGGR_DISABLE \ + UINT32_C(0x1) + /* + * If this bit is set to 1, the driver is requesting FW to enable + * link aggregation feature during run time. + */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_AGGR_ENABLE \ + UINT32_C(0x2) + /* rsvd2 is 6 b */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_RSVD2_MASK \ + UINT32_C(0xfc) + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_RSVD2_SFT 2 + /* + * This is the bitmap of all active ports in the LAG. Each bit + * represents a front panel port of the device starting from port 0. + * The number of front panel ports is specified in the port_cnt field + * of the HWRM_PORT_PHY_QCAPS response. + * The term "active port" is one of member ports which is eligible to + * send or receive the traffic. + * In the active-backup mode, only one member port is active port at + * any given time. If the active port fails, another member port + * automatically takes over the active role to ensure continuous + * network connectivity. + * In the active-active, balance_xor or 802_3_ad mode, all member ports + * could be active port, if link status on one port is down, driver + * needs to send the NIC a new active-port bitmap with marking this + * port as not active port. + * The PORT_2 and PORT_3 are only valid if the NIC has four front + * panel ports. + */ + uint8_t active_port_map; + /* If this bit is set to '1', the port0 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_0 \ + UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_1 \ + UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_2 \ + UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_3 \ + UINT32_C(0x8) + /* rsvd3 is 4 b */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_RSVD3_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_RSVD3_SFT 4 + /* + * This is the bitmap of all member ports in the LAG. Each bit + * represents a front panel port of the device starting from port 0. + * The number of front panel ports is specified in the port_cnt field + * of the HWRM_PORT_PHY_QCAPS response. + * The term "member port" refers to a front panel port that is added to + * the bond group as a slave device. These member ports are combined to + * create a logical bond interface. + * For a 4-port NIC, the LAG member port combination can consist of + * either two ports or four ports. However, it is important to note + * that the case with three ports in the same lag group is not + * supported. + * The PORT_2 and PORT_3 are only valid if the NIC has four front + * panel ports. There could be a case to use multiple LAG groups, + * for example, if the NIC has four front panel ports, the lag feature + * can use up to two LAG groups, with two ports assigned to each group. + */ + uint8_t member_port_map; + /* If this bit is set to '1', the port0 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_0 \ + UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_1 \ + UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_2 \ + UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_3 \ + UINT32_C(0x8) + /* rsvd4 is 4 b */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_RSVD4_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_RSVD4_SFT 4 + /* Link aggregation mode being used. */ + uint8_t link_aggr_mode; + /* active active mode. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_ACTIVE_ACTIVE \ + UINT32_C(0x1) + /* active backup mode. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_ACTIVE_BACKUP \ + UINT32_C(0x2) + /* Balance XOR mode. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_BALANCE_XOR \ + UINT32_C(0x3) + /* 802.3AD mode. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_802_3_AD \ + UINT32_C(0x4) + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_LAST \ + HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_802_3_AD + /* Link aggregation group idx being used. */ + uint8_t lag_id; + uint8_t unused_0[2]; } __rte_packed; -/* hwrm_func_drv_if_change_output (size:128b/16B) */ -struct hwrm_func_drv_if_change_output { +/* hwrm_func_lag_mode_cfg_output (size:128b/16B) */ +struct hwrm_func_lag_mode_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24939,39 +26075,26 @@ struct hwrm_func_drv_if_change_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; - /* - * When this bit is '1', it indicates that the resources reserved - * for this function may have changed. The driver should check - * resource capabilities and reserve resources again before - * allocating resources. - */ - #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \ - UINT32_C(0x1) - /* - * When this bit is '1', it indicates that the firmware got changed / reset. - * The driver should do complete re-initialization when that bit is set. - */ - #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \ - UINT32_C(0x2) - uint8_t unused_0[3]; + /* Link aggregation group idx being used. */ + uint8_t lag_id; + uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/******************************* - * hwrm_func_host_pf_ids_query * - *******************************/ +/*************************** + * hwrm_func_lag_mode_qcfg * + ***************************/ -/* hwrm_func_host_pf_ids_query_input (size:192b/24B) */ -struct hwrm_func_host_pf_ids_query_input { +/* hwrm_func_lag_mode_qcfg_input (size:192b/24B) */ +struct hwrm_func_lag_mode_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25000,59 +26123,11 @@ struct hwrm_func_host_pf_ids_query_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t host; - /* - * # If this bit is set to '1', the query will contain PF(s) - * belongs to SOC host. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1) - /* - * # If this bit is set to '1', the query will contain PF(s) - * belongs to EP0 host. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2) - /* - * # If this bit is set to '1', the query will contain PF(s) - * belongs to EP1 host. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4) - /* - * # If this bit is set to '1', the query will contain PF(s) - * belongs to EP2 host. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8) - /* - * # If this bit is set to '1', the query will contain PF(s) - * belongs to EP3 host. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10) - /* - * This provides a filter of what PF(s) will be returned in the - * query.. - */ - uint8_t filter; - /* - * all available PF(s) belong to the host(s) (defined in the - * host field). This includes the hidden PFs. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0) - /* - * all available PF(s) belong to the host(s) (defined in the - * host field) that is available for L2 traffic. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1) - /* - * all available PF(s) belong to the host(s) (defined in the - * host field) that is available for ROCE traffic. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2) - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \ - HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE - uint8_t unused_1[6]; + uint8_t unused_0[8]; } __rte_packed; -/* hwrm_func_host_pf_ids_query_output (size:128b/16B) */ -struct hwrm_func_host_pf_ids_query_output { +/* hwrm_func_lag_mode_qcfg_output (size:128b/16B) */ +struct hwrm_func_lag_mode_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25061,123 +26136,118 @@ struct hwrm_func_host_pf_ids_query_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This provides the first PF ID of the device. */ - uint16_t first_pf_id; - uint16_t pf_ordinal_mask; - /* - * When this bit is '1', it indicates first PF belongs to one of - * the hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \ + uint8_t aggr_enabled; + /* + * This flag is used to query whether link aggregation is enabled + * or disabled during run time. + */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_ENABLED UINT32_C(0x1) + /* rsvd1 is 7 b */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_RSVD1_MASK UINT32_C(0xfe) + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_RSVD1_SFT 1 + /* + * This is the bitmap of all active ports in the LAG. Each bit + * represents a front panel port of the device starting from port 0. + * The number of front panel ports is specified in the port_cnt field + * of the HWRM_PORT_PHY_QCAPS response. + * The term "active port" is one of member ports which is eligible to + * send or receive the traffic. + * In the active-backup mode, only one member port is active port at + * any given time. If the active port fails, another member port + * automatically takes over the active role to ensure continuous + * network connectivity. + * In the active-active, balance_xor or 802_3_ad mode, all member ports + * could be active port, if link status on one port is down, driver + * needs to send the NIC a new active-port bitmap with marking this + * port as not active port. + * The PORT_2 and PORT_3 are only valid if the NIC has four front + * panel ports. + */ + uint8_t active_port_map; + /* If this bit is set to '1', the port0 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_0 \ UINT32_C(0x1) - /* - * When this bit is '1', it indicates 2nd PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \ + /* If this bit is set to '1', the port1 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_1 \ UINT32_C(0x2) - /* - * When this bit is '1', it indicates 3rd PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \ + /* If this bit is set to '1', the port2 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_2 \ UINT32_C(0x4) - /* - * When this bit is '1', it indicates 4th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \ + /* If this bit is set to '1', the port3 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_3 \ UINT32_C(0x8) - /* - * When this bit is '1', it indicates 5th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \ - UINT32_C(0x10) - /* - * When this bit is '1', it indicates 6th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \ - UINT32_C(0x20) - /* - * When this bit is '1', it indicates 7th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \ - UINT32_C(0x40) - /* - * When this bit is '1', it indicates 8th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \ - UINT32_C(0x80) - /* - * When this bit is '1', it indicates 9th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \ - UINT32_C(0x100) - /* - * When this bit is '1', it indicates 10th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \ - UINT32_C(0x200) - /* - * When this bit is '1', it indicates 11th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \ - UINT32_C(0x400) - /* - * When this bit is '1', it indicates 12th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \ - UINT32_C(0x800) - /* - * When this bit is '1', it indicates 13th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \ - UINT32_C(0x1000) - /* - * When this bit is '1', it indicates 14th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \ - UINT32_C(0x2000) - /* - * When this bit is '1', it indicates 15th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \ - UINT32_C(0x4000) - /* - * When this bit is '1', it indicates 16th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \ - UINT32_C(0x8000) - uint8_t unused_1[3]; + /* rsvd2 is 4 b */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_RSVD2_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_RSVD2_SFT 4 + /* + * This is the bitmap of all member ports in the LAG. Each bit + * represents a front panel port of the device starting from port 0. + * The number of front panel ports is specified in the port_cnt field + * of the HWRM_PORT_PHY_QCAPS response. + * The term "member port" refers to a front panel port that is added to + * the bond group as a slave device. These member ports are combined to + * create a logical bond interface. + * For a 4-port NIC, the LAG member port combination can consist of + * either two ports or four ports. However, it is important to note + * that the case with three ports in the same lag group is not + * supported. + * The PORT_2 and PORT_3 are only valid if the NIC has four front + * panel ports. There could be a case to use multiple LAG groups, + * for example, if the NIC has four front panel ports, the lag feature + * can use up to two LAG groups, with two ports assigned to each group. + */ + uint8_t member_port_map; + /* If this bit is set to '1', the port0 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_0 \ + UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_1 \ + UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_2 \ + UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_3 \ + UINT32_C(0x8) + /* rsvd3 is 4 b */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_RSVD3_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_RSVD3_SFT 4 + /* Link aggregation mode being used. */ + uint8_t link_aggr_mode; + /* active active mode. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_ACTIVE_ACTIVE \ + UINT32_C(0x1) + /* active backup mode. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_ACTIVE_BACKUP \ + UINT32_C(0x2) + /* Balance XOR mode. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_BALANCE_XOR \ + UINT32_C(0x3) + /* 802.3AD mode. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_802_3_AD \ + UINT32_C(0x4) + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_LAST \ + HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_802_3_AD + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/********************* - * hwrm_func_spd_cfg * - *********************/ +/*********************** + * hwrm_func_vlan_qcfg * + ***********************/ -/* hwrm_func_spd_cfg_input (size:384b/48B) */ -struct hwrm_func_spd_cfg_input { +/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ +struct hwrm_func_vlan_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25206,157 +26276,165 @@ struct hwrm_func_spd_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* Set this bit is '1' to enable the SPD datapath forwarding. */ - #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_ENABLE UINT32_C(0x1) - /* Set this bit is '1' to disable the SPD datapath forwarding. */ - #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_DISABLE UINT32_C(0x2) /* - * Set this bit is '1' to enable the SPD datapath checksum - * feature. + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. */ - #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_ENABLE UINT32_C(0x4) + uint16_t fid; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ +struct hwrm_func_vlan_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint64_t unused_0; + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; /* - * Set this bit is '1' to disable the SPD datapath checksum - * feature. + * S-TAG TPID value configured for the function. This field is + * specified in network byte order. */ - #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_DISABLE UINT32_C(0x8) + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; /* - * Set this bit is '1' to enable the SPD datapath debug - * feature. + * C-TAG TPID value configured for the function. This field is + * specified in network byte order. */ - #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_ENABLE UINT32_C(0x10) + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd2; + /* Future use. */ + uint32_t rsvd3; + uint8_t unused_3[3]; /* - * Set this bit is '1' to disable the SPD datapath debug - * feature. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_DISABLE UINT32_C(0x20) - uint32_t enables; + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_func_vlan_cfg * + **********************/ + + +/* hwrm_func_vlan_cfg_input (size:384b/48B) */ +struct hwrm_func_vlan_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This bit must be '1' for the ethertype field to be - * configured. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_ETHERTYPE \ - UINT32_C(0x1) + uint16_t cmpl_ring; /* - * This bit must be '1' for the hash_mode_flags field to be - * configured. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_MODE_FLAGS \ - UINT32_C(0x2) + uint16_t seq_id; /* - * This bit must be '1' for the hash_type field to be - * configured. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_TYPE \ - UINT32_C(0x4) + uint16_t target_id; /* - * This bit must be '1' for the ring_tbl_addr field to be - * configured. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_RING_TBL_ADDR \ - UINT32_C(0x8) + uint64_t resp_addr; /* - * This bit must be '1' for the hash_key_tbl_addr field to be + * Function ID of the function that is being * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. */ - #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_KEY_TBL_ADDR \ - UINT32_C(0x10) + uint16_t fid; + uint8_t unused_0[2]; + uint32_t enables; /* - * Ethertype value used in the encapsulated SPD packet header. - * The user must choose a value that is not conflicting with - * publicly defined ethertype values. By default, the ethertype - * value of 0xffff is used if there is no user specified value. + * This bit must be '1' for the stag_vid field to be + * configured. */ - uint16_t ethertype; - /* Flags to specify different RSS hash modes. */ - uint8_t hash_mode_flags; + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1) /* - * When this bit is '1', it indicates using current RSS - * hash mode setting configured in the device. + * This bit must be '1' for the ctag_vid field to be + * configured. */ - #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \ - UINT32_C(0x1) + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2) /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 4 tuples {l3.src, l3.dest, - * l4.src, l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. + * This bit must be '1' for the stag_pcp field to be + * configured. */ - #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \ - UINT32_C(0x2) + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4) /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. + * This bit must be '1' for the ctag_pcp field to be + * configured. */ - #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \ - UINT32_C(0x4) + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8) /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, - * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. + * This bit must be '1' for the stag_tpid field to be + * configured. */ - #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ - UINT32_C(0x8) + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10) /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. + * This bit must be '1' for the ctag_tpid field to be + * configured. */ - #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ - UINT32_C(0x10) + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20) + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; uint8_t unused_1; - uint32_t hash_type; - /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv4 - * packets. - */ - #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of TCP/IPv4 packets. - */ - #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of UDP/IPv4 packets. - */ - #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) - /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv6 - * packets. - */ - #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8) /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of TCP/IPv6 packets. + * S-TAG TPID value configured for the function. This field is + * specified in network byte order. */ - #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of UDP/IPv6 packets. + * C-TAG TPID value configured for the function. This field is + * specified in network byte order. */ - #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) - /* This is the address for rss ring group table */ - uint64_t ring_grp_tbl_addr; - /* This is the address for rss hash key table */ - uint64_t hash_key_tbl_addr; + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd1; + /* Future use. */ + uint32_t rsvd2; + uint8_t unused_3[4]; } __rte_packed; -/* hwrm_func_spd_cfg_output (size:128b/16B) */ -struct hwrm_func_spd_cfg_output { +/* hwrm_func_vlan_cfg_output (size:128b/16B) */ +struct hwrm_func_vlan_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25368,21 +26446,21 @@ struct hwrm_func_spd_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/********************** - * hwrm_func_spd_qcfg * - **********************/ +/******************************* + * hwrm_func_vf_vnic_ids_query * + *******************************/ -/* hwrm_func_spd_qcfg_input (size:128b/16B) */ -struct hwrm_func_spd_qcfg_input { +/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ +struct hwrm_func_vf_vnic_ids_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25411,10 +26489,20 @@ struct hwrm_func_spd_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. + */ + uint16_t vf_id; + uint8_t unused_0[2]; + /* Max number of vnic ids in vnic id table */ + uint32_t max_vnic_id_cnt; + /* This is the address for VF VNIC ID table */ + uint64_t vnic_id_tbl_addr; } __rte_packed; -/* hwrm_func_spd_qcfg_output (size:512b/64B) */ -struct hwrm_func_spd_qcfg_output { +/* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */ +struct hwrm_func_vf_vnic_ids_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25423,129 +26511,155 @@ struct hwrm_func_spd_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; - /* - * The SPD datapath forwarding is currently enabled when this - * flag is set to '1'. - */ - #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_FWD_ENABLED UINT32_C(0x1) - /* - * The SPD datapath checksum feature is currently enabled when - * this flag is set to '1'. - */ - #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_CSUM_ENABLED UINT32_C(0x2) - /* - * The SPD datapath debug feature is currently enabled when - * this flag is set to '1'. - */ - #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_DBG_ENABLED UINT32_C(0x4) - uint32_t hash_type; - /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv4 - * packets. - */ - #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of TCP/IPv4 packets. - */ - #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of UDP/IPv4 packets. - */ - #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) - /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv6 - * packets. - */ - #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of TCP/IPv6 packets. + * Actual number of vnic ids + * + * Each VNIC ID is written as a 32-bit number. */ - #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + uint32_t vnic_id_cnt; + uint8_t unused_0[3]; /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of UDP/IPv6 packets. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) - /* This is the value of rss hash key */ - uint32_t hash_key[10]; - /* Flags to specify different RSS hash modes. */ - uint8_t hash_mode_flags; + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_func_vf_bw_cfg * + ***********************/ + + +/* hwrm_func_vf_bw_cfg_input (size:960b/120B) */ +struct hwrm_func_vf_bw_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * When this bit is '1', it indicates using current RSS - * hash mode setting configured in the device. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \ - UINT32_C(0x1) + uint16_t cmpl_ring; /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 4 tuples {l3.src, l3.dest, - * l4.src, l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \ - UINT32_C(0x2) + uint16_t seq_id; /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \ - UINT32_C(0x4) + uint16_t target_id; /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, - * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ - UINT32_C(0x8) + uint64_t resp_addr; /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. + * The number of VF functions that are being configured. + * The cmd space allows up to 50 VFs' BW to be configured with one cmd. */ - #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ - UINT32_C(0x10) - uint8_t unused_1; + uint16_t num_vfs; + uint16_t unused[3]; + /* These 16-bit fields contain the VF fid and the rate scale percentage. */ + uint16_t vfn[48]; + /* The physical VF id the adjustment will be made to. */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff) + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0 /* - * Ethertype value used in the encapsulated SPD packet header. - * The user must choose a value that is not conflicting with - * publicly defined ethertype values. By default, the ethertype - * value of 0xffff is used if there is no user specified value. + * This field configures the rate scale percentage of the VF as specified + * by the physical VF id. */ - uint16_t ethertype; - uint8_t unused_2[3]; + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000) + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12 + /* 0% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \ + (UINT32_C(0x0) << 12) + /* 6.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \ + (UINT32_C(0x1) << 12) + /* 13.33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \ + (UINT32_C(0x2) << 12) + /* 20% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \ + (UINT32_C(0x3) << 12) + /* 26.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \ + (UINT32_C(0x4) << 12) + /* 33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \ + (UINT32_C(0x5) << 12) + /* 40% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \ + (UINT32_C(0x6) << 12) + /* 46.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \ + (UINT32_C(0x7) << 12) + /* 53.33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \ + (UINT32_C(0x8) << 12) + /* 60% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \ + (UINT32_C(0x9) << 12) + /* 66.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \ + (UINT32_C(0xa) << 12) + /* 53.33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \ + (UINT32_C(0xb) << 12) + /* 80% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \ + (UINT32_C(0xc) << 12) + /* 86.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \ + (UINT32_C(0xd) << 12) + /* 93.33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \ + (UINT32_C(0xe) << 12) + /* 100% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \ + (UINT32_C(0xf) << 12) + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \ + HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 +} __rte_packed; + +/* hwrm_func_vf_bw_cfg_output (size:128b/16B) */ +struct hwrm_func_vf_bw_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/********************* - * hwrm_port_phy_cfg * - *********************/ +/************************ + * hwrm_func_vf_bw_qcfg * + ************************/ -/* hwrm_port_phy_cfg_input (size:512b/64B) */ -struct hwrm_port_phy_cfg_input { +/* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */ +struct hwrm_func_vf_bw_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25574,765 +26688,601 @@ struct hwrm_port_phy_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; /* - * When this bit is set to '1', the PHY for the port shall - * be reset. - * - * # If this bit is set to 1, then the HWRM shall reset the - * PHY after applying PHY configuration changes specified - * in this command. - * # In order to guarantee that PHY configuration changes - * specified in this command take effect, the HWRM - * client should set this flag to 1. - * # If this bit is not set to 1, then the HWRM may reset - * the PHY depending on the current PHY configuration and - * settings specified in this command. + * The number of VF functions that are being queried. + * The inline response space allows the host to query up to 50 VFs' + * rate scale percentage */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \ - UINT32_C(0x1) - /* deprecated bit. Do not use!!! */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \ - UINT32_C(0x2) + uint16_t num_vfs; + uint16_t unused[3]; + /* These 16-bit fields contain the VF fid */ + uint16_t vfn[48]; + /* The physical VF id of interest */ + #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff) + #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0 +} __rte_packed; + +/* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */ +struct hwrm_func_vf_bw_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; /* - * When this bit is set to '1', and the force_pam4_link_speed - * bit in the 'enables' field is '0', the link shall be forced - * to the force_link_speed value. - * - * When this bit is set to '1', and the force_pam4_link_speed - * bit in the 'enables' field is '1', the link shall be forced - * to the force_pam4_link_speed value. - * - * When this bit is set to '1', the HWRM client should - * not enable any of the auto negotiation related - * fields represented by auto_XXX fields in this command. - * When this bit is set to '1' and the HWRM client has - * enabled a auto_XXX field in this command, then the - * HWRM shall ignore the enabled auto_XXX field. - * - * When this bit is set to zero, the link - * shall be allowed to autoneg. + * The number of VF functions that are being queried. + * The inline response space allows the host to query up to 50 VFs' + * rate scale percentage. */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \ - UINT32_C(0x4) + uint16_t num_vfs; + uint16_t unused[3]; + /* These 16-bit fields contain the VF fid and the rate scale percentage. */ + uint16_t vfn[48]; + /* The physical VF id the adjustment will be made to. */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff) + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0 /* - * When this bit is set to '1', the auto-negotiation process - * shall be restarted on the link. + * This field configures the rate scale percentage of the VF as specified + * by the physical VF id. */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \ - UINT32_C(0x8) + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000) + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12 + /* 0% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \ + (UINT32_C(0x0) << 12) + /* 6.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \ + (UINT32_C(0x1) << 12) + /* 13.33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \ + (UINT32_C(0x2) << 12) + /* 20% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \ + (UINT32_C(0x3) << 12) + /* 26.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \ + (UINT32_C(0x4) << 12) + /* 33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \ + (UINT32_C(0x5) << 12) + /* 40% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \ + (UINT32_C(0x6) << 12) + /* 46.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \ + (UINT32_C(0x7) << 12) + /* 53.33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \ + (UINT32_C(0x8) << 12) + /* 60% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \ + (UINT32_C(0x9) << 12) + /* 66.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \ + (UINT32_C(0xa) << 12) + /* 53.33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \ + (UINT32_C(0xb) << 12) + /* 80% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \ + (UINT32_C(0xc) << 12) + /* 86.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \ + (UINT32_C(0xd) << 12) + /* 93.33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \ + (UINT32_C(0xe) << 12) + /* 100% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \ + (UINT32_C(0xf) << 12) + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \ + HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 + uint8_t unused_0[7]; /* - * When this bit is set to '1', Energy Efficient Ethernet - * (EEE) is requested to be enabled on this link. - * If EEE is not supported on this port, then this flag - * shall be ignored by the HWRM. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \ - UINT32_C(0x10) + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_func_drv_if_change * + ***************************/ + + +/* hwrm_func_drv_if_change_input (size:192b/24B) */ +struct hwrm_func_drv_if_change_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * When this bit is set to '1', Energy Efficient Ethernet - * (EEE) is requested to be disabled on this link. - * If EEE is not supported on this port, then this flag - * shall be ignored by the HWRM. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \ - UINT32_C(0x20) + uint16_t cmpl_ring; /* - * When this bit is set to '1' and EEE is enabled on this - * link, then TX LPI is requested to be enabled on the link. - * If EEE is not supported on this port, then this flag - * shall be ignored by the HWRM. - * If EEE is disabled on this port, then this flag shall be - * ignored by the HWRM. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \ - UINT32_C(0x40) + uint16_t seq_id; /* - * When this bit is set to '1' and EEE is enabled on this - * link, then TX LPI is requested to be disabled on the link. - * If EEE is not supported on this port, then this flag - * shall be ignored by the HWRM. - * If EEE is disabled on this port, then this flag shall be - * ignored by the HWRM. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \ - UINT32_C(0x80) + uint16_t target_id; /* - * When set to 1, then the HWRM shall enable FEC autonegotitation - * on this port if supported. When enabled, at least one of the - * FEC modes must be advertised by enabling the fec_clause_74_enable, - * fec_clause_91_enable, fec_rs544_1xn_enable, fec_rs544_ieee_enable, - * fec_rs272_1xn_enable, or fec_rs272_ieee_enable flag. If none - * of the FEC mode is currently enabled, the HWRM shall choose - * a default advertisement setting. - * The default advertisement setting can be queried by calling - * hwrm_port_phy_qcfg. Note that the link speed must be - * in autonegotiation mode for FEC autonegotiation to take effect. - * When set to 0, then this flag shall be ignored. - * If FEC autonegotiation is not supported, then the HWRM shall ignore this - * flag. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \ - UINT32_C(0x100) + uint64_t resp_addr; + uint32_t flags; /* - * When set to 1, then the HWRM shall disable FEC autonegotiation - * on this port and use forced FEC mode. In forced FEC mode, one - * or more FEC forced settings under the same clause can be set. - * When set to 0, then this flag shall be ignored. - * If FEC autonegotiation is not supported, then the HWRM shall ignore this - * flag. + * When this bit is '1', the function driver is indicating + * that the IF state is changing to UP state. The call should + * be made at the beginning of the driver's open call before + * resources are allocated. After making the call, the driver + * should check the response to see if any resources may have + * changed (see the response below). If the driver fails + * the open call, the driver should make this call again with + * this bit cleared to indicate that the IF state is not UP. + * During the driver's close call when the IF state is changing + * to DOWN, the driver should make this call with the bit cleared + * after all resources have been freed. */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \ - UINT32_C(0x200) + #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1) + uint32_t unused; +} __rte_packed; + +/* hwrm_func_drv_if_change_output (size:128b/16B) */ +struct hwrm_func_drv_if_change_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; /* - * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code) - * on this port if supported, by advertising FEC CLAUSE 74 if - * FEC autonegotiation is enabled or force enabled otherwise. - * When set to 0, then this flag shall be ignored. - * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this - * flag. + * When this bit is '1', it indicates that the resources reserved + * for this function may have changed. The driver should check + * resource capabilities and reserve resources again before + * allocating resources. */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \ - UINT32_C(0x400) + #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \ + UINT32_C(0x1) /* - * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code) - * on this port if supported, by not advertising FEC CLAUSE 74 if - * FEC autonegotiation is enabled or force disabled otherwise. - * When set to 0, then this flag shall be ignored. - * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this - * flag. + * When this bit is '1', it indicates that the firmware got changed / + * reset. The driver should do complete re-initialization when that + * bit is set. */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \ - UINT32_C(0x800) + #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \ + UINT32_C(0x2) /* - * When set to 1, then the HWRM shall enable FEC CLAUSE 91 - * (Reed Solomon RS(528,514) for NRZ) on this port if supported, - * by advertising FEC RS(528,514) if FEC autonegotiation is enabled - * or force enabled otherwise. In forced FEC mode, this flag - * will only take effect if the speed is NRZ. Additional - * RS544 or RS272 flags (also under clause 91) may be set for PAM4 - * in forced FEC mode. - * When set to 0, then this flag shall be ignored. - * If FEC RS(528,514) is not supported, then the HWRM shall ignore - * this flag. + * When this bit is '1', it indicates that capabilities + * for this function may have changed. The driver should + * query for changes to capabilities. + * The CAPS_CHANGE bit will only be set when it is safe for the + * driver to completely re-initialize all resources for the function + * including any children VFs. */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \ - UINT32_C(0x1000) + #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_CAPS_CHANGE \ + UINT32_C(0x4) + uint8_t unused_0[3]; /* - * When set to 1, then the HWRM shall disable FEC CLAUSE 91 - * (Reed Solomon RS(528,514) for NRZ) on this port if supported, by - * not advertising RS(528,514) if FEC autonegotiation is enabled or - * force disabled otherwise. When set to 0, then this flag shall be - * ignored. If FEC RS(528,514) is not supported, then the HWRM - * shall ignore this flag. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \ - UINT32_C(0x2000) + uint8_t valid; +} __rte_packed; + +/******************************* + * hwrm_func_host_pf_ids_query * + *******************************/ + + +/* hwrm_func_host_pf_ids_query_input (size:192b/24B) */ +struct hwrm_func_host_pf_ids_query_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * When this bit is set to '1', the link shall be forced to - * be taken down. - * - * # When this bit is set to '1", all other - * command input settings related to the link speed shall - * be ignored. - * Once the link state is forced down, it can be - * explicitly cleared from that state by setting this flag - * to '0'. - * # If this flag is set to '0', then the link shall be - * cleared from forced down state if the link is in forced - * down state. - * There may be conditions (e.g. out-of-band or sideband - * configuration changes for the link) outside the scope - * of the HWRM implementation that may clear forced down - * link state. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \ - UINT32_C(0x4000) + uint16_t cmpl_ring; /* - * When set to 1, then the HWRM shall enable FEC RS544_1XN - * on this port if supported, by advertising FEC RS544_1XN if - * FEC autonegotiation is enabled or force enabled otherwise. - * In forced mode, this flag will only take effect if the speed is - * PAM4. If this flag and fec_rs544_ieee_enable are set, the - * HWRM shall choose one of the RS544 modes. - * When set to 0, then this flag shall be ignored. - * If FEC RS544_1XN is not supported, then the HWRM shall ignore this - * flag. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_ENABLE \ - UINT32_C(0x8000) + uint16_t seq_id; /* - * When set to 1, then the HWRM shall disable FEC RS544_1XN - * on this port if supported, by not advertising FEC RS544_1XN if - * FEC autonegotiation is enabled or force disabled otherwise. - * When set to 0, then this flag shall be ignored. - * If FEC RS544_1XN is not supported, then the HWRM shall ignore this - * flag. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE \ - UINT32_C(0x10000) + uint16_t target_id; /* - * When set to 1, then the HWRM shall enable FEC RS(544,514) - * on this port if supported, by advertising FEC RS(544,514) if - * FEC autonegotiation is enabled or force enabled otherwise. - * In forced mode, this flag will only take effect if the speed is - * PAM4. If this flag and fec_rs544_1xn_enable are set, the - * HWRM shall choose one of the RS544 modes. - * When set to 0, then this flag shall be ignored. - * If FEC RS(544,514) is not supported, then the HWRM shall ignore - * this flag. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_ENABLE \ - UINT32_C(0x20000) + uint64_t resp_addr; + uint8_t host; /* - * When set to 1, then the HWRM shall disable FEC RS(544,514) - * on this port if supported, by not advertising FEC RS(544,514) if - * FEC autonegotiation is enabled or force disabled otherwise. - * When set to 0, then this flag shall be ignored. - * If FEC RS(544,514) is not supported, then the HWRM shall ignore - * this flag. + * # If this bit is set to '1', the query will contain PF(s) + * belongs to SOC host. */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_DISABLE \ - UINT32_C(0x40000) + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1) /* - * When set to 1, then the HWRM shall enable FEC RS272_1XN - * on this port if supported, by advertising FEC RS272_1XN if - * FEC autonegotiation is enabled or force enabled otherwise. - * In forced mode, this flag will only take effect if the speed is - * PAM4. If this flag and fec_rs272_ieee_enable are set, the - * HWRM shall choose one of the RS272 modes. Note that RS272 - * and RS544 modes cannot be set at the same time in forced FEC mode. - * When set to 0, then this flag shall be ignored. - * If FEC RS272_1XN is not supported, then the HWRM shall ignore this - * flag. + * # If this bit is set to '1', the query will contain PF(s) + * belongs to EP0 host. */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_ENABLE \ - UINT32_C(0x80000) + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2) /* - * When set to 1, then the HWRM shall disable FEC RS272_1XN - * on this port if supported, by not advertising FEC RS272_1XN if - * FEC autonego