diff mbox series

[v2] net/mlx5: fix miniCQEs number calculation

Message ID 20241028171458.2264985-1-akozyrev@nvidia.com (mailing list archive)
State Superseded, archived
Delegated to: Raslan Darawsheh
Headers
Series [v2] net/mlx5: fix miniCQEs number calculation |

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Commit Message

Alexander Kozyrev Oct. 28, 2024, 5:14 p.m. UTC 
Use the information from the CQE, not from the title packet,
for getting the number of miniCQEs in the compressed CQEs array.
This way we can avoid segfaults in the rxq_cq_decompress_v()
in case of mbuf corruption (due to double mbuf free, for example).

Fixes: 6cb559d67b ("net/mlx5: add vectorized Rx/Tx burst for x86")

Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
---
 drivers/net/mlx5/mlx5_rxtx_vec_altivec.h | 3 +--
 drivers/net/mlx5/mlx5_rxtx_vec_neon.h    | 3 +--
 drivers/net/mlx5/mlx5_rxtx_vec_sse.h     | 3 +--
 3 files changed, 3 insertions(+), 6 deletions(-)

Comments

Viacheslav Ovsiienko Nov. 12, 2024, 2:49 p.m. UTC | #1 
> -----Original Message-----
> From: Alexander Kozyrev <akozyrev@nvidia.com>
> Sent: Monday, October 28, 2024 7:15 PM
> To: dev@dpdk.org
> Cc: stable@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>; Slava
> Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com>;
> Dariusz Sosnowski <dsosnowski@nvidia.com>; Bing Zhao
> <bingz@nvidia.com>; Suanming Mou <suanmingm@nvidia.com>
> Subject: [PATCH v2] net/mlx5: fix miniCQEs number calculation
> 
> Use the information from the CQE, not from the title packet, for getting the
> number of miniCQEs in the compressed CQEs array.
> This way we can avoid segfaults in the rxq_cq_decompress_v() in case of
> mbuf corruption (due to double mbuf free, for example).
> 
> Fixes: 6cb559d67b ("net/mlx5: add vectorized Rx/Tx burst for x86")
> 
> Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h
index b2bbc4ba17..265c81d8dc 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h
@@ -98,8 +98,7 @@  rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
 			11, 10,  9,  8};  /* bswap32, rss */
 	/* Restore the compressed count. Must be 16 bits. */
 	uint16_t mcqe_n = (rxq->cqe_comp_layout) ?
-		(MLX5_CQE_NUM_MINIS(cq->op_own) + 1) :
-		t_pkt->data_len + (rxq->crc_present * RTE_ETHER_CRC_LEN);
+		(MLX5_CQE_NUM_MINIS(cq->op_own) + 1U) : rte_be_to_cpu_32(cqe->byte_cnt)
 	uint16_t pkts_n = mcqe_n;
 	const __vector unsigned char rearm =
 		(__vector unsigned char)vec_vsx_ld(0,
diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
index 510f60b25d..a4d4f3b582 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
@@ -97,8 +97,7 @@  rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
 	};
 	/* Restore the compressed count. Must be 16 bits. */
 	uint16_t mcqe_n = (rxq->cqe_comp_layout) ?
-		(MLX5_CQE_NUM_MINIS(cq->op_own) + 1) :
-		t_pkt->data_len + (rxq->crc_present * RTE_ETHER_CRC_LEN);
+		(MLX5_CQE_NUM_MINIS(cq->op_own) + 1U) : rte_be_to_cpu_32(cq->byte_cnt);
 	uint16_t pkts_n = mcqe_n;
 	const uint64x2_t rearm =
 		vld1q_u64((void *)&t_pkt->rearm_data);
diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h
index e71d6c303f..0273fdb54a 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h
@@ -96,8 +96,7 @@  rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
 			    -1, -1, -1, -1  /* skip packet_type */);
 	/* Restore the compressed count. Must be 16 bits. */
 	uint16_t mcqe_n = (rxq->cqe_comp_layout) ?
-		(MLX5_CQE_NUM_MINIS(cq->op_own) + 1) :
-		t_pkt->data_len + (rxq->crc_present * RTE_ETHER_CRC_LEN);
+		(MLX5_CQE_NUM_MINIS(cq->op_own) + 1U) : rte_be_to_cpu_32(cq->byte_cnt);
 	uint16_t pkts_n = mcqe_n;
 	const __m128i rearm =
 		_mm_loadu_si128((__m128i *)&t_pkt->rearm_data);