From patchwork Thu Oct 26 08:15:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gowrishankar Muthukrishnan X-Patchwork-Id: 133379 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 732F343206; Thu, 26 Oct 2023 10:15:41 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3B23842DFF; Thu, 26 Oct 2023 10:15:28 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id DB4F342DEA for ; Thu, 26 Oct 2023 10:15:26 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39Q71eTW017512; Thu, 26 Oct 2023 01:15:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=K9O3M69nniP7/08w3X/Vdcm017LL5whMYKdZU+bQsgU=; b=k+e8n6nN/xH8/P3wUxsUBKWrr3VyDTfQO6WlvERWYQ2ToGK/OpWgtYlHefoNAkAKmYDC EvxRgs5tIQHqsLg0xgW7ihlUysLdVV9skl0qpSTfYOruEzJScX178PDxaBeb/E7+TJCa JjivfWgPQV3fl7J906Zn6m7HRmDbbrCr4kaZcCDO4YDz3NZ0d20ap1vTbnIfzz+IhBhp CFxFxcH/pC2Y8ZvUI4dbS9fmL+OAfbkNRXKq94lX3WjC+aqxA0QDTJWfTrwoqS2Yq9Qs aInHWdkSPUtTK+qVpOsh9YerI0zNcgDZQMIaYWqdTjuRxkOufqij1UOjyKoQv86FVYlA 8g== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3txcsr1b2k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 26 Oct 2023 01:15:26 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 26 Oct 2023 01:15:24 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 26 Oct 2023 01:15:24 -0700 Received: from BG-LT91401.marvell.com (BG-LT91401.marvell.com [10.28.168.34]) by maili.marvell.com (Postfix) with ESMTP id 54F9F3F704D; Thu, 26 Oct 2023 01:15:22 -0700 (PDT) From: Gowrishankar Muthukrishnan To: CC: , Akhil Goyal , Fan Zhang , Gowrishankar Muthukrishnan Subject: [PATCH v1 2/4] crypto/cnxk: use generic EC opcodes Date: Thu, 26 Oct 2023 13:45:10 +0530 Message-ID: <2b4e2e189aed1dba8de03742b752267f9e9ad973.1698307299.git.gmuthukrishn@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: swpvs9yUKJSMp1eup4I7_-fy6kFwy_8b X-Proofpoint-GUID: swpvs9yUKJSMp1eup4I7_-fy6kFwy_8b X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-26_05,2023-10-25_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Use generic EC opcodes for sign and verify ops in ECDSA and SM2 implementations. Signed-off-by: Gowrishankar Muthukrishnan --- drivers/common/cnxk/roc_ae.h | 14 +++++++--- drivers/crypto/cnxk/cnxk_ae.h | 50 +++++++++++++++++++---------------- 2 files changed, 38 insertions(+), 26 deletions(-) diff --git a/drivers/common/cnxk/roc_ae.h b/drivers/common/cnxk/roc_ae.h index d459c5e680..eaf12ab254 100644 --- a/drivers/common/cnxk/roc_ae.h +++ b/drivers/common/cnxk/roc_ae.h @@ -5,9 +5,11 @@ #ifndef __ROC_AE_H__ #define __ROC_AE_H__ +#include "roc_platform.h" + /* AE opcodes */ #define ROC_AE_MAJOR_OP_MODEX 0x03 -#define ROC_AE_MAJOR_OP_ECDSA 0x04 +#define ROC_AE_MAJOR_OP_EC 0x04 #define ROC_AE_MAJOR_OP_ECC 0x05 #define ROC_AE_MINOR_OP_MODEX 0x01 #define ROC_AE_MINOR_OP_PKCS_ENC 0x02 @@ -15,8 +17,8 @@ #define ROC_AE_MINOR_OP_PKCS_DEC 0x04 #define ROC_AE_MINOR_OP_PKCS_DEC_CRT 0x05 #define ROC_AE_MINOR_OP_MODEX_CRT 0x06 -#define ROC_AE_MINOR_OP_ECDSA_SIGN 0x01 -#define ROC_AE_MINOR_OP_ECDSA_VERIFY 0x02 +#define ROC_AE_MINOR_OP_EC_SIGN 0x01 +#define ROC_AE_MINOR_OP_EC_VERIFY 0x02 #define ROC_AE_MINOR_OP_ECC_UMP 0x03 #define ROC_AE_MINOR_OP_ECC_FPM 0x04 @@ -38,6 +40,12 @@ typedef enum { ROC_AE_EC_ID_PMAX } roc_ae_ec_id; +/* EC param1 fields */ +#define ROC_AE_EC_PARAM1_ECDSA (0 << 7) +#define ROC_AE_EC_PARAM1_SM2 (1 << 7) +#define ROC_AE_EC_PARAM1_NIST (0 << 6) +#define ROC_AE_EC_PARAM1_NONNIST (1 << 6) + /* Prime and order fields of built-in elliptic curves */ struct roc_ae_ec_group { struct { diff --git a/drivers/crypto/cnxk/cnxk_ae.h b/drivers/crypto/cnxk/cnxk_ae.h index 09468d58b0..6e61ccb0c5 100644 --- a/drivers/crypto/cnxk/cnxk_ae.h +++ b/drivers/crypto/cnxk/cnxk_ae.h @@ -588,8 +588,8 @@ cnxk_ae_ecdsa_sign_prep(struct rte_crypto_ecdsa_op_param *ecdsa, dptr += p_align; /* Setup opcodes */ - w4.s.opcode_major = ROC_AE_MAJOR_OP_ECDSA; - w4.s.opcode_minor = ROC_AE_MINOR_OP_ECDSA_SIGN; + w4.s.opcode_major = ROC_AE_MAJOR_OP_EC; + w4.s.opcode_minor = ROC_AE_MINOR_OP_EC_SIGN; w4.s.param1 = curveid | (message_len << 8); w4.s.param2 = (p_align << 8) | k_len; @@ -683,8 +683,8 @@ cnxk_ae_ecdsa_verify_prep(struct rte_crypto_ecdsa_op_param *ecdsa, dptr += p_align; /* Setup opcodes */ - w4.s.opcode_major = ROC_AE_MAJOR_OP_ECDSA; - w4.s.opcode_minor = ROC_AE_MINOR_OP_ECDSA_VERIFY; + w4.s.opcode_major = ROC_AE_MAJOR_OP_EC; + w4.s.opcode_minor = ROC_AE_MINOR_OP_EC_VERIFY; w4.s.param1 = curveid | (message_len << 8); w4.s.param2 = 0; @@ -719,9 +719,9 @@ cnxk_ae_enqueue_ecdsa_op(struct rte_crypto_op *op, static __rte_always_inline void cnxk_ae_sm2_sign_prep(struct rte_crypto_sm2_op_param *sm2, - struct roc_ae_buf_ptr *meta_buf, - uint64_t fpm_table_iova, struct roc_ae_ec_group *ec_grp, - struct cnxk_ae_sess *sess, struct cpt_inst_s *inst) + struct roc_ae_buf_ptr *meta_buf, + uint64_t fpm_table_iova, struct roc_ae_ec_group *ec_grp, + struct cnxk_ae_sess *sess, struct cpt_inst_s *inst) { uint16_t message_len = sm2->message.length; uint16_t pkey_len = sess->ec_ctx.pkey.length; @@ -787,10 +787,12 @@ cnxk_ae_sm2_sign_prep(struct rte_crypto_sm2_op_param *sm2, dptr += p_align; /* Setup opcodes */ - w4.s.opcode_major = ROC_AE_MAJOR_OP_ECDSA; - w4.s.opcode_minor = ROC_AE_MINOR_OP_ECDSA_SIGN; + w4.s.opcode_major = ROC_AE_MAJOR_OP_EC; + w4.s.opcode_minor = ROC_AE_MINOR_OP_EC_SIGN; - w4.s.param1 = 2 | 1 << 7 | 1 << 6 | (message_len << 8); + /* prime length of SM2 curve is same as that of P256. */ + w4.s.param1 = ROC_AE_EC_ID_P256 | + ROC_AE_EC_PARAM1_SM2 | ROC_AE_EC_PARAM1_NONNIST | (message_len << 8); w4.s.param2 = (p_align << 8) | k_len; w4.s.dlen = dlen; @@ -800,10 +802,10 @@ cnxk_ae_sm2_sign_prep(struct rte_crypto_sm2_op_param *sm2, static __rte_always_inline void cnxk_ae_sm2_verify_prep(struct rte_crypto_sm2_op_param *sm2, - struct roc_ae_buf_ptr *meta_buf, - uint64_t fpm_table_iova, - struct roc_ae_ec_group *ec_grp, struct cnxk_ae_sess *sess, - struct cpt_inst_s *inst) + struct roc_ae_buf_ptr *meta_buf, + uint64_t fpm_table_iova, + struct roc_ae_ec_group *ec_grp, struct cnxk_ae_sess *sess, + struct cpt_inst_s *inst) { uint32_t message_len = sm2->message.length; uint16_t o_offset, r_offset, s_offset; @@ -881,10 +883,12 @@ cnxk_ae_sm2_verify_prep(struct rte_crypto_sm2_op_param *sm2, dptr += p_align; /* Setup opcodes */ - w4.s.opcode_major = ROC_AE_MAJOR_OP_ECDSA; - w4.s.opcode_minor = ROC_AE_MINOR_OP_ECDSA_VERIFY; + w4.s.opcode_major = ROC_AE_MAJOR_OP_EC; + w4.s.opcode_minor = ROC_AE_MINOR_OP_EC_VERIFY; - w4.s.param1 = 2 | 1 << 7 | 1 << 6 | (message_len << 8); + /* prime length of SM2 curve is same as that of P256. */ + w4.s.param1 = ROC_AE_EC_ID_P256 | + ROC_AE_EC_PARAM1_SM2 | ROC_AE_EC_PARAM1_NONNIST | (message_len << 8); w4.s.param2 = 0; w4.s.dlen = dlen; @@ -894,20 +898,20 @@ cnxk_ae_sm2_verify_prep(struct rte_crypto_sm2_op_param *sm2, static __rte_always_inline int __rte_hot cnxk_ae_enqueue_sm2_op(struct rte_crypto_op *op, - struct roc_ae_buf_ptr *meta_buf, - struct cnxk_ae_sess *sess, uint64_t *fpm_iova, - struct roc_ae_ec_group **ec_grp, - struct cpt_inst_s *inst) + struct roc_ae_buf_ptr *meta_buf, + struct cnxk_ae_sess *sess, uint64_t *fpm_iova, + struct roc_ae_ec_group **ec_grp, + struct cpt_inst_s *inst) { struct rte_crypto_sm2_op_param *sm2 = &op->asym->sm2; uint8_t curveid = sess->ec_ctx.curveid; if (sm2->op_type == RTE_CRYPTO_ASYM_OP_SIGN) cnxk_ae_sm2_sign_prep(sm2, meta_buf, fpm_iova[curveid], - ec_grp[curveid], sess, inst); + ec_grp[curveid], sess, inst); else if (sm2->op_type == RTE_CRYPTO_ASYM_OP_VERIFY) cnxk_ae_sm2_verify_prep(sm2, meta_buf, fpm_iova[curveid], - ec_grp[curveid], sess, inst); + ec_grp[curveid], sess, inst); else { op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS; return -EINVAL;