diff mbox series

[v3,29/36] net/e1000/base: hardcode bus parameters for ICH8

Message ID 3b90935d182d7c3a1bc2a776b701310b41792407.1738932115.git.anatoly.burakov@intel.com (mailing list archive)
State Accepted
Delegated to: Bruce Richardson
Headers
Series Merge Intel IGC and E1000 drivers, and update E1000 base code |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Burakov, Anatoly Feb. 7, 2025, 12:45 p.m. UTC 
From: Dima Ruinskiy <dima.ruinskiy@intel.com>

Current implementation of e1000_get_bus_info_ich8lan first attempts to
call e1000_get_bus_info_pcie_generic, and hard codes the bus width if the
latter does not return a valid value.

However, e1000_get_bus_info_pcie_generic will always fail on an ICH
device, since no PCIe capability is present in the ICH config space.
Therefore, there is no need to call it at all. Instead, we set the bus
parameters to their appropriate default values.

Signed-off-by: Dima Ruinskiy <dima.ruinskiy@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
 drivers/net/intel/e1000/base/e1000_ich8lan.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/intel/e1000/base/e1000_ich8lan.c b/drivers/net/intel/e1000/base/e1000_ich8lan.c
index 0bb67ca621..342a09e8b8 100644
--- a/drivers/net/intel/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/intel/e1000/base/e1000_ich8lan.c
@@ -4885,21 +4885,20 @@  STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
 {
 	struct e1000_bus_info *bus = &hw->bus;
-	s32 ret_val;
 
 	DEBUGFUNC("e1000_get_bus_info_ich8lan");
 
-	ret_val = e1000_get_bus_info_pcie_generic(hw);
-
 	/* ICH devices are "PCI Express"-ish.  They have
 	 * a configuration space, but do not contain
-	 * PCI Express Capability registers, so bus width
+	 * PCI Express Capability registers, so bus parameters
 	 * must be hardcoded.
 	 */
-	if (bus->width == e1000_bus_width_unknown)
-		bus->width = e1000_bus_width_pcie_x1;
+	bus->type = e1000_bus_type_pci_express;
+	bus->width = e1000_bus_width_pcie_x1;
+	bus->speed = e1000_bus_speed_unknown;
+	bus->func = 0;
 
-	return ret_val;
+	return E1000_SUCCESS;
 }
 
 /**