From patchwork Thu Nov 20 05:17:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yerden Zhumabekov X-Patchwork-Id: 1361 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 4C4917F68; Thu, 20 Nov 2014 06:07:47 +0100 (CET) Received: from mgw.gov.kz (mgw.gov.kz [89.218.88.242]) by dpdk.org (Postfix) with ESMTP id 7E1187F60 for ; Thu, 20 Nov 2014 06:07:44 +0100 (CET) Received: from mgw.gov.kz (mx.ctsat.kz [178.89.4.95]) by mgw.gov.kz with ESMTP id sAK5I2UQ000627-sAK5I2US000627 (version=TLSv1.0 cipher=AES128-SHA bits=128 verify=NO); Thu, 20 Nov 2014 11:18:04 +0600 Received: from EXCASHUB2.rgp.local (192.168.40.53) by EdgeForefront.rgp.local (192.168.40.59) with Microsoft SMTP Server (TLS) id 14.2.247.3; Thu, 20 Nov 2014 11:17:49 +0600 Received: from r220.rgp.local (192.168.59.10) by excashub2.rgp.local (192.168.40.48) with Microsoft SMTP Server (TLS) id 14.2.247.3; Thu, 20 Nov 2014 11:18:00 +0600 From: Yerden Zhumabekov To: Date: Thu, 20 Nov 2014 11:17:44 +0600 Message-ID: <3e8c67c58253f65e2378121ca671a0dc6d7c4c1c.1416459284.git.e_zhumabekov@sts.kz> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: <1409724351-23786-1-git-send-email-e_zhumabekov@sts.kz> MIME-Version: 1.0 X-Originating-IP: [192.168.59.10] X-FEAS-SYSTEM-WL: e_zhumabekov@sts.kz Subject: [dpdk-dev] [PATCH v5 5/7] hash: add fallback to software CRC32 implementation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Initially, SSE4.2 support is detected via CPUID instruction via the constructor function. Added rte_hash_crc_set_alg() function to detect and set CRC32 implementation if necessary. SSE4.2 is allowed by default. rte_hash_crc_*byte() functions reworked so they choose available CRC32 implementation in the runtime. Signed-off-by: Yerden Zhumabekov --- lib/librte_hash/rte_hash_crc.h | 61 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 59 insertions(+), 2 deletions(-) diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h index 2c8ec99..469b4f5 100644 --- a/lib/librte_hash/rte_hash_crc.h +++ b/lib/librte_hash/rte_hash_crc.h @@ -45,6 +45,8 @@ extern "C" { #endif #include +#include +#include /* Lookup tables for software implementation of CRC32C */ static uint32_t crc32c_tables[8][256] = {{ @@ -396,8 +398,52 @@ crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val) return init_val; } +#define CRC32_SW (1U << 0) +#define CRC32_SSE42 (1U << 1) +#define CRC32_x64 (1U << 2) +#define CRC32_SSE42_x64 (CRC32_x64|CRC32_SSE42) + +static uint8_t crc32_alg = CRC32_SW; + +/** + * Allow or disallow use of SSE4.2 instrinsics for CRC32 hash + * calculation. + * + * @param flag + * An OR of following flags: + * - (CRC32_SW) Don't use SSE4.2 intrinsics + * - (CRC32_SSE42) Use SSE4.2 intrinsics if available + * - (CRC32_SSE42_x64) Use 64-bit SSE4.2 intrinsic if available (default) + * + */ +static inline void +rte_hash_crc_set_alg(uint8_t alg) +{ + switch (alg) { + case CRC32_SSE42_x64: + if (! rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T)) + alg = CRC32_SSE42; + case CRC32_SSE42: + if (! rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_2)) + alg = CRC32_SW; + case CRC32_SW: + crc32_alg = alg; + default: + break; + } +} + +/* Setting the best available algorithm */ +static inline void __attribute__((constructor)) +rte_hash_crc_init_alg(void) +{ + rte_hash_crc_set_alg(CRC32_SSE42_x64); +} + /** * Use single crc32 instruction to perform a hash on a 4 byte value. + * Fall back to software crc32 implementation in case SSE4.2 is + * not supported * * @param data * Data to perform hash on. @@ -409,11 +455,16 @@ crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val) static inline uint32_t rte_hash_crc_4byte(uint32_t data, uint32_t init_val) { - return crc32c_sse42_u32(data, init_val); + if (likely(crc32_alg & CRC32_SSE42)) + return crc32c_sse42_u32(data, init_val); + + return crc32c_1word(data, init_val); } /** * Use single crc32 instruction to perform a hash on a 8 byte value. + * Fall back to software crc32 implementation in case SSE4.2 is + * not supported * * @param data * Data to perform hash on. @@ -425,7 +476,13 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val) static inline uint32_t rte_hash_crc_8byte(uint64_t data, uint32_t init_val) { - return crc32c_sse42_u64(data, init_val); + if (likely(crc32_alg == CRC32_SSE42_x64)) + return crc32c_sse42_u64(data, init_val); + + if (likely(crc32_alg & CRC32_SSE42)) + return crc32c_sse42_u64_mimic(data, init_val); + + return crc32c_2words(data, init_val); } /**