From patchwork Wed Jan 3 07:16:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shahaf Shuler X-Patchwork-Id: 32842 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 027831B1AB; Wed, 3 Jan 2018 08:17:15 +0100 (CET) Received: from EUR01-VE1-obe.outbound.protection.outlook.com (mail-ve1eur01on0069.outbound.protection.outlook.com [104.47.1.69]) by dpdk.org (Postfix) with ESMTP id 87B4E1B198 for ; Wed, 3 Jan 2018 08:17:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=L/LkdbIkA93vXYY8oSo6CV5hXnHLVKJ3nLq5nbs+1AM=; b=WlIac0LWH4pwmgNIBX64FdApoCwIsKDLQUNcJ1Iv+KTbAWVqmsY5UEP4ANCGAN1si91aL9RGimvNbP+bjVkoVP/fY8oLtgVt8JQ+a7YA1b8W7kK2TXasDNDGCMGfX6yVzTUE3FwzzbtwTtRH9A8hE/08ZV/QQAk/0fP+UQ2wxmU= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=shahafs@mellanox.com; Received: from mellanox.com (82.166.227.17) by HE1PR05MB3148.eurprd05.prod.outlook.com (2603:10a6:7:36::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.366.8; Wed, 3 Jan 2018 07:17:11 +0000 From: Shahaf Shuler To: nelio.laranjeiro@6wind.com, yskoh@mellanox.com, adrien.mazarguil@6wind.com Cc: dev@dpdk.org Date: Wed, 3 Jan 2018 09:16:15 +0200 Message-Id: <43ca45bbb786d83b7870b590f00a5b1027a33076.1514963302.git.shahafs@mellanox.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: References: <20171123120252.143695-1-shahafs@mellanox.com> MIME-Version: 1.0 X-Originating-IP: [82.166.227.17] X-ClientProxiedBy: DB6P193CA0018.EURP193.PROD.OUTLOOK.COM (2603:10a6:6:29::28) To HE1PR05MB3148.eurprd05.prod.outlook.com (2603:10a6:7:36::18) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 1d1a9912-9b69-4696-3018-08d5527a024e X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(4534020)(4602075)(4627115)(201703031133081)(201702281549075)(48565401081)(5600026)(4604075)(2017052603307)(7153060); SRVR:HE1PR05MB3148; X-Microsoft-Exchange-Diagnostics: 1; HE1PR05MB3148; 3:/oS0ZEFP7WwfpTBbtHv1zV2C99iyinlnsK8bXwGBBLHrwaFIkDBTrXXFvDrAePNAmIRBvDUYXWYqceq4nsgXEhKvs00DOaVbrYYxpFHY/YwMrbOWUKdyBwFCw/IJ3T7aOwuDNdh4TNyHUX8xyOYBeiJHvBvTJvyFdM0CsLr/V87LXiIxGx0aI7LMBEFqhUzie6H108ArFNkXlTB0cm+kqAsgX/9MN6CocPt06vE/rlh7PVaAFnvbBpDkQySctIX7; 25:CoXpM/MipLtp18y9oR76NWlmNX0Za4S75EEe8W/A0+W0l6Yw1oNh6ehE/ADr6t5ZtHnYATJJjYWNLtACpSpRM4Qq5r3KZczUsLEeVMXU66vlXQfNq9NMDAZkpjBU/BD4mo8gmSQ7xw9U3fHMVagfxRQB5WgyTGHdnt253Bf6eviCxbPwo/zYpkdjwwNNmYTBUCCQPkRU+M25RhUi3htiPGdqWeWSUhqmVZWkyo5V5tgfhY9WurXO9OcRabOp/IGsXiA4fhmn07FSkYFAxKtwCrLnA8mIQZyUfRmnA2+iklDY6Q5MREiAtzDDoGVpsZQcwQfqlIzlvo7CMbEcyztfVg==; 31:ysAie0hbhO0+ZL00zEpJFPHLGOOTqTV6IZPwpqN2Hp27csXVCOYCPdGlE0W9Ui4svEfIyp4IcuQbQxUlynWSOqEPpvoX/z3mSkz6XJnCYD66nk8RBpzbPYLO03OXVaFZtTih9slZHOTnBg9hiAU5v+arGuT+sh68spYHZqfisyp2RbMfWnROZKcLldcmWEcKMerKMFCfP+uQupLpFdLyrQ4/YOKxuLdMPProOnjU+jA= X-MS-TrafficTypeDiagnostic: HE1PR05MB3148: X-LD-Processed: a652971c-7d2e-4d9b-a6a4-d149256f461b,ExtAddr X-Microsoft-Exchange-Diagnostics: 1; HE1PR05MB3148; 20:kaSq+Lgkgk/815QOKVBSql8ftptj6NBH6TwPKNlN+j7zJZzOxfc1RkxmFTPOzSI15hKWySuygpYqhUdfIVBmJOlmRFbYuEuN2yCYuDZHJGT38jvHe5SgTWa4dnIIlLI4MzMBpA56G5tPqt1wpLcFfASbXwqooCp17J258exirGf6Dekf09DqH95nUFG1FlJKvVfkJBhaGsHtCj37wOwdWnijqdTfE7RZG2uR7Ot5xjrdE7w8GMOiT50B28iWQYApriEavEaYTQXFvQeRTMN/HgRf7ikZNrbNBO6yuMINRt1j6DRXMjr13NwI+SlEiJvPlFeHOxwkA2KJcR0HledprLYh/PDIoCD3duYmY6KglkXBeNblebuqQ/O3MEaMYznx/79h4yxvyifGgygKtBzzJpp5POMeTXd7Xgi9g7Vw5kyom2JkAR6Wjiftq/iet0jm+5e7OgbbkxNDAk4me6OmbIeTbyLcdnHD6r74vx42UJ21Xbu8Pmz/FZmXiLTZl6T8; 4:XfzF79yY0FC5u4wFR1c9UprZu5F4Sy8InF16JwSUGmM6CPpaCIFE4Gkss9D1rmRFMeplnmPtfkK3HuifihUez12il9ThbU+wL7RTkFpZfTI8vYtaXgKQ5htQtMmNuBQs8j86dSkeRkQVIgl1bu31C1RD/63Q9ynm5+SpT8BoElHupdb1JuBNaoV8jk3u458NomB/5Hv+VxN/iuwALPoO/ROOpv/jr/WNTrUP7BwavJdbfmlYRZqJJJJ6oKuVz4sCVEutxv8cNx2TkwSl23ocNg== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040470)(2401047)(5005006)(8121501046)(10201501046)(93006095)(93001095)(3231023)(944501075)(3002001)(6055026)(6041268)(20161123560045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123564045)(20161123562045)(20161123558120)(6072148)(201708071742011); SRVR:HE1PR05MB3148; BCL:0; PCL:0; RULEID:(100000803101)(100110400095); SRVR:HE1PR05MB3148; X-Forefront-PRVS: 0541031FF6 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(39380400002)(376002)(346002)(39860400002)(396003)(366004)(199004)(189003)(5660300001)(76176011)(51416003)(52116002)(4326008)(50226002)(7696005)(59450400001)(7736002)(8936002)(386003)(2950100002)(69596002)(81166006)(118296001)(81156014)(55016002)(478600001)(68736007)(8676002)(33026002)(106356001)(105586002)(53936002)(50466002)(3846002)(48376002)(6116002)(25786009)(2906002)(97736004)(305945005)(21086003)(66066001)(16586007)(36756003)(316002)(86362001)(16526018)(47776003)(309714004); DIR:OUT; SFP:1101; SCL:1; SRVR:HE1PR05MB3148; H:mellanox.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; Received-SPF: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; HE1PR05MB3148; 23:wwqtmgjcueLKRuwip0dFJntogpOd1eO8X2lc0N1bD?= RD93aiALZOXm5jGqy4L+YpaSTplPRN6+A0669Fc5ZvMzX1oke7A04bz9DiNYIoOu4uaIuauKrY3aXYCCDFlmhXeOkyHwlv1KmK6DAZyK6YDDF/2E47Yft4hpUAj5rAb8JkWjTsYqBc8SYEQ/fMU9mhHpluC6d1bjJ5fRnb3sMU2wQcDFl1pcr0FmQ0jDhVPy88O071v8WPv0l+CEnTQxAu9uF4LYhVWaxURmG551WcIByTdG/5DpbjwZYVgprc94GFiRCAMU/A4pvFv/82Nog0jWqCBz02Wm7ztlnc3nLlSKR0zI/mW2BUTvNj0BIJTDYsvER7XVvEk8XcqrRa8aRxVZe4oSKrLx97o4UpIGOvQezHOKjp+wIiixDsF69sM4kgAmYt7qoJQtcupxTIboq4TcyHMDevZMMeOuYDJfGgExj/nc/iSv38d5udcy0cDNF/89aOMXW/1hW4XlxT/F265PmtsXBeGqmh1qk/U+sg02WWw6wCmiY2DepoMynYuGgNoPZTEZY66tNETd2mIzb8jl1EZMrofNygWIrKhvENdq9K9BjYTy9La8DKbMUet5/c0Cp+iGZBe2vRBejYulWPp2aLtb2VSrMYadxZTg8DNYrBKlyTqR5OjNmiM8X0GoDN5aQWrP+9h7Rb+8raJkfYXyoyUZNbbSFPhZzqo7/nSO6MDbsRMuMJ4Jg1XGQ5WI82aHHt8cqUczDu2YOle5g/l05OHHr3cBcewESlSFda3LptAdgev03rJjAmfBSKU5QqOHPw7ia9JIGKi8R0XtcaKH/UN+WRusVi8/8kP/DfhWHZvr6Am7dE+qxPdEnVtEif5WnXNjEJttx0igW8a04vNm+XLaRkT2w7K9DUQNYL/pBy/OM2eeCT8ZlYcofYUnSLKsxOh0HrjlusNuyun+vLIlOxTmxNab41kWqmhsK4M9BX/eDxQ1SVEgvhKFz7yln1axhJbTfVUKYr3OKIBRvN7cQPXeEJxDYUcz2DKkuifvLKYuX8QYjXeQMQt09mx0mrDrUF8ckNT4GFMCoNdJfZ4mc86CozkS7+B7py5JM6w6P0bcDtGRAWestOTex1oEBS5P8BODCHzBIqlkgRc/ZuGxHNCMquR7V8oo27zhUn+oQ== X-Microsoft-Exchange-Diagnostics: 1; HE1PR05MB3148; 6:juWGc0aqiNeOqz/1qOmuXMCDS0YLL+FpLQUruHGd/vU1cEO4Fniu2nJ8vyOvnxL1NZ2lA2QxzdWo0L2U3E2c4EugrPdKAdCXhusthb17b8+53/6p3l9ERzLQvCyimEdjgoT33SBurK54h04OcIkEriM8Av1OKitIKVPJFK6CRhqMZxDx6v6EcQDEHkJKmi+TGHV+DplhaEdHFk0hWBcrdPUxH4kxWr+yRPGY5ObHh89jhwYorX9vN2BGLiMz9LAhidrQ2xGsFveCoccF3/qIA3LhGFd/Ninh2pEtPN/ihfEUJyjdnYyYSqsIGR55Y7ZGEoK4NViQmj0UuDR+S4sNhzP4mi5e/2D4fzVf6lio2MA=; 5:n6gBvayXG2xSWyo0/s73cQ9aeQdFiHahvPeMvmA3n2lrGuD/1CjtPLug12t3YqKWvelx3Ap/K6Q5/saQrpWBeYnctN28BACuDqt45RfAQdaujjMhKuGbW4zpoJ/0Z3e1DmNA6cCcy3tO4+0qclfY9IDGK8WW+Fl+QH0638OXvqQ=; 24:3IoHrA40sLsuayLjBaCHH++w+ef6n8nkS5zfkFlyKtT7OG/1LU3jaonzo1QyA/MvEKRpDSR7jAW75GAam4swlFN9rhsXe6PHiWderglUeCQ=; 7:5ss+xMEWE2ybF9LYZ8gYpnUJpQpFEfI3yu2a9xNywIMDyrAxml94Rhn/q1ASAdIXNYFwxzMueHUz1nAZa2AdtlHv31GFTJFZFcQnrNR07giphDhDNq1rHD5Cmb9TokchcdnUGxlI4eExldx6+gLMit7tNCQDRFoFmTl8ud0CWYL6NeGXZBfz1wiBO/Ir+hUhbebYETnmY0e7HQnq8C+KFzh4kxWvSUXLgX9mx94lco969FtUxTrvFrIno2sRlo04 SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jan 2018 07:17:11.2990 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1d1a9912-9b69-4696-3018-08d5527a024e X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR05MB3148 Subject: [dpdk-dev] [PATCH v2 5/7] net/mlx5: convert to new Rx offloads API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Ethdev Rx offloads API has changed since: commit ce17eddefc20 ("ethdev: introduce Rx queue offloads API") This commit support the new Rx offloads API. Signed-off-by: Shahaf Shuler Acked-by: Nelio Laranjeiro --- drivers/net/mlx5/mlx5_ethdev.c | 23 +++++--- drivers/net/mlx5/mlx5_rxq.c | 106 +++++++++++++++++++++++++++++++----- drivers/net/mlx5/mlx5_rxtx.h | 3 + drivers/net/mlx5/mlx5_vlan.c | 3 +- 4 files changed, 111 insertions(+), 24 deletions(-) diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c index 8be4f43f7..adaa34fff 100644 --- a/drivers/net/mlx5/mlx5_ethdev.c +++ b/drivers/net/mlx5/mlx5_ethdev.c @@ -553,6 +553,10 @@ dev_configure(struct rte_eth_dev *dev) !!dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key; uint64_t supp_tx_offloads = mlx5_priv_get_tx_port_offloads(priv); uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads; + uint64_t supp_rx_offloads = + (mlx5_priv_get_rx_port_offloads(priv) | + mlx5_priv_get_rx_queue_offloads(priv)); + uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; if ((tx_offloads & supp_tx_offloads) != tx_offloads) { ERROR("Some Tx offloads are not supported " @@ -560,6 +564,12 @@ dev_configure(struct rte_eth_dev *dev) tx_offloads, supp_tx_offloads); return ENOTSUP; } + if ((rx_offloads & supp_rx_offloads) != rx_offloads) { + ERROR("Some Rx offloads are not supported " + "requested 0x%lx supported 0x%lx\n", + rx_offloads, supp_rx_offloads); + return ENOTSUP; + } if (use_app_rss_key && (dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key_len != rss_hash_default_key_len)) { @@ -671,15 +681,10 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) info->max_rx_queues = max; info->max_tx_queues = max; info->max_mac_addrs = RTE_DIM(priv->mac); - info->rx_offload_capa = - (config->hw_csum ? - (DEV_RX_OFFLOAD_IPV4_CKSUM | - DEV_RX_OFFLOAD_UDP_CKSUM | - DEV_RX_OFFLOAD_TCP_CKSUM) : - 0) | - (priv->config.hw_vlan_strip ? DEV_RX_OFFLOAD_VLAN_STRIP : 0) | - DEV_RX_OFFLOAD_TIMESTAMP; - + info->rx_queue_offload_capa = + mlx5_priv_get_rx_queue_offloads(priv); + info->rx_offload_capa = (mlx5_priv_get_rx_port_offloads(priv) | + info->rx_queue_offload_capa); info->tx_offload_capa = mlx5_priv_get_tx_port_offloads(priv); if (priv_get_ifname(priv, &ifname) == 0) info->if_index = if_nametoindex(ifname); diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index 81363ecd7..232e660ce 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -213,6 +213,78 @@ mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *rxq_ctrl) } /** + * Returns the per-queue supported offloads. + * + * @param priv + * Pointer to private structure. + * + * @return + * Supported Rx offloads. + */ +uint64_t +mlx5_priv_get_rx_queue_offloads(struct priv *priv) +{ + struct mlx5_dev_config *config = &priv->config; + uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER | + DEV_RX_OFFLOAD_TIMESTAMP | + DEV_RX_OFFLOAD_JUMBO_FRAME); + + if (config->hw_fcs_strip) + offloads |= DEV_RX_OFFLOAD_CRC_STRIP; + if (config->hw_csum) + offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM | + DEV_RX_OFFLOAD_UDP_CKSUM | + DEV_RX_OFFLOAD_TCP_CKSUM); + if (config->hw_vlan_strip) + offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; + return offloads; +} + + +/** + * Returns the per-port supported offloads. + * + * @param priv + * Pointer to private structure. + * @return + * Supported Rx offloads. + */ +uint64_t +mlx5_priv_get_rx_port_offloads(struct priv *priv __rte_unused) +{ + uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER; + + return offloads; +} + +/** + * Checks if the per-queue offload configuration is valid. + * + * @param priv + * Pointer to private structure. + * @param offloads + * Per-queue offloads configuration. + * + * @return + * 1 if the configuration is valid, 0 otherwise. + */ +static int +priv_is_rx_queue_offloads_allowed(struct priv *priv, uint64_t offloads) +{ + uint64_t port_offloads = priv->dev->data->dev_conf.rxmode.offloads; + uint64_t queue_supp_offloads = + mlx5_priv_get_rx_queue_offloads(priv); + uint64_t port_supp_offloads = mlx5_priv_get_rx_port_offloads(priv); + + if ((offloads & (queue_supp_offloads | port_supp_offloads)) != + offloads) + return 0; + if (((port_offloads ^ offloads) & port_supp_offloads)) + return 0; + return 1; +} + +/** * * @param dev * Pointer to Ethernet device structure. @@ -241,7 +313,6 @@ mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, container_of(rxq, struct mlx5_rxq_ctrl, rxq); int ret = 0; - (void)conf; priv_lock(priv); if (!rte_is_power_of_2(desc)) { desc = 1 << log2above(desc); @@ -257,6 +328,16 @@ mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, priv_unlock(priv); return -EOVERFLOW; } + if (!priv_is_rx_queue_offloads_allowed(priv, conf->offloads)) { + ret = ENOTSUP; + ERROR("%p: Rx queue offloads 0x%lx don't match port " + "offloads 0x%lx or supported offloads 0x%lx", + (void *)dev, conf->offloads, + dev->data->dev_conf.rxmode.offloads, + (mlx5_priv_get_rx_port_offloads(priv) | + mlx5_priv_get_rx_queue_offloads(priv))); + goto out; + } if (!mlx5_priv_rxq_releasable(priv, idx)) { ret = EBUSY; ERROR("%p: unable to release queue index %u", @@ -264,7 +345,7 @@ mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, goto out; } mlx5_priv_rxq_release(priv, idx); - rxq_ctrl = mlx5_priv_rxq_new(priv, idx, desc, socket, mp); + rxq_ctrl = mlx5_priv_rxq_new(priv, idx, desc, socket, conf, mp); if (!rxq_ctrl) { ERROR("%p: unable to allocate queue index %u", (void *)dev, idx); @@ -875,7 +956,8 @@ mlx5_priv_rxq_ibv_releasable(struct priv *priv, struct mlx5_rxq_ibv *rxq_ibv) */ struct mlx5_rxq_ctrl* mlx5_priv_rxq_new(struct priv *priv, uint16_t idx, uint16_t desc, - unsigned int socket, struct rte_mempool *mp) + unsigned int socket, const struct rte_eth_rxconf *conf, + struct rte_mempool *mp) { struct rte_eth_dev *dev = priv->dev; struct mlx5_rxq_ctrl *tmpl; @@ -899,7 +981,7 @@ mlx5_priv_rxq_new(struct priv *priv, uint16_t idx, uint16_t desc, if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= (mb_len - RTE_PKTMBUF_HEADROOM)) { tmpl->rxq.sges_n = 0; - } else if (dev->data->dev_conf.rxmode.enable_scatter) { + } else if (conf->offloads & DEV_RX_OFFLOAD_SCATTER) { unsigned int size = RTE_PKTMBUF_HEADROOM + dev->data->dev_conf.rxmode.max_rx_pkt_len; @@ -941,18 +1023,14 @@ mlx5_priv_rxq_new(struct priv *priv, uint16_t idx, uint16_t desc, goto error; } /* Toggle RX checksum offload if hardware supports it. */ - if (config->hw_csum) - tmpl->rxq.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum; - if (config->hw_csum_l2tun) - tmpl->rxq.csum_l2tun = - !!dev->data->dev_conf.rxmode.hw_ip_checksum; - tmpl->rxq.hw_timestamp = - !!dev->data->dev_conf.rxmode.hw_timestamp; + tmpl->rxq.csum = !!(conf->offloads & DEV_RX_OFFLOAD_CHECKSUM); + tmpl->rxq.csum_l2tun = (!!(conf->offloads & DEV_RX_OFFLOAD_CHECKSUM) && + priv->config.hw_csum_l2tun); + tmpl->rxq.hw_timestamp = !!(conf->offloads & DEV_RX_OFFLOAD_TIMESTAMP); /* Configure VLAN stripping. */ - tmpl->rxq.vlan_strip = (config->hw_vlan_strip && - !!dev->data->dev_conf.rxmode.hw_vlan_strip); + tmpl->rxq.vlan_strip = !!(conf->offloads & DEV_RX_OFFLOAD_VLAN_STRIP); /* By default, FCS (CRC) is stripped by hardware. */ - if (dev->data->dev_conf.rxmode.hw_strip_crc) { + if (conf->offloads & DEV_RX_OFFLOAD_CRC_STRIP) { tmpl->rxq.crc_present = 0; } else if (config->hw_fcs_strip) { tmpl->rxq.crc_present = 1; diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h index 2728e8d5e..4ade8bee1 100644 --- a/drivers/net/mlx5/mlx5_rxtx.h +++ b/drivers/net/mlx5/mlx5_rxtx.h @@ -253,6 +253,7 @@ int mlx5_priv_rxq_ibv_releasable(struct priv *, struct mlx5_rxq_ibv *); int mlx5_priv_rxq_ibv_verify(struct priv *); struct mlx5_rxq_ctrl *mlx5_priv_rxq_new(struct priv *, uint16_t, uint16_t, unsigned int, + const struct rte_eth_rxconf *, struct rte_mempool *); struct mlx5_rxq_ctrl *mlx5_priv_rxq_get(struct priv *, uint16_t); int mlx5_priv_rxq_release(struct priv *, uint16_t); @@ -273,6 +274,8 @@ struct mlx5_hrxq *mlx5_priv_hrxq_get(struct priv *, uint8_t *, uint8_t, uint64_t, uint16_t [], uint16_t); int mlx5_priv_hrxq_release(struct priv *, struct mlx5_hrxq *); int mlx5_priv_hrxq_ibv_verify(struct priv *); +uint64_t mlx5_priv_get_rx_port_offloads(struct priv *); +uint64_t mlx5_priv_get_rx_queue_offloads(struct priv *); /* mlx5_txq.c */ diff --git a/drivers/net/mlx5/mlx5_vlan.c b/drivers/net/mlx5/mlx5_vlan.c index 2ab865264..9443e4f03 100644 --- a/drivers/net/mlx5/mlx5_vlan.c +++ b/drivers/net/mlx5/mlx5_vlan.c @@ -196,7 +196,8 @@ mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask) unsigned int i; if (mask & ETH_VLAN_STRIP_MASK) { - int hw_vlan_strip = !!dev->data->dev_conf.rxmode.hw_vlan_strip; + int hw_vlan_strip = !!(dev->data->dev_conf.rxmode.offloads & + DEV_RX_OFFLOAD_VLAN_STRIP); if (!priv->config.hw_vlan_strip) { ERROR("VLAN stripping is not supported");