From patchwork Wed Mar 17 08:04:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shijith Thotton X-Patchwork-Id: 89349 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DB146A00C2; Wed, 17 Mar 2021 09:06:18 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C8987242B62; Wed, 17 Mar 2021 09:06:18 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id AE5244014D for ; Wed, 17 Mar 2021 09:06:16 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 12H80RCt017591; Wed, 17 Mar 2021 01:06:15 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=8Q3W1/sFhY+3dsJni8Xm76wSJWXV5iTtVFCDmBOBvjI=; b=JGDShQw7y6fupE8jMxYylP81T/C+/euTcXVUAHscKo58fxtNPw8eRgr3CVyJLbcGyM8w rpfA4KXeNt8F0jHSHnJeXklw6WmY5K6qLbQVX4EQM1eX8oV1gXCoZTsBi/AAJ9heJqQ2 4JGhF/3uoUhPldl6nwAkkD5U7CepxTkLOuf7FqGAkwnaLp29oGwJ7Pt+ujTvYjwMB2cj 9nZ8RphQp3cRs7+WTjOdk1tH7Fm5sGbA/M3EzadYtlMl9aXAI/JDK0FGwMqqZo5s43nH SNR3mRbD4tgYw/4q2o342LJrxjx5JRSPOmiqiNK7r57TpD43kBhPI62gNIuAvFxQiwsk og== Received: from dc6wp-exch01.marvell.com ([4.21.29.232]) by mx0a-0016f401.pphosted.com with ESMTP id 37b5vdhbnd-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 17 Mar 2021 01:06:15 -0700 Received: from DC6WP-EXCH01.marvell.com (10.76.176.21) by DC6WP-EXCH01.marvell.com (10.76.176.21) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Mar 2021 04:06:13 -0400 Received: from maili.marvell.com (10.76.176.51) by DC6WP-EXCH01.marvell.com (10.76.176.21) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 17 Mar 2021 04:06:13 -0400 Received: from localhost.localdomain (unknown [10.28.34.29]) by maili.marvell.com (Postfix) with ESMTP id DAA473F7040; Wed, 17 Mar 2021 01:06:10 -0700 (PDT) From: Shijith Thotton To: Erik Gabriel Carrillo CC: Shijith Thotton , Pavan Nikhilesh , Jerin Jacob , Date: Wed, 17 Mar 2021 13:34:21 +0530 Message-ID: <51c875237a4f639dd566eca8cfc181aecc06b513.1615967694.git.sthotton@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-17_02:2021-03-17, 2021-03-17 signatures=0 Subject: [dpdk-dev] [PATCH v3 3/3] event/octeontx2: add timer periodic mode support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for periodic mode in event timer adapter. Signed-off-by: Shijith Thotton Acked-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_tim_evdev.c | 29 ++++++++++++++++++++---- drivers/event/octeontx2/otx2_tim_evdev.h | 1 + 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c index 4c24cc8a6..39a29f17f 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.c +++ b/drivers/event/octeontx2/otx2_tim_evdev.c @@ -65,7 +65,8 @@ otx2_tim_ring_info_get(const struct rte_event_timer_adapter *adptr, struct otx2_tim_ring *tim_ring = adptr->data->adapter_priv; adptr_info->max_tmo_ns = tim_ring->max_tout; - adptr_info->min_resolution_ns = tim_ring->tck_nsec; + adptr_info->min_resolution_ns = tim_ring->ena_periodic ? + tim_ring->max_tout : tim_ring->tck_nsec; rte_memcpy(&adptr_info->conf, &adptr->data->conf, sizeof(struct rte_event_timer_adapter_conf)); } @@ -163,7 +164,7 @@ tim_chnk_pool_create(struct otx2_tim_ring *tim_ring, } tim_ring->aura = npa_lf_aura_handle_to_aura( tim_ring->chunk_pool->pool_id); - tim_ring->ena_dfb = 0; + tim_ring->ena_dfb = tim_ring->ena_periodic ? 1 : 0; } else { tim_ring->chunk_pool = rte_mempool_create(pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz, @@ -254,6 +255,7 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr) struct tim_ring_req *free_req; struct tim_lf_alloc_req *req; struct tim_lf_alloc_rsp *rsp; + uint8_t is_periodic; int i, rc; if (dev == NULL) @@ -284,6 +286,20 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr) } } + is_periodic = 0; + if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_PERIODIC) { + if (rcfg->max_tmo_ns && + rcfg->max_tmo_ns != rcfg->timer_tick_ns) { + rc = -ERANGE; + goto rng_mem_err; + } + + /* Use 2 buckets to avoid contention */ + rcfg->max_tmo_ns = rcfg->timer_tick_ns; + rcfg->timer_tick_ns /= 2; + is_periodic = 1; + } + tim_ring = rte_zmalloc("otx2_tim_prv", sizeof(struct otx2_tim_ring), 0); if (tim_ring == NULL) { rc = -ENOMEM; @@ -296,11 +312,13 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr) tim_ring->clk_src = (int)rcfg->clk_src; tim_ring->ring_id = adptr->data->id; tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10); - tim_ring->max_tout = rcfg->max_tmo_ns; + tim_ring->max_tout = is_periodic ? + rcfg->timer_tick_ns * 2 : rcfg->max_tmo_ns; tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec); tim_ring->chunk_sz = dev->chunk_sz; tim_ring->nb_timers = rcfg->nb_timers; tim_ring->disable_npa = dev->disable_npa; + tim_ring->ena_periodic = is_periodic; tim_ring->enable_stats = dev->enable_stats; for (i = 0; i < dev->ring_ctl_cnt ; i++) { @@ -348,7 +366,7 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr) cfg_req->ring = tim_ring->ring_id; cfg_req->bigendian = false; cfg_req->clocksource = tim_ring->clk_src; - cfg_req->enableperiodic = false; + cfg_req->enableperiodic = tim_ring->ena_periodic; cfg_req->enabledontfreebuffer = tim_ring->ena_dfb; cfg_req->bucketsize = tim_ring->nb_bkts; cfg_req->chunksize = tim_ring->chunk_sz; @@ -568,7 +586,8 @@ otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, /* Store evdev pointer for later use. */ dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev; - *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT; + *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT | + RTE_EVENT_TIMER_ADAPTER_CAP_PERIODIC; *ops = &otx2_tim_ops; return 0; diff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h index 44e3c7b51..82d116c09 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.h +++ b/drivers/event/octeontx2/otx2_tim_evdev.h @@ -155,6 +155,7 @@ struct otx2_tim_ring { uint8_t disable_npa; uint8_t optimized; uint8_t ena_dfb; + uint8_t ena_periodic; uint16_t ring_id; uint32_t aura; uint64_t nb_timers;