From patchwork Wed Oct 11 18:32:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrien Mazarguil X-Patchwork-Id: 30167 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C35651B205; Wed, 11 Oct 2017 20:32:26 +0200 (CEST) Received: from mail-wm0-f47.google.com (mail-wm0-f47.google.com [74.125.82.47]) by dpdk.org (Postfix) with ESMTP id 71EC91B1BF for ; Wed, 11 Oct 2017 20:32:23 +0200 (CEST) Received: by mail-wm0-f47.google.com with SMTP id t69so7217260wmt.2 for ; Wed, 11 Oct 2017 11:32:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Cu+iVbXOKrvjRc9pQil4IS+eIGMPNovo8d5B7ZWJ/Ss=; b=pMzeLcjiePQR8LHgzCAmHjCsaKLUY7N+77esyWVx/sw74cB2/gNVrex1bYEqO163hW YLlcWPJsFLjHRBecOGsSqEylFeZiLlA6Y0/xjgI2GJUupsIg8FR7KVqgEHYfC2CfSkz3 4YL14+VRtdAnFEVdyonQZly9GSe5f3guoXzNRxDCeooJQKzMBXygKmezvaD70RFtjUUF tR10m9FyNBJ8dKtFKbkAZtavojgDE++YJpup55I1ruGuM0kCcNPKA3Sw3fpp18TIOdnS 96SpXjejmQBWmub+J23iKXvpvQOYMGR3ruIXGLzlq21zn9mtXcBD7fqYA5/eEaEOb935 NFhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Cu+iVbXOKrvjRc9pQil4IS+eIGMPNovo8d5B7ZWJ/Ss=; b=GYJ8CJIKvwi60FWyDEUPE14daXEOJC/y385r7siJnYnhorNEW9vLPWx1BKBWl0D67W JoLUYAaptVWb4vDyu06EUHeFjLJc7GlONqPv716OY/GN62jCl+L5WP7v+EuiExX82oWD LlksDavvoJ7nRugWCbH6e68QcAvqgQCcW2g1Gamasa1PX816rdYvI51I3oswEgJM2obR FDVNI+vif7dCO0L2jB0CBcMeuCQpU8VWP96LVAxSTkUNrfInlNGRuwOalg/ReQ5UfKLx au9mScg4Q1hDMwqs7Fnz1lZGgPa6xzSXkosiLmMhQWKx0Ml7mN0RBPCHAh0KzSD7/zHz gHOw== X-Gm-Message-State: AMCzsaVmbGOsD9YOj9cpv0YOwK9Ri2yYgUfGU5Jt2as0RvCk0qo3G98e GaJszbL+QcwaEiFBbhEbUPxOSQ== X-Google-Smtp-Source: AOwi7QA18Q1aQL+ysq+4sj6Hbq4Z92eF+vmNfE1IMc4pGAXJXJCqFtEvR+JQ+00sb/KqqCBCKTN6/g== X-Received: by 10.223.196.199 with SMTP id o7mr396723wrf.119.1507746742958; Wed, 11 Oct 2017 11:32:22 -0700 (PDT) Received: from 6wind.com (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id 64sm8649885wma.21.2017.10.11.11.32.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Oct 2017 11:32:22 -0700 (PDT) From: Adrien Mazarguil To: Ferruh Yigit Cc: dev@dpdk.org, Matan Azrad , Ophir Munk , Moti Haimovsky Date: Wed, 11 Oct 2017 20:32:00 +0200 Message-Id: <5699f8d141eb5cec7dcff89a3c5ebc93b9836808.1507746059.git.adrien.mazarguil@6wind.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: References: <1507195992-12513-1-git-send-email-ophirmu@mellanox.com> Subject: [dpdk-dev] [PATCH v5 3/5] net/mlx4: restore Tx checksum offloads X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Moti Haimovsky This patch adds hardware offloading support for IPv4, UDP and TCP checksum calculation, including inner/outer checksums on supported tunnel types. Signed-off-by: Moti Haimovsky Acked-by: Adrien Mazarguil --- drivers/net/mlx4/mlx4.c | 11 +++++++++++ drivers/net/mlx4/mlx4.h | 2 ++ drivers/net/mlx4/mlx4_ethdev.c | 6 ++++++ drivers/net/mlx4/mlx4_prm.h | 2 ++ drivers/net/mlx4/mlx4_rxtx.c | 19 +++++++++++++++++++ drivers/net/mlx4/mlx4_rxtx.h | 2 ++ drivers/net/mlx4/mlx4_txq.c | 2 ++ 7 files changed, 44 insertions(+) diff --git a/drivers/net/mlx4/mlx4.c b/drivers/net/mlx4/mlx4.c index 0db9a19..a297b9a 100644 --- a/drivers/net/mlx4/mlx4.c +++ b/drivers/net/mlx4/mlx4.c @@ -566,6 +566,17 @@ mlx4_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) priv->pd = pd; priv->mtu = ETHER_MTU; priv->vf = vf; + priv->hw_csum = !!(device_attr.device_cap_flags & + IBV_DEVICE_RAW_IP_CSUM); + DEBUG("checksum offloading is %ssupported", + (priv->hw_csum ? "" : "not ")); + /* Only ConnectX-3 Pro supports tunneling. */ + priv->hw_csum_l2tun = + priv->hw_csum && + (device_attr.vendor_part_id == + PCI_DEVICE_ID_MELLANOX_CONNECTX3PRO); + DEBUG("L2 tunnel checksum offloads are %ssupported", + (priv->hw_csum_l2tun ? "" : "not ")); /* Configure the first MAC address by default. */ if (mlx4_get_mac(priv, &mac.addr_bytes)) { ERROR("cannot get MAC address, is mlx4_en loaded?" diff --git a/drivers/net/mlx4/mlx4.h b/drivers/net/mlx4/mlx4.h index f4da8c6..e0a9853 100644 --- a/drivers/net/mlx4/mlx4.h +++ b/drivers/net/mlx4/mlx4.h @@ -113,6 +113,8 @@ struct priv { uint32_t vf:1; /**< This is a VF device. */ uint32_t intr_alarm:1; /**< An interrupt alarm is scheduled. */ uint32_t isolated:1; /**< Toggle isolated mode. */ + uint32_t hw_csum:1; /* Checksum offload is supported. */ + uint32_t hw_csum_l2tun:1; /* Checksum support for L2 tunnels. */ struct rte_intr_handle intr_handle; /**< Port interrupt handle. */ struct mlx4_drop *drop; /**< Shared resources for drop flow rules. */ LIST_HEAD(, mlx4_rss) rss; /**< Shared targets for Rx flow rules. */ diff --git a/drivers/net/mlx4/mlx4_ethdev.c b/drivers/net/mlx4/mlx4_ethdev.c index 3623909..a8c0ee2 100644 --- a/drivers/net/mlx4/mlx4_ethdev.c +++ b/drivers/net/mlx4/mlx4_ethdev.c @@ -767,6 +767,12 @@ mlx4_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) info->max_mac_addrs = RTE_DIM(priv->mac); info->rx_offload_capa = 0; info->tx_offload_capa = 0; + if (priv->hw_csum) + info->tx_offload_capa |= (DEV_TX_OFFLOAD_IPV4_CKSUM | + DEV_TX_OFFLOAD_UDP_CKSUM | + DEV_TX_OFFLOAD_TCP_CKSUM); + if (priv->hw_csum_l2tun) + info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; if (mlx4_get_ifname(priv, &ifname) == 0) info->if_index = if_nametoindex(ifname); info->hash_key_size = MLX4_RSS_HASH_KEY_SIZE; diff --git a/drivers/net/mlx4/mlx4_prm.h b/drivers/net/mlx4/mlx4_prm.h index 085a595..df5a6b4 100644 --- a/drivers/net/mlx4/mlx4_prm.h +++ b/drivers/net/mlx4/mlx4_prm.h @@ -64,6 +64,8 @@ /* Work queue element (WQE) flags. */ #define MLX4_BIT_WQE_OWN 0x80000000 +#define MLX4_WQE_CTRL_IIP_HDR_CSUM (1 << 28) +#define MLX4_WQE_CTRL_IL4_HDR_CSUM (1 << 27) #define MLX4_SIZE_TO_TXBBS(size) \ (RTE_ALIGN((size), (MLX4_TXBB_SIZE)) >> (MLX4_TXBB_SHIFT)) diff --git a/drivers/net/mlx4/mlx4_rxtx.c b/drivers/net/mlx4/mlx4_rxtx.c index cc0baaa..fe7d5d0 100644 --- a/drivers/net/mlx4/mlx4_rxtx.c +++ b/drivers/net/mlx4/mlx4_rxtx.c @@ -431,6 +431,25 @@ mlx4_post_send(struct txq *txq, struct rte_mbuf *pkt) } else { srcrb_flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT); } + /* Enable HW checksum offload if requested */ + if (txq->csum && + (pkt->ol_flags & + (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))) { + const uint64_t is_tunneled = (pkt->ol_flags & + (PKT_TX_TUNNEL_GRE | + PKT_TX_TUNNEL_VXLAN)); + + if (is_tunneled && txq->csum_l2tun) { + owner_opcode |= MLX4_WQE_CTRL_IIP_HDR_CSUM | + MLX4_WQE_CTRL_IL4_HDR_CSUM; + if (pkt->ol_flags & PKT_TX_OUTER_IP_CKSUM) + srcrb_flags |= + RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM); + } else { + srcrb_flags |= RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM | + MLX4_WQE_CTRL_TCP_UDP_CSUM); + } + } ctrl->srcrb_flags = srcrb_flags; /* * Make sure descriptor is fully written before diff --git a/drivers/net/mlx4/mlx4_rxtx.h b/drivers/net/mlx4/mlx4_rxtx.h index fa5738f..6c88efb 100644 --- a/drivers/net/mlx4/mlx4_rxtx.h +++ b/drivers/net/mlx4/mlx4_rxtx.h @@ -124,6 +124,8 @@ struct txq { struct txq_elt (*elts)[]; /**< Tx elements. */ struct mlx4_txq_stats stats; /**< Tx queue counters. */ uint32_t max_inline; /**< Max inline send size. */ + uint32_t csum:1; /**< Enable checksum offloading. */ + uint32_t csum_l2tun:1; /**< Same for L2 tunnels. */ uint8_t *bounce_buf; /**< Memory used for storing the first DWORD of data TXBBs. */ struct { diff --git a/drivers/net/mlx4/mlx4_txq.c b/drivers/net/mlx4/mlx4_txq.c index 4258513..41cdc4d 100644 --- a/drivers/net/mlx4/mlx4_txq.c +++ b/drivers/net/mlx4/mlx4_txq.c @@ -276,6 +276,8 @@ mlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, RTE_MIN(MLX4_PMD_TX_PER_COMP_REQ, desc / 4), .elts_comp_cd_init = RTE_MIN(MLX4_PMD_TX_PER_COMP_REQ, desc / 4), + .csum = priv->hw_csum, + .csum_l2tun = priv->hw_csum_l2tun, .bounce_buf = bounce_buf, }; txq->cq = ibv_create_cq(priv->ctx, desc, NULL, NULL, 0);