[v1,03/24] net/igc/base: fix bitwise op type mismatch

Message ID 7d0d5ba85d3bbf68cc08be40c7208437607f7e6b.1738858026.git.anatoly.burakov@intel.com (mailing list archive)
State Accepted
Delegated to: Bruce Richardson
Headers
Series Fixes for igc and e1000 |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Burakov, Anatoly Feb. 6, 2025, 4:08 p.m. UTC
From: Przemyslaw Ciesielski <przemyslaw.ciesielski@intel.com>

Static analysis has found type mismatch between mask and register value.
Fix the bitwise operation type to avoid potential issues.

Fixes: 8cb7c57d9b3c ("net/igc: support device initialization")
Cc: stable@dpdk.org

Signed-off-by: Przemyslaw Ciesielski <przemyslaw.ciesielski@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
 drivers/net/intel/igc/base/igc_i225.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
  

Patch

diff --git a/drivers/net/intel/igc/base/igc_i225.c b/drivers/net/intel/igc/base/igc_i225.c
index 8f01f8d918..1277f59885 100644
--- a/drivers/net/intel/igc/base/igc_i225.c
+++ b/drivers/net/intel/igc/base/igc_i225.c
@@ -344,7 +344,7 @@  void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask)
 	}
 
 	swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC);
-	swfw_sync &= ~mask;
+	swfw_sync &= ~(u32)mask;
 	IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync);
 
 	igc_put_hw_semaphore_generic(hw);