diff mbox series

[v3,12/36] net/e1000/base: add PHY power management control

Message ID 872a0eb37e95919957937619f2b3b2e00bf3bdb4.1738932115.git.anatoly.burakov@intel.com (mailing list archive)
State Accepted
Delegated to: Bruce Richardson
Headers
Series Merge Intel IGC and E1000 drivers, and update E1000 base code |

Checks

Context Check Description
ci/checkpatch warning coding style issues

Commit Message

Burakov, Anatoly Feb. 7, 2025, 12:45 p.m. UTC 
From: Sasha Neftin <sasha.neftin@intel.com>

PHY power management control is expected to provide a reliable and
accurate indication of PHY reset completion, which allows us to decrease
the delay time after a PHY reset.

Signed-off-by: Sasha Neftin <sasha.neftin@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
 drivers/net/intel/e1000/base/e1000_defines.h |  2 ++
 drivers/net/intel/e1000/base/e1000_phy.c     | 16 +++++++++++++++-
 2 files changed, 17 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/net/intel/e1000/base/e1000_defines.h b/drivers/net/intel/e1000/base/e1000_defines.h
index 2037e006c4..2c3b806c92 100644
--- a/drivers/net/intel/e1000/base/e1000_defines.h
+++ b/drivers/net/intel/e1000/base/e1000_defines.h
@@ -1100,6 +1100,8 @@ 
 
 #define PHY_CONTROL_LB		0x4000 /* PHY Loopback bit */
 
+#define E1000_PHY_RST_COMP	0x0100 /* Internal PHY reset completion */
+
 /* NVM Control */
 #define E1000_EECD_SK		0x00000001 /* NVM Clock */
 #define E1000_EECD_CS		0x00000002 /* NVM Chip Select */
diff --git a/drivers/net/intel/e1000/base/e1000_phy.c b/drivers/net/intel/e1000/base/e1000_phy.c
index 4b6401b06a..d3d7ff6ba8 100644
--- a/drivers/net/intel/e1000/base/e1000_phy.c
+++ b/drivers/net/intel/e1000/base/e1000_phy.c
@@ -2918,6 +2918,10 @@  s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
 	if (ret_val)
 		return ret_val;
 
+	if (hw->mac.type == e1000_i225) {
+		E1000_READ_REG(hw, E1000_I225_PHPM);
+	}
+
 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
 	E1000_WRITE_FLUSH(hw);
@@ -2927,7 +2931,17 @@  s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 	E1000_WRITE_FLUSH(hw);
 
-	usec_delay(150);
+	if (hw->mac.type == e1000_i225) {
+		u32 phpm = 0, timeout = 10000;
+		/* SW should guarantee 100us for the completion of the PHY reset */
+		usec_delay(100);
+		do {
+			phpm = E1000_READ_REG(hw, E1000_I225_PHPM);
+			timeout--;
+			usec_delay(1);
+		} while (!(phpm & E1000_PHY_RST_COMP) && timeout);
+	}
+	usec_delay(100);
 
 	phy->ops.release(hw);