From patchwork Wed Mar 17 08:04:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shijith Thotton X-Patchwork-Id: 89348 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6C885A00C2; Wed, 17 Mar 2021 09:05:47 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5AE32242B55; Wed, 17 Mar 2021 09:05:47 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 4B76D4014D for ; Wed, 17 Mar 2021 09:05:45 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 12H80a5g017780; Wed, 17 Mar 2021 01:05:44 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=hgVcnlo3VkKA6sO7p9lpImpCS3k36Xs8l7FgewBQ59c=; b=hRwW7/J7+V1MBjgaGGbgYU8oLud7fJimMqfokcVlGyytQPUMGaH9fJpexcfhXwC1oqxo OyMPBMCXR2so6CqxwmvDo8nbyePfHd0YAt7AenUvbul+JvfJqotMtcUelfUwbICe0cZZ npFbNqVpQKRyA7CbOnio+NoXvEZd6QT7mquWkESVij3ZoQdbVDZLVi5HUR0nACSOUUmy DREcxPGrp/tBK9bvFvNHnRNNs6aUD/Pq3J5JQD1THPDCuIySJQok8TwrfNpdTc2DYGJc YjnvR7oWRmv1TopBSqn/NCssiPq+BVOHwvHLYm0WPtnyc0ZkL2iCVFI1Cq1ETrzkZNLd JQ== Received: from dc6wp-exch01.marvell.com ([4.21.29.232]) by mx0a-0016f401.pphosted.com with ESMTP id 37b5vdhbkh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 17 Mar 2021 01:05:44 -0700 Received: from DC6WP-EXCH01.marvell.com (10.76.176.21) by DC6WP-EXCH01.marvell.com (10.76.176.21) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Mar 2021 04:05:42 -0400 Received: from maili.marvell.com (10.76.176.51) by DC6WP-EXCH01.marvell.com (10.76.176.21) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 17 Mar 2021 04:05:42 -0400 Received: from localhost.localdomain (unknown [10.28.34.29]) by maili.marvell.com (Postfix) with ESMTP id 625D73F703F; Wed, 17 Mar 2021 01:05:40 -0700 (PDT) From: Shijith Thotton To: Erik Gabriel Carrillo CC: Shijith Thotton , Pavan Nikhilesh , Jerin Jacob , Date: Wed, 17 Mar 2021 13:34:20 +0530 Message-ID: <8be24528babf59590d137de77ccdc2ef86e19d39.1615967694.git.sthotton@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-17_02:2021-03-17, 2021-03-17 signatures=0 Subject: [dpdk-dev] [PATCH v3 2/3] test/event: add unit tests for periodic timer X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add tests to arm and cancel periodic timer. Signed-off-by: Shijith Thotton Acked-by: Erik Gabriel Carrillo --- app/test/test_event_timer_adapter.c | 138 +++++++++++++++++++++++++--- 1 file changed, 125 insertions(+), 13 deletions(-) diff --git a/app/test/test_event_timer_adapter.c b/app/test/test_event_timer_adapter.c index b536ddef4..c36ab32ac 100644 --- a/app/test/test_event_timer_adapter.c +++ b/app/test/test_event_timer_adapter.c @@ -283,7 +283,7 @@ test_port_conf_cb(uint16_t id, uint8_t event_dev_id, uint8_t *event_port_id, } static int -_timdev_setup(uint64_t max_tmo_ns, uint64_t bkt_tck_ns) +_timdev_setup(uint64_t max_tmo_ns, uint64_t bkt_tck_ns, uint64_t flags) { struct rte_event_timer_adapter_info info; struct rte_event_timer_adapter_conf config = { @@ -292,7 +292,7 @@ _timdev_setup(uint64_t max_tmo_ns, uint64_t bkt_tck_ns) .timer_tick_ns = bkt_tck_ns, .max_tmo_ns = max_tmo_ns, .nb_timers = MAX_TIMERS * 10, - .flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES, + .flags = flags, }; uint32_t caps = 0; const char *pool_name = "timdev_test_pool"; @@ -301,6 +301,13 @@ _timdev_setup(uint64_t max_tmo_ns, uint64_t bkt_tck_ns) TEST_ASSERT_SUCCESS(rte_event_timer_adapter_caps_get(evdev, &caps), "failed to get adapter capabilities"); + + if (flags & RTE_EVENT_TIMER_ADAPTER_F_PERIODIC && + !(caps & RTE_EVENT_TIMER_ADAPTER_CAP_PERIODIC)) { + printf("Adapter does not support periodic timers\n"); + return TEST_SKIPPED; + } + if (!(caps & RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT)) { timdev = rte_event_timer_adapter_create_ext(&config, test_port_conf_cb, @@ -338,42 +345,72 @@ _timdev_setup(uint64_t max_tmo_ns, uint64_t bkt_tck_ns) static int timdev_setup_usec(void) { + uint64_t flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES; + return using_services ? /* Max timeout is 10,000us and bucket interval is 100us */ - _timdev_setup(1E7, 1E5) : + _timdev_setup(1E7, 1E5, flags) : /* Max timeout is 100us and bucket interval is 1us */ - _timdev_setup(1E5, 1E3); + _timdev_setup(1E5, 1E3, flags); } static int timdev_setup_usec_multicore(void) { + uint64_t flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES; + return using_services ? /* Max timeout is 10,000us and bucket interval is 100us */ - _timdev_setup(1E7, 1E5) : + _timdev_setup(1E7, 1E5, flags) : /* Max timeout is 100us and bucket interval is 1us */ - _timdev_setup(1E5, 1E3); + _timdev_setup(1E5, 1E3, flags); } static int timdev_setup_msec(void) { - /* Max timeout is 2 mins, and bucket interval is 100 ms */ - return _timdev_setup(180 * NSECPERSEC, NSECPERSEC / 10); + uint64_t flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES; + + /* Max timeout is 3 mins, and bucket interval is 100 ms */ + return _timdev_setup(180 * NSECPERSEC, NSECPERSEC / 10, flags); +} + +static int +timdev_setup_msec_periodic(void) +{ + uint64_t flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES | + RTE_EVENT_TIMER_ADAPTER_F_PERIODIC; + + /* Periodic mode with 100 ms resolution */ + return _timdev_setup(0, NSECPERSEC / 10, flags); } static int timdev_setup_sec(void) { + uint64_t flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES; + /* Max timeout is 100sec and bucket interval is 1sec */ - return _timdev_setup(1E11, 1E9); + return _timdev_setup(1E11, 1E9, flags); +} + +static int +timdev_setup_sec_periodic(void) +{ + uint64_t flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES | + RTE_EVENT_TIMER_ADAPTER_F_PERIODIC; + + /* Periodic mode with 1 sec resolution */ + return _timdev_setup(0, NSECPERSEC, flags); } static int timdev_setup_sec_multicore(void) { + uint64_t flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES; + /* Max timeout is 100sec and bucket interval is 1sec */ - return _timdev_setup(1E11, 1E9); + return _timdev_setup(1E11, 1E9, flags); } static void @@ -513,6 +550,19 @@ test_timer_arm(void) return TEST_SUCCESS; } +static inline int +test_timer_arm_periodic(void) +{ + TEST_ASSERT_SUCCESS(_arm_timers(1, MAX_TIMERS), + "Failed to arm timers"); + /* With a resolution of 100ms and wait time of 1sec, + * there will be 10 * MAX_TIMERS periodic timer triggers. + */ + TEST_ASSERT_SUCCESS(_wait_timer_triggers(1, 10 * MAX_TIMERS, 0), + "Timer triggered count doesn't match arm count"); + return TEST_SUCCESS; +} + static int _arm_wrapper(void *arg) { @@ -588,6 +638,20 @@ test_timer_arm_burst(void) return TEST_SUCCESS; } +static inline int +test_timer_arm_burst_periodic(void) +{ + TEST_ASSERT_SUCCESS(_arm_timers_burst(1, MAX_TIMERS), + "Failed to arm timers"); + /* With a resolution of 100ms and wait time of 1sec, + * there will be 10 * MAX_TIMERS periodic timer triggers. + */ + TEST_ASSERT_SUCCESS(_wait_timer_triggers(1, 10 * MAX_TIMERS, 0), + "Timer triggered count doesn't match arm count"); + + return TEST_SUCCESS; +} + static int _arm_wrapper_burst(void *arg) { @@ -612,6 +676,48 @@ test_timer_arm_burst_multicore(void) return TEST_SUCCESS; } +static inline int +test_timer_cancel_periodic(void) +{ + uint64_t i; + struct rte_event_timer *ev_tim; + const struct rte_event_timer tim = { + .ev.op = RTE_EVENT_OP_NEW, + .ev.queue_id = 0, + .ev.sched_type = RTE_SCHED_TYPE_ATOMIC, + .ev.priority = RTE_EVENT_DEV_PRIORITY_NORMAL, + .ev.event_type = RTE_EVENT_TYPE_TIMER, + .state = RTE_EVENT_TIMER_NOT_ARMED, + .timeout_ticks = CALC_TICKS(1), + }; + + for (i = 0; i < MAX_TIMERS; i++) { + TEST_ASSERT_SUCCESS(rte_mempool_get(eventdev_test_mempool, + (void **)&ev_tim), + "mempool alloc failed"); + *ev_tim = tim; + ev_tim->ev.event_ptr = ev_tim; + + TEST_ASSERT_EQUAL(rte_event_timer_arm_burst(timdev, &ev_tim, + 1), 1, "Failed to arm timer %d", + rte_errno); + + rte_delay_us(100 + (i % 5000)); + + TEST_ASSERT_EQUAL(rte_event_timer_cancel_burst(timdev, + &ev_tim, 1), 1, + "Failed to cancel event timer %d", rte_errno); + rte_mempool_put(eventdev_test_mempool, ev_tim); + } + + + TEST_ASSERT_SUCCESS(_wait_timer_triggers(30, MAX_TIMERS, + MAX_TIMERS), + "Timer triggered count doesn't match arm, cancel count"); + + return TEST_SUCCESS; +} + static inline int test_timer_cancel(void) { @@ -1028,9 +1134,9 @@ adapter_lookup(void) static int adapter_start(void) { - TEST_ASSERT_SUCCESS(_timdev_setup(180 * NSECPERSEC, - NSECPERSEC / 10), - "Failed to start adapter"); + TEST_ASSERT_SUCCESS(_timdev_setup(180 * NSECPERSEC, NSECPERSEC / 10, + RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES), + "Failed to start adapter"); TEST_ASSERT_EQUAL(rte_event_timer_adapter_start(timdev), -EALREADY, "Timer adapter started without call to stop."); @@ -1786,10 +1892,16 @@ static struct unit_test_suite event_timer_adptr_functional_testsuite = { test_timer_state), TEST_CASE_ST(timdev_setup_usec, timdev_teardown, test_timer_arm), + TEST_CASE_ST(timdev_setup_msec_periodic, timdev_teardown, + test_timer_arm_periodic), TEST_CASE_ST(timdev_setup_usec, timdev_teardown, test_timer_arm_burst), + TEST_CASE_ST(timdev_setup_msec_periodic, timdev_teardown, + test_timer_arm_burst_periodic), TEST_CASE_ST(timdev_setup_sec, timdev_teardown, test_timer_cancel), + TEST_CASE_ST(timdev_setup_sec_periodic, timdev_teardown, + test_timer_cancel_periodic), TEST_CASE_ST(timdev_setup_sec, timdev_teardown, test_timer_cancel_random), TEST_CASE_ST(timdev_setup_usec_multicore, timdev_teardown,