From patchwork Thu Sep 2 14:41:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shijith Thotton X-Patchwork-Id: 97828 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 08FAFA0C4C; Thu, 2 Sep 2021 16:43:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7B78840E2D; Thu, 2 Sep 2021 16:43:16 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 2E5BF40698 for ; Thu, 2 Sep 2021 16:43:15 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18280qPl010845 for ; Thu, 2 Sep 2021 07:43:13 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=1ooP44cncvEiFgrXni0SimD2D09H09GCz47L7qUVpeE=; b=b1RErO0XUZw+aPbxwtYpRTp56CJ/gWxdHUfAwvippxrW7kEVUiPEsr2u9/gG2WJeN/OD GiYrNbZzX+J3oLVEs/rCPd3jDVDp95gSiQ2XTVLTGk1tqR82HGvWuj8/2slOlstmb5HF QaVLrWHjHntl1IU5Tl0odQgdhAMkTSTf4WQ3gFDXkN2b9YSjyGmOb2EsuoAHvXgQQwly i+z3g1i7+PX+EtXVcR5Pk2BJlSJMipwaQUZWr9WhuqPSSypXHBzTYTuV/s47BRqb0/1c H/vOv1AGVZ4hig677CSOf7BVSX0zFBPQ7ZbBMpQ5guhV9nnjC5uzvsTWtcysMSmg5uN7 Fg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3attqmhc83-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 02 Sep 2021 07:43:13 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 2 Sep 2021 07:43:11 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 2 Sep 2021 07:43:11 -0700 Received: from localhost.localdomain (unknown [10.28.34.29]) by maili.marvell.com (Postfix) with ESMTP id 33E4C3F705F; Thu, 2 Sep 2021 07:43:08 -0700 (PDT) From: Shijith Thotton To: CC: Shijith Thotton , , , , , , Kiran Kumar K , "Sunil Kumar Kori" , Satha Rao Date: Thu, 2 Sep 2021 20:11:51 +0530 Message-ID: <8e365d37c0475a35485b3bce15e8fe749cfe35f6.1630593512.git.sthotton@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-GUID: xBtVA2Hbjap1uYs7OZZBF_ldhKnWo4AL X-Proofpoint-ORIG-GUID: xBtVA2Hbjap1uYs7OZZBF_ldhKnWo4AL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-02_04,2021-09-02_03,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 3/8] common/cnxk: add API to check CPT IQ is full X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Added flow control based check to determine CPT IQ is full. Signed-off-by: Shijith Thotton --- drivers/common/cnxk/roc_cpt.c | 6 ++++-- drivers/common/cnxk/roc_cpt.h | 11 +++++++++++ drivers/common/cnxk/roc_cpt_priv.h | 6 ------ 3 files changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index c001497f74..5e35d1bdda 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -464,6 +464,8 @@ cpt_iq_init(struct roc_cpt_lf *lf) plt_write64(lf_q_size.u, lf->rbase + CPT_LF_Q_SIZE); lf->fc_addr = (uint64_t *)addr; + lf->fc_hyst_bits = plt_log2_u32(lf->nb_desc) / 2; + lf->fc_thresh = lf->nb_desc - (lf->nb_desc % (1 << lf->fc_hyst_bits)); } int @@ -809,8 +811,8 @@ roc_cpt_iq_enable(struct roc_cpt_lf *lf) lf_ctl.u = plt_read64(lf->rbase + CPT_LF_CTL); lf_ctl.s.ena = 1; lf_ctl.s.fc_ena = 1; - lf_ctl.s.fc_up_crossing = 1; - lf_ctl.s.fc_hyst_bits = CPT_FC_NUM_HYST_BITS; + lf_ctl.s.fc_up_crossing = 0; + lf_ctl.s.fc_hyst_bits = lf->fc_hyst_bits; plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL); cpt_lf_dump(lf); diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index 3a2f5b97e1..f0f505a8c2 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -94,6 +94,8 @@ struct roc_cpt_lf { uint16_t msixoff; uint16_t pf_func; uint64_t *fc_addr; + uint32_t fc_hyst_bits; + uint64_t fc_thresh; uint64_t io_addr; uint8_t *iq_vaddr; struct roc_nix *inl_outb_nix; @@ -121,6 +123,15 @@ struct roc_cpt_rxc_time_cfg { uint16_t zombie_thres; }; +static inline int +roc_cpt_is_iq_full(struct roc_cpt_lf *lf) +{ + if (*lf->fc_addr < lf->fc_thresh) + return 0; + + return 1; +} + int __roc_api roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg); int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt); diff --git a/drivers/common/cnxk/roc_cpt_priv.h b/drivers/common/cnxk/roc_cpt_priv.h index 0880ec098d..21911e5d79 100644 --- a/drivers/common/cnxk/roc_cpt_priv.h +++ b/drivers/common/cnxk/roc_cpt_priv.h @@ -5,12 +5,6 @@ #ifndef _ROC_CPT_PRIV_H_ #define _ROC_CPT_PRIV_H_ -/* Set number of hystbits to 6. - * This will trigger the FC writes whenever number of outstanding commands in - * the queue becomes multiple of 32. - */ -#define CPT_FC_NUM_HYST_BITS 6 - struct cpt { struct plt_pci_device *pci_dev; struct dev dev;