[dpdk-dev,1/2] eal:Introduce rte_dma_wmb/rte_dma_rmb.
Commit Message
These macro can be used to replace current PMD's compiler memory barrier (volatile varible) and rte_wmb.
In x86, they implement to compiler memory barrier.
In power, they implement to processor memory barrier.
---
.../common/include/arch/ppc_64/rte_atomic.h | 4 ++++
.../common/include/arch/x86/rte_atomic.h | 4 ++++
lib/librte_eal/common/include/generic/rte_atomic.h | 25 ++++++++++++++++++++++
3 files changed, 33 insertions(+)
@@ -72,6 +72,10 @@ extern "C" {
*/
#define rte_rmb() {asm volatile("sync" : : : "memory"); }
+#define rte_dma_wmb() {asm volatile("sync" : : : "memory"); }
+
+#define rte_dma_rmb() {asm volatile("sync" : : : "memory");
+
/*------------------------- 16 bit atomic operations -------------------------*/
/* To be compatible with Power7, use GCC built-in functions for 16 bit
* operations */
@@ -53,6 +53,10 @@ extern "C" {
#define rte_rmb() _mm_lfence()
+#define rte_dma_wmb() rte_compiler_barrier()
+
+#define rte_dma_rmb() rte_compiler_barrier()
+
/*------------------------- 16 bit atomic operations -------------------------*/
#ifndef RTE_FORCE_INTRINSICS
@@ -72,6 +72,31 @@ static inline void rte_wmb(void);
*/
static inline void rte_rmb(void);
+/**
+ * Write memory barrier for DMA.
+ *
+ * Be used in PMD, unlike rte_wmb() which use processor memory barrier,
+ * this memory barrier focus on performance, if compiler memory barrier
+ * is sufficient for guarantee memory ordering, this function will
+ * use compiler memory barrier.
+ *
+ * This function is architecture dependent.
+ */
+static inline void rte_dma_wmb(void);
+
+/**
+ * Read memory barrier for DMA.
+ *
+ * Be used in PMD, unlike rte_rmb() which use processor memory barrier,
+ * this memory barrier focus on performance, if compiler memory barrier
+ * is sufficient for guarantee memory ordering, this function will
+ * use compiler memory barrier.
+ *
+ * This function is architecture dependent.
+ */
+static inline void rte_dma_rmb(void);
+
+
#endif /* __DOXYGEN__ */
/**