On Fri, Feb 07, 2025 at 02:12:27PM +0100, Burakov, Anatoly wrote:
> On 07/02/2025 14:04, Bruce Richardson wrote:
> > On Fri, Feb 07, 2025 at 12:44:59PM +0000, Anatoly Burakov wrote:
> > > From: Vitaly Lifshits <vitaly.lifshits@intel.com>
> > >
> > > Add support for new hardware ID's from the I219 series.
> > >
> > > Signed-off-by: Vitaly Lifshits <vitaly.lifshits@intel.com>
> > > Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
> > > ---
> >
> > Should i219 be added to the base code README as a supported device family?
> > If so, I can just add on apply, if no other issues with this set.
>
> i219 NICs were already supported by the driver. This is just adding missing
> *kinds* of i219 NICs. However, I can see that the support for i219 was
> called out in 17.02 release notes:
>
> 31d4210971c54952afc9a1455ca40861634206e0
> net/e1000/base: announce supported devices
>
> Document all supported NICs.
> Add Intel I219 NICs support in release note.
>
> Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
>
> It was not added to the list of supported NICs in igb documentation. So,
> yes, I think it is worth calling out support in this patch.
>
For i219, I see that it is actually in the list of devices given in the
REAME, with the list in that doc not being in sorted order, but more in
order of which sub-driver (e1000, igb and igc) supports them. The original
e1000 driver is the one supporting i219, so it's earlier in the list, which
is why I missed it.
For other docs, the e1000 driver guide doesn't call out the various
families of HW NICs supported, so no minor update needed there either it
seem. I'll therefore take this patch as-is.
/Bruce
@@ -278,6 +278,8 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
case E1000_DEV_ID_PCH_SPT_I219_V4:
case E1000_DEV_ID_PCH_SPT_I219_LM5:
case E1000_DEV_ID_PCH_SPT_I219_V5:
+ case E1000_DEV_ID_PCH_CMP_I219_LM12:
+ case E1000_DEV_ID_PCH_CMP_I219_V12:
mac->type = e1000_pch_spt;
break;
case E1000_DEV_ID_PCH_CNP_I219_LM6:
@@ -288,8 +290,18 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
case E1000_DEV_ID_PCH_ICP_I219_V8:
case E1000_DEV_ID_PCH_ICP_I219_LM9:
case E1000_DEV_ID_PCH_ICP_I219_V9:
+ case E1000_DEV_ID_PCH_CMP_I219_LM10:
+ case E1000_DEV_ID_PCH_CMP_I219_V10:
+ case E1000_DEV_ID_PCH_CMP_I219_LM11:
+ case E1000_DEV_ID_PCH_CMP_I219_V11:
mac->type = e1000_pch_cnp;
break;
+ case E1000_DEV_ID_PCH_TGP_I219_LM13:
+ case E1000_DEV_ID_PCH_TGP_I219_V13:
+ case E1000_DEV_ID_PCH_TGP_I219_LM14:
+ case E1000_DEV_ID_PCH_TGP_I219_V14:
+ case E1000_DEV_ID_PCH_TGP_I219_LM15:
+ case E1000_DEV_ID_PCH_TGP_I219_V15:
case E1000_DEV_ID_PCH_ADL_I219_LM16:
case E1000_DEV_ID_PCH_ADL_I219_V16:
case E1000_DEV_ID_PCH_RPL_I219_LM23:
@@ -302,6 +314,24 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
case E1000_DEV_ID_PCH_RPL_I219_V22:
mac->type = e1000_pch_adp;
break;
+ case E1000_DEV_ID_PCH_MTP_I219_LM18:
+ case E1000_DEV_ID_PCH_MTP_I219_V18:
+ case E1000_DEV_ID_PCH_MTP_I219_LM19:
+ case E1000_DEV_ID_PCH_MTP_I219_V19:
+ case E1000_DEV_ID_PCH_LNL_I219_LM20:
+ case E1000_DEV_ID_PCH_LNL_I219_V20:
+ case E1000_DEV_ID_PCH_ARL_I219_LM24:
+ case E1000_DEV_ID_PCH_ARL_I219_V24:
+ mac->type = e1000_pch_mtp;
+ break;
+ case E1000_DEV_ID_PCH_PTP_I219_LM25:
+ case E1000_DEV_ID_PCH_PTP_I219_V25:
+ case E1000_DEV_ID_PCH_WCL_I219_LM27:
+ case E1000_DEV_ID_PCH_WCL_I219_V27:
+ case E1000_DEV_ID_PCH_NVL_I219_LM29:
+ case E1000_DEV_ID_PCH_NVL_I219_V29:
+ mac->type = e1000_pch_ptp;
+ break;
case E1000_DEV_ID_82575EB_COPPER:
case E1000_DEV_ID_82575EB_FIBER_SERDES:
case E1000_DEV_ID_82575GB_QUAD_COPPER:
@@ -474,6 +504,8 @@ s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device)
case e1000_pch_cnp:
case e1000_pch_adp:
case e1000_pch_tgp:
+ case e1000_pch_mtp:
+ case e1000_pch_ptp:
e1000_init_function_pointers_ich8lan(hw);
break;
case e1000_82575:
@@ -124,14 +124,40 @@ struct e1000_hw;
#define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0
#define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1
#define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2
+#define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E
+#define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F
+#define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C
+#define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D
+#define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53
+#define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55
+#define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB
+#define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC
+#define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9
+#define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA
+#define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4
+#define E1000_DEV_ID_PCH_TGP_I219_V15 0x15F5
#define E1000_DEV_ID_PCH_ADL_I219_LM16 0x1A1E
#define E1000_DEV_ID_PCH_ADL_I219_V16 0x1A1F
#define E1000_DEV_ID_PCH_ADL_I219_LM17 0x1A1C
#define E1000_DEV_ID_PCH_ADL_I219_V17 0x1A1D
-#define E1000_DEV_ID_PCH_RPL_I219_LM23 0x0DC5
-#define E1000_DEV_ID_PCH_RPL_I219_V23 0x0DC6
-#define E1000_DEV_ID_PCH_RPL_I219_LM22 0x0DC7
-#define E1000_DEV_ID_PCH_RPL_I219_V22 0x0DC8
+#define E1000_DEV_ID_PCH_MTP_I219_LM18 0x550A
+#define E1000_DEV_ID_PCH_MTP_I219_V18 0x550B
+#define E1000_DEV_ID_PCH_MTP_I219_LM19 0x550C
+#define E1000_DEV_ID_PCH_MTP_I219_V19 0x550D
+#define E1000_DEV_ID_PCH_LNL_I219_LM20 0x550E
+#define E1000_DEV_ID_PCH_LNL_I219_V20 0x550F
+#define E1000_DEV_ID_PCH_RPL_I219_LM22 0x0DC7
+#define E1000_DEV_ID_PCH_RPL_I219_V22 0x0DC8
+#define E1000_DEV_ID_PCH_RPL_I219_LM23 0x0DC5
+#define E1000_DEV_ID_PCH_RPL_I219_V23 0x0DC6
+#define E1000_DEV_ID_PCH_ARL_I219_LM24 0x57A0
+#define E1000_DEV_ID_PCH_ARL_I219_V24 0x57A1
+#define E1000_DEV_ID_PCH_PTP_I219_LM25 0x57B3
+#define E1000_DEV_ID_PCH_PTP_I219_V25 0x57B4
+#define E1000_DEV_ID_PCH_WCL_I219_LM27 0x57B7
+#define E1000_DEV_ID_PCH_WCL_I219_V27 0x57B8
+#define E1000_DEV_ID_PCH_NVL_I219_LM29 0x57B9
+#define E1000_DEV_ID_PCH_NVL_I219_V29 0x57BA
#define E1000_DEV_ID_82576 0x10C9
#define E1000_DEV_ID_82576_FIBER 0x10E6
#define E1000_DEV_ID_82576_SERDES 0x10E7
@@ -237,6 +263,8 @@ enum e1000_mac_type {
e1000_pch_spt,
e1000_pch_cnp,
e1000_pch_adp,
+ e1000_pch_mtp,
+ e1000_pch_ptp,
e1000_pch_tgp,
e1000_82575,
e1000_82576,
@@ -314,7 +314,10 @@ STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
case e1000_pch_lpt:
case e1000_pch_spt:
case e1000_pch_cnp:
+ case e1000_pch_tgp:
case e1000_pch_adp:
+ case e1000_pch_mtp:
+ case e1000_pch_ptp:
if (e1000_phy_is_accessible_pchlan(hw))
break;
@@ -464,7 +467,10 @@ STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
case e1000_pch_lpt:
case e1000_pch_spt:
case e1000_pch_cnp:
+ case e1000_pch_tgp:
case e1000_pch_adp:
+ case e1000_pch_mtp:
+ case e1000_pch_ptp:
/* In case the PHY needs to be in mdio slow mode,
* set slow mode and try to get the PHY id again.
*/
@@ -768,7 +774,10 @@ STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
case e1000_pch_lpt:
case e1000_pch_spt:
case e1000_pch_cnp:
+ case e1000_pch_tgp:
case e1000_pch_adp:
+ case e1000_pch_mtp:
+ case e1000_pch_ptp:
/* multicast address update for pch2 */
mac->ops.update_mc_addr_list =
e1000_update_mc_addr_list_pch2lan;
@@ -1757,7 +1766,10 @@ void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
case e1000_pch_lpt:
case e1000_pch_spt:
case e1000_pch_cnp:
+ case e1000_pch_tgp:
case e1000_pch_adp:
+ case e1000_pch_mtp:
+ case e1000_pch_ptp:
hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
break;
default:
@@ -2223,7 +2235,10 @@ STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
case e1000_pch_lpt:
case e1000_pch_spt:
case e1000_pch_cnp:
+ case e1000_pch_tgp:
case e1000_pch_adp:
+ case e1000_pch_mtp:
+ case e1000_pch_ptp:
sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
break;
default:
@@ -3344,7 +3359,10 @@ STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
switch (hw->mac.type) {
case e1000_pch_spt:
case e1000_pch_cnp:
+ case e1000_pch_tgp:
case e1000_pch_adp:
+ case e1000_pch_mtp:
+ case e1000_pch_ptp:
bank1_offset = nvm->flash_bank_size;
act_offset = E1000_ICH_NVM_SIG_WORD;
@@ -4316,7 +4334,10 @@ STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
case e1000_pch_lpt:
case e1000_pch_spt:
case e1000_pch_cnp:
+ case e1000_pch_tgp:
case e1000_pch_adp:
+ case e1000_pch_mtp:
+ case e1000_pch_ptp:
word = NVM_COMPAT;
valid_csum_mask = NVM_COMPAT_VALID_CSUM;
break;
@@ -159,14 +159,34 @@ static const struct rte_pci_id pci_id_em_map[] = {
{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_ICP_I219_V8) },
{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_ICP_I219_LM9) },
{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_ICP_I219_V9) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CMP_I219_LM10) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CMP_I219_V10) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CMP_I219_LM11) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CMP_I219_V11) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CMP_I219_LM12) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CMP_I219_V12) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_TGP_I219_LM13) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_TGP_I219_V13) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_TGP_I219_LM14) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_TGP_I219_V14) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_TGP_I219_LM15) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_TGP_I219_V15) },
{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_ADL_I219_LM16) },
{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_ADL_I219_V16) },
{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_ADL_I219_LM17) },
{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_ADL_I219_V17) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_MTP_I219_LM18) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_MTP_I219_V18) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_MTP_I219_LM19) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_MTP_I219_V19) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LNL_I219_LM20) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LNL_I219_V20) },
{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_RPL_I219_LM22) },
{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_RPL_I219_V22) },
{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_RPL_I219_LM23) },
{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_RPL_I219_V23) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_ARL_I219_LM24) },
+ { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_ARL_I219_V24) },
{ .vendor_id = 0, /* sentinel */ },
};
@@ -501,6 +521,8 @@ em_set_pba(struct e1000_hw *hw)
case e1000_pch_cnp:
case e1000_pch_adp:
case e1000_pch_tgp:
+ case e1000_pch_mtp:
+ case e1000_pch_ptp:
pba = E1000_PBA_26K;
break;
default:
@@ -873,7 +895,9 @@ em_hardware_init(struct e1000_hw *hw)
hw->mac.type == e1000_pch_spt ||
hw->mac.type == e1000_pch_cnp ||
hw->mac.type == e1000_pch_adp ||
- hw->mac.type == e1000_pch_tgp) {
+ hw->mac.type == e1000_pch_tgp ||
+ hw->mac.type == e1000_pch_mtp ||
+ hw->mac.type == e1000_pch_ptp) {
hw->fc.requested_mode = e1000_fc_full;
}
@@ -1056,6 +1080,8 @@ em_get_max_pktlen(struct rte_eth_dev *dev)
case e1000_pch_cnp:
case e1000_pch_adp:
case e1000_pch_tgp:
+ case e1000_pch_mtp:
+ case e1000_pch_ptp:
case e1000_82574:
case e1000_80003es2lan: /* 9K Jumbo Frame size */
case e1000_82583: