From patchwork Thu Apr 15 19:10:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shijith Thotton X-Patchwork-Id: 91602 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C5D18A0C3F; Thu, 15 Apr 2021 21:10:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6A7FA162435; Thu, 15 Apr 2021 21:10:38 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id F073A162431 for ; Thu, 15 Apr 2021 21:10:36 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 13FItZbn021225 for ; Thu, 15 Apr 2021 12:10:36 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=LvdAaTyfbFMio2NZZzCYQPgCOCLwZYFyb/U+sJmGLVk=; b=PpNs3lUaLxvz2wglxqibAAjjFoq2fbheqhxW2+Etsj0BnHu9JCs7jio91pVl8CdoOhSd 1xQOkvk37QY1ZLnOJctiqTjMyk8qcuotma4dt0yaMA7LddG47Cd4P5X0htzBYRkgX1Kl o81HThPNLjWDlbUKGcyVOPZ5X1W+0rHGOA0iqMFSxdoduO5Oc/3mGj5sQRBd73kSIImv BxNckRB1i4Z8dci0eXb/Olrt8agFJOr1u++BubkTY7c/bi5YVyVUfUQ4x+5lr/qwvh/n 46eGKN8zw82pcsq3zU8819/yjQ11e6DzmlfGwhHmo1J6hV4VFk8DBHIGo8RTQlI9vHrn tA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 37wqtm71qq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 15 Apr 2021 12:10:36 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 15 Apr 2021 12:10:34 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 15 Apr 2021 12:10:34 -0700 Received: from localhost.localdomain (unknown [10.28.34.29]) by maili.marvell.com (Postfix) with ESMTP id 523953F7048; Thu, 15 Apr 2021 12:10:32 -0700 (PDT) From: Shijith Thotton To: CC: Shijith Thotton , Jerin Jacob , Akhil Goyal , Anoob Joseph , "Ankur Dwivedi" , Pavan Nikhilesh Date: Fri, 16 Apr 2021 00:40:15 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: R8uYX-_wqqL48kWhWRL1iAi2f13W2rtd X-Proofpoint-GUID: R8uYX-_wqqL48kWhWRL1iAi2f13W2rtd X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-15_09:2021-04-15, 2021-04-15 signatures=0 Subject: [dpdk-dev] [PATCH v1 2/2] event/octeontx2: configure crypto adapter xaq pool X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Configure xaq pool based on number of in-use crypto queues to avoid CPT add work failure due to xaq buffer run out. This patch configures OTX2_CPT_DEFAULT_CMD_QLEN number of xae entries per queue pair. Fixes: 29768f78d5a7 ("event/octeontx2: add crypto adapter framework") Signed-off-by: Shijith Thotton Acked-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_evdev_adptr.c | 2 +- drivers/event/octeontx2/otx2_evdev_crypto_adptr.c | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/event/octeontx2/otx2_evdev_adptr.c b/drivers/event/octeontx2/otx2_evdev_adptr.c index d69f269df..d85c3665c 100644 --- a/drivers/event/octeontx2/otx2_evdev_adptr.c +++ b/drivers/event/octeontx2/otx2_evdev_adptr.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(C) 2019 Marvell International Ltd. + * Copyright(C) 2019-2021 Marvell. */ #include "otx2_evdev.h" diff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c index 3a96b2e34..79a6d5577 100644 --- a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c +++ b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c @@ -88,6 +88,14 @@ otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev, sso_evdev->rx_offloads |= NIX_RX_OFFLOAD_SECURITY_F; sso_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)dev); + /* Update crypto adapter xae count */ + if (queue_pair_id == -1) + sso_evdev->adptr_xae_cnt = + vf->nb_queues * OTX2_CPT_DEFAULT_CMD_QLEN; + else + sso_evdev->adptr_xae_cnt += OTX2_CPT_DEFAULT_CMD_QLEN; + sso_xae_reconfigure((struct rte_eventdev *)(uintptr_t)dev); + return 0; }