From patchwork Tue Aug 1 16:54:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrien Mazarguil X-Patchwork-Id: 27329 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 652EFA0EE; Tue, 1 Aug 2017 18:55:37 +0200 (CEST) Received: from mail-wm0-f42.google.com (mail-wm0-f42.google.com [74.125.82.42]) by dpdk.org (Postfix) with ESMTP id 67CF9A0E0 for ; Tue, 1 Aug 2017 18:55:15 +0200 (CEST) Received: by mail-wm0-f42.google.com with SMTP id m85so20310869wma.1 for ; Tue, 01 Aug 2017 09:55:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:in-reply-to:references; bh=gP1TSQL83FJzRK9hKpVFa/dwqVYIKOfLvy1PFV98bd4=; b=GNUZIoCXStqM+D2MkYt4NZs7YcMIFQ9xolNsYAWlUWX10uev+Z2sPUVJAwuZ+7pNsC CxGIN286F/pkjk1kyCpUFwGTOm41oY8FbgTw8WKW4DgTxuOa7BYlqMYLCqcnPhSRwH3i wdSPG6kN3HqWLgW76wABBNwRcK5yae2Ar2na2XGJGKbPuqziBCK+QDyK6Ug3VSU9vedG 9xadVgmuu/68g5fS8gg+RAl9kk0WHwnm7HJg4HTTCcmp7u3HEmfqEWll0fVdA7xymxhs KS32lnJ4d2QUtAbqpo4rILARpQlTwoPGZf9lSSxoaovwUcPKL4A9ZRdGi1URSQmVaidS BX1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=gP1TSQL83FJzRK9hKpVFa/dwqVYIKOfLvy1PFV98bd4=; b=sNWBt7Q4XAQnTJ8WJRPae2raWct8psI9AoeD+jVnuHznnLLaLJ6PAeIgDupX60Mxj5 RAMpMiRaBaQX2RTV2Yzs8cPyS0mX12AxiHU9qAbkrzFOmOwR7VfXSJT/JUuZ+kYMqS65 xbdXgsqcnmDMMo96dmjXlaDCR/6nV/oURV+pzYsMeezwK5izeIXjifOq5HMyEo5QftKs +lTWW/zfp0d/IKxWIB1iHVNy/5iJP4whg/n1QpvQd1RyQqqxq+UU9/1e0UkRgod1rib9 BVHs6DEK7iRFzvTTc9PvtrkKY/oPoRmZCUCbd15sPSuXddwQ6O3g8ioe7Fdqk369RsyJ twrQ== X-Gm-Message-State: AIVw113JMSbSmTYY2oRaHNhFl8M7NoWnEOvHRrVe8d/j+eYxldlsq6a9 519nM37lGK2N+7KXdts= X-Received: by 10.28.154.85 with SMTP id c82mr1931117wme.151.1501606514637; Tue, 01 Aug 2017 09:55:14 -0700 (PDT) Received: from 6wind.com (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id p72sm16921711wmb.1.2017.08.01.09.55.13 for (version=TLS1_2 cipher=AES128-SHA bits=128/128); Tue, 01 Aug 2017 09:55:13 -0700 (PDT) From: Adrien Mazarguil To: dev@dpdk.org Date: Tue, 1 Aug 2017 18:54:04 +0200 Message-Id: X-Mailer: git-send-email 2.1.4 In-Reply-To: References: Subject: [dpdk-dev] [PATCH v1 17/48] net/mlx4: drop checksum offloads support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The Verbs API used to implement Tx and Rx checksum offloads is deprecated. Support for these will be added back after refactoring the PMD. Signed-off-by: Adrien Mazarguil --- doc/guides/nics/features/mlx4.ini | 4 -- doc/guides/nics/mlx4.rst | 2 - drivers/net/mlx4/mlx4.c | 91 ++-------------------------------- drivers/net/mlx4/mlx4.h | 4 -- 4 files changed, 4 insertions(+), 97 deletions(-) diff --git a/doc/guides/nics/features/mlx4.ini b/doc/guides/nics/features/mlx4.ini index aa1ad21..08a2e17 100644 --- a/doc/guides/nics/features/mlx4.ini +++ b/doc/guides/nics/features/mlx4.ini @@ -14,10 +14,6 @@ MTU update = Y Jumbo frame = Y Scattered Rx = Y SR-IOV = Y -L3 checksum offload = Y -L4 checksum offload = Y -Inner L3 checksum = Y -Inner L4 checksum = Y Packet type parsing = Y Basic stats = Y Stats per queue = Y diff --git a/doc/guides/nics/mlx4.rst b/doc/guides/nics/mlx4.rst index e906b8d..3f54343 100644 --- a/doc/guides/nics/mlx4.rst +++ b/doc/guides/nics/mlx4.rst @@ -80,8 +80,6 @@ Features - Multi arch support: x86_64 and POWER8. - Link state information is provided. - Scattered packets are supported for TX and RX. -- Inner L3/L4 (IP, TCP and UDP) TX/RX checksum offloading and validation. -- Outer L3 (IP) TX/RX checksum offloading and validation for VXLAN frames. - RX interrupts. Configuration diff --git a/drivers/net/mlx4/mlx4.c b/drivers/net/mlx4/mlx4.c index a1ff62a..36a616b 100644 --- a/drivers/net/mlx4/mlx4.c +++ b/drivers/net/mlx4/mlx4.c @@ -1258,17 +1258,6 @@ mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n) ++elts_comp; send_flags |= IBV_EXP_QP_BURST_SIGNALED; } - /* Should we enable HW CKSUM offload */ - if (buf->ol_flags & - (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) { - send_flags |= IBV_EXP_QP_BURST_IP_CSUM; - /* HW does not support checksum offloads at arbitrary - * offsets but automatically recognizes the packet - * type. For inner L3/L4 checksums, only VXLAN (UDP) - * tunnels are currently supported. */ - if (RTE_ETH_IS_TUNNEL_PKT(buf->packet_type)) - send_flags |= IBV_EXP_QP_BURST_TUNNEL; - } if (likely(segs == 1)) { uintptr_t addr; uint32_t length; @@ -2140,41 +2129,6 @@ rxq_cq_to_pkt_type(uint32_t flags) return pkt_type; } -/** - * Translate RX completion flags to offload flags. - * - * @param[in] rxq - * Pointer to RX queue structure. - * @param flags - * RX completion flags returned by poll_length_flags(). - * - * @return - * Offload flags (ol_flags) for struct rte_mbuf. - */ -static inline uint32_t -rxq_cq_to_ol_flags(const struct rxq *rxq, uint32_t flags) -{ - uint32_t ol_flags = 0; - - if (rxq->csum) - ol_flags |= - TRANSPOSE(flags, - IBV_EXP_CQ_RX_IP_CSUM_OK, - PKT_RX_IP_CKSUM_GOOD) | - TRANSPOSE(flags, - IBV_EXP_CQ_RX_TCP_UDP_CSUM_OK, - PKT_RX_L4_CKSUM_GOOD); - if ((flags & IBV_EXP_CQ_RX_TUNNEL_PACKET) && (rxq->csum_l2tun)) - ol_flags |= - TRANSPOSE(flags, - IBV_EXP_CQ_RX_OUTER_IP_CSUM_OK, - PKT_RX_IP_CKSUM_GOOD) | - TRANSPOSE(flags, - IBV_EXP_CQ_RX_OUTER_TCP_UDP_CSUM_OK, - PKT_RX_L4_CKSUM_GOOD); - return ol_flags; -} - static uint16_t mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n); @@ -2362,7 +2316,7 @@ mlx4_rx_burst_sp(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n) PORT(pkt_buf) = rxq->port_id; PKT_LEN(pkt_buf) = pkt_buf_len; pkt_buf->packet_type = rxq_cq_to_pkt_type(flags); - pkt_buf->ol_flags = rxq_cq_to_ol_flags(rxq, flags); + pkt_buf->ol_flags = 0; /* Return packet. */ *(pkts++) = pkt_buf; @@ -2517,7 +2471,7 @@ mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n) PKT_LEN(seg) = len; DATA_LEN(seg) = len; seg->packet_type = rxq_cq_to_pkt_type(flags); - seg->ol_flags = rxq_cq_to_ol_flags(rxq, flags); + seg->ol_flags = 0; /* Return packet. */ *(pkts++) = seg; @@ -2626,15 +2580,6 @@ rxq_rehash(struct rte_eth_dev *dev, struct rxq *rxq) /* Number of descriptors and mbufs currently allocated. */ desc_n = (tmpl.elts_n * (tmpl.sp ? MLX4_PMD_SGE_WR_N : 1)); mbuf_n = desc_n; - /* Toggle RX checksum offload if hardware supports it. */ - if (priv->hw_csum) { - tmpl.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum; - rxq->csum = tmpl.csum; - } - if (priv->hw_csum_l2tun) { - tmpl.csum_l2tun = !!dev->data->dev_conf.rxmode.hw_ip_checksum; - rxq->csum_l2tun = tmpl.csum_l2tun; - } /* Enable scattered packets support for this queue if necessary. */ assert(mb_len >= RTE_PKTMBUF_HEADROOM); if (dev->data->dev_conf.rxmode.enable_scatter && @@ -2808,11 +2753,6 @@ rxq_setup(struct rte_eth_dev *dev, struct rxq *rxq, uint16_t desc, " multiple of %d)", (void *)dev, MLX4_PMD_SGE_WR_N); return EINVAL; } - /* Toggle RX checksum offload if hardware supports it. */ - if (priv->hw_csum) - tmpl.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum; - if (priv->hw_csum_l2tun) - tmpl.csum_l2tun = !!dev->data->dev_conf.rxmode.hw_ip_checksum; /* Enable scattered packets support for this queue if necessary. */ assert(mb_len >= RTE_PKTMBUF_HEADROOM); if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= @@ -3416,18 +3356,8 @@ mlx4_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) info->max_tx_queues = max; /* Last array entry is reserved for broadcast. */ info->max_mac_addrs = 1; - info->rx_offload_capa = - (priv->hw_csum ? - (DEV_RX_OFFLOAD_IPV4_CKSUM | - DEV_RX_OFFLOAD_UDP_CKSUM | - DEV_RX_OFFLOAD_TCP_CKSUM) : - 0); - info->tx_offload_capa = - (priv->hw_csum ? - (DEV_TX_OFFLOAD_IPV4_CKSUM | - DEV_TX_OFFLOAD_UDP_CKSUM | - DEV_TX_OFFLOAD_TCP_CKSUM) : - 0); + info->rx_offload_capa = 0; + info->tx_offload_capa = 0; if (priv_get_ifname(priv, &ifname) == 0) info->if_index = if_nametoindex(ifname); info->speed_capa = @@ -4649,19 +4579,6 @@ mlx4_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) goto port_error; } - priv->hw_csum = - ((exp_device_attr.exp_device_cap_flags & - IBV_EXP_DEVICE_RX_CSUM_TCP_UDP_PKT) && - (exp_device_attr.exp_device_cap_flags & - IBV_EXP_DEVICE_RX_CSUM_IP_PKT)); - DEBUG("checksum offloading is %ssupported", - (priv->hw_csum ? "" : "not ")); - - priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags & - IBV_EXP_DEVICE_VXLAN_SUPPORT); - DEBUG("L2 tunnel checksum offloads are %ssupported", - (priv->hw_csum_l2tun ? "" : "not ")); - priv->inl_recv_size = mlx4_getenv_int("MLX4_INLINE_RECV_SIZE"); if (priv->inl_recv_size) { diff --git a/drivers/net/mlx4/mlx4.h b/drivers/net/mlx4/mlx4.h index fa703a2..5a0a7a1 100644 --- a/drivers/net/mlx4/mlx4.h +++ b/drivers/net/mlx4/mlx4.h @@ -173,8 +173,6 @@ struct rxq { struct rxq_elt (*no_sp)[]; /* RX elements. */ } elts; unsigned int sp:1; /* Use scattered RX elements. */ - unsigned int csum:1; /* Enable checksum offloading. */ - unsigned int csum_l2tun:1; /* Same for L2 tunnels. */ struct mlx4_rxq_stats stats; /* RX queue counters. */ unsigned int socket; /* CPU socket ID for allocations. */ struct ibv_exp_res_domain *rd; /* Resource Domain. */ @@ -242,8 +240,6 @@ struct priv { uint16_t mtu; /* Configured MTU. */ uint8_t port; /* Physical port number. */ unsigned int started:1; /* Device started, flows enabled. */ - unsigned int hw_csum:1; /* Checksum offload is supported. */ - unsigned int hw_csum_l2tun:1; /* Same for L2 tunnels. */ unsigned int vf:1; /* This is a VF device. */ unsigned int pending_alarm:1; /* An alarm is pending. */ unsigned int isolated:1; /* Toggle isolated mode. */