diff mbox series

[v3,17/36] net/e1000/base: correct disable k1 logic

Message ID e46b029a18b1e225386eee1295a33296e98d07e1.1738932115.git.anatoly.burakov@intel.com (mailing list archive)
State Accepted
Delegated to: Bruce Richardson
Headers
Series Merge Intel IGC and E1000 drivers, and update E1000 base code |

Checks

Context Check Description
ci/checkpatch warning coding style issues

Commit Message

Burakov, Anatoly Feb. 7, 2025, 12:45 p.m. UTC 
From: Vitaly Lifshits <vitaly.lifshits@intel.com>

Starting from MTP PHY type there is a synchronization issue between the
PHY's clock and PCH's synopsis PHY. This causes Tx packets corruptions.

The workaround to this issue is to change P0s power down state from
P0/P0s to P1 prior to disabling K1.

Signed-off-by: Vitaly Lifshits <vitaly.lifshits@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
 drivers/net/intel/e1000/base/e1000_ich8lan.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)
diff mbox series

Patch

diff --git a/drivers/net/intel/e1000/base/e1000_ich8lan.c b/drivers/net/intel/e1000/base/e1000_ich8lan.c
index 97e3144810..18e193861e 100644
--- a/drivers/net/intel/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/intel/e1000/base/e1000_ich8lan.c
@@ -2427,6 +2427,18 @@  s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
 
 	DEBUGFUNC("e1000_configure_k1_ich8lan");
 
+	/* Due to clock synchronization issue on MTL and above prior to
+	 * disabling k1 it is required to disable P0s state
+	 */
+	if ((!k1_enable) && (hw->mac.type >= e1000_pch_mtp)) {
+		u32 fextnvm12 = E1000_READ_REG(hw, E1000_FEXTNVM12);
+		fextnvm12 |= (1 << 23);
+		fextnvm12 &= ~((1 << 22));
+		E1000_WRITE_REG(hw, E1000_FEXTNVM12, fextnvm12);
+
+		usec_delay(100);
+	}
+
 	ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 					     &kmrn_reg);
 	if (ret_val)