From patchwork Mon Sep 2 09:54:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Burakov, Anatoly" X-Patchwork-Id: 143556 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4D536458CD; Mon, 2 Sep 2024 11:57:22 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B011E40A82; Mon, 2 Sep 2024 11:55:41 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by mails.dpdk.org (Postfix) with ESMTP id 9743640668 for ; Mon, 2 Sep 2024 11:55:19 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725270919; x=1756806919; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1WDzunNXPF+I2MrHm1FRrNkQgaZWSTy737Ruh/tCCG4=; b=fMev6HeM4ezdeVdBLYSyCNXV53s7Ki8qjcpRydytEJo1U9bUy/zB8jwo I/2PwbBX358hzyoW5I+dGM76Hg4BZr7ut+Tcl4vt43DLxmmF46PhZMVDk aXE2vdRo//HZIru2q/pD1e840Gu+RHU32kMJyu7pKW7elLbHeUgEy/Ag+ Pkh6/l72YM1gPH17uJh6Z7Rn3xc3Kiwy+FqpeYSZHcAbrak5lNfuYBkso WY2SlJND4GHTio+awwZeakyURx0fVNTjjkEJaYPAqb7Zxa8gCLxvwbcUr ycnaQab759yEGj3/97o4u97sB/xkzyHM/+vk0cm/5mewrTZKyQYOnXrPA Q==; X-CSE-ConnectionGUID: wjHSNGo9RjiWrLH2xMdi0w== X-CSE-MsgGUID: wXsKLIaMQrep4O7O86gJxw== X-IronPort-AV: E=McAfee;i="6700,10204,11182"; a="26747242" X-IronPort-AV: E=Sophos;i="6.10,195,1719903600"; d="scan'208";a="26747242" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Sep 2024 02:55:19 -0700 X-CSE-ConnectionGUID: r4xVOrHkRAy/3gYThW8F3Q== X-CSE-MsgGUID: HcgCqL0zTr2NKXowbh7YDw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,195,1719903600"; d="scan'208";a="64597961" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by fmviesa009.fm.intel.com with ESMTP; 02 Sep 2024 02:55:18 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: bruce.richardson@intel.com Subject: [PATCH v1 21/30] net/i40e/base: make register dump read-only Date: Mon, 2 Sep 2024 10:54:33 +0100 Message-ID: X-Mailer: git-send-email 2.43.5 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Radoslaw Tyl Currently, when registers are dumped, the data inside them is changed, so repeated dumps lead to unexpected results. Fix this by making register list read-only. Signed-off-by: Radoslaw Tyl Signed-off-by: Anatoly Burakov --- drivers/net/i40e/base/i40e_diag.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/i40e/base/i40e_diag.c b/drivers/net/i40e/base/i40e_diag.c index b3c4cfd3aa..4ca102cdd5 100644 --- a/drivers/net/i40e/base/i40e_diag.c +++ b/drivers/net/i40e/base/i40e_diag.c @@ -55,7 +55,7 @@ static enum i40e_status_code i40e_diag_reg_pattern_test(struct i40e_hw *hw, return I40E_SUCCESS; } -static struct i40e_diag_reg_test_info i40e_reg_list[] = { +static const struct i40e_diag_reg_test_info i40e_reg_list[] = { /* offset mask elements stride */ {I40E_QTX_CTL(0), 0x0000FFBF, 1, I40E_QTX_CTL(1) - I40E_QTX_CTL(0)}, {I40E_PFINT_ITR0(0), 0x00000FFF, 3, I40E_PFINT_ITR0(1) - I40E_PFINT_ITR0(0)}, @@ -81,28 +81,28 @@ enum i40e_status_code i40e_diag_reg_test(struct i40e_hw *hw) { enum i40e_status_code ret_code = I40E_SUCCESS; u32 reg, mask; + u32 elements; u32 i, j; for (i = 0; i40e_reg_list[i].offset != 0 && ret_code == I40E_SUCCESS; i++) { + elements = i40e_reg_list[i].elements; /* set actual reg range for dynamically allocated resources */ if (i40e_reg_list[i].offset == I40E_QTX_CTL(0) && hw->func_caps.num_tx_qp != 0) - i40e_reg_list[i].elements = hw->func_caps.num_tx_qp; + elements = hw->func_caps.num_tx_qp; if ((i40e_reg_list[i].offset == I40E_PFINT_ITRN(0, 0) || i40e_reg_list[i].offset == I40E_PFINT_ITRN(1, 0) || i40e_reg_list[i].offset == I40E_PFINT_ITRN(2, 0) || i40e_reg_list[i].offset == I40E_QINT_TQCTL(0) || i40e_reg_list[i].offset == I40E_QINT_RQCTL(0)) && hw->func_caps.num_msix_vectors != 0) - i40e_reg_list[i].elements = - hw->func_caps.num_msix_vectors - 1; + elements = hw->func_caps.num_msix_vectors - 1; /* test register access */ mask = i40e_reg_list[i].mask; - for (j = 0; j < i40e_reg_list[i].elements && - ret_code == I40E_SUCCESS; j++) { + for (j = 0; j < elements && ret_code == I40E_SUCCESS; j++) { reg = i40e_reg_list[i].offset + (j * i40e_reg_list[i].stride); ret_code = i40e_diag_reg_pattern_test(hw, reg, mask);