From patchwork Fri Sep 18 05:46:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Guo, Jia" X-Patchwork-Id: 78071 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 15225A04C7; Fri, 18 Sep 2020 07:49:56 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5AABA1D8D4; Fri, 18 Sep 2020 07:49:55 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id BC5F41D8D3 for ; Fri, 18 Sep 2020 07:49:53 +0200 (CEST) IronPort-SDR: F6BFS+Z5Kq4IU4e2hL0Lv+WYJCGV+NKLm0ghfgkObH9iFlSsAsQS+LpiAmHH6iRoHiuLYPlNSf rgyHHtuny24A== X-IronPort-AV: E=McAfee;i="6000,8403,9747"; a="159919301" X-IronPort-AV: E=Sophos;i="5.77,273,1596524400"; d="scan'208";a="159919301" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2020 22:49:50 -0700 IronPort-SDR: 4y/fEL5lYkMNqvPPLIZsvftEfUavXIss1259uz/E9mxn5mCXlT34B9Okhqyq3PfMhXSuCKXvx7 xrpHfXEqEeeg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,273,1596524400"; d="scan'208";a="484057718" Received: from npg-dpdk-cvl-jeffguo-01.sh.intel.com ([10.67.111.128]) by orsmga005.jf.intel.com with ESMTP; 17 Sep 2020 22:49:48 -0700 From: Jeff Guo To: jingjing.wu@intel.com, qi.z.zhang@intel.com, beilei.xing@intel.com Cc: dev@dpdk.org, jia.guo@intel.com Date: Fri, 18 Sep 2020 13:46:56 +0800 Message-Id: <20200918054656.94560-1-jia.guo@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200909082031.28299-1-jia.guo@intel.com> References: <20200909082031.28299-1-jia.guo@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4] net/iavf: support gtpu outer and inner co-exist X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Although currently only the gtpu inner hash be enabled while not the gtpu outer hash, but the outer protocol still needed to co-exist with inner protocol when configure the gtpu inner hash rule, that would allow the gtpu innner hash support for the different outer protocols. Signed-off-by: Jeff Guo Acked-by: Qi Zhang --- v4->v3: refine the header set --- drivers/net/iavf/iavf_hash.c | 53 ++++++++++++++++++++++++++---------- 1 file changed, 39 insertions(+), 14 deletions(-) diff --git a/drivers/net/iavf/iavf_hash.c b/drivers/net/iavf/iavf_hash.c index 3152218dc..34c425cdb 100644 --- a/drivers/net/iavf/iavf_hash.c +++ b/drivers/net/iavf/iavf_hash.c @@ -28,12 +28,17 @@ #define IAVF_PHINT_GTPU_EH BIT_ULL(1) #define IAVF_PHINT_GTPU_EH_DWN BIT_ULL(2) #define IAVF_PHINT_GTPU_EH_UP BIT_ULL(3) +#define IAVF_PHINT_OUTER_IPV4 BIT_ULL(4) +#define IAVF_PHINT_OUTER_IPV6 BIT_ULL(5) #define IAVF_PHINT_GTPU_MSK (IAVF_PHINT_GTPU | \ IAVF_PHINT_GTPU_EH | \ IAVF_PHINT_GTPU_EH_DWN | \ IAVF_PHINT_GTPU_EH_UP) +#define IAVF_PHINT_LAYERS_MSK (IAVF_PHINT_OUTER_IPV4 | \ + IAVF_PHINT_OUTER_IPV6) + #define IAVF_GTPU_EH_DWNLINK 0 #define IAVF_GTPU_EH_UPLINK 1 @@ -499,8 +504,7 @@ iavf_hash_init(struct iavf_adapter *ad) } static int -iavf_hash_parse_pattern(struct iavf_pattern_match_item *pattern_match_item, - const struct rte_flow_item pattern[], uint64_t *phint, +iavf_hash_parse_pattern(const struct rte_flow_item pattern[], uint64_t *phint, struct rte_flow_error *error) { const struct rte_flow_item *item = pattern; @@ -515,6 +519,14 @@ iavf_hash_parse_pattern(struct iavf_pattern_match_item *pattern_match_item, } switch (item->type) { + case RTE_FLOW_ITEM_TYPE_IPV4: + if (!(*phint & IAVF_PHINT_GTPU_MSK)) + *phint |= IAVF_PHINT_OUTER_IPV4; + break; + case RTE_FLOW_ITEM_TYPE_IPV6: + if (!(*phint & IAVF_PHINT_GTPU_MSK)) + *phint |= IAVF_PHINT_OUTER_IPV6; + break; case RTE_FLOW_ITEM_TYPE_GTPU: *phint |= IAVF_PHINT_GTPU; break; @@ -533,9 +545,6 @@ iavf_hash_parse_pattern(struct iavf_pattern_match_item *pattern_match_item, } } - /* update and restore pattern hint */ - *phint |= *(uint64_t *)(pattern_match_item->meta); - return 0; } @@ -714,22 +723,39 @@ iavf_refine_proto_hdrs_by_pattern(struct virtchnl_proto_hdrs *proto_hdrs, { struct virtchnl_proto_hdr *hdr1; struct virtchnl_proto_hdr *hdr2; - int i; + int i, shift_count = 1; if (!(phint & IAVF_PHINT_GTPU_MSK)) return; + if (phint & IAVF_PHINT_LAYERS_MSK) + shift_count++; + if (proto_hdrs->tunnel_level == TUNNEL_LEVEL_INNER) { - /* shift headers 1 layer */ - for (i = proto_hdrs->count; i > 0; i--) { + /* shift headers layer */ + for (i = proto_hdrs->count - 1 + shift_count; + i > shift_count - 1; i--) { hdr1 = &proto_hdrs->proto_hdr[i]; - hdr2 = &proto_hdrs->proto_hdr[i - 1]; - + hdr2 = &proto_hdrs->proto_hdr[i - shift_count]; *hdr1 = *hdr2; } - /* adding gtpu header at layer 0 */ - hdr1 = &proto_hdrs->proto_hdr[0]; + if (shift_count == 1) { + /* adding gtpu header at layer 0 */ + hdr1 = &proto_hdrs->proto_hdr[0]; + } else { + /* adding gtpu header and outer ip header */ + hdr1 = &proto_hdrs->proto_hdr[1]; + hdr2 = &proto_hdrs->proto_hdr[0]; + hdr2->field_selector = 0; + proto_hdrs->count++; + proto_hdrs->tunnel_level = TUNNEL_LEVEL_OUTER; + + if (phint & IAVF_PHINT_OUTER_IPV4) + VIRTCHNL_SET_PROTO_HDR_TYPE(hdr2, IPV4); + else if (phint & IAVF_PHINT_OUTER_IPV6) + VIRTCHNL_SET_PROTO_HDR_TYPE(hdr2, IPV6); + } } else { hdr1 = &proto_hdrs->proto_hdr[proto_hdrs->count]; } @@ -908,8 +934,7 @@ iavf_hash_parse_pattern_action(__rte_unused struct iavf_adapter *ad, goto error; } - ret = iavf_hash_parse_pattern(pattern_match_item, pattern, &phint, - error); + ret = iavf_hash_parse_pattern(pattern, &phint, error); if (ret) goto error;