From patchwork Fri Sep 25 11:55:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manish Chopra X-Patchwork-Id: 78834 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3A7F9A04C0; Fri, 25 Sep 2020 13:56:06 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 090F41E926; Fri, 25 Sep 2020 13:56:06 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 2E2FD1E916 for ; Fri, 25 Sep 2020 13:56:04 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 08PBtxtJ003666; Fri, 25 Sep 2020 04:56:03 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=RLiLPq54umMoh/kAnAAd4qctrtEPYc2NZ8ls+/dKez4=; b=ZupdlBxcDCeKYLL/C5YiLbnMaXTP6pd0SR7XGpi8uHd7/YQ3b45K5l8oxzqdr8LTFPru AQaA3yg/Vdk3yGRId6/sC2cH2/MM34CqGWLbGnlg+mBrZnZg4ibkzlyMzUO2tl5b6POE QX2Xo9gzFlGkr2J8gl4kiEhdFi7fJYGIbg4J9PG3otHwWJ5ZADWsL7yb/LLENGYFU0xH mjAjODnYIWgDFNlHBCgwYoRWSWN95DTYIkcSR6HcYbDWb8zTJWirDrcJaOHAh29Nvc4l A4tvNeYi3oHOPJgWBbXZATgpfzdTCFekNc4g1AaIy/FKwxIpcWrAp5cNHi116r8mkQ/5 5A== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 33nfbqb0ed-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 25 Sep 2020 04:56:03 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 25 Sep 2020 04:55:59 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 25 Sep 2020 04:56:00 -0700 Received: from dut1171.mv.qlogic.com (unknown [10.112.88.18]) by maili.marvell.com (Postfix) with ESMTP id DC9663F703F; Fri, 25 Sep 2020 04:55:59 -0700 (PDT) Received: from dut1171.mv.qlogic.com (localhost [127.0.0.1]) by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 08PBtxuZ004228; Fri, 25 Sep 2020 04:55:59 -0700 Received: (from root@localhost) by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 08PBtxJq004227; Fri, 25 Sep 2020 04:55:59 -0700 From: Manish Chopra To: , , , CC: , , , , , , , , Date: Fri, 25 Sep 2020 04:55:03 -0700 Message-ID: <20200925115508.4179-2-manishc@marvell.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20200925115508.4179-1-manishc@marvell.com> References: <20200925115508.4179-1-manishc@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-09-25_08:2020-09-24, 2020-09-25 signatures=0 Subject: [dpdk-dev] [PATCH v6 1/6] drivers: add generic API to find PCI extended cap X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" By adding generic API, this patch removes individual functions/defines implemented by drivers to find extended PCI capabilities. Signed-off-by: Manish Chopra Signed-off-by: Igor Russkikh Reviewed-by: Gaetan Rivet Reviewed-by: Jerin Jacob --- drivers/bus/pci/pci_common.c | 43 ++++++++++++++++++ drivers/bus/pci/rte_bus_pci.h | 19 ++++++++ drivers/bus/pci/rte_bus_pci_version.map | 6 +++ drivers/net/ice/ice_ethdev.c | 51 +--------------------- drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c | 48 +------------------- drivers/raw/ifpga/ifpga_rawdev.c | 17 +++----- lib/librte_pci/rte_pci.h | 16 +++++++ 7 files changed, 94 insertions(+), 106 deletions(-) diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c index a8e5fd52c..b686aad6a 100644 --- a/drivers/bus/pci/pci_common.c +++ b/drivers/bus/pci/pci_common.c @@ -665,6 +665,49 @@ rte_pci_get_iommu_class(void) return iova_mode; } +off_t +rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap) +{ + off_t offset = RTE_PCI_CFG_SPACE_SIZE; + uint32_t header; + int ttl; + + /* minimum 8 bytes per capability */ + ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8; + + if (rte_pci_read_config(dev, &header, 4, offset) < 0) { + RTE_LOG(ERR, EAL, "error in reading extended capabilities\n"); + return -1; + } + + /* + * If we have no capabilities, this is indicated by cap ID, + * cap version and next pointer all being 0. + */ + if (header == 0) + return 0; + + while (ttl != 0) { + if (RTE_PCI_EXT_CAP_ID(header) == cap) + return offset; + + offset = RTE_PCI_EXT_CAP_NEXT(header); + + if (offset < RTE_PCI_CFG_SPACE_SIZE) + break; + + if (rte_pci_read_config(dev, &header, 4, offset) < 0) { + RTE_LOG(ERR, EAL, + "error in reading extended capabilities\n"); + return -1; + } + + ttl--; + } + + return 0; +} + struct rte_pci_bus rte_pci_bus = { .bus = { .scan = rte_pci_scan, diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h index 29bea6d70..5bb1854d6 100644 --- a/drivers/bus/pci/rte_bus_pci.h +++ b/drivers/bus/pci/rte_bus_pci.h @@ -224,6 +224,25 @@ void rte_pci_unmap_device(struct rte_pci_device *dev); */ void rte_pci_dump(FILE *f); +/** + * Find device's extended PCI capability. + * + * @param dev + * A pointer to rte_pci_device structure. + * + * @param cap + * Extended capability to be found, which can be any from + * RTE_PCI_EXT_CAP_ID_*, defined in librte_pci. + * + * @return + * > 0: The offset of the next matching extended capability structure + * within the device's PCI configuration space. + * < 0: An error in PCI config space read. + * = 0: Device does not support it. + */ +__rte_experimental +off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap); + /** * Register a PCI driver. * diff --git a/drivers/bus/pci/rte_bus_pci_version.map b/drivers/bus/pci/rte_bus_pci_version.map index 5b75d2367..f33ed0abd 100644 --- a/drivers/bus/pci/rte_bus_pci_version.map +++ b/drivers/bus/pci/rte_bus_pci_version.map @@ -16,3 +16,9 @@ DPDK_21 { local: *; }; + +EXPERIMENTAL { + global: + + rte_pci_find_ext_capability; +}; diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index cfd357b05..6513cc36b 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -1753,53 +1753,6 @@ ice_pf_setup(struct ice_pf *pf) return 0; } -/* PCIe configuration space setting */ -#define PCI_CFG_SPACE_SIZE 256 -#define PCI_CFG_SPACE_EXP_SIZE 4096 -#define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff) -#define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc) -#define PCI_EXT_CAP_ID_DSN 0x03 - -static int -ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap) -{ - uint32_t header; - int ttl; - int pos = PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - - if (rte_pci_read_config(dev, &header, 4, pos) < 0) { - PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n"); - return -1; - } - - /* - * If we have no capabilities, this is indicated by cap ID, - * cap version and next pointer all being 0. - */ - if (header == 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) == cap) - return pos; - - pos = PCI_EXT_CAP_NEXT(header); - - if (pos < PCI_CFG_SPACE_SIZE) - break; - - if (rte_pci_read_config(dev, &header, 4, pos) < 0) { - PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n"); - return -1; - } - } - - return 0; -} - /* * Extract device serial number from PCIe Configuration Space and * determine the pkg file path according to the DSN. @@ -1807,12 +1760,12 @@ ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap) static int ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file) { - int pos; + off_t pos; char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE]; uint32_t dsn_low, dsn_high; memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE); - pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN); + pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN); if (pos) { rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4); diff --git a/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c b/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c index 0b9db974e..36725d69a 100644 --- a/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c +++ b/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c @@ -746,59 +746,15 @@ nfp6000_set_interface(struct rte_pci_device *dev, struct nfp_cpp *cpp) return 0; } -#define PCI_CFG_SPACE_SIZE 256 -#define PCI_CFG_SPACE_EXP_SIZE 4096 -#define PCI_EXT_CAP_ID(header) (int)(header & 0x0000ffff) -#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) -#define PCI_EXT_CAP_ID_DSN 0x03 -static int -nfp_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap) -{ - uint32_t header; - int ttl; - int pos = PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - - if (rte_pci_read_config(dev, &header, 4, pos) < 0) { - printf("nfp error reading extended capabilities\n"); - return -1; - } - - /* - * If we have no capabilities, this is indicated by cap ID, - * cap version and next pointer all being 0. - */ - if (header == 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) == cap) - return pos; - - pos = PCI_EXT_CAP_NEXT(header); - if (pos < PCI_CFG_SPACE_SIZE) - break; - - if (rte_pci_read_config(dev, &header, 4, pos) < 0) { - printf("nfp error reading extended capabilities\n"); - return -1; - } - } - - return 0; -} - static int nfp6000_set_serial(struct rte_pci_device *dev, struct nfp_cpp *cpp) { uint16_t tmp; uint8_t serial[6]; int serial_len = 6; - int pos; + off_t pos; - pos = nfp_pci_find_next_ext_capability(dev, PCI_EXT_CAP_ID_DSN); + pos = rte_pci_find_ext_capability(dev, RTE_PCI_EXT_CAP_ID_DSN); if (pos <= 0) { printf("PCI_EXT_CAP_ID_DSN not found. nfp set serial failed\n"); return -1; diff --git a/drivers/raw/ifpga/ifpga_rawdev.c b/drivers/raw/ifpga/ifpga_rawdev.c index a50173264..a7463de8e 100644 --- a/drivers/raw/ifpga/ifpga_rawdev.c +++ b/drivers/raw/ifpga/ifpga_rawdev.c @@ -41,12 +41,6 @@ #include "ifpga_rawdev.h" #include "ipn3ke_rawdev_api.h" -#define RTE_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ -#define RTE_PCI_CFG_SPACE_SIZE 256 -#define RTE_PCI_CFG_SPACE_EXP_SIZE 4096 -#define RTE_PCI_EXT_CAP_ID(header) (int)(header & 0x0000ffff) -#define RTE_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) - #define PCI_VENDOR_ID_INTEL 0x8086 /* PCI Device ID */ #define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD @@ -86,8 +80,8 @@ ifpga_rawdev_allocate(struct rte_rawdev *rawdev); static int set_surprise_link_check_aer( struct ifpga_rawdev *ifpga_rdev, int force_disable); static int ifpga_pci_find_next_ext_capability(unsigned int fd, - int start, int cap); -static int ifpga_pci_find_ext_capability(unsigned int fd, int cap); + int start, uint32_t cap); +static int ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap); struct ifpga_rawdev * ifpga_rawdev_get(const struct rte_rawdev *rawdev) @@ -144,8 +138,8 @@ ifpga_rawdev_allocate(struct rte_rawdev *rawdev) return dev; } -static int ifpga_pci_find_next_ext_capability(unsigned int fd, -int start, int cap) +static int +ifpga_pci_find_next_ext_capability(unsigned int fd, int start, uint32_t cap) { uint32_t header; int ttl; @@ -183,7 +177,8 @@ int start, int cap) return 0; } -static int ifpga_pci_find_ext_capability(unsigned int fd, int cap) +static int +ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap) { return ifpga_pci_find_next_ext_capability(fd, 0, cap); } diff --git a/lib/librte_pci/rte_pci.h b/lib/librte_pci/rte_pci.h index a03235da1..fec51e15a 100644 --- a/lib/librte_pci/rte_pci.h +++ b/lib/librte_pci/rte_pci.h @@ -22,6 +22,22 @@ extern "C" { #include #include + +/* + * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of + * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of + * configuration space. + */ +#define RTE_PCI_CFG_SPACE_SIZE 256 +#define RTE_PCI_CFG_SPACE_EXP_SIZE 4096 + +/* Extended Capabilities (PCI-X 2.0 and Express) */ +#define RTE_PCI_EXT_CAP_ID(header) (header & 0x0000ffff) +#define RTE_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) + +#define RTE_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ +#define RTE_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ + /** Formatting string for PCI device identifier: Ex: 0000:00:01.0 */ #define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8 #define PCI_PRI_STR_SIZE sizeof("XXXXXXXX:XX:XX.X") From patchwork Fri Sep 25 11:55:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manish Chopra X-Patchwork-Id: 78835 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4DC86A04C0; Fri, 25 Sep 2020 13:56:29 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2CF101E910; Fri, 25 Sep 2020 13:56:29 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 549D51E90C for ; Fri, 25 Sep 2020 13:56:27 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 08PBuDK2003749; Fri, 25 Sep 2020 04:56:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=lEqWN9szu3TrLoq2AMvcw52Hif6qy623ZHW97Fzf48Q=; b=RGAqCBvwcrUBbtRdetlMc9gDJmKpouwaCjpVieOydLDRej3pW/IdD0ZUkmw1rc9p/4jX LLllMcNNw3vO0bxLI/q+nPewLcPSonwcNlUSKsEqJMWYFN1AZGhJ+ruCYJN0AoKSK71g 2Qd9vEBwmymUpLF25bOx+jDgcsBOYv3cZaRp9ha/W2m57pbf7h11DsCqMltxPAEXr17B UnFMFfx4c0KfRx1Hcz3MKpwYth/m6Fu3QnYUEFMsQGWzJVd4Tqjwqy+1AKJKXYDxsWh6 B8M9GNGldSZNDPS/SDlid3LJB2hO+CRGwZw+x7UmNEJyEc04xh9vNcgRxtkHs+1l00/d hw== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0a-0016f401.pphosted.com with ESMTP id 33nfbqb0fk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 25 Sep 2020 04:56:26 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 25 Sep 2020 04:56:25 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 25 Sep 2020 04:56:24 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 25 Sep 2020 04:56:24 -0700 Received: from dut1171.mv.qlogic.com (unknown [10.112.88.18]) by maili.marvell.com (Postfix) with ESMTP id 266D83F703F; Fri, 25 Sep 2020 04:56:24 -0700 (PDT) Received: from dut1171.mv.qlogic.com (localhost [127.0.0.1]) by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 08PBuNQb004240; Fri, 25 Sep 2020 04:56:23 -0700 Received: (from root@localhost) by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 08PBuNLe004231; Fri, 25 Sep 2020 04:56:23 -0700 From: Manish Chopra To: , , , CC: , , , , , , , , Date: Fri, 25 Sep 2020 04:55:04 -0700 Message-ID: <20200925115508.4179-3-manishc@marvell.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20200925115508.4179-1-manishc@marvell.com> References: <20200925115508.4179-1-manishc@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-09-25_08:2020-09-24, 2020-09-25 signatures=0 Subject: [dpdk-dev] [PATCH v6 2/6] net/qede: define PCI config space specific osals X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch defines various PCI config space access APIs in order to read and find IOV specific PCI capabilities. With these definitions implemented, it enables the base driver to do SR-IOV specific initialization and HW specific configuration required from PF-PMD driver instance. Signed-off-by: Manish Chopra Signed-off-by: Igor Russkikh Signed-off-by: Rasesh Mody --- drivers/net/qede/base/bcm_osal.h | 14 +++++++++----- drivers/net/qede/base/ecore.h | 3 +++ drivers/net/qede/base/ecore_dev.c | 6 +++--- drivers/net/qede/base/ecore_sriov.c | 28 +++++++++++++++------------- drivers/net/qede/base/meson.build | 2 +- drivers/net/qede/qede_main.c | 1 + lib/librte_pci/rte_pci.h | 23 +++++++++++++++++++++-- 7 files changed, 53 insertions(+), 24 deletions(-) diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h index ded4fb0f5..681d2d5b6 100644 --- a/drivers/net/qede/base/bcm_osal.h +++ b/drivers/net/qede/base/bcm_osal.h @@ -21,6 +21,7 @@ #include #include #include +#include /* Forward declaration */ struct ecore_dev; @@ -285,11 +286,14 @@ typedef struct osal_list_t { OSAL_LIST_PUSH_HEAD(new_entry, list) /* PCI config space */ - -#define OSAL_PCI_READ_CONFIG_BYTE(dev, address, dst) nothing -#define OSAL_PCI_READ_CONFIG_WORD(dev, address, dst) nothing -#define OSAL_PCI_READ_CONFIG_DWORD(dev, address, dst) nothing -#define OSAL_PCI_FIND_EXT_CAPABILITY(dev, pcie_id) 0 +#define OSAL_PCI_READ_CONFIG_BYTE(dev, address, dst) \ + rte_pci_read_config((dev)->pci_dev, dst, 1, address) +#define OSAL_PCI_READ_CONFIG_WORD(dev, address, dst) \ + rte_pci_read_config((dev)->pci_dev, dst, 2, address) +#define OSAL_PCI_READ_CONFIG_DWORD(dev, address, dst) \ + rte_pci_read_config((dev)->pci_dev, dst, 4, address) +#define OSAL_PCI_FIND_EXT_CAPABILITY(dev, cap) \ + rte_pci_find_ext_capability((dev)->pci_dev, cap) #define OSAL_PCI_FIND_CAPABILITY(dev, pcie_id) 0 #define OSAL_PCI_WRITE_CONFIG_WORD(dev, address, val) nothing #define OSAL_BAR_SIZE(dev, bar_id) 0 diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h index 63bd7466a..750e99a8f 100644 --- a/drivers/net/qede/base/ecore.h +++ b/drivers/net/qede/base/ecore.h @@ -937,6 +937,9 @@ struct ecore_dev { struct ecore_dbg_feature dbg_features[DBG_FEATURE_NUM]; struct ecore_dbg_params dbg_params; osal_mutex_t dbg_lock; + + /* DPDK specific ecore field */ + struct rte_pci_device *pci_dev; }; enum ecore_hsi_def_type { diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c index 35a8394de..e895dee40 100644 --- a/drivers/net/qede/base/ecore_dev.c +++ b/drivers/net/qede/base/ecore_dev.c @@ -2787,7 +2787,7 @@ static enum _ecore_status_t ecore_hw_init_chip(struct ecore_dev *p_dev, return ECORE_IO; } - OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + PCI_EXP_DEVCTL, &ctrl); + OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_EXP_DEVCTL, &ctrl); wr_mbs = (ctrl & PCI_EXP_DEVCTL_PAYLOAD) >> 5; ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0, wr_mbs); @@ -5499,9 +5499,9 @@ static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn, u32 tmp; /* Read Vendor Id / Device Id */ - OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET, + OSAL_PCI_READ_CONFIG_WORD(p_dev, RTE_PCI_VENDOR_ID, &p_dev->vendor_id); - OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET, + OSAL_PCI_READ_CONFIG_WORD(p_dev, RTE_PCI_DEVICE_ID, &p_dev->device_id); /* Determine type */ diff --git a/drivers/net/qede/base/ecore_sriov.c b/drivers/net/qede/base/ecore_sriov.c index e60257e19..dac4cbee8 100644 --- a/drivers/net/qede/base/ecore_sriov.c +++ b/drivers/net/qede/base/ecore_sriov.c @@ -417,15 +417,16 @@ static enum _ecore_status_t ecore_iov_pci_cfg_info(struct ecore_dev *p_dev) int pos = iov->pos; DP_VERBOSE(p_dev, ECORE_MSG_IOV, "sriov ext pos %d\n", pos); - OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + PCI_SRIOV_CTRL, &iov->ctrl); + OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_SRIOV_CTRL, &iov->ctrl); + OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_SRIOV_TOTAL_VF, + &iov->total_vfs); OSAL_PCI_READ_CONFIG_WORD(p_dev, - pos + PCI_SRIOV_TOTAL_VF, &iov->total_vfs); - OSAL_PCI_READ_CONFIG_WORD(p_dev, - pos + PCI_SRIOV_INITIAL_VF, + pos + RTE_PCI_SRIOV_INITIAL_VF, &iov->initial_vfs); - OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + PCI_SRIOV_NUM_VF, &iov->num_vfs); + OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_SRIOV_NUM_VF, + &iov->num_vfs); if (iov->num_vfs) { /* @@@TODO - in future we might want to add an OSAL here to * allow each OS to decide on its own how to act. @@ -437,20 +438,21 @@ static enum _ecore_status_t ecore_iov_pci_cfg_info(struct ecore_dev *p_dev) } OSAL_PCI_READ_CONFIG_WORD(p_dev, - pos + PCI_SRIOV_VF_OFFSET, &iov->offset); + pos + RTE_PCI_SRIOV_VF_OFFSET, &iov->offset); OSAL_PCI_READ_CONFIG_WORD(p_dev, - pos + PCI_SRIOV_VF_STRIDE, &iov->stride); + pos + RTE_PCI_SRIOV_VF_STRIDE, &iov->stride); - OSAL_PCI_READ_CONFIG_WORD(p_dev, - pos + PCI_SRIOV_VF_DID, &iov->vf_device_id); + OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_SRIOV_VF_DID, + &iov->vf_device_id); OSAL_PCI_READ_CONFIG_DWORD(p_dev, - pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz); + pos + RTE_PCI_SRIOV_SUP_PGSIZE, &iov->pgsz); - OSAL_PCI_READ_CONFIG_DWORD(p_dev, pos + PCI_SRIOV_CAP, &iov->cap); + OSAL_PCI_READ_CONFIG_DWORD(p_dev, pos + RTE_PCI_SRIOV_CAP, &iov->cap); - OSAL_PCI_READ_CONFIG_BYTE(p_dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link); + OSAL_PCI_READ_CONFIG_BYTE(p_dev, pos + RTE_PCI_SRIOV_FUNC_LINK, + &iov->link); DP_VERBOSE(p_dev, ECORE_MSG_IOV, "IOV info: nres %d, cap 0x%x," "ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d," @@ -669,7 +671,7 @@ enum _ecore_status_t ecore_iov_hw_info(struct ecore_hwfn *p_hwfn) /* Learn the PCI configuration */ pos = OSAL_PCI_FIND_EXT_CAPABILITY(p_hwfn->p_dev, - PCI_EXT_CAP_ID_SRIOV); + RTE_PCI_EXT_CAP_ID_SRIOV); if (!pos) { DP_VERBOSE(p_hwfn, ECORE_MSG_IOV, "No PCIe IOV support\n"); return ECORE_SUCCESS; diff --git a/drivers/net/qede/base/meson.build b/drivers/net/qede/base/meson.build index 59b41c895..03a6c44f5 100644 --- a/drivers/net/qede/base/meson.build +++ b/drivers/net/qede/base/meson.build @@ -52,6 +52,6 @@ foreach flag: error_cflags endforeach base_lib = static_library('qede_base', sources, - dependencies: static_rte_net, + dependencies: [static_rte_net, static_rte_bus_pci], c_args: c_args) base_objs = base_lib.extract_all_objects() diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c index aecb98261..94061ec11 100644 --- a/drivers/net/qede/qede_main.c +++ b/drivers/net/qede/qede_main.c @@ -37,6 +37,7 @@ static void qed_init_pci(struct ecore_dev *edev, struct rte_pci_device *pci_dev) edev->regview = pci_dev->mem_resource[0].addr; edev->doorbells = pci_dev->mem_resource[2].addr; edev->db_size = pci_dev->mem_resource[2].len; + edev->pci_dev = pci_dev; } static int diff --git a/lib/librte_pci/rte_pci.h b/lib/librte_pci/rte_pci.h index fec51e15a..a018a6e9a 100644 --- a/lib/librte_pci/rte_pci.h +++ b/lib/librte_pci/rte_pci.h @@ -31,12 +31,31 @@ extern "C" { #define RTE_PCI_CFG_SPACE_SIZE 256 #define RTE_PCI_CFG_SPACE_EXP_SIZE 4096 +#define RTE_PCI_VENDOR_ID 0x00 /* 16 bits */ +#define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */ + +/* PCI Express capability registers */ +#define RTE_PCI_EXP_DEVCTL 8 /* Device Control */ + /* Extended Capabilities (PCI-X 2.0 and Express) */ #define RTE_PCI_EXT_CAP_ID(header) (header & 0x0000ffff) #define RTE_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) -#define RTE_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ -#define RTE_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ +#define RTE_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ +#define RTE_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ +#define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV*/ + +/* Single Root I/O Virtualization */ +#define RTE_PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ +#define RTE_PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ +#define RTE_PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ +#define RTE_PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ +#define RTE_PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ +#define RTE_PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */ +#define RTE_PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ +#define RTE_PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ +#define RTE_PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ +#define RTE_PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */ /** Formatting string for PCI device identifier: Ex: 0000:00:01.0 */ #define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8 From patchwork Fri Sep 25 11:55:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manish Chopra X-Patchwork-Id: 78836 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id F29DBA04C0; Fri, 25 Sep 2020 13:56:51 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DB0E51C244; Fri, 25 Sep 2020 13:56:51 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id CCB281C243 for ; Fri, 25 Sep 2020 13:56:50 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 08PBtIna010841; Fri, 25 Sep 2020 04:56:50 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; 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Fri, 25 Sep 2020 04:56:48 -0700 (PDT) Received: from dut1171.mv.qlogic.com (localhost [127.0.0.1]) by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 08PBum4D004244; Fri, 25 Sep 2020 04:56:48 -0700 Received: (from root@localhost) by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 08PBumAm004243; Fri, 25 Sep 2020 04:56:48 -0700 From: Manish Chopra To: , , , CC: , , , , , , , , Date: Fri, 25 Sep 2020 04:55:05 -0700 Message-ID: <20200925115508.4179-4-manishc@marvell.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20200925115508.4179-1-manishc@marvell.com> References: <20200925115508.4179-1-manishc@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-09-25_08:2020-09-24, 2020-09-25 signatures=0 Subject: [dpdk-dev] [PATCH v6 3/6] net/qede: configure VFs on hardware X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Based on number of VFs enabled at PCI, PF-PMD driver instance enables/configures those VFs from hardware perspective, such that in later patches they could get required HW access to communicate with PFs for slowpath configuration and run the fastpath themsleves. This patch also add two new qede IOV files [qede_sriov(.c|.h)] under qede directory to add non-base driver IOV APIs/contents there. Signed-off-by: Manish Chopra Signed-off-by: Igor Russkikh Signed-off-by: Rasesh Mody --- drivers/net/qede/meson.build | 1 + drivers/net/qede/qede_ethdev.c | 1 + drivers/net/qede/qede_ethdev.h | 1 + drivers/net/qede/qede_if.h | 1 + drivers/net/qede/qede_main.c | 1 + drivers/net/qede/qede_sriov.c | 85 ++++++++++++++++++++++++++++++++++ drivers/net/qede/qede_sriov.h | 9 ++++ 7 files changed, 99 insertions(+) create mode 100644 drivers/net/qede/qede_sriov.c create mode 100644 drivers/net/qede/qede_sriov.h diff --git a/drivers/net/qede/meson.build b/drivers/net/qede/meson.build index 05c9bff73..ff0ac0b03 100644 --- a/drivers/net/qede/meson.build +++ b/drivers/net/qede/meson.build @@ -11,6 +11,7 @@ sources = files( 'qede_rxtx.c', 'qede_debug.c', 'qede_regs.c', + 'qede_sriov.c', ) if cc.has_argument('-Wno-format-nonliteral') diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c index 59f1746ee..27ec42e2c 100644 --- a/drivers/net/qede/qede_ethdev.c +++ b/drivers/net/qede/qede_ethdev.c @@ -2699,6 +2699,7 @@ static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) adapter->vxlan.enable = false; adapter->geneve.enable = false; adapter->ipgre.enable = false; + qed_ops->sriov_configure(edev, pci_dev->max_vfs); } DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n", diff --git a/drivers/net/qede/qede_ethdev.h b/drivers/net/qede/qede_ethdev.h index 76c5dae3b..4fb77b05c 100644 --- a/drivers/net/qede/qede_ethdev.h +++ b/drivers/net/qede/qede_ethdev.h @@ -34,6 +34,7 @@ #include "base/ecore_l2.h" #include "base/ecore_vf.h" +#include "qede_sriov.h" #include "qede_logs.h" #include "qede_if.h" #include "qede_rxtx.h" diff --git a/drivers/net/qede/qede_if.h b/drivers/net/qede/qede_if.h index c5ae3fb2e..1693a243f 100644 --- a/drivers/net/qede/qede_if.h +++ b/drivers/net/qede/qede_if.h @@ -82,6 +82,7 @@ struct qed_eth_ops { const struct qed_common_ops *common; int (*fill_dev_info)(struct ecore_dev *edev, struct qed_dev_eth_info *info); + void (*sriov_configure)(struct ecore_dev *edev, int num_vfs); }; struct qed_link_params { diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c index 94061ec11..c1135822b 100644 --- a/drivers/net/qede/qede_main.c +++ b/drivers/net/qede/qede_main.c @@ -821,6 +821,7 @@ const struct qed_common_ops qed_common_ops_pass = { const struct qed_eth_ops qed_eth_ops_pass = { INIT_STRUCT_FIELD(common, &qed_common_ops_pass), INIT_STRUCT_FIELD(fill_dev_info, &qed_fill_eth_dev_info), + INIT_STRUCT_FIELD(sriov_configure, &qed_sriov_configure), }; const struct qed_eth_ops *qed_get_eth_ops(void) diff --git a/drivers/net/qede/qede_sriov.c b/drivers/net/qede/qede_sriov.c new file mode 100644 index 000000000..ba4384e90 --- /dev/null +++ b/drivers/net/qede/qede_sriov.c @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2020 Marvell. + * All rights reserved. + * www.marvell.com + */ + +#include "qede_sriov.h" + +static void qed_sriov_enable_qid_config(struct ecore_hwfn *hwfn, + u16 vfid, + struct ecore_iov_vf_init_params *params) +{ + u16 num_pf_l2_queues, base, i; + + /* Since we have an equal resource distribution per-VF, and we assume + * PF has acquired its first queues, we start setting sequentially from + * there. + */ + num_pf_l2_queues = (u16)FEAT_NUM(hwfn, ECORE_PF_L2_QUE); + + base = num_pf_l2_queues + vfid * params->num_queues; + params->rel_vf_id = vfid; + + for (i = 0; i < params->num_queues; i++) { + params->req_rx_queue[i] = base + i; + params->req_tx_queue[i] = base + i; + } + + /* PF uses indices 0 for itself; Set vport/RSS afterwards */ + params->vport_id = vfid + 1; + params->rss_eng_id = vfid + 1; +} + +static void qed_sriov_enable(struct ecore_dev *edev, int num) +{ + struct ecore_iov_vf_init_params params; + struct ecore_hwfn *p_hwfn; + struct ecore_ptt *p_ptt; + int i, j, rc; + + if ((u32)num >= RESC_NUM(&edev->hwfns[0], ECORE_VPORT)) { + DP_NOTICE(edev, false, "Can start at most %d VFs\n", + RESC_NUM(&edev->hwfns[0], ECORE_VPORT) - 1); + return; + } + + OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_iov_vf_init_params)); + + for_each_hwfn(edev, j) { + int feat_num; + + p_hwfn = &edev->hwfns[j]; + p_ptt = ecore_ptt_acquire(p_hwfn); + feat_num = FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE) / num; + + params.num_queues = OSAL_MIN_T(int, feat_num, 16); + + for (i = 0; i < num; i++) { + if (!ecore_iov_is_valid_vfid(p_hwfn, i, false, true)) + continue; + + qed_sriov_enable_qid_config(p_hwfn, i, ¶ms); + + rc = ecore_iov_init_hw_for_vf(p_hwfn, p_ptt, ¶ms); + if (rc) { + DP_ERR(edev, "Failed to enable VF[%d]\n", i); + ecore_ptt_release(p_hwfn, p_ptt); + return; + } + } + + ecore_ptt_release(p_hwfn, p_ptt); + } +} + +void qed_sriov_configure(struct ecore_dev *edev, int num_vfs_param) +{ + if (!IS_ECORE_SRIOV(edev)) { + DP_VERBOSE(edev, ECORE_MSG_IOV, "SR-IOV is not supported\n"); + return; + } + + if (num_vfs_param) + qed_sriov_enable(edev, num_vfs_param); +} diff --git a/drivers/net/qede/qede_sriov.h b/drivers/net/qede/qede_sriov.h new file mode 100644 index 000000000..6c85b1dd5 --- /dev/null +++ b/drivers/net/qede/qede_sriov.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2020 Marvell. + * All rights reserved. + * www.marvell.com + */ + +#include "qede_ethdev.h" + +void qed_sriov_configure(struct ecore_dev *edev, int num_vfs_param); From patchwork Fri Sep 25 11:55:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manish Chopra X-Patchwork-Id: 78837 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8E652A04C0; Fri, 25 Sep 2020 13:57:16 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 679901E948; Fri, 25 Sep 2020 13:57:16 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id BAC371E910 for ; Fri, 25 Sep 2020 13:57:14 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 08PBu0xj003673; Fri, 25 Sep 2020 04:57:14 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=0BwlJS5V39Okn+3yDdrNT+RDQSzDgVoMC4lzVHSBZ9g=; b=Sr/AxF8odMU+gyCxltp4xtAfKZZ2V2sniyA8tk19KfNIpGmIfmhS9TagSetcBVRfAv3B G+nuqnjhoox56JcJYb4eEvUw5/zq7IanJA/07/jcQSpIe2uLtgxPcNBLurCuK5273UVw WD4+eVc+TFY226x3aTkANIL/HFmIj4yyAlwm9MNVwra6UtGpVZsSo2udhWzcNXLA+ug2 XhLKdn6eZtmZPLoYmMZ/NazFENhvMS2ua3M6neSwgiM/nqVoFAnLGs5w6Q23WadJHvmJ qyRoYhx3YaZbTvgUJuy0zC4NLTrNUuxy1f/M5XNpDKVrynttw1gBKLImnIqWlMsfOTJS 3w== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 33nfbqb0kk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 25 Sep 2020 04:57:13 -0700 Received: from SC-EXCH04.marvell.com (10.93.176.84) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 25 Sep 2020 04:57:12 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 25 Sep 2020 04:57:12 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 25 Sep 2020 04:57:12 -0700 Received: from dut1171.mv.qlogic.com (unknown [10.112.88.18]) by maili.marvell.com (Postfix) with ESMTP id 77B273F703F; Fri, 25 Sep 2020 04:57:12 -0700 (PDT) Received: from dut1171.mv.qlogic.com (localhost [127.0.0.1]) by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 08PBvCuG004248; Fri, 25 Sep 2020 04:57:12 -0700 Received: (from root@localhost) by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 08PBvCc0004247; Fri, 25 Sep 2020 04:57:12 -0700 From: Manish Chopra To: , , , CC: , , , , , , , , Date: Fri, 25 Sep 2020 04:55:06 -0700 Message-ID: <20200925115508.4179-5-manishc@marvell.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20200925115508.4179-1-manishc@marvell.com> References: <20200925115508.4179-1-manishc@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-09-25_08:2020-09-24, 2020-09-25 signatures=0 Subject: [dpdk-dev] [PATCH v6 4/6] net/qede: add infrastructure support for VF load X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds necessary infrastructure support (required to handle messages from VF and sending ramrod on behalf of VF's configuration request from alarm handler context) to start/load the VF-PMD driver instance on top of PF-PMD driver instance. Signed-off-by: Manish Chopra Signed-off-by: Igor Russkikh Signed-off-by: Rasesh Mody --- drivers/net/qede/base/bcm_osal.c | 26 ++++++++++++ drivers/net/qede/base/bcm_osal.h | 11 +++-- drivers/net/qede/base/ecore.h | 4 ++ drivers/net/qede/base/ecore_iov_api.h | 3 ++ drivers/net/qede/qede_ethdev.c | 2 + drivers/net/qede/qede_main.c | 4 +- drivers/net/qede/qede_sriov.c | 61 +++++++++++++++++++++++++++ drivers/net/qede/qede_sriov.h | 16 ++++++- 8 files changed, 121 insertions(+), 6 deletions(-) diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c index 65837b53d..ef47339df 100644 --- a/drivers/net/qede/base/bcm_osal.c +++ b/drivers/net/qede/base/bcm_osal.c @@ -14,6 +14,32 @@ #include "ecore_iov_api.h" #include "ecore_mcp_api.h" #include "ecore_l2_api.h" +#include "../qede_sriov.h" + +int osal_pf_vf_msg(struct ecore_hwfn *p_hwfn) +{ + int rc; + + rc = qed_schedule_iov(p_hwfn, QED_IOV_WQ_MSG_FLAG); + if (rc) { + DP_VERBOSE(p_hwfn, ECORE_MSG_IOV, + "Failed to schedule alarm handler rc=%d\n", rc); + } + + return rc; +} + +void osal_poll_mode_dpc(osal_int_ptr_t hwfn_cookie) +{ + struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie; + + if (!p_hwfn) + return; + + OSAL_SPIN_LOCK(&p_hwfn->spq_lock); + ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn)); + OSAL_SPIN_UNLOCK(&p_hwfn->spq_lock); +} /* Array of memzone pointers */ static const struct rte_memzone *ecore_mz_mapping[RTE_MAX_MEMZONE]; diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h index 681d2d5b6..e7212f40c 100644 --- a/drivers/net/qede/base/bcm_osal.h +++ b/drivers/net/qede/base/bcm_osal.h @@ -177,9 +177,12 @@ typedef pthread_mutex_t osal_mutex_t; /* DPC */ +void osal_poll_mode_dpc(osal_int_ptr_t hwfn_cookie); #define OSAL_DPC_ALLOC(hwfn) OSAL_ALLOC(hwfn, GFP, sizeof(osal_dpc_t)) -#define OSAL_DPC_INIT(dpc, hwfn) nothing -#define OSAL_POLL_MODE_DPC(hwfn) nothing +#define OSAL_DPC_INIT(dpc, hwfn) \ + OSAL_SPIN_LOCK_INIT(&(hwfn)->spq_lock) +#define OSAL_POLL_MODE_DPC(hwfn) \ + osal_poll_mode_dpc((osal_int_ptr_t)(p_hwfn)) #define OSAL_DPC_SYNC(hwfn) nothing /* Lists */ @@ -344,10 +347,12 @@ u32 qede_find_first_zero_bit(u32 *bitmap, u32 length); /* SR-IOV channel */ +int osal_pf_vf_msg(struct ecore_hwfn *p_hwfn); #define OSAL_VF_FLR_UPDATE(hwfn) nothing #define OSAL_VF_SEND_MSG2PF(dev, done, msg, reply_addr, msg_size, reply_size) 0 #define OSAL_VF_CQE_COMPLETION(_dev_p, _cqe, _protocol) (0) -#define OSAL_PF_VF_MSG(hwfn, vfid) 0 +#define OSAL_PF_VF_MSG(hwfn, vfid) \ + osal_pf_vf_msg(hwfn) #define OSAL_PF_VF_MALICIOUS(hwfn, vfid) nothing #define OSAL_IOV_CHK_UCAST(hwfn, vfid, params) 0 #define OSAL_IOV_POST_START_VPORT(hwfn, vf, vport_id, opaque_fid) nothing diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h index 750e99a8f..6c8e6d407 100644 --- a/drivers/net/qede/base/ecore.h +++ b/drivers/net/qede/base/ecore.h @@ -714,6 +714,10 @@ struct ecore_hwfn { /* @DPDK */ struct ecore_ptt *p_arfs_ptt; + + /* DPDK specific, not the part of vanilla ecore */ + osal_spinlock_t spq_lock; + u32 iov_task_flags; }; enum ecore_mf_mode { diff --git a/drivers/net/qede/base/ecore_iov_api.h b/drivers/net/qede/base/ecore_iov_api.h index 545001812..bd7c5703f 100644 --- a/drivers/net/qede/base/ecore_iov_api.h +++ b/drivers/net/qede/base/ecore_iov_api.h @@ -14,6 +14,9 @@ #define ECORE_ETH_VF_NUM_VLAN_FILTERS 2 #define ECORE_VF_ARRAY_LENGTH (3) +#define ECORE_VF_ARRAY_GET_VFID(arr, vfid) \ + (((arr)[(vfid) / 64]) & (1ULL << ((vfid) % 64))) + #define IS_VF(p_dev) ((p_dev)->b_is_vf) #define IS_PF(p_dev) (!((p_dev)->b_is_vf)) #ifdef CONFIG_ECORE_SRIOV diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c index 27ec42e2c..3cc141954 100644 --- a/drivers/net/qede/qede_ethdev.c +++ b/drivers/net/qede/qede_ethdev.c @@ -281,7 +281,9 @@ qede_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size) static void qede_interrupt_action(struct ecore_hwfn *p_hwfn) { + OSAL_SPIN_LOCK(&p_hwfn->spq_lock); ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn)); + OSAL_SPIN_UNLOCK(&p_hwfn->spq_lock); } static void diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c index c1135822b..6a7bfc188 100644 --- a/drivers/net/qede/qede_main.c +++ b/drivers/net/qede/qede_main.c @@ -221,7 +221,9 @@ static void qed_stop_iov_task(struct ecore_dev *edev) for_each_hwfn(edev, i) { p_hwfn = &edev->hwfns[i]; - if (!IS_PF(edev)) + if (IS_PF(edev)) + rte_eal_alarm_cancel(qed_iov_pf_task, p_hwfn); + else rte_eal_alarm_cancel(qede_vf_task, p_hwfn); } } diff --git a/drivers/net/qede/qede_sriov.c b/drivers/net/qede/qede_sriov.c index ba4384e90..6d620dde8 100644 --- a/drivers/net/qede/qede_sriov.c +++ b/drivers/net/qede/qede_sriov.c @@ -4,6 +4,14 @@ * www.marvell.com */ +#include + +#include "base/bcm_osal.h" +#include "base/ecore.h" +#include "base/ecore_sriov.h" +#include "base/ecore_mcp.h" +#include "base/ecore_vf.h" + #include "qede_sriov.h" static void qed_sriov_enable_qid_config(struct ecore_hwfn *hwfn, @@ -83,3 +91,56 @@ void qed_sriov_configure(struct ecore_dev *edev, int num_vfs_param) if (num_vfs_param) qed_sriov_enable(edev, num_vfs_param); } + +static void qed_handle_vf_msg(struct ecore_hwfn *hwfn) +{ + u64 events[ECORE_VF_ARRAY_LENGTH]; + struct ecore_ptt *ptt; + int i; + + ptt = ecore_ptt_acquire(hwfn); + if (!ptt) { + DP_NOTICE(hwfn, true, "PTT acquire failed\n"); + qed_schedule_iov(hwfn, QED_IOV_WQ_MSG_FLAG); + return; + } + + ecore_iov_pf_get_pending_events(hwfn, events); + + ecore_for_each_vf(hwfn, i) { + /* Skip VFs with no pending messages */ + if (!ECORE_VF_ARRAY_GET_VFID(events, i)) + continue; + + DP_VERBOSE(hwfn, ECORE_MSG_IOV, + "Handling VF message from VF 0x%02x [Abs 0x%02x]\n", + i, hwfn->p_dev->p_iov_info->first_vf_in_pf + i); + + /* Copy VF's message to PF's request buffer for that VF */ + if (ecore_iov_copy_vf_msg(hwfn, ptt, i)) + continue; + + ecore_iov_process_mbx_req(hwfn, ptt, i); + } + + ecore_ptt_release(hwfn, ptt); +} + +void qed_iov_pf_task(void *arg) +{ + struct ecore_hwfn *p_hwfn = arg; + + if (OSAL_GET_BIT(QED_IOV_WQ_MSG_FLAG, &p_hwfn->iov_task_flags)) { + OSAL_CLEAR_BIT(QED_IOV_WQ_MSG_FLAG, &p_hwfn->iov_task_flags); + qed_handle_vf_msg(p_hwfn); + } +} + +int qed_schedule_iov(struct ecore_hwfn *p_hwfn, enum qed_iov_wq_flag flag) +{ + DP_VERBOSE(p_hwfn, ECORE_MSG_IOV, "Scheduling iov task [Flag: %d]\n", + flag); + + OSAL_SET_BIT(flag, &p_hwfn->iov_task_flags); + return rte_eal_alarm_set(1, qed_iov_pf_task, p_hwfn); +} diff --git a/drivers/net/qede/qede_sriov.h b/drivers/net/qede/qede_sriov.h index 6c85b1dd5..8b7fa7daa 100644 --- a/drivers/net/qede/qede_sriov.h +++ b/drivers/net/qede/qede_sriov.h @@ -4,6 +4,18 @@ * www.marvell.com */ -#include "qede_ethdev.h" - void qed_sriov_configure(struct ecore_dev *edev, int num_vfs_param); + +enum qed_iov_wq_flag { + QED_IOV_WQ_MSG_FLAG, + QED_IOV_WQ_SET_UNICAST_FILTER_FLAG, + QED_IOV_WQ_BULLETIN_UPDATE_FLAG, + QED_IOV_WQ_STOP_WQ_FLAG, + QED_IOV_WQ_FLR_FLAG, + QED_IOV_WQ_TRUST_FLAG, + QED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG, + QED_IOV_WQ_DB_REC_HANDLER, +}; + +int qed_schedule_iov(struct ecore_hwfn *p_hwfn, enum qed_iov_wq_flag flag); +void qed_iov_pf_task(void *arg); From patchwork Fri Sep 25 11:55:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manish Chopra X-Patchwork-Id: 78838 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 89BBDA04C0; Fri, 25 Sep 2020 13:57:41 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6122C1E94D; Fri, 25 Sep 2020 13:57:41 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id B3DC81C244 for ; Fri, 25 Sep 2020 13:57:38 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 08PBuBgo003730; Fri, 25 Sep 2020 04:57:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=Ri4iT/8dMs+1NcDtePNL6MlxAoNJmCpzlx3F8In/Sdg=; b=ehO/ASSasDKf4pCJRP5slgZHy4h+UPpfNVhcMA7WSoqWuHAqbM2gsIcgBZn3J2ENQrP2 qxHtQ9qOeyJBS3Dnv1Jkm5x07kpLsWpapdoGuhWjG9fMjhlxSLnJ/FaLUTXQFzj7R1kD Q+6tDOpUBl4dj5jLbJcq3g6FcZr87jPOL6FBhKoE2G+7Mi7nianYupiCEsG6JnYixs7d Qdn/gh8h6khNaZaxI0A6hH0hMYXMJhAajaQmgRn2ZcjN1oi3hQzaW1VaSzR8/Oo4j4Cf q2f/+Oeb6guRYhXacZ6C87Nte0Fuc7GwwnIDZQDyIbc4D6Xgn5BysFmasxbe3meG1GPe pw== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0a-0016f401.pphosted.com with ESMTP id 33nfbqb0q5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 25 Sep 2020 04:57:37 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 25 Sep 2020 04:57:36 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 25 Sep 2020 04:57:36 -0700 Received: from dut1171.mv.qlogic.com (unknown [10.112.88.18]) by maili.marvell.com (Postfix) with ESMTP id 9C3003F703F; Fri, 25 Sep 2020 04:57:36 -0700 (PDT) Received: from dut1171.mv.qlogic.com (localhost [127.0.0.1]) by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 08PBvaWi004260; Fri, 25 Sep 2020 04:57:36 -0700 Received: (from root@localhost) by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 08PBvajQ004251; Fri, 25 Sep 2020 04:57:36 -0700 From: Manish Chopra To: , , , CC: , , , , , , , , Date: Fri, 25 Sep 2020 04:55:07 -0700 Message-ID: <20200925115508.4179-6-manishc@marvell.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20200925115508.4179-1-manishc@marvell.com> References: <20200925115508.4179-1-manishc@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-09-25_08:2020-09-24, 2020-09-25 signatures=0 Subject: [dpdk-dev] [PATCH v6 5/6] net/qede: initialize VF MAC and link X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch configures VFs with random mac if no MAC is provided by the PF/bulletin. This also adds required bulletin APIs by PF-PMD driver to communicate LINK properties/changes to the VFs through bulletin update mechanism. With these changes, VF-PMD instance is able to run fastpath over PF-PMD driver instance. Signed-off-by: Manish Chopra Signed-off-by: Igor Russkikh Signed-off-by: Rasesh Mody --- drivers/net/qede/qede_ethdev.c | 34 ++++++++++++++++++++- drivers/net/qede/qede_main.c | 6 +++- drivers/net/qede/qede_sriov.c | 55 ++++++++++++++++++++++++++++++++++ drivers/net/qede/qede_sriov.h | 1 + 4 files changed, 94 insertions(+), 2 deletions(-) diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c index 3cc141954..150c70d94 100644 --- a/drivers/net/qede/qede_ethdev.c +++ b/drivers/net/qede/qede_ethdev.c @@ -2477,6 +2477,24 @@ static void qede_update_pf_params(struct ecore_dev *edev) qed_ops->common->update_pf_params(edev, &pf_params); } +static void qede_generate_random_mac_addr(struct rte_ether_addr *mac_addr) +{ + uint64_t random; + + /* Set Organizationally Unique Identifier (OUI) prefix. */ + mac_addr->addr_bytes[0] = 0x00; + mac_addr->addr_bytes[1] = 0x09; + mac_addr->addr_bytes[2] = 0xC0; + + /* Force indication of locally assigned MAC address. */ + mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR; + + /* Generate the last 3 bytes of the MAC address with a random number. */ + random = rte_rand(); + + memcpy(&mac_addr->addr_bytes[3], &random, 3); +} + static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) { struct rte_pci_device *pci_dev; @@ -2489,7 +2507,7 @@ static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) uint8_t bulletin_change; uint8_t vf_mac[RTE_ETHER_ADDR_LEN]; uint8_t is_mac_forced; - bool is_mac_exist; + bool is_mac_exist = false; /* Fix up ecore debug level */ uint32_t dp_module = ~0 & ~ECORE_MSG_HW; uint8_t dp_level = ECORE_LEVEL_VERBOSE; @@ -2667,6 +2685,20 @@ static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) DP_ERR(edev, "No VF macaddr assigned\n"); } } + + /* If MAC doesn't exist from PF, generate random one */ + if (!is_mac_exist) { + struct rte_ether_addr *mac_addr; + + mac_addr = (struct rte_ether_addr *)&vf_mac; + qede_generate_random_mac_addr(mac_addr); + + rte_ether_addr_copy(mac_addr, + ð_dev->data->mac_addrs[0]); + + rte_ether_addr_copy(ð_dev->data->mac_addrs[0], + &adapter->primary_mac); + } } eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops; diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c index 6a7bfc188..0d3cea6e4 100644 --- a/drivers/net/qede/qede_main.c +++ b/drivers/net/qede/qede_main.c @@ -651,8 +651,12 @@ void qed_link_update(struct ecore_hwfn *hwfn) struct ecore_dev *edev = hwfn->p_dev; struct qede_dev *qdev = (struct qede_dev *)edev; struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev; + int rc; + + rc = qede_link_update(dev, 0); + qed_inform_vf_link_state(hwfn); - if (!qede_link_update(dev, 0)) + if (!rc) rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); } diff --git a/drivers/net/qede/qede_sriov.c b/drivers/net/qede/qede_sriov.c index 6d620dde8..93f7a2a55 100644 --- a/drivers/net/qede/qede_sriov.c +++ b/drivers/net/qede/qede_sriov.c @@ -126,6 +126,28 @@ static void qed_handle_vf_msg(struct ecore_hwfn *hwfn) ecore_ptt_release(hwfn, ptt); } +static void qed_handle_bulletin_post(struct ecore_hwfn *hwfn) +{ + struct ecore_ptt *ptt; + int i; + + ptt = ecore_ptt_acquire(hwfn); + if (!ptt) { + DP_NOTICE(hwfn, true, "PTT acquire failed\n"); + qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG); + return; + } + + /* TODO - at the moment update bulletin board of all VFs. + * if this proves to costly, we can mark VFs that need their + * bulletins updated. + */ + ecore_for_each_vf(hwfn, i) + ecore_iov_post_vf_bulletin(hwfn, i, ptt); + + ecore_ptt_release(hwfn, ptt); +} + void qed_iov_pf_task(void *arg) { struct ecore_hwfn *p_hwfn = arg; @@ -134,6 +156,13 @@ void qed_iov_pf_task(void *arg) OSAL_CLEAR_BIT(QED_IOV_WQ_MSG_FLAG, &p_hwfn->iov_task_flags); qed_handle_vf_msg(p_hwfn); } + + if (OSAL_GET_BIT(QED_IOV_WQ_BULLETIN_UPDATE_FLAG, + &p_hwfn->iov_task_flags)) { + OSAL_CLEAR_BIT(QED_IOV_WQ_BULLETIN_UPDATE_FLAG, + &p_hwfn->iov_task_flags); + qed_handle_bulletin_post(p_hwfn); + } } int qed_schedule_iov(struct ecore_hwfn *p_hwfn, enum qed_iov_wq_flag flag) @@ -144,3 +173,29 @@ int qed_schedule_iov(struct ecore_hwfn *p_hwfn, enum qed_iov_wq_flag flag) OSAL_SET_BIT(flag, &p_hwfn->iov_task_flags); return rte_eal_alarm_set(1, qed_iov_pf_task, p_hwfn); } + +void qed_inform_vf_link_state(struct ecore_hwfn *hwfn) +{ + struct ecore_hwfn *lead_hwfn = ECORE_LEADING_HWFN(hwfn->p_dev); + struct ecore_mcp_link_capabilities caps; + struct ecore_mcp_link_params params; + struct ecore_mcp_link_state link; + int i; + + if (!hwfn->pf_iov_info) + return; + + rte_memcpy(¶ms, ecore_mcp_get_link_params(lead_hwfn), + sizeof(params)); + rte_memcpy(&link, ecore_mcp_get_link_state(lead_hwfn), sizeof(link)); + rte_memcpy(&caps, ecore_mcp_get_link_capabilities(lead_hwfn), + sizeof(caps)); + + /* Update bulletin of all future possible VFs with link configuration */ + for (i = 0; i < hwfn->p_dev->p_iov_info->total_vfs; i++) { + ecore_iov_set_link(hwfn, i, + ¶ms, &link, &caps); + } + + qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG); +} diff --git a/drivers/net/qede/qede_sriov.h b/drivers/net/qede/qede_sriov.h index 8b7fa7daa..e58ecc2a5 100644 --- a/drivers/net/qede/qede_sriov.h +++ b/drivers/net/qede/qede_sriov.h @@ -17,5 +17,6 @@ enum qed_iov_wq_flag { QED_IOV_WQ_DB_REC_HANDLER, }; +void qed_inform_vf_link_state(struct ecore_hwfn *hwfn); int qed_schedule_iov(struct ecore_hwfn *p_hwfn, enum qed_iov_wq_flag flag); void qed_iov_pf_task(void *arg); From patchwork Fri Sep 25 11:55:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manish Chopra X-Patchwork-Id: 78839 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 74A25A04C0; Fri, 25 Sep 2020 13:58:07 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 54FF31C297; Fri, 25 Sep 2020 13:58:07 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 162791C243 for ; Fri, 25 Sep 2020 13:58:05 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 08PBtInk010841; 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Fri, 25 Sep 2020 04:58:00 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 25 Sep 2020 04:58:00 -0700 Received: from dut1171.mv.qlogic.com (unknown [10.112.88.18]) by maili.marvell.com (Postfix) with ESMTP id C2B353F703F; Fri, 25 Sep 2020 04:58:00 -0700 (PDT) Received: from dut1171.mv.qlogic.com (localhost [127.0.0.1]) by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 08PBw0n5004265; Fri, 25 Sep 2020 04:58:00 -0700 Received: (from root@localhost) by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 08PBw0ht004263; Fri, 25 Sep 2020 04:58:00 -0700 From: Manish Chopra To: , , , CC: , , , , , , , , Date: Fri, 25 Sep 2020 04:55:08 -0700 Message-ID: <20200925115508.4179-7-manishc@marvell.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20200925115508.4179-1-manishc@marvell.com> References: <20200925115508.4179-1-manishc@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-09-25_08:2020-09-24, 2020-09-25 signatures=0 Subject: [dpdk-dev] [PATCH v6 6/6] net/qede: add VF FLR support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds required bit to handle VF FLR indication from Management FW (MFW) of the device With that VFs were able to load in VM (VF attached as PCI passthrough to the guest VM) followed by FLR successfully Updated the docs/guides with the feature support Signed-off-by: Manish Chopra Signed-off-by: Igor Russkikh Signed-off-by: Rasesh Mody --- doc/guides/nics/features/qede.ini | 1 + doc/guides/nics/qede.rst | 7 +------ drivers/net/qede/base/bcm_osal.c | 5 +++++ drivers/net/qede/base/bcm_osal.h | 4 +++- drivers/net/qede/qede_sriov.c | 18 ++++++++++++++++++ 5 files changed, 28 insertions(+), 7 deletions(-) diff --git a/doc/guides/nics/features/qede.ini b/doc/guides/nics/features/qede.ini index f8716523e..46fba8e6c 100644 --- a/doc/guides/nics/features/qede.ini +++ b/doc/guides/nics/features/qede.ini @@ -32,6 +32,7 @@ Basic stats = Y Extended stats = Y Stats per queue = Y Registers dump = Y +SR-IOV = Y Multiprocess aware = Y Linux UIO = Y Linux VFIO = Y diff --git a/doc/guides/nics/qede.rst b/doc/guides/nics/qede.rst index 5b2f86895..e874915c2 100644 --- a/doc/guides/nics/qede.rst +++ b/doc/guides/nics/qede.rst @@ -34,18 +34,13 @@ Supported Features - VLAN offload - Filtering and stripping - N-tuple filter and flow director (limited support) - NPAR (NIC Partitioning) -- SR-IOV VF +- SR-IOV PF and VF - GRE Tunneling offload - GENEVE Tunneling offload - VXLAN Tunneling offload - MPLSoUDP Tx Tunneling offload - Generic flow API -Non-supported Features ----------------------- - -- SR-IOV PF - Co-existence considerations --------------------------- diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c index ef47339df..44a8692f5 100644 --- a/drivers/net/qede/base/bcm_osal.c +++ b/drivers/net/qede/base/bcm_osal.c @@ -29,6 +29,11 @@ int osal_pf_vf_msg(struct ecore_hwfn *p_hwfn) return rc; } +void osal_vf_flr_update(struct ecore_hwfn *p_hwfn) +{ + qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); +} + void osal_poll_mode_dpc(osal_int_ptr_t hwfn_cookie) { struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie; diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h index e7212f40c..575d4d099 100644 --- a/drivers/net/qede/base/bcm_osal.h +++ b/drivers/net/qede/base/bcm_osal.h @@ -348,7 +348,9 @@ u32 qede_find_first_zero_bit(u32 *bitmap, u32 length); /* SR-IOV channel */ int osal_pf_vf_msg(struct ecore_hwfn *p_hwfn); -#define OSAL_VF_FLR_UPDATE(hwfn) nothing +void osal_vf_flr_update(struct ecore_hwfn *p_hwfn); +#define OSAL_VF_FLR_UPDATE(hwfn) \ + osal_vf_flr_update(hwfn) #define OSAL_VF_SEND_MSG2PF(dev, done, msg, reply_addr, msg_size, reply_size) 0 #define OSAL_VF_CQE_COMPLETION(_dev_p, _cqe, _protocol) (0) #define OSAL_PF_VF_MSG(hwfn, vfid) \ diff --git a/drivers/net/qede/qede_sriov.c b/drivers/net/qede/qede_sriov.c index 93f7a2a55..0b99a8d6f 100644 --- a/drivers/net/qede/qede_sriov.c +++ b/drivers/net/qede/qede_sriov.c @@ -151,6 +151,7 @@ static void qed_handle_bulletin_post(struct ecore_hwfn *hwfn) void qed_iov_pf_task(void *arg) { struct ecore_hwfn *p_hwfn = arg; + int rc; if (OSAL_GET_BIT(QED_IOV_WQ_MSG_FLAG, &p_hwfn->iov_task_flags)) { OSAL_CLEAR_BIT(QED_IOV_WQ_MSG_FLAG, &p_hwfn->iov_task_flags); @@ -163,6 +164,23 @@ void qed_iov_pf_task(void *arg) &p_hwfn->iov_task_flags); qed_handle_bulletin_post(p_hwfn); } + + if (OSAL_GET_BIT(QED_IOV_WQ_FLR_FLAG, &p_hwfn->iov_task_flags)) { + struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn); + + OSAL_CLEAR_BIT(QED_IOV_WQ_FLR_FLAG, &p_hwfn->iov_task_flags); + + if (!p_ptt) { + qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); + return; + } + + rc = ecore_iov_vf_flr_cleanup(p_hwfn, p_ptt); + if (rc) + qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); + + ecore_ptt_release(p_hwfn, p_ptt); + } } int qed_schedule_iov(struct ecore_hwfn *p_hwfn, enum qed_iov_wq_flag flag)