From patchwork Wed Nov 18 10:48:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feifei Wang X-Patchwork-Id: 84312 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E201CA04E6; Wed, 18 Nov 2020 11:49:56 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BF807C8B6; Wed, 18 Nov 2020 11:49:40 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 83047C8B2 for ; Wed, 18 Nov 2020 11:49:39 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EAB2BD6E; Wed, 18 Nov 2020 02:49:37 -0800 (PST) Received: from net-arm-n1sdp.shanghai.arm.com (net-arm-n1sdp.shanghai.arm.com [10.169.208.219]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 74A223F719; Wed, 18 Nov 2020 02:49:35 -0800 (PST) From: Feifei Wang To: Jerin Jacob , Ruifeng Wang , Jeff Guo , Haiyue Wang Cc: dev@dpdk.org, nd@arm.com, Feifei Wang Date: Wed, 18 Nov 2020 04:48:56 -0600 Message-Id: <20201118104859.29047-2-feifei.wang2@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201118104859.29047-1-feifei.wang2@arm.com> References: <20201118073524.25646-1-feifei.wang2@arm.com> <20201118104859.29047-1-feifei.wang2@arm.com> Subject: [dpdk-dev] [PATCH v2 1/4] net/ixgbe: add new flag of stripped VLAN for NEON vector X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" For NEON vector of IXGBE PMD, introduce new flag PKT_RX_VLAN_STRIPPED to show the case that the VLAN is stripped from the VLAN tagged packet. This is because that the old flag PKT_RX_VLAN_PKT only indicates that the packet is VLAN tagged, but cannot show whether VLAN is in m->vlan_tci or in the packet at present. So add new flag to show the vlan has been stripped by the hardware and its tci is saved in m->vlan_tci when vlan stripping is enabled in the RX configuration of the IXGBE PMD. Signed-off-by: Feifei Wang Reviewed-by: Ruifeng Wang Acked-by: Haiyue Wang --- drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c | 36 ++++++++++++++++--------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c b/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c index 4c81ae9dc..e6d877af9 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c +++ b/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c @@ -81,11 +81,9 @@ ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq) IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id); } -#define VTAG_SHIFT (3) - static inline void desc_to_olflags_v(uint8x16x2_t sterr_tmp1, uint8x16x2_t sterr_tmp2, - uint8x16_t staterr, struct rte_mbuf **rx_pkts) + uint8x16_t staterr, uint8_t vlan_flags, struct rte_mbuf **rx_pkts) { uint8x16_t ptype; uint8x16_t vtag; @@ -95,13 +93,6 @@ desc_to_olflags_v(uint8x16x2_t sterr_tmp1, uint8x16x2_t sterr_tmp2, uint32_t word; } vol; - const uint8x16_t pkttype_msk = { - PKT_RX_VLAN, PKT_RX_VLAN, - PKT_RX_VLAN, PKT_RX_VLAN, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00}; - const uint8x16_t rsstype_msk = { 0x0F, 0x0F, 0x0F, 0x0F, 0x00, 0x00, 0x00, 0x00, @@ -114,12 +105,26 @@ desc_to_olflags_v(uint8x16x2_t sterr_tmp1, uint8x16x2_t sterr_tmp2, PKT_RX_RSS_HASH, 0, 0, 0, 0, 0, 0, PKT_RX_FDIR}; + const uint8x16_t vlan_msk = { + IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP, + IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0}; + + const uint8x16_t vlan_map = { + 0, 0, 0, 0, + 0, 0, 0, 0, + vlan_flags, 0, 0, 0, + 0, 0, 0, 0}; + ptype = vzipq_u8(sterr_tmp1.val[0], sterr_tmp2.val[0]).val[0]; ptype = vandq_u8(ptype, rsstype_msk); ptype = vqtbl1q_u8(rss_flags, ptype); - vtag = vshrq_n_u8(staterr, VTAG_SHIFT); - vtag = vandq_u8(vtag, pkttype_msk); + /* extract vlan_flags from IXGBE_RXD_STAT_VP bits of staterr */ + vtag = vandq_u8(staterr, vlan_msk); + vtag = vqtbl1q_u8(vlan_map, vtag); vtag = vorrq_u8(ptype, vtag); vol.word = vgetq_lane_u32(vreinterpretq_u32_u8(vtag), 0); @@ -221,6 +226,7 @@ _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts, }; uint16x8_t crc_adjust = {0, 0, rxq->crc_len, 0, rxq->crc_len, 0, 0, 0}; + uint8_t vlan_flags; /* nb_pkts has to be floor-aligned to RTE_IXGBE_DESCS_PER_LOOP */ nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_IXGBE_DESCS_PER_LOOP); @@ -250,6 +256,10 @@ _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts, */ sw_ring = &rxq->sw_ring[rxq->rx_tail]; + /* ensure these 2 flags are in the lower 8 bits */ + RTE_BUILD_BUG_ON((PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED) > UINT8_MAX); + vlan_flags = rxq->vlan_flags & UINT8_MAX; + /* A. load 4 packet in one loop * B. copy 4 mbuf point from swring to rx_pkts * C. calc the number of DD bits among the 4 packets @@ -311,7 +321,7 @@ _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts, staterr = vzipq_u8(sterr_tmp1.val[1], sterr_tmp2.val[1]).val[0]; /* set ol_flags with vlan packet type */ - desc_to_olflags_v(sterr_tmp1, sterr_tmp2, staterr, + desc_to_olflags_v(sterr_tmp1, sterr_tmp2, staterr, vlan_flags, &rx_pkts[pos]); /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */ From patchwork Wed Nov 18 10:48:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feifei Wang X-Patchwork-Id: 84313 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5088DA04E6; Wed, 18 Nov 2020 11:50:18 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C5283C900; Wed, 18 Nov 2020 11:49:43 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 846ACC8FC for ; Wed, 18 Nov 2020 11:49:42 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 09A8FD6E; Wed, 18 Nov 2020 02:49:41 -0800 (PST) Received: from net-arm-n1sdp.shanghai.arm.com (net-arm-n1sdp.shanghai.arm.com [10.169.208.219]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 888903F719; Wed, 18 Nov 2020 02:49:38 -0800 (PST) From: Feifei Wang To: Jerin Jacob , Ruifeng Wang , Jeff Guo , Haiyue Wang Cc: dev@dpdk.org, nd@arm.com, Feifei Wang Date: Wed, 18 Nov 2020 04:48:57 -0600 Message-Id: <20201118104859.29047-3-feifei.wang2@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201118104859.29047-1-feifei.wang2@arm.com> References: <20201118073524.25646-1-feifei.wang2@arm.com> <20201118104859.29047-1-feifei.wang2@arm.com> Subject: [dpdk-dev] [PATCH v2 2/4] net/ixgbe: support bad checksum flag for NEON vector X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Updated desc_to_olflags_v() to support PKT_RX_IP_CKSUM_BAD and PKT_RX_L4_CKSUM_BAD in the ol_flags of the mbuf. And then the NEON vector RX function can be called with hw_ip_checksum enabled. Signed-off-by: Feifei Wang Reviewed-by: Ruifeng Wang Acked-by: Haiyue Wang --- drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c | 47 +++++++++++++++++++------ 1 file changed, 36 insertions(+), 11 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c b/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c index e6d877af9..4d6f057e7 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c +++ b/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c @@ -87,6 +87,8 @@ desc_to_olflags_v(uint8x16x2_t sterr_tmp1, uint8x16x2_t sterr_tmp2, { uint8x16_t ptype; uint8x16_t vtag; + uint8x16_t temp_csum; + uint32x4_t csum = {0, 0, 0, 0}; union { uint8_t e[4]; @@ -105,26 +107,51 @@ desc_to_olflags_v(uint8x16x2_t sterr_tmp1, uint8x16x2_t sterr_tmp2, PKT_RX_RSS_HASH, 0, 0, 0, 0, 0, 0, PKT_RX_FDIR}; - const uint8x16_t vlan_msk = { + /* mask everything except vlan present and l4/ip csum error */ + const uint8x16_t vlan_csum_msk = { IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0}; - - const uint8x16_t vlan_map = { + (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 24, + (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 24, + (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 24, + (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 24}; + + /* map vlan present (0x8), IPE (0x2), L4E (0x1) to ol_flags */ + const uint8x16_t vlan_csum_map = { + 0, + PKT_RX_L4_CKSUM_BAD, + PKT_RX_IP_CKSUM_BAD, + PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD, 0, 0, 0, 0, - 0, 0, 0, 0, - vlan_flags, 0, 0, 0, + vlan_flags, + vlan_flags | PKT_RX_L4_CKSUM_BAD, + vlan_flags | PKT_RX_IP_CKSUM_BAD, + vlan_flags | PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD, 0, 0, 0, 0}; ptype = vzipq_u8(sterr_tmp1.val[0], sterr_tmp2.val[0]).val[0]; ptype = vandq_u8(ptype, rsstype_msk); ptype = vqtbl1q_u8(rss_flags, ptype); - /* extract vlan_flags from IXGBE_RXD_STAT_VP bits of staterr */ - vtag = vandq_u8(staterr, vlan_msk); - vtag = vqtbl1q_u8(vlan_map, vtag); + /* extract vlan_flags and csum_error from staterr */ + vtag = vandq_u8(staterr, vlan_csum_msk); + + /* csum bits are in the most significant, to use shuffle we need to + * shift them. Change mask from 0xc0 to 0x03. + */ + temp_csum = vshrq_n_u8(vtag, 6); + + /* 'OR' the most significant 32 bits containing the checksum + * flags with the vlan present flags + * Then bits layout of each lane(8bits) will be 'xxxx,VP,x,IPE,L4E' + */ + csum = vsetq_lane_u32(vgetq_lane_u32(vreinterpretq_u32_u8(temp_csum), 3), csum, 0); + vtag = vorrq_u8(vreinterpretq_u8_u32(csum), vtag); + + /* convert VP, IPE, L4E to ol_flags */ + vtag = vqtbl1q_u8(vlan_csum_map, vtag); vtag = vorrq_u8(ptype, vtag); vol.word = vgetq_lane_u32(vreinterpretq_u32_u8(vtag), 0); @@ -391,7 +418,6 @@ _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts, * Notice: * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two - * - don't support ol_flags for rss and csum err */ uint16_t ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, @@ -404,7 +430,6 @@ ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, * vPMD receive routine that reassembles scattered packets * * Notice: - * - don't support ol_flags for rss and csum err * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two */ From patchwork Wed Nov 18 10:48:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feifei Wang X-Patchwork-Id: 84314 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id CAE8FA04E6; Wed, 18 Nov 2020 11:50:35 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 779D8C90E; Wed, 18 Nov 2020 11:49:47 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 9D78AC90A for ; Wed, 18 Nov 2020 11:49:45 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1E560D6E; Wed, 18 Nov 2020 02:49:44 -0800 (PST) Received: from net-arm-n1sdp.shanghai.arm.com (net-arm-n1sdp.shanghai.arm.com [10.169.208.219]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9D46B3F719; Wed, 18 Nov 2020 02:49:41 -0800 (PST) From: Feifei Wang To: Jerin Jacob , Ruifeng Wang , Jeff Guo , Haiyue Wang Cc: dev@dpdk.org, nd@arm.com, Feifei Wang Date: Wed, 18 Nov 2020 04:48:58 -0600 Message-Id: <20201118104859.29047-4-feifei.wang2@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201118104859.29047-1-feifei.wang2@arm.com> References: <20201118073524.25646-1-feifei.wang2@arm.com> <20201118104859.29047-1-feifei.wang2@arm.com> Subject: [dpdk-dev] [PATCH v2 3/4] net/ixgbe: support good checksum flag for NEON vector X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add CKSUM_GOOD flag to distinguish a good checksum from an unknown one in neon vertor RX function. Signed-off-by: Feifei Wang Reviewed-by: Ruifeng Wang Acked-by: Haiyue Wang --- drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c | 37 +++++++++++++++++-------- 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c b/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c index 4d6f057e7..b2bee2228 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c +++ b/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c @@ -86,13 +86,13 @@ desc_to_olflags_v(uint8x16x2_t sterr_tmp1, uint8x16x2_t sterr_tmp2, uint8x16_t staterr, uint8_t vlan_flags, struct rte_mbuf **rx_pkts) { uint8x16_t ptype; - uint8x16_t vtag; + uint8x16_t vtag_lo, vtag_hi, vtag; uint8x16_t temp_csum; uint32x4_t csum = {0, 0, 0, 0}; union { - uint8_t e[4]; - uint32_t word; + uint16_t e[4]; + uint64_t word; } vol; const uint8x16_t rsstype_msk = { @@ -119,18 +119,26 @@ desc_to_olflags_v(uint8x16x2_t sterr_tmp1, uint8x16x2_t sterr_tmp2, (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 24}; /* map vlan present (0x8), IPE (0x2), L4E (0x1) to ol_flags */ - const uint8x16_t vlan_csum_map = { - 0, - PKT_RX_L4_CKSUM_BAD, + const uint8x16_t vlan_csum_map_lo = { + PKT_RX_IP_CKSUM_GOOD, + PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD, 0, 0, 0, 0, - vlan_flags, - vlan_flags | PKT_RX_L4_CKSUM_BAD, + vlan_flags | PKT_RX_IP_CKSUM_GOOD, + vlan_flags | PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD, vlan_flags | PKT_RX_IP_CKSUM_BAD, vlan_flags | PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD, 0, 0, 0, 0}; + const uint8x16_t vlan_csum_map_hi = { + PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t), 0, + PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t), 0, + 0, 0, 0, 0, + PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t), 0, + PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t), 0, + 0, 0, 0, 0}; + ptype = vzipq_u8(sterr_tmp1.val[0], sterr_tmp2.val[0]).val[0]; ptype = vandq_u8(ptype, rsstype_msk); ptype = vqtbl1q_u8(rss_flags, ptype); @@ -150,11 +158,16 @@ desc_to_olflags_v(uint8x16x2_t sterr_tmp1, uint8x16x2_t sterr_tmp2, csum = vsetq_lane_u32(vgetq_lane_u32(vreinterpretq_u32_u8(temp_csum), 3), csum, 0); vtag = vorrq_u8(vreinterpretq_u8_u32(csum), vtag); - /* convert VP, IPE, L4E to ol_flags */ - vtag = vqtbl1q_u8(vlan_csum_map, vtag); - vtag = vorrq_u8(ptype, vtag); + /* convert L4 checksum correct type to vtag_hi */ + vtag_hi = vqtbl1q_u8(vlan_csum_map_hi, vtag); + vtag_hi = vshrq_n_u8(vtag_hi, 7); + + /* convert VP, IPE, L4E to vtag_lo */ + vtag_lo = vqtbl1q_u8(vlan_csum_map_lo, vtag); + vtag_lo = vorrq_u8(ptype, vtag_lo); - vol.word = vgetq_lane_u32(vreinterpretq_u32_u8(vtag), 0); + vtag = vzipq_u8(vtag_lo, vtag_hi).val[0]; + vol.word = vgetq_lane_u64(vreinterpretq_u64_u8(vtag), 0); rx_pkts[0]->ol_flags = vol.e[0]; rx_pkts[1]->ol_flags = vol.e[1]; From patchwork Wed Nov 18 10:48:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feifei Wang X-Patchwork-Id: 84315 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E1F31A04E6; Wed, 18 Nov 2020 11:50:51 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0F29CC916; Wed, 18 Nov 2020 11:49:50 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id B4A03C916 for ; Wed, 18 Nov 2020 11:49:48 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 39F3411D4; Wed, 18 Nov 2020 02:49:47 -0800 (PST) Received: from net-arm-n1sdp.shanghai.arm.com (net-arm-n1sdp.shanghai.arm.com [10.169.208.219]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B01CC3F719; Wed, 18 Nov 2020 02:49:44 -0800 (PST) From: Feifei Wang To: Jerin Jacob , Ruifeng Wang , Jeff Guo , Haiyue Wang Cc: dev@dpdk.org, nd@arm.com, Feifei Wang Date: Wed, 18 Nov 2020 04:48:59 -0600 Message-Id: <20201118104859.29047-5-feifei.wang2@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201118104859.29047-1-feifei.wang2@arm.com> References: <20201118073524.25646-1-feifei.wang2@arm.com> <20201118104859.29047-1-feifei.wang2@arm.com> Subject: [dpdk-dev] [PATCH v2 4/4] net/ixgbe: enable IXGBE NEON vector when need to checksum X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" IXGBE NEON vector PMD now supports checksum offloading, hence can be used when DEV_RX_OFFLOAD_CHECKSUM is set. Signed-off-by: Feifei Wang Reviewed-by: Ruifeng Wang Acked-by: Haiyue Wang --- drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c b/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c index b2bee2228..a5a5b2167 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c +++ b/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c @@ -638,11 +638,5 @@ ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq) int __rte_cold ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev) { - struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; - - /* no csum error report support */ - if (rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM) - return -1; - return ixgbe_rx_vec_dev_conf_condition_check_default(dev); }