From patchwork Mon Dec 28 19:44:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiri Kuzin X-Patchwork-Id: 85847 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E6B5AA09FF; Mon, 28 Dec 2020 20:45:27 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 13CB8CA4D; Mon, 28 Dec 2020 20:44:54 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 57373CA4C for ; Mon, 28 Dec 2020 20:44:51 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from shirik@nvidia.com) with SMTP; 28 Dec 2020 21:44:48 +0200 Received: from nvidia.com (c-236-148-180-183.mtl.labs.mlnx [10.236.148.183]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BSJicFX018969; Mon, 28 Dec 2020 21:44:43 +0200 From: Shiri Kuzin To: dev@dpdk.org Cc: viacheslavo@nvidia.com, adrien.mazarguil@6wind.com, orika@nvidia.com, ferruh.yigit@intel.com, thomas@monjalon.net, rasland@nvidia.com Date: Mon, 28 Dec 2020 21:44:27 +0200 Message-Id: <20201228194432.30512-2-shirik@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20201228194432.30512-1-shirik@nvidia.com> References: <20201228194432.30512-1-shirik@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 1/6] ethdev: update GTP headers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Viacheslav Ovsiienko This patch introduces the GTP header individual flag bit fields and the header optional word with N-PDU number, Sequence Number and Next Extension Header type. Signed-off-by: Viacheslav Ovsiienko Acked-by: Ori Kam --- lib/librte_net/rte_gtp.h | 33 ++++++++++++++++++++++++++++++--- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/lib/librte_net/rte_gtp.h b/lib/librte_net/rte_gtp.h index 104384cc53..6a6f9b238d 100644 --- a/lib/librte_net/rte_gtp.h +++ b/lib/librte_net/rte_gtp.h @@ -27,13 +27,40 @@ extern "C" { * 16-bit payload length after mandatory header, 32-bit TEID. * No optional fields and next extension header. */ +__extension__ struct rte_gtp_hdr { - uint8_t gtp_hdr_info; /**< GTP header info */ + union { + uint8_t gtp_hdr_info; /**< GTP header info */ + struct { +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN + uint8_t pn:1; /**< N-PDU Number present bit */ + uint8_t s:1; /**< Sequence Number Present bit */ + uint8_t e:1; /**< Extension Present bit */ + uint8_t res1:1; /**< Reserved */ + uint8_t pt:1; /**< Protocol Type bit */ + uint8_t ver:3; /**< Version Number */ +#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN + uint8_t ver:3; /**< Version Number */ + uint8_t pt:1; /**< Protocol Type bit */ + uint8_t res1:1; /**< Reserved */ + uint8_t e:1; /**< Extension Present bit */ + uint8_t s:1; /**< Sequence Number Present bit */ + uint8_t pn:1; /**< N-PDU Number present bit */ +#endif + }; + }; uint8_t msg_type; /**< GTP message type */ - uint16_t plen; /**< Total payload length */ - uint32_t teid; /**< Tunnel endpoint ID */ + rte_be16_t plen; /**< Total payload length */ + rte_be32_t teid; /**< Tunnel endpoint ID */ } __rte_packed; +/* Optional word of GTP header, present if any of E, S, PN is set. */ +struct rte_gtp_hdr_ext_word { + rte_be16_t sqn; /**< Sequence Number. */ + uint8_t npdu; /**< N-PDU number. */ + uint8_t next_ext; /**< Next Extension Header Type. */ +} __rte_packed; + /** GTP header length */ #define RTE_ETHER_GTP_HLEN \ (sizeof(struct rte_udp_hdr) + sizeof(struct rte_gtp_hdr)) From patchwork Mon Dec 28 19:44:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiri Kuzin X-Patchwork-Id: 85846 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4C8BDA09FF; Mon, 28 Dec 2020 20:45:05 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 18E06CA36; Mon, 28 Dec 2020 20:44:49 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 582CCCA35 for ; Mon, 28 Dec 2020 20:44:46 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from shirik@nvidia.com) with SMTP; 28 Dec 2020 21:44:45 +0200 Received: from nvidia.com (c-236-148-180-183.mtl.labs.mlnx [10.236.148.183]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BSJicFY018969; Mon, 28 Dec 2020 21:44:45 +0200 From: Shiri Kuzin To: dev@dpdk.org Cc: viacheslavo@nvidia.com, adrien.mazarguil@6wind.com, orika@nvidia.com, ferruh.yigit@intel.com, thomas@monjalon.net, rasland@nvidia.com Date: Mon, 28 Dec 2020 21:44:28 +0200 Message-Id: <20201228194432.30512-3-shirik@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20201228194432.30512-1-shirik@nvidia.com> References: <20201228194432.30512-1-shirik@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 2/6] app/testpmd: add GTP PSC option support in raw sets X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Viacheslav Ovsiienko This patch add support for generating GTP PDU container session option for the raw encap and raw decap sets. The generated options is single 32-bit word with minimal length specified as 4, no extra fields in the option are supported. The option item must be preceded with the GTP item itself, and GTP item flags must be set accordingly: - E flag must be set, we are going to provide extension - S flag must be reset, because GTP item does not provide the value for SQN field, we can't fill this one - PN flag must be reset, no N-PDU value provided by GTP item either The raw set example: set raw_encap 2 eth / ipv4 / udp / gtp v_pt_rsv_flags is 0x34 / gtp_psc / end_set Please, note - value 0x34 provides the required flag combination. Signed-off-by: Viacheslav Ovsiienko Acked-by: Ori Kam --- app/test-pmd/cmdline_flow.c | 66 +++++++++++++++++++++++++++++++++++-- 1 file changed, 63 insertions(+), 3 deletions(-) diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c index 585cab98b4..37b10e61bf 100644 --- a/app/test-pmd/cmdline_flow.c +++ b/app/test-pmd/cmdline_flow.c @@ -7581,6 +7581,7 @@ cmd_set_raw_parsed(const struct buffer *in) uint16_t upper_layer = 0; uint16_t proto = 0; uint16_t idx = in->port; /* We borrow port field as index */ + int gtp_psc = -1; /* GTP PSC option index. */ if (in->command == SET_SAMPLE_ACTIONS) return cmd_set_raw_parsed_sample(in); @@ -7598,6 +7599,8 @@ cmd_set_raw_parsed(const struct buffer *in) /* process hdr from upper layer to low layer (L3/L4 -> L2). */ data_tail = data + ACTION_RAW_ENCAP_MAX_DATA; for (i = n - 1 ; i >= 0; --i) { + const struct rte_flow_item_gtp *gtp; + item = in->args.vc.pattern + i; if (item->spec == NULL) item->spec = flow_item_default_mask(item); @@ -7663,16 +7666,68 @@ cmd_set_raw_parsed(const struct buffer *in) proto = 0x33; break; case RTE_FLOW_ITEM_TYPE_GTP: + if (gtp_psc < 0) { + size = sizeof(struct rte_gtp_hdr); + break; + } + if (gtp_psc != i + 1) { + printf("Error - GTP PSC does not follow GTP\n"); + goto error; + } + gtp = item->spec; + if ((gtp->v_pt_rsv_flags & 0x07) != 0x04) { + /* Only E flag should be set. */ + printf("Error - GTP unsupported flags\n"); + goto error; + } else { + struct rte_gtp_hdr_ext_word ext_word = { + .next_ext = 0x85 + }; + + /* We have to add GTP header extra word. */ + *total_size += sizeof(ext_word); + rte_memcpy(data_tail - (*total_size), + &ext_word, sizeof(ext_word)); + } size = sizeof(struct rte_gtp_hdr); break; + case RTE_FLOW_ITEM_TYPE_GTP_PSC: + if (gtp_psc >= 0) { + printf("Error - Multiple GTP PSC items\n"); + goto error; + } else { + const struct rte_flow_item_gtp_psc + *opt = item->spec; + struct { + uint8_t len; + uint8_t pdu_type; + uint8_t qfi; + uint8_t next; + } psc; + + if (opt->pdu_type & 0x0F) { + /* Support the minimal option only. */ + printf("Error - GTP PSC option with " + "extra fields not supported\n"); + goto error; + } + psc.len = sizeof(psc); + psc.pdu_type = opt->pdu_type; + psc.qfi = opt->qfi; + psc.next = 0; + *total_size += sizeof(psc); + rte_memcpy(data_tail - (*total_size), + &psc, sizeof(psc)); + gtp_psc = i; + size = 0; + } + break; case RTE_FLOW_ITEM_TYPE_PFCP: size = sizeof(struct rte_flow_item_pfcp); break; default: printf("Error - Not supported item\n"); - *total_size = 0; - memset(data, 0x00, ACTION_RAW_ENCAP_MAX_DATA); - return; + goto error; } *total_size += size; rte_memcpy(data_tail - (*total_size), item->spec, size); @@ -7685,6 +7740,11 @@ cmd_set_raw_parsed(const struct buffer *in) printf("total data size is %zu\n", (*total_size)); RTE_ASSERT((*total_size) <= ACTION_RAW_ENCAP_MAX_DATA); memmove(data, (data_tail - (*total_size)), *total_size); + return; + +error: + *total_size = 0; + memset(data, 0x00, ACTION_RAW_ENCAP_MAX_DATA); } /** Populate help strings for current token (cmdline API). */ From patchwork Mon Dec 28 19:44:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiri Kuzin X-Patchwork-Id: 85848 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 08FDCA09FF; Mon, 28 Dec 2020 20:45:45 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 88C6CCA5E; Mon, 28 Dec 2020 20:44:55 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 64B5BCA4D for ; Mon, 28 Dec 2020 20:44:52 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from shirik@nvidia.com) with SMTP; 28 Dec 2020 21:44:48 +0200 Received: from nvidia.com (c-236-148-180-183.mtl.labs.mlnx [10.236.148.183]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BSJicFZ018969; Mon, 28 Dec 2020 21:44:48 +0200 From: Shiri Kuzin To: dev@dpdk.org Cc: viacheslavo@nvidia.com, adrien.mazarguil@6wind.com, orika@nvidia.com, ferruh.yigit@intel.com, thomas@monjalon.net, rasland@nvidia.com Date: Mon, 28 Dec 2020 21:44:29 +0200 Message-Id: <20201228194432.30512-4-shirik@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20201228194432.30512-1-shirik@nvidia.com> References: <20201228194432.30512-1-shirik@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 3/6] common/mlx5: add matcher fields for GTP extensions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This is a preparation step to support GTP extension header. In this patch we add the matcher fields that will be used to match on the GTP extension header. Signed-off-by: Shiri Kuzin --- drivers/common/mlx5/mlx5_prm.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 58d180486e..2878223ed9 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -791,7 +791,12 @@ struct mlx5_ifc_fte_match_set_misc3_bits { u8 gtpu_teid[0x20]; u8 gtpu_msg_type[0x08]; u8 gtpu_msg_flags[0x08]; - u8 reserved_at_170[0x90]; + u8 reserved_at_170[0x10]; + u8 gtpu_dw_2[0x20]; + u8 gtpu_first_ext_dw_0[0x20]; + u8 gtpu_dw_0[0x20]; + u8 reserved_at_240[0x20]; + }; struct mlx5_ifc_fte_match_set_misc4_bits { From patchwork Mon Dec 28 19:44:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiri Kuzin X-Patchwork-Id: 85850 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 15682A09FF; Mon, 28 Dec 2020 20:46:14 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E0E83CA89; Mon, 28 Dec 2020 20:45:00 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 691E6CA67 for ; Mon, 28 Dec 2020 20:44:57 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from shirik@nvidia.com) with SMTP; 28 Dec 2020 21:44:51 +0200 Received: from nvidia.com (c-236-148-180-183.mtl.labs.mlnx [10.236.148.183]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BSJicFa018969; Mon, 28 Dec 2020 21:44:51 +0200 From: Shiri Kuzin To: dev@dpdk.org Cc: viacheslavo@nvidia.com, adrien.mazarguil@6wind.com, orika@nvidia.com, ferruh.yigit@intel.com, thomas@monjalon.net, rasland@nvidia.com Date: Mon, 28 Dec 2020 21:44:30 +0200 Message-Id: <20201228194432.30512-5-shirik@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20201228194432.30512-1-shirik@nvidia.com> References: <20201228194432.30512-1-shirik@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 4/6] net/mlx5: add GTP PSC flow validation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In this patch we add validation routine for GTP PSC extension header. The GTP PSC extension header must follow the GTP item. Signed-off-by: Shiri Kuzin --- drivers/net/mlx5/mlx5_flow.h | 5 +++ drivers/net/mlx5/mlx5_flow_dv.c | 70 +++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index d85dd19929..fd6b24c32d 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -138,6 +138,9 @@ enum mlx5_feature_name { #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30) #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31) +/* Pattern tunnel Layer bits (continued). */ +#define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33) + /* Outer Masks. */ #define MLX5_FLOW_LAYER_OUTER_L3 \ (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) @@ -348,6 +351,8 @@ enum mlx5_feature_name { #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \ sizeof(struct rte_ipv4_hdr)) +/* GTP extension header flag. */ +#define MLX5_GTP_EXT_HEADER_FLAG 4 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */ #define MLX5_IPV4_FRAG_OFFSET_MASK \ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 4f638e24ad..3f6d44a265 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1759,6 +1759,66 @@ flow_dv_validate_item_gtp(struct rte_eth_dev *dev, MLX5_ITEM_RANGE_NOT_ACCEPTED, error); } +/** + * Validate GTP PSC item. + * + * @param[in] item + * Item specification. + * @param[in] last_item + * Previous validated item in the pattern items. + * @param[in] gtp_item + * Previous GTP item specification. + * @param[in] attr + * Pointer to flow attributes. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item, + uint64_t last_item, + const struct rte_flow_item *gtp_item, + const struct rte_flow_attr *attr, + struct rte_flow_error *error) +{ + const struct rte_flow_item_gtp *gtp_spec; + const struct rte_flow_item_gtp *gtp_mask; + const struct rte_flow_item_gtp_psc *mask; + const struct rte_flow_item_gtp_psc nic_mask = { + .pdu_type = 0xFF, + .qfi = 0xFF, + }; + + if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP)) + return rte_flow_error_set + (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, + "GTP PSC item must be preceded with GTP item"); + gtp_spec = gtp_item->spec; + gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask; + /* GTP spec and E flag is requested to match zero. */ + if (gtp_spec && + (gtp_mask->v_pt_rsv_flags & + ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG)) + return rte_flow_error_set + (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, + "GTP E flag must be 1 to match GTP PSC"); + /* Check the flow is not created in group zero. */ + if (!attr->transfer && !attr->group) + return rte_flow_error_set + (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "GTP PSC is not supported for group 0"); + /* GTP spec is here and E flag is requested to match zero. */ + if (!item->spec) + return 0; + mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask; + return mlx5_flow_item_acceptable(item, (const uint8_t *)mask, + (const uint8_t *)&nic_mask, + sizeof(struct rte_flow_item_gtp_psc), + MLX5_ITEM_RANGE_NOT_ACCEPTED, error); +} + /** * Validate IPV4 item. * Use existing validation function mlx5_flow_validate_item_ipv4(), and @@ -5219,6 +5279,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, int actions_n = 0; uint8_t item_ipv6_proto = 0; const struct rte_flow_item *gre_item = NULL; + const struct rte_flow_item *gtp_item = NULL; const struct rte_flow_action_raw_decap *decap; const struct rte_flow_action_raw_encap *encap; const struct rte_flow_action_rss *rss; @@ -5556,8 +5617,17 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, error); if (ret < 0) return ret; + gtp_item = items; last_item = MLX5_FLOW_LAYER_GTP; break; + case RTE_FLOW_ITEM_TYPE_GTP_PSC: + ret = flow_dv_validate_item_gtp_psc(items, last_item, + gtp_item, attr, + error); + if (ret < 0) + return ret; + last_item = MLX5_FLOW_LAYER_GTP_PSC; + break; case RTE_FLOW_ITEM_TYPE_ECPRI: /* Capacity will be checked in the translate stage. */ ret = mlx5_flow_validate_item_ecpri(items, item_flags, From patchwork Mon Dec 28 19:44:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiri Kuzin X-Patchwork-Id: 85849 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9EDCBA09FF; Mon, 28 Dec 2020 20:46:00 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1AEE0CA45; Mon, 28 Dec 2020 20:44:59 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 65079CA45 for ; Mon, 28 Dec 2020 20:44:57 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from shirik@nvidia.com) with SMTP; 28 Dec 2020 21:44:53 +0200 Received: from nvidia.com (c-236-148-180-183.mtl.labs.mlnx [10.236.148.183]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BSJicFb018969; Mon, 28 Dec 2020 21:44:53 +0200 From: Shiri Kuzin To: dev@dpdk.org Cc: viacheslavo@nvidia.com, adrien.mazarguil@6wind.com, orika@nvidia.com, ferruh.yigit@intel.com, thomas@monjalon.net, rasland@nvidia.com Date: Mon, 28 Dec 2020 21:44:31 +0200 Message-Id: <20201228194432.30512-6-shirik@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20201228194432.30512-1-shirik@nvidia.com> References: <20201228194432.30512-1-shirik@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 5/6] net/mlx5: add GTP PSC item translation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds the translation function which sets the qfi, PDU type. The next extension header which indicates the following extension header type is set to 0x85 - a PDU session container. Signed-off-by: Shiri Kuzin --- drivers/net/mlx5/mlx5_flow_dv.c | 85 +++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 3f6d44a265..7a85ad0887 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -7903,6 +7903,81 @@ flow_dv_translate_item_gtp(void *matcher, void *key, rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid)); } +/** + * Add GTP PSC item to matcher. + * + * @param[in, out] matcher + * Flow matcher. + * @param[in, out] key + * Flow matcher value. + * @param[in] item + * Flow pattern to translate. + */ +static int +flow_dv_translate_item_gtp_psc(void *matcher, void *key, + const struct rte_flow_item *item) +{ + const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask; + const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec; + void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher, + misc_parameters_3); + void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3); + union { + uint32_t w32; + struct { + uint16_t seq_num; + uint8_t npdu_num; + uint8_t next_ext_header_type; + }; + } dw_2; + uint8_t gtp_flags; + + /* Always set E-flag match on one, regardless of GTP item settings. */ + gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags); + gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG; + MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags); + gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags); + gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG; + MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags); + /*Set next extension header type. */ + dw_2.seq_num = 0; + dw_2.npdu_num = 0; + dw_2.next_ext_header_type = 0xff; + MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2, + rte_cpu_to_be_32(dw_2.w32)); + dw_2.seq_num = 0; + dw_2.npdu_num = 0; + dw_2.next_ext_header_type = 0x85; + MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2, + rte_cpu_to_be_32(dw_2.w32)); + if (gtp_psc_v) { + union { + uint32_t w32; + struct { + uint8_t len; + uint8_t pdu_type; + uint8_t qfi; + uint8_t reserved; + }; + } dw_0; + + /*Set extension header PDU type and Qos. */ + if (!gtp_psc_m) + gtp_psc_m = &rte_flow_item_gtp_psc_mask; + dw_0.w32 = 0; + dw_0.pdu_type = gtp_psc_m->pdu_type; + dw_0.qfi = gtp_psc_m->qfi; + MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0, + rte_cpu_to_be_32(dw_0.w32)); + dw_0.w32 = 0; + dw_0.pdu_type = gtp_psc_v->pdu_type & gtp_psc_m->pdu_type; + dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi; + MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0, + rte_cpu_to_be_32(dw_0.w32)); + } + return 0; +} + /** * Add eCPRI item to matcher and to the value. * @@ -10585,6 +10660,16 @@ flow_dv_translate(struct rte_eth_dev *dev, matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc); last_item = MLX5_FLOW_LAYER_GTP; break; + case RTE_FLOW_ITEM_TYPE_GTP_PSC: + ret = flow_dv_translate_item_gtp_psc(match_mask, + match_value, + items); + if (ret) + return rte_flow_error_set(error, -ret, + RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "cannot create GTP PSC item"); + last_item = MLX5_FLOW_LAYER_GTP_PSC; + break; case RTE_FLOW_ITEM_TYPE_ECPRI: if (!mlx5_flex_parser_ecpri_exist(dev)) { /* Create it only the first time to be used. */ From patchwork Mon Dec 28 19:44:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiri Kuzin X-Patchwork-Id: 85851 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C48E2A09FF; Mon, 28 Dec 2020 20:46:32 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 914FDCA44; Mon, 28 Dec 2020 20:45:04 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 625DDCA42 for ; Mon, 28 Dec 2020 20:45:02 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from shirik@nvidia.com) with SMTP; 28 Dec 2020 21:44:57 +0200 Received: from nvidia.com (c-236-148-180-183.mtl.labs.mlnx [10.236.148.183]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BSJicFc018969; Mon, 28 Dec 2020 21:44:57 +0200 From: Shiri Kuzin To: dev@dpdk.org Cc: viacheslavo@nvidia.com, adrien.mazarguil@6wind.com, orika@nvidia.com, ferruh.yigit@intel.com, thomas@monjalon.net, rasland@nvidia.com Date: Mon, 28 Dec 2020 21:44:32 +0200 Message-Id: <20201228194432.30512-7-shirik@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20201228194432.30512-1-shirik@nvidia.com> References: <20201228194432.30512-1-shirik@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 6/6] doc: update GTP extension header support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" added GTP extension header support to mlx5 PMD. The limitations and support were updated in documentation. Signed-off-by: Shiri Kuzin --- doc/guides/nics/mlx5.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 3bda0f8417..3b1a08f40a 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -98,6 +98,7 @@ Features - Hardware LRO. - Hairpin. - Multiple-thread flow insertion. +- Matching on GTP extension header with raw encap/decap action. Limitations ----------- @@ -186,6 +187,10 @@ Limitations - msg_type - teid +- Match on GTP extension header only for GTP PDU session container (next + extension header type = 0x85). +- Match on GTP extension header is not supported in group 0. + - No Tx metadata go to the E-Switch steering domain for the Flow group 0. The flows within group 0 and set metadata action are rejected by hardware.