From patchwork Mon Mar 29 05:49:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alvin Zhang X-Patchwork-Id: 89996 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 424DAA034F; Mon, 29 Mar 2021 07:49:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 29CA340151; Mon, 29 Mar 2021 07:49:32 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id CC7C940042 for ; Mon, 29 Mar 2021 07:49:29 +0200 (CEST) IronPort-SDR: RaDvdeLa4ndrJzySS23MLeh1JlwvcmuOe6fnuL2dBrPlpHGZZ3i7e6r16M0eUVmavhl4WPVgA+ bXrrYYSWW5tw== X-IronPort-AV: E=McAfee;i="6000,8403,9937"; a="211675867" X-IronPort-AV: E=Sophos;i="5.81,285,1610438400"; d="scan'208";a="211675867" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Mar 2021 22:49:28 -0700 IronPort-SDR: MOS9pCE5s+sZthnW7pCq6/AzOjeMvpQtb9kdabDz6Xxv6gc4PukDJymsRWRJ6xE5HlUWlPjGZy Eca7eP0nNkRQ== X-IronPort-AV: E=Sophos;i="5.81,285,1610438400"; d="scan'208";a="444413043" Received: from shwdenpg235.ccr.corp.intel.com ([10.240.182.60]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Mar 2021 22:49:27 -0700 From: Alvin Zhang To: qiming.yang@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org Date: Mon, 29 Mar 2021 13:49:23 +0800 Message-Id: <20210329054923.11424-1-alvinx.zhang@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH] net/ice/base: support MPLS ethertype switch filter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add MPLS training packet and offsets. Add check if the type is MPLS for ethertype filters. For example: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 type is 0x8847 / end actions queue index 2 / end This flow will result in all the matched ingress packets be forwarded to queue 2. Signed-off-by: Alvin Zhang --- drivers/net/ice/base/ice_switch.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 3dc7642..5a64cb7 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -15,6 +15,7 @@ #define ICE_IPV6_ETHER_ID 0x86DD #define ICE_TCP_PROTO_ID 0x06 #define ICE_ETH_P_8021Q 0x8100 +#define ICE_MPLS_ETHER_ID 0x8847 /* Dummy ethernet header needed in the ice_aqc_sw_rules_elem * struct to configure any switch filter rules. @@ -319,6 +320,25 @@ struct ice_dummy_pkt_offsets { 0x00, 0x00, /* 2 bytes for 4 byte alignment */ }; +/* offset info for MAC + MPLS dummy packet */ +static const struct ice_dummy_pkt_offsets dummy_mpls_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +/* Dummy packet for MAC + MPLS */ +static const u8 dummy_mpls_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x88, 0x47, /* ICE_ETYPE_OL 12 */ + 0x00, 0x00, 0x01, 0x00, + + 0x00, 0x00, /* 2 bytes for 4 byte alignment */ +}; + /* offset info for MAC + VLAN (C-tag, 802.1Q) + IPv4 + TCP dummy packet */ static const struct ice_dummy_pkt_offsets dummy_vlan_tcp_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, @@ -7727,7 +7747,7 @@ bool ice_is_prof_rule(enum ice_sw_tunnel_type type) const struct ice_dummy_pkt_offsets **offsets) { bool tcp = false, udp = false, ipv6 = false, vlan = false; - bool gre = false; + bool gre = false, mpls = false; u16 i; for (i = 0; i < lkups_cnt; i++) { @@ -7763,6 +7783,11 @@ bool ice_is_prof_rule(enum ice_sw_tunnel_type type) lkups[i].m_u.ipv4_hdr.protocol == 0xFF) tcp = true; + else if (lkups[i].type == ICE_ETYPE_OL && + lkups[i].h_u.ethertype.ethtype_id == + CPU_TO_BE16(ICE_MPLS_ETHER_ID) && + lkups[i].m_u.ethertype.ethtype_id == 0xFFFF) + mpls = true; } if ((tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ || @@ -8058,6 +8083,10 @@ bool ice_is_prof_rule(enum ice_sw_tunnel_type type) *pkt = dummy_vlan_tcp_packet; *pkt_len = sizeof(dummy_vlan_tcp_packet); *offsets = dummy_vlan_tcp_packet_offsets; + } else if (mpls) { + *pkt = dummy_mpls_packet; + *pkt_len = sizeof(dummy_mpls_packet); + *offsets = dummy_mpls_packet_offsets; } else { *pkt = dummy_tcp_packet; *pkt_len = sizeof(dummy_tcp_packet);