From patchwork Thu Apr 15 19:10:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shijith Thotton X-Patchwork-Id: 91601 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DB111A0C3F; Thu, 15 Apr 2021 21:10:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 36CA616242C; Thu, 15 Apr 2021 21:10:36 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3BB55162425 for ; Thu, 15 Apr 2021 21:10:34 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 13FItmgD008750 for ; Thu, 15 Apr 2021 12:10:33 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=77H4NOkgY7DIxKB+JhS2yy2RW2BBcvkgIh65xKLz/sA=; b=QVWKbSgJm6EMnu3NGvyJZ0nWf7jHUprz76CAs0oMvKI0bUv1VoENhIiALe2TKPHdG8Fo UasuOKkQRyb4M4HXv79kiqI79fjQxpD/qFwu0RtZRoH1tG1adgsmDZF2o9oa7SuWSaFe qo5PalU38CPzQAVWahal9qmaX5isXylIPt5JeMkTiwC1StsMQHXbslOD4lx2VkCFB4lZ 4BrOqzPl7w0ckiPnjscMEszH0zj5W1LiZ/xGDkX/gEtfq4bv01nXUsVipV5t7UBjDXZj DuoD6QtNVvA2MYVQDhOW5SwlBCPjL/8YDoIbnpio402Oq492mm9jg7PGYO68TMkUBS7O Zg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 37xcn4u32h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 15 Apr 2021 12:10:33 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 15 Apr 2021 12:10:32 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 15 Apr 2021 12:10:32 -0700 Received: from localhost.localdomain (unknown [10.28.34.29]) by maili.marvell.com (Postfix) with ESMTP id C6ED83F7044; Thu, 15 Apr 2021 12:10:29 -0700 (PDT) From: Shijith Thotton To: CC: Shijith Thotton , Jerin Jacob , Akhil Goyal , Anoob Joseph , "Ankur Dwivedi" , Pavan Nikhilesh Date: Fri, 16 Apr 2021 00:40:14 +0530 Message-ID: <41acb2e28e28cb765dff41b1a3c6388f1e7e2d56.1618513149.git.sthotton@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: pi56Rk_19GdSW9DwOxRcZLzxK5JW02y5 X-Proofpoint-GUID: pi56Rk_19GdSW9DwOxRcZLzxK5JW02y5 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-15_09:2021-04-15, 2021-04-15 signatures=0 Subject: [dpdk-dev] [PATCH v1 1/2] event/octeontx2: fix crypto adapter queue pair ops X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Parameter queue_pair_id of crypto adapter queue pair add/del operation can be -1 to select all pre configured crypto queue pairs. Added support for the same in driver. Also added a member in cpt qp structure to indicate binding state of a queue pair to an event queue. Fixes: 29768f78d5a7 ("event/octeontx2: add crypto adapter framework") Signed-off-by: Shijith Thotton --- drivers/crypto/octeontx2/otx2_cryptodev_qp.h | 4 +- .../event/octeontx2/otx2_evdev_crypto_adptr.c | 102 ++++++++++++------ 2 files changed, 75 insertions(+), 31 deletions(-) diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h index 189fa3db4..95bce3621 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright (C) 2020 Marvell International Ltd. + * Copyright (C) 2020-2021 Marvell. */ #ifndef _OTX2_CRYPTODEV_QP_H_ @@ -39,6 +39,8 @@ struct otx2_cpt_qp { */ uint8_t ca_enable; /**< Set when queue pair is added to crypto adapter */ + uint8_t qp_ev_bind; + /**< Set when queue pair is bound to event queue */ }; #endif /* _OTX2_CRYPTODEV_QP_H_ */ diff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c index 4e8a96cb6..3a96b2e34 100644 --- a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c +++ b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright (C) 2020 Marvell International Ltd. + * Copyright (C) 2020-2021 Marvell. */ #include #include +#include "otx2_cryptodev.h" #include "otx2_cryptodev_hw_access.h" #include "otx2_cryptodev_qp.h" #include "otx2_cryptodev_mbox.h" @@ -23,30 +24,66 @@ otx2_ca_caps_get(const struct rte_eventdev *dev, return 0; } -int -otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev, - int32_t queue_pair_id, const struct rte_event *event) +static int +otx2_ca_qp_sso_link(const struct rte_cryptodev *cdev, struct otx2_cpt_qp *qp, + uint16_t sso_pf_func) { - struct otx2_sso_evdev *sso_evdev = sso_pmd_priv(dev); union otx2_cpt_af_lf_ctl2 af_lf_ctl2; - struct otx2_cpt_qp *qp; int ret; - qp = cdev->data->queue_pairs[queue_pair_id]; - - qp->ca_enable = 1; - rte_memcpy(&qp->ev, event, sizeof(struct rte_event)); - ret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id), - qp->blkaddr, &af_lf_ctl2.u); + qp->blkaddr, &af_lf_ctl2.u); if (ret) return ret; - af_lf_ctl2.s.sso_pf_func = otx2_sso_pf_func_get(); + af_lf_ctl2.s.sso_pf_func = sso_pf_func; ret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id), - qp->blkaddr, af_lf_ctl2.u); - if (ret) - return ret; + qp->blkaddr, af_lf_ctl2.u); + return ret; +} + +static void +otx2_ca_qp_init(struct otx2_cpt_qp *qp, const struct rte_event *event) +{ + if (event) { + qp->qp_ev_bind = 1; + rte_memcpy(&qp->ev, event, sizeof(struct rte_event)); + } else { + qp->qp_ev_bind = 0; + } + qp->ca_enable = 1; +} + +int +otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev, + int32_t queue_pair_id, const struct rte_event *event) +{ + struct otx2_sso_evdev *sso_evdev = sso_pmd_priv(dev); + struct otx2_cpt_vf *vf = cdev->data->dev_private; + uint16_t sso_pf_func = otx2_sso_pf_func_get(); + struct otx2_cpt_qp *qp; + uint8_t qp_id; + int ret; + + if (queue_pair_id == -1) { + for (qp_id = 0; qp_id < vf->nb_queues; qp_id++) { + qp = cdev->data->queue_pairs[qp_id]; + ret = otx2_ca_qp_sso_link(cdev, qp, sso_pf_func); + if (ret) { + uint8_t qp_tmp; + for (qp_tmp = 0; qp_tmp < qp_id; qp_tmp++) + otx2_ca_qp_del(dev, cdev, qp_tmp); + return ret; + } + otx2_ca_qp_init(qp, event); + } + } else { + qp = cdev->data->queue_pairs[queue_pair_id]; + ret = otx2_ca_qp_sso_link(cdev, qp, sso_pf_func); + if (ret) + return ret; + otx2_ca_qp_init(qp, event); + } sso_evdev->rx_offloads |= NIX_RX_OFFLOAD_SECURITY_F; sso_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)dev); @@ -58,24 +95,29 @@ int otx2_ca_qp_del(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev, int32_t queue_pair_id) { - union otx2_cpt_af_lf_ctl2 af_lf_ctl2; + struct otx2_cpt_vf *vf = cdev->data->dev_private; struct otx2_cpt_qp *qp; + uint8_t qp_id; int ret; RTE_SET_USED(dev); - qp = cdev->data->queue_pairs[queue_pair_id]; - qp->ca_enable = 0; - memset(&qp->ev, 0, sizeof(struct rte_event)); + ret = 0; + if (queue_pair_id == -1) { + for (qp_id = 0; qp_id < vf->nb_queues; qp_id++) { + qp = cdev->data->queue_pairs[qp_id]; + ret = otx2_ca_qp_sso_link(cdev, qp, 0); + if (ret) + return ret; + qp->ca_enable = 0; + } + } else { + qp = cdev->data->queue_pairs[queue_pair_id]; + ret = otx2_ca_qp_sso_link(cdev, qp, 0); + if (ret) + return ret; + qp->ca_enable = 0; + } - ret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id), - qp->blkaddr, &af_lf_ctl2.u); - if (ret) - return ret; - - af_lf_ctl2.s.sso_pf_func = 0; - ret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id), - qp->blkaddr, af_lf_ctl2.u); - - return ret; + return 0; } From patchwork Thu Apr 15 19:10:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shijith Thotton X-Patchwork-Id: 91602 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C5D18A0C3F; Thu, 15 Apr 2021 21:10:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6A7FA162435; Thu, 15 Apr 2021 21:10:38 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id F073A162431 for ; Thu, 15 Apr 2021 21:10:36 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 13FItZbn021225 for ; Thu, 15 Apr 2021 12:10:36 -0700 DKIM-Signature: v=1; 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Thu, 15 Apr 2021 12:10:34 -0700 Received: from localhost.localdomain (unknown [10.28.34.29]) by maili.marvell.com (Postfix) with ESMTP id 523953F7048; Thu, 15 Apr 2021 12:10:32 -0700 (PDT) From: Shijith Thotton To: CC: Shijith Thotton , Jerin Jacob , Akhil Goyal , Anoob Joseph , "Ankur Dwivedi" , Pavan Nikhilesh Date: Fri, 16 Apr 2021 00:40:15 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: R8uYX-_wqqL48kWhWRL1iAi2f13W2rtd X-Proofpoint-GUID: R8uYX-_wqqL48kWhWRL1iAi2f13W2rtd X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-15_09:2021-04-15, 2021-04-15 signatures=0 Subject: [dpdk-dev] [PATCH v1 2/2] event/octeontx2: configure crypto adapter xaq pool X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Configure xaq pool based on number of in-use crypto queues to avoid CPT add work failure due to xaq buffer run out. This patch configures OTX2_CPT_DEFAULT_CMD_QLEN number of xae entries per queue pair. Fixes: 29768f78d5a7 ("event/octeontx2: add crypto adapter framework") Signed-off-by: Shijith Thotton Acked-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_evdev_adptr.c | 2 +- drivers/event/octeontx2/otx2_evdev_crypto_adptr.c | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/event/octeontx2/otx2_evdev_adptr.c b/drivers/event/octeontx2/otx2_evdev_adptr.c index d69f269df..d85c3665c 100644 --- a/drivers/event/octeontx2/otx2_evdev_adptr.c +++ b/drivers/event/octeontx2/otx2_evdev_adptr.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(C) 2019 Marvell International Ltd. + * Copyright(C) 2019-2021 Marvell. */ #include "otx2_evdev.h" diff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c index 3a96b2e34..79a6d5577 100644 --- a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c +++ b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c @@ -88,6 +88,14 @@ otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev, sso_evdev->rx_offloads |= NIX_RX_OFFLOAD_SECURITY_F; sso_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)dev); + /* Update crypto adapter xae count */ + if (queue_pair_id == -1) + sso_evdev->adptr_xae_cnt = + vf->nb_queues * OTX2_CPT_DEFAULT_CMD_QLEN; + else + sso_evdev->adptr_xae_cnt += OTX2_CPT_DEFAULT_CMD_QLEN; + sso_xae_reconfigure((struct rte_eventdev *)(uintptr_t)dev); + return 0; }