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[89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:11 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, stable@dpdk.org, Michal Krawczyk , Artur Rojek Date: Tue, 11 May 2021 08:45:36 +0200 Message-Id: <20210511064554.10656-2-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 01/19] net/ena: switch memcpy to dpdk-optimized version X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Igor Chauskin memcpy is now mapped to rte_memcpy macro on x86 architectures. Fixes: 9ba7981ec992 ("ena: add communication layer for DPDK") Cc: stable@dpdk.org Signed-off-by: Igor Chauskin Reviewed-by: Michal Krawczyk Reviewed-by: Artur Rojek --- v4: * Add release notes v2: * Fix nested declaration of the rte_memcpy on arm64 architecture. doc/guides/rel_notes/release_21_05.rst | 7 +++++++ drivers/net/ena/base/ena_plat_dpdk.h | 7 ++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index 30dec1c1d1..eb1107729a 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -202,6 +202,13 @@ New Features Added packed ring support for async vhost. +* **Updated Amazon ENA PMD.** + + The new driver version (v2.3.0) introduces bug fixes and improvements, + including: + + * Changed memcpy mapping to the dpdk-optimized version. + * **Added support of multiple data-units in cryptodev API.** The cryptodev library has been enhanced to allow operations on multiple diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index a1d749f83f..ae68f860a5 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -25,6 +25,7 @@ #include #include +#include typedef uint64_t u64; typedef uint32_t u32; @@ -62,7 +63,11 @@ typedef uint64_t dma_addr_t; #define ENA_UDELAY(x) rte_delay_us_block(x) #define ENA_TOUCH(x) ((void)(x)) -#define memcpy_toio memcpy +/* Avoid nested declaration on arm64, as it may define rte_memcpy as memcpy. */ +#if defined(RTE_ARCH_X86) +#undef memcpy +#define memcpy rte_memcpy +#endif #define wmb rte_wmb #define rmb rte_rmb #define mb rte_mb From patchwork Tue May 11 06:45:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93130 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D5693A0C41; Tue, 11 May 2021 08:46:25 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 986CF410ED; Tue, 11 May 2021 08:46:16 +0200 (CEST) Received: from mail-lf1-f46.google.com (mail-lf1-f46.google.com [209.85.167.46]) by mails.dpdk.org (Postfix) with ESMTP id 7367E410FE for ; Tue, 11 May 2021 08:46:13 +0200 (CEST) Received: by mail-lf1-f46.google.com with SMTP id z9so27017511lfu.8 for ; Mon, 10 May 2021 23:46:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iOj5HAkZjqQwDmJE/xl+ihCnHHirGbFSersJIIzN0co=; b=RC8R5xigflE+29LKF97H/N2NIMuqoaVTvOLUfEQLOxfErI6FyJLytpeIYjmSplq+aM WX0t5LBw71gyVGzk+spIpgZDn/nBJPnZlKTRnZ77FGovE7P6S9122eRE6PRjXWXze2W3 dITgZoyE5gTNb7WH31bocUtx6ZRORWgwbq9LEb+SFVSFvYOaB5OiHrDuSfULAe6AP3Tb oQ5uQbgltULsr7xBlOuHj20JBHO7gnF8zSj4aM30HVIy15fd6zO87qti7CLHUhXDsUWi iQqJu9tljuJFB7WyflkSrB8RDcALmPzY6PIGWS3SIB8O0KWFZURuo4fxDE4f4YseDlvM naaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iOj5HAkZjqQwDmJE/xl+ihCnHHirGbFSersJIIzN0co=; b=EcWEZPXzRGz2lsacWesWgXzQ8ehMb82fmZaOxkdQ43WVUAw/DRtJHnGAnx8RcusR7f 2p5dq/OeUCvan59kiwmXG+m3QUVgIcMR0eG6cIp6afc+8RtG41VQXiKDydDfv2vlUrJF HymyeMK+kqwTph4bux46G6ZL9OmfyNn6CeGOhElFmXNbtgYkbpnxbqKTn4x9fsCDWE+B hPBLWbhmr3Vu7aWdglFfuiz1fKrcpOGFnfncs8GB4F/kCpGKkjVR+5E1epS9dlNXxN6+ lxYpSlyLdWmeeHpbIJz6Lf2EUCg8ANtB2guautVVH+5Sz5rTn2lMsi/hahmtwm0Sa33o 0QXQ== X-Gm-Message-State: AOAM533f3ydXuXNoY3ujKjh2IgLTYHJo5tziHU4TKcH66faznQ/AkZWi ZRX0p29guazUDU0m2+vYswvhJ0Btt693NLH5 X-Google-Smtp-Source: ABdhPJx5fwyhYgS4wK7NFBmNBZ6QKYGGn1qXAipCUo8sV9vIqD2dwrXZWzFWj+JZG3MMzHfES9cUhw== X-Received: by 2002:ac2:555e:: with SMTP id l30mr19201265lfk.199.1620715573088; Mon, 10 May 2021 23:46:13 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:12 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk Date: Tue, 11 May 2021 08:45:37 +0200 Message-Id: <20210511064554.10656-3-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 02/19] net/ena/base: unify arg names for the functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Instead of using 'queue' for struct ena_com_admin_queue and 'dev' for struct ena_com_dev variables, use more descriptive 'admin_queue' and 'ena_dev'. This also unifies the names of variables of the type struct ena_com_dev in the driver. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- v4: * Add release notes doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/ena/base/ena_com.c | 74 +++++++++++++------------- drivers/net/ena/base/ena_com.h | 2 +- 3 files changed, 39 insertions(+), 38 deletions(-) diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index eb1107729a..6e4fcde1bc 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -208,6 +208,7 @@ New Features including: * Changed memcpy mapping to the dpdk-optimized version. + * Updated ena_com (HAL) to the latest version. * **Added support of multiple data-units in cryptodev API.** diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index aae68721fb..f7258254a5 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -80,12 +80,12 @@ static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, return 0; } -static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue) +static int ena_com_admin_init_sq(struct ena_com_admin_queue *admin_queue) { - struct ena_com_admin_sq *sq = &queue->sq; - u16 size = ADMIN_SQ_SIZE(queue->q_depth); + struct ena_com_admin_sq *sq = &admin_queue->sq; + u16 size = ADMIN_SQ_SIZE(admin_queue->q_depth); - ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, sq->entries, sq->dma_addr, + ENA_MEM_ALLOC_COHERENT(admin_queue->q_dmadev, size, sq->entries, sq->dma_addr, sq->mem_handle); if (!sq->entries) { @@ -102,12 +102,12 @@ static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue) return 0; } -static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue) +static int ena_com_admin_init_cq(struct ena_com_admin_queue *admin_queue) { - struct ena_com_admin_cq *cq = &queue->cq; - u16 size = ADMIN_CQ_SIZE(queue->q_depth); + struct ena_com_admin_cq *cq = &admin_queue->cq; + u16 size = ADMIN_CQ_SIZE(admin_queue->q_depth); - ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, cq->entries, cq->dma_addr, + ENA_MEM_ALLOC_COHERENT(admin_queue->q_dmadev, size, cq->entries, cq->dma_addr, cq->mem_handle); if (!cq->entries) { @@ -121,16 +121,16 @@ static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue) return 0; } -static int ena_com_admin_init_aenq(struct ena_com_dev *dev, +static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev, struct ena_aenq_handlers *aenq_handlers) { - struct ena_com_aenq *aenq = &dev->aenq; + struct ena_com_aenq *aenq = &ena_dev->aenq; u32 addr_low, addr_high, aenq_caps; u16 size; - dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH; + ena_dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH; size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH); - ENA_MEM_ALLOC_COHERENT(dev->dmadev, size, + ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, size, aenq->entries, aenq->dma_addr, aenq->mem_handle); @@ -146,15 +146,15 @@ static int ena_com_admin_init_aenq(struct ena_com_dev *dev, addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr); addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr); - ENA_REG_WRITE32(dev->bus, addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF); - ENA_REG_WRITE32(dev->bus, addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF); + ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF); + ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF); aenq_caps = 0; - aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK; + aenq_caps |= ena_dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK; aenq_caps |= (sizeof(struct ena_admin_aenq_entry) << ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) & ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK; - ENA_REG_WRITE32(dev->bus, aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF); + ENA_REG_WRITE32(ena_dev->bus, aenq_caps, ena_dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF); if (unlikely(!aenq_handlers)) { ena_trc_err("aenq handlers pointer is NULL\n"); @@ -173,31 +173,31 @@ static void comp_ctxt_release(struct ena_com_admin_queue *queue, ATOMIC32_DEC(&queue->outstanding_cmds); } -static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue, +static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *admin_queue, u16 command_id, bool capture) { - if (unlikely(command_id >= queue->q_depth)) { + if (unlikely(command_id >= admin_queue->q_depth)) { ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n", - command_id, queue->q_depth); + command_id, admin_queue->q_depth); return NULL; } - if (unlikely(!queue->comp_ctx)) { + if (unlikely(!admin_queue->comp_ctx)) { ena_trc_err("Completion context is NULL\n"); return NULL; } - if (unlikely(queue->comp_ctx[command_id].occupied && capture)) { + if (unlikely(admin_queue->comp_ctx[command_id].occupied && capture)) { ena_trc_err("Completion context is occupied\n"); return NULL; } if (capture) { - ATOMIC32_INC(&queue->outstanding_cmds); - queue->comp_ctx[command_id].occupied = true; + ATOMIC32_INC(&admin_queue->outstanding_cmds); + admin_queue->comp_ctx[command_id].occupied = true; } - return &queue->comp_ctx[command_id]; + return &admin_queue->comp_ctx[command_id]; } static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue, @@ -260,20 +260,20 @@ static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queu return comp_ctx; } -static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue) +static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *admin_queue) { - size_t size = queue->q_depth * sizeof(struct ena_comp_ctx); + size_t size = admin_queue->q_depth * sizeof(struct ena_comp_ctx); struct ena_comp_ctx *comp_ctx; u16 i; - queue->comp_ctx = ENA_MEM_ALLOC(queue->q_dmadev, size); - if (unlikely(!queue->comp_ctx)) { + admin_queue->comp_ctx = ENA_MEM_ALLOC(admin_queue->q_dmadev, size); + if (unlikely(!admin_queue->comp_ctx)) { ena_trc_err("memory allocation failed\n"); return ENA_COM_NO_MEM; } - for (i = 0; i < queue->q_depth; i++) { - comp_ctx = get_comp_ctxt(queue, i, false); + for (i = 0; i < admin_queue->q_depth; i++) { + comp_ctx = get_comp_ctxt(admin_queue, i, false); if (comp_ctx) ENA_WAIT_EVENT_INIT(comp_ctx->wait_event); } @@ -2049,10 +2049,10 @@ void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev) /* ena_handle_specific_aenq_event: * return the handler that is relevant to the specific event group */ -static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev, +static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *ena_dev, u16 group) { - struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers; + struct ena_aenq_handlers *aenq_handlers = ena_dev->aenq.aenq_handlers; if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group]) return aenq_handlers->handlers[group]; @@ -2064,11 +2064,11 @@ static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev, * handles the aenq incoming events. * pop events from the queue and apply the specific handler */ -void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data) +void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data) { struct ena_admin_aenq_entry *aenq_e; struct ena_admin_aenq_common_desc *aenq_common; - struct ena_com_aenq *aenq = &dev->aenq; + struct ena_com_aenq *aenq = &ena_dev->aenq; u64 timestamp; ena_aenq_handler handler_cb; u16 masked_head, processed = 0; @@ -2096,7 +2096,7 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data) timestamp); /* Handle specific event*/ - handler_cb = ena_com_get_specific_aenq_cb(dev, + handler_cb = ena_com_get_specific_aenq_cb(ena_dev, aenq_common->group); handler_cb(data, aenq_e); /* call the actual event handler*/ @@ -2121,8 +2121,8 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data) /* write the aenq doorbell after all AENQ descriptors were read */ mb(); - ENA_REG_WRITE32_RELAXED(dev->bus, (u32)aenq->head, - dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); + ENA_REG_WRITE32_RELAXED(ena_dev->bus, (u32)aenq->head, + ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); mmiowb(); } diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h index 64d8f247cb..e9601b1a8e 100644 --- a/drivers/net/ena/base/ena_com.h +++ b/drivers/net/ena/base/ena_com.h @@ -522,7 +522,7 @@ void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev); * This method goes over the async event notification queue and calls the proper * aenq handler. */ -void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data); +void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data); /* ena_com_abort_admin_commands - Abort all the outstanding admin commands. * @ena_dev: ENA communication layer struct From patchwork Tue May 11 06:45:38 2021 Content-Type: text/plain; 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[89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:13 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk Date: Tue, 11 May 2021 08:45:38 +0200 Message-Id: <20210511064554.10656-4-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 03/19] net/ena/base: add dev arg to the logging macros X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Some platforms may make use of the device argument to make the logs more verbose and specific for the appropriate device. As it's not used by the ENA DPDK PMD for the logging, the type is just defined, but never used. It may be reconsidered to change this in the future by adding port ID to the message logs, but as for now the logging behavior won't change. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- v4: * Fix checkpatch warning regarding line length. v3: * Fix ena_trc_log macro, by adding missing '\' and removing extra ')'. drivers/net/ena/base/ena_com.c | 238 ++++++++++++++------------- drivers/net/ena/base/ena_com.h | 21 +++ drivers/net/ena/base/ena_eth_com.c | 78 ++++++--- drivers/net/ena/base/ena_eth_com.h | 17 +- drivers/net/ena/base/ena_plat_dpdk.h | 45 ++--- 5 files changed, 237 insertions(+), 162 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index f7258254a5..9931819bbb 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -70,7 +70,7 @@ static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, dma_addr_t addr) { if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) { - ena_trc_err("dma address has more bits that the device supports\n"); + ena_trc_err(ena_dev, "DMA address has more bits than the device supports\n"); return ENA_COM_INVAL; } @@ -82,6 +82,7 @@ static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, static int ena_com_admin_init_sq(struct ena_com_admin_queue *admin_queue) { + struct ena_com_dev *ena_dev = admin_queue->ena_dev; struct ena_com_admin_sq *sq = &admin_queue->sq; u16 size = ADMIN_SQ_SIZE(admin_queue->q_depth); @@ -89,7 +90,7 @@ static int ena_com_admin_init_sq(struct ena_com_admin_queue *admin_queue) sq->mem_handle); if (!sq->entries) { - ena_trc_err("memory allocation failed\n"); + ena_trc_err(ena_dev, "Memory allocation failed\n"); return ENA_COM_NO_MEM; } @@ -104,6 +105,7 @@ static int ena_com_admin_init_sq(struct ena_com_admin_queue *admin_queue) static int ena_com_admin_init_cq(struct ena_com_admin_queue *admin_queue) { + struct ena_com_dev *ena_dev = admin_queue->ena_dev; struct ena_com_admin_cq *cq = &admin_queue->cq; u16 size = ADMIN_CQ_SIZE(admin_queue->q_depth); @@ -111,7 +113,7 @@ static int ena_com_admin_init_cq(struct ena_com_admin_queue *admin_queue) cq->mem_handle); if (!cq->entries) { - ena_trc_err("memory allocation failed\n"); + ena_trc_err(ena_dev, "Memory allocation failed\n"); return ENA_COM_NO_MEM; } @@ -136,7 +138,7 @@ static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev, aenq->mem_handle); if (!aenq->entries) { - ena_trc_err("memory allocation failed\n"); + ena_trc_err(ena_dev, "Memory allocation failed\n"); return ENA_COM_NO_MEM; } @@ -157,7 +159,7 @@ static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev, ENA_REG_WRITE32(ena_dev->bus, aenq_caps, ena_dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF); if (unlikely(!aenq_handlers)) { - ena_trc_err("aenq handlers pointer is NULL\n"); + ena_trc_err(ena_dev, "AENQ handlers pointer is NULL\n"); return ENA_COM_INVAL; } @@ -177,18 +179,21 @@ static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *admin_queu u16 command_id, bool capture) { if (unlikely(command_id >= admin_queue->q_depth)) { - ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n", + ena_trc_err(admin_queue->ena_dev, + "Command id is larger than the queue size. cmd_id: %u queue size %d\n", command_id, admin_queue->q_depth); return NULL; } if (unlikely(!admin_queue->comp_ctx)) { - ena_trc_err("Completion context is NULL\n"); + ena_trc_err(admin_queue->ena_dev, + "Completion context is NULL\n"); return NULL; } if (unlikely(admin_queue->comp_ctx[command_id].occupied && capture)) { - ena_trc_err("Completion context is occupied\n"); + ena_trc_err(admin_queue->ena_dev, + "Completion context is occupied\n"); return NULL; } @@ -218,7 +223,7 @@ static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queu /* In case of queue FULL */ cnt = (u16)ATOMIC32_READ(&admin_queue->outstanding_cmds); if (cnt >= admin_queue->q_depth) { - ena_trc_dbg("admin queue is full.\n"); + ena_trc_dbg(admin_queue->ena_dev, "Admin queue is full.\n"); admin_queue->stats.out_of_space++; return ERR_PTR(ENA_COM_NO_SPACE); } @@ -262,13 +267,14 @@ static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queu static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *admin_queue) { + struct ena_com_dev *ena_dev = admin_queue->ena_dev; size_t size = admin_queue->q_depth * sizeof(struct ena_comp_ctx); struct ena_comp_ctx *comp_ctx; u16 i; admin_queue->comp_ctx = ENA_MEM_ALLOC(admin_queue->q_dmadev, size); if (unlikely(!admin_queue->comp_ctx)) { - ena_trc_err("memory allocation failed\n"); + ena_trc_err(ena_dev, "Memory allocation failed\n"); return ENA_COM_NO_MEM; } @@ -341,7 +347,7 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev, } if (!io_sq->desc_addr.virt_addr) { - ena_trc_err("memory allocation failed\n"); + ena_trc_err(ena_dev, "Memory allocation failed\n"); return ENA_COM_NO_MEM; } } @@ -366,7 +372,7 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev, io_sq->bounce_buf_ctrl.base_buffer = ENA_MEM_ALLOC(ena_dev->dmadev, size); if (!io_sq->bounce_buf_ctrl.base_buffer) { - ena_trc_err("bounce buffer memory allocation failed\n"); + ena_trc_err(ena_dev, "Bounce buffer memory allocation failed\n"); return ENA_COM_NO_MEM; } @@ -431,7 +437,7 @@ static int ena_com_init_io_cq(struct ena_com_dev *ena_dev, } if (!io_cq->cdesc_addr.virt_addr) { - ena_trc_err("memory allocation failed\n"); + ena_trc_err(ena_dev, "Memory allocation failed\n"); return ENA_COM_NO_MEM; } @@ -452,7 +458,8 @@ static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *a comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false); if (unlikely(!comp_ctx)) { - ena_trc_err("comp_ctx is NULL. Changing the admin queue running state\n"); + ena_trc_err(admin_queue->ena_dev, + "comp_ctx is NULL. Changing the admin queue running state\n"); admin_queue->running_state = false; return; } @@ -504,10 +511,12 @@ static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_qu admin_queue->stats.completed_cmd += comp_num; } -static int ena_com_comp_status_to_errno(u8 comp_status) +static int ena_com_comp_status_to_errno(struct ena_com_admin_queue *admin_queue, + u8 comp_status) { if (unlikely(comp_status != 0)) - ena_trc_err("admin command failed[%u]\n", comp_status); + ena_trc_err(admin_queue->ena_dev, + "Admin command failed[%u]\n", comp_status); switch (comp_status) { case ENA_ADMIN_SUCCESS: @@ -554,7 +563,8 @@ static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_c break; if (ENA_TIME_EXPIRE(timeout)) { - ena_trc_err("Wait for completion (polling) timeout\n"); + ena_trc_err(admin_queue->ena_dev, + "Wait for completion (polling) timeout\n"); /* ENA didn't have any completion */ ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); admin_queue->stats.no_completion++; @@ -570,7 +580,7 @@ static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_c } if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) { - ena_trc_err("Command was aborted\n"); + ena_trc_err(admin_queue->ena_dev, "Command was aborted\n"); ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); admin_queue->stats.aborted_cmd++; ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); @@ -579,9 +589,10 @@ static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_c } ENA_WARN(comp_ctx->status != ENA_CMD_COMPLETED, - "Invalid comp status %d\n", comp_ctx->status); + admin_queue->ena_dev, "Invalid comp status %d\n", + comp_ctx->status); - ret = ena_com_comp_status_to_errno(comp_ctx->comp_status); + ret = ena_com_comp_status_to_errno(admin_queue, comp_ctx->comp_status); err: comp_ctxt_release(admin_queue, comp_ctx); return ret; @@ -623,7 +634,7 @@ static int ena_com_set_llq(struct ena_com_dev *ena_dev) sizeof(resp)); if (unlikely(ret)) - ena_trc_err("Failed to set LLQ configurations: %d\n", ret); + ena_trc_err(ena_dev, "Failed to set LLQ configurations: %d\n", ret); return ret; } @@ -645,7 +656,7 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, llq_info->header_location_ctrl = llq_default_cfg->llq_header_location; } else { - ena_trc_err("Invalid header location control, supported: 0x%x\n", + ena_trc_err(ena_dev, "Invalid header location control, supported: 0x%x\n", supported_feat); return -EINVAL; } @@ -660,12 +671,12 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) { llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY; } else { - ena_trc_err("Invalid desc_stride_ctrl, supported: 0x%x\n", + ena_trc_err(ena_dev, "Invalid desc_stride_ctrl, supported: 0x%x\n", supported_feat); return -EINVAL; } - ena_trc_err("Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", + ena_trc_err(ena_dev, "Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", llq_default_cfg->llq_stride_ctrl, supported_feat, llq_info->desc_stride_ctrl); @@ -689,11 +700,12 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B; llq_info->desc_list_entry_size = 256; } else { - ena_trc_err("Invalid entry_size_ctrl, supported: 0x%x\n", supported_feat); + ena_trc_err(ena_dev, "Invalid entry_size_ctrl, supported: 0x%x\n", + supported_feat); return -EINVAL; } - ena_trc_err("Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", + ena_trc_err(ena_dev, "Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", llq_default_cfg->llq_ring_entry_size, supported_feat, llq_info->desc_list_entry_size); @@ -702,7 +714,7 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, /* The desc list entry size should be whole multiply of 8 * This requirement comes from __iowrite64_copy() */ - ena_trc_err("illegal entry size %d\n", + ena_trc_err(ena_dev, "Illegal entry size %d\n", llq_info->desc_list_entry_size); return -EINVAL; } @@ -726,12 +738,12 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) { llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8; } else { - ena_trc_err("Invalid descs_num_before_header, supported: 0x%x\n", + ena_trc_err(ena_dev, "Invalid descs_num_before_header, supported: 0x%x\n", supported_feat); return -EINVAL; } - ena_trc_err("Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", + ena_trc_err(ena_dev, "Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", llq_default_cfg->llq_num_decs_before_header, supported_feat, llq_info->descs_num_before_header); @@ -750,7 +762,7 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, rc = ena_com_set_llq(ena_dev); if (rc) - ena_trc_err("Cannot set LLQ configuration: %d\n", rc); + ena_trc_err(ena_dev, "Cannot set LLQ configuration: %d\n", rc); return rc; } @@ -776,13 +788,15 @@ static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *com ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); if (comp_ctx->status == ENA_CMD_COMPLETED) { - ena_trc_err("The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n", + ena_trc_err(admin_queue->ena_dev, + "The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n", comp_ctx->cmd_opcode, admin_queue->auto_polling ? "ON" : "OFF"); /* Check if fallback to polling is enabled */ if (admin_queue->auto_polling) admin_queue->polling = true; } else { - ena_trc_err("The ena device didn't send a completion for the admin cmd %d status %d\n", + ena_trc_err(admin_queue->ena_dev, + "The ena device didn't send a completion for the admin cmd %d status %d\n", comp_ctx->cmd_opcode, comp_ctx->status); } /* Check if shifted to polling mode. @@ -796,7 +810,7 @@ static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *com } } - ret = ena_com_comp_status_to_errno(comp_ctx->comp_status); + ret = ena_com_comp_status_to_errno(admin_queue, comp_ctx->comp_status); err: comp_ctxt_release(admin_queue, comp_ctx); return ret; @@ -844,7 +858,7 @@ static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset) } if (unlikely(i == timeout)) { - ena_trc_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n", + ena_trc_err(ena_dev, "Reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n", mmio_read->seq_num, offset, read_resp->req_id, @@ -854,7 +868,7 @@ static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset) } if (read_resp->reg_off != offset) { - ena_trc_err("Read failure: wrong offset provided\n"); + ena_trc_err(ena_dev, "Read failure: wrong offset provided\n"); ret = ENA_MMIO_READ_TIMEOUT; } else { ret = read_resp->reg_val; @@ -913,7 +927,7 @@ static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev, sizeof(destroy_resp)); if (unlikely(ret && (ret != ENA_COM_NO_DEVICE))) - ena_trc_err("failed to destroy io sq error: %d\n", ret); + ena_trc_err(ena_dev, "Failed to destroy io sq error: %d\n", ret); return ret; } @@ -969,7 +983,7 @@ static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout, val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) { - ena_trc_err("Reg read timeout occurred\n"); + ena_trc_err(ena_dev, "Reg read timeout occurred\n"); return ENA_COM_TIMER_EXPIRED; } @@ -1009,7 +1023,7 @@ static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev, int ret; if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) { - ena_trc_dbg("Feature %d isn't supported\n", feature_id); + ena_trc_dbg(ena_dev, "Feature %d isn't supported\n", feature_id); return ENA_COM_UNSUPPORTED; } @@ -1028,7 +1042,7 @@ static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev, &get_cmd.control_buffer.address, control_buf_dma_addr); if (unlikely(ret)) { - ena_trc_err("memory address set failed\n"); + ena_trc_err(ena_dev, "Memory address set failed\n"); return ret; } @@ -1045,7 +1059,7 @@ static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev, sizeof(*get_resp)); if (unlikely(ret)) - ena_trc_err("Failed to submit get_feature command %d error: %d\n", + ena_trc_err(ena_dev, "Failed to submit get_feature command %d error: %d\n", feature_id, ret); return ret; @@ -1157,7 +1171,7 @@ static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev, if ((get_resp.u.ind_table.min_size > log_size) || (get_resp.u.ind_table.max_size < log_size)) { - ena_trc_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n", + ena_trc_err(ena_dev, "Indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n", 1 << log_size, 1 << get_resp.u.ind_table.min_size, 1 << get_resp.u.ind_table.max_size); @@ -1261,7 +1275,7 @@ static int ena_com_create_io_sq(struct ena_com_dev *ena_dev, &create_cmd.sq_ba, io_sq->desc_addr.phys_addr); if (unlikely(ret)) { - ena_trc_err("memory address set failed\n"); + ena_trc_err(ena_dev, "Memory address set failed\n"); return ret; } } @@ -1272,7 +1286,7 @@ static int ena_com_create_io_sq(struct ena_com_dev *ena_dev, (struct ena_admin_acq_entry *)&cmd_completion, sizeof(cmd_completion)); if (unlikely(ret)) { - ena_trc_err("Failed to create IO SQ. error: %d\n", ret); + ena_trc_err(ena_dev, "Failed to create IO SQ. error: %d\n", ret); return ret; } @@ -1290,7 +1304,7 @@ static int ena_com_create_io_sq(struct ena_com_dev *ena_dev, cmd_completion.llq_descriptors_offset); } - ena_trc_dbg("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth); + ena_trc_dbg(ena_dev, "Created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth); return ret; } @@ -1324,7 +1338,7 @@ static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev, u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution; if (unlikely(!intr_delay_resolution)) { - ena_trc_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n"); + ena_trc_err(ena_dev, "Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n"); intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION; } @@ -1360,10 +1374,12 @@ int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, comp, comp_size); if (IS_ERR(comp_ctx)) { if (comp_ctx == ERR_PTR(ENA_COM_NO_DEVICE)) - ena_trc_dbg("Failed to submit command [%ld]\n", + ena_trc_dbg(admin_queue->ena_dev, + "Failed to submit command [%ld]\n", PTR_ERR(comp_ctx)); else - ena_trc_err("Failed to submit command [%ld]\n", + ena_trc_err(admin_queue->ena_dev, + "Failed to submit command [%ld]\n", PTR_ERR(comp_ctx)); return PTR_ERR(comp_ctx); @@ -1372,11 +1388,11 @@ int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue); if (unlikely(ret)) { if (admin_queue->running_state) - ena_trc_err("Failed to process command. ret = %d\n", - ret); + ena_trc_err(admin_queue->ena_dev, + "Failed to process command. ret = %d\n", ret); else - ena_trc_dbg("Failed to process command. ret = %d\n", - ret); + ena_trc_dbg(admin_queue->ena_dev, + "Failed to process command. ret = %d\n", ret); } return ret; } @@ -1405,7 +1421,7 @@ int ena_com_create_io_cq(struct ena_com_dev *ena_dev, &create_cmd.cq_ba, io_cq->cdesc_addr.phys_addr); if (unlikely(ret)) { - ena_trc_err("memory address set failed\n"); + ena_trc_err(ena_dev, "Memory address set failed\n"); return ret; } @@ -1415,7 +1431,7 @@ int ena_com_create_io_cq(struct ena_com_dev *ena_dev, (struct ena_admin_acq_entry *)&cmd_completion, sizeof(cmd_completion)); if (unlikely(ret)) { - ena_trc_err("Failed to create IO CQ. error: %d\n", ret); + ena_trc_err(ena_dev, "Failed to create IO CQ. error: %d\n", ret); return ret; } @@ -1434,7 +1450,7 @@ int ena_com_create_io_cq(struct ena_com_dev *ena_dev, (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + cmd_completion.numa_node_register_offset); - ena_trc_dbg("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth); + ena_trc_dbg(ena_dev, "Created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth); return ret; } @@ -1444,7 +1460,7 @@ int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, struct ena_com_io_cq **io_cq) { if (qid >= ENA_TOTAL_NUM_QUEUES) { - ena_trc_err("Invalid queue number %d but the max is %d\n", + ena_trc_err(ena_dev, "Invalid queue number %d but the max is %d\n", qid, ENA_TOTAL_NUM_QUEUES); return ENA_COM_INVAL; } @@ -1510,7 +1526,7 @@ int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, sizeof(destroy_resp)); if (unlikely(ret && (ret != ENA_COM_NO_DEVICE))) - ena_trc_err("Failed to destroy IO CQ. error: %d\n", ret); + ena_trc_err(ena_dev, "Failed to destroy IO CQ. error: %d\n", ret); return ret; } @@ -1534,7 +1550,7 @@ void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev) { u16 depth = ena_dev->aenq.q_depth; - ENA_WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n"); + ENA_WARN(ena_dev->aenq.head != depth, ena_dev, "Invalid AENQ state\n"); /* Init head_db to mark that all entries in the queue * are initially available @@ -1552,12 +1568,12 @@ int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag) ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0); if (ret) { - ena_trc_info("Can't get aenq configuration\n"); + ena_trc_info(ena_dev, "Can't get aenq configuration\n"); return ret; } if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) { - ena_trc_warn("Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n", + ena_trc_warn(ena_dev, "Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n", get_resp.u.aenq.supported_groups, groups_flag); return ENA_COM_UNSUPPORTED; @@ -1578,7 +1594,7 @@ int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag) sizeof(resp)); if (unlikely(ret)) - ena_trc_err("Failed to config AENQ ret: %d\n", ret); + ena_trc_err(ena_dev, "Failed to config AENQ ret: %d\n", ret); return ret; } @@ -1589,17 +1605,17 @@ int ena_com_get_dma_width(struct ena_com_dev *ena_dev) int width; if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) { - ena_trc_err("Reg read timeout occurred\n"); + ena_trc_err(ena_dev, "Reg read timeout occurred\n"); return ENA_COM_TIMER_EXPIRED; } width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >> ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT; - ena_trc_dbg("ENA dma width: %d\n", width); + ena_trc_dbg(ena_dev, "ENA dma width: %d\n", width); if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) { - ena_trc_err("DMA width illegal value: %d\n", width); + ena_trc_err(ena_dev, "DMA width illegal value: %d\n", width); return ENA_COM_INVAL; } @@ -1623,16 +1639,16 @@ int ena_com_validate_version(struct ena_com_dev *ena_dev) if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) || (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) { - ena_trc_err("Reg read timeout occurred\n"); + ena_trc_err(ena_dev, "Reg read timeout occurred\n"); return ENA_COM_TIMER_EXPIRED; } - ena_trc_info("ena device version: %d.%d\n", + ena_trc_info(ena_dev, "ENA device version: %d.%d\n", (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >> ENA_REGS_VERSION_MAJOR_VERSION_SHIFT, ver & ENA_REGS_VERSION_MINOR_VERSION_MASK); - ena_trc_info("ena controller version: %d.%d.%d implementation version %d\n", + ena_trc_info(ena_dev, "ENA controller version: %d.%d.%d implementation version %d\n", (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >> ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT, (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) @@ -1648,7 +1664,7 @@ int ena_com_validate_version(struct ena_com_dev *ena_dev) /* Validate the ctrl version without the implementation ID */ if (ctrl_ver_masked < MIN_ENA_CTRL_VER) { - ena_trc_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n"); + ena_trc_err(ena_dev, "ENA ctrl version is lower than the minimal ctrl version the driver supports\n"); return -1; } @@ -1786,12 +1802,12 @@ int ena_com_admin_init(struct ena_com_dev *ena_dev, dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) { - ena_trc_err("Reg read timeout occurred\n"); + ena_trc_err(ena_dev, "Reg read timeout occurred\n"); return ENA_COM_TIMER_EXPIRED; } if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) { - ena_trc_err("Device isn't ready, abort com init\n"); + ena_trc_err(ena_dev, "Device isn't ready, abort com init\n"); return ENA_COM_NO_DEVICE; } @@ -1869,7 +1885,7 @@ int ena_com_create_io_queue(struct ena_com_dev *ena_dev, int ret; if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) { - ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n", + ena_trc_err(ena_dev, "Qid (%d) is bigger than max num of queues (%d)\n", ctx->qid, ENA_TOTAL_NUM_QUEUES); return ENA_COM_INVAL; } @@ -1928,7 +1944,7 @@ void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid) struct ena_com_io_cq *io_cq; if (qid >= ENA_TOTAL_NUM_QUEUES) { - ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n", + ena_trc_err(ena_dev, "Qid (%d) is bigger than max num of queues (%d)\n", qid, ENA_TOTAL_NUM_QUEUES); return; } @@ -2090,7 +2106,7 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data) timestamp = (u64)aenq_common->timestamp_low | ((u64)aenq_common->timestamp_high << 32); ENA_TOUCH(timestamp); /* In case debug is disabled */ - ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%" ENA_PRIu64 "s]\n", + ena_trc_dbg(ena_dev, "AENQ! Group[%x] Syndrom[%x] timestamp: [%" ENA_PRIu64 "s]\n", aenq_common->group, aenq_common->syndrom, timestamp); @@ -2137,19 +2153,19 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev, if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) || (cap == ENA_MMIO_READ_TIMEOUT))) { - ena_trc_err("Reg read32 timeout occurred\n"); + ena_trc_err(ena_dev, "Reg read32 timeout occurred\n"); return ENA_COM_TIMER_EXPIRED; } if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) { - ena_trc_err("Device isn't ready, can't reset device\n"); + ena_trc_err(ena_dev, "Device isn't ready, can't reset device\n"); return ENA_COM_INVAL; } timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >> ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT; if (timeout == 0) { - ena_trc_err("Invalid timeout value\n"); + ena_trc_err(ena_dev, "Invalid timeout value\n"); return ENA_COM_INVAL; } @@ -2165,7 +2181,7 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev, rc = wait_for_reset_state(ena_dev, timeout, ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK); if (rc != 0) { - ena_trc_err("Reset indication didn't turn on\n"); + ena_trc_err(ena_dev, "Reset indication didn't turn on\n"); return rc; } @@ -2173,7 +2189,7 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev, ENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); rc = wait_for_reset_state(ena_dev, timeout, 0); if (rc != 0) { - ena_trc_err("Reset indication didn't turn off\n"); + ena_trc_err(ena_dev, "Reset indication didn't turn off\n"); return rc; } @@ -2210,7 +2226,7 @@ static int ena_get_dev_stats(struct ena_com_dev *ena_dev, sizeof(*get_resp)); if (unlikely(ret)) - ena_trc_err("Failed to get stats. error: %d\n", ret); + ena_trc_err(ena_dev, "Failed to get stats. error: %d\n", ret); return ret; } @@ -2253,7 +2269,7 @@ int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu) int ret; if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) { - ena_trc_dbg("Feature %d isn't supported\n", ENA_ADMIN_MTU); + ena_trc_dbg(ena_dev, "Feature %d isn't supported\n", ENA_ADMIN_MTU); return ENA_COM_UNSUPPORTED; } @@ -2272,7 +2288,7 @@ int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu) sizeof(resp)); if (unlikely(ret)) - ena_trc_err("Failed to set mtu %d. error: %d\n", mtu, ret); + ena_trc_err(ena_dev, "Failed to set mtu %d. error: %d\n", mtu, ret); return ret; } @@ -2286,7 +2302,7 @@ int ena_com_get_offload_settings(struct ena_com_dev *ena_dev, ret = ena_com_get_feature(ena_dev, &resp, ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0); if (unlikely(ret)) { - ena_trc_err("Failed to get offload capabilities %d\n", ret); + ena_trc_err(ena_dev, "Failed to get offload capabilities %d\n", ret); return ret; } @@ -2306,7 +2322,7 @@ int ena_com_set_hash_function(struct ena_com_dev *ena_dev) if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_FUNCTION)) { - ena_trc_dbg("Feature %d isn't supported\n", + ena_trc_dbg(ena_dev, "Feature %d isn't supported\n", ENA_ADMIN_RSS_HASH_FUNCTION); return ENA_COM_UNSUPPORTED; } @@ -2318,7 +2334,7 @@ int ena_com_set_hash_function(struct ena_com_dev *ena_dev) return ret; if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) { - ena_trc_err("Func hash %d isn't supported by device, abort\n", + ena_trc_err(ena_dev, "Func hash %d isn't supported by device, abort\n", rss->hash_func); return ENA_COM_UNSUPPORTED; } @@ -2336,7 +2352,7 @@ int ena_com_set_hash_function(struct ena_com_dev *ena_dev) &cmd.control_buffer.address, rss->hash_key_dma_addr); if (unlikely(ret)) { - ena_trc_err("memory address set failed\n"); + ena_trc_err(ena_dev, "Memory address set failed\n"); return ret; } @@ -2348,7 +2364,7 @@ int ena_com_set_hash_function(struct ena_com_dev *ena_dev) (struct ena_admin_acq_entry *)&resp, sizeof(resp)); if (unlikely(ret)) { - ena_trc_err("Failed to set hash function %d. error: %d\n", + ena_trc_err(ena_dev, "Failed to set hash function %d. error: %d\n", rss->hash_func, ret); return ENA_COM_INVAL; } @@ -2380,7 +2396,7 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, return rc; if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) { - ena_trc_err("Flow hash function %d isn't supported\n", func); + ena_trc_err(ena_dev, "Flow hash function %d isn't supported\n", func); return ENA_COM_UNSUPPORTED; } @@ -2388,7 +2404,7 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, case ENA_ADMIN_TOEPLITZ: if (key) { if (key_len != sizeof(hash_key->key)) { - ena_trc_err("key len (%hu) doesn't equal the supported size (%zu)\n", + ena_trc_err(ena_dev, "key len (%hu) doesn't equal the supported size (%zu)\n", key_len, sizeof(hash_key->key)); return ENA_COM_INVAL; } @@ -2401,7 +2417,7 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, rss->hash_init_val = init_val; break; default: - ena_trc_err("Invalid hash function (%d)\n", func); + ena_trc_err(ena_dev, "Invalid hash function (%d)\n", func); return ENA_COM_INVAL; } @@ -2486,7 +2502,7 @@ int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev) if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_INPUT)) { - ena_trc_dbg("Feature %d isn't supported\n", + ena_trc_dbg(ena_dev, "Feature %d isn't supported\n", ENA_ADMIN_RSS_HASH_INPUT); return ENA_COM_UNSUPPORTED; } @@ -2505,7 +2521,7 @@ int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev) &cmd.control_buffer.address, rss->hash_ctrl_dma_addr); if (unlikely(ret)) { - ena_trc_err("memory address set failed\n"); + ena_trc_err(ena_dev, "Memory address set failed\n"); return ret; } cmd.control_buffer.length = sizeof(*hash_ctrl); @@ -2516,7 +2532,7 @@ int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev) (struct ena_admin_acq_entry *)&resp, sizeof(resp)); if (unlikely(ret)) - ena_trc_err("Failed to set hash input. error: %d\n", ret); + ena_trc_err(ena_dev, "Failed to set hash input. error: %d\n", ret); return ret; } @@ -2566,7 +2582,7 @@ int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev) available_fields = hash_ctrl->selected_fields[i].fields & hash_ctrl->supported_fields[i].fields; if (available_fields != hash_ctrl->selected_fields[i].fields) { - ena_trc_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n", + ena_trc_err(ena_dev, "Hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n", i, hash_ctrl->supported_fields[i].fields, hash_ctrl->selected_fields[i].fields); return ENA_COM_UNSUPPORTED; @@ -2592,7 +2608,7 @@ int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, int rc; if (proto >= ENA_ADMIN_RSS_PROTO_NUM) { - ena_trc_err("Invalid proto num (%u)\n", proto); + ena_trc_err(ena_dev, "Invalid proto num (%u)\n", proto); return ENA_COM_INVAL; } @@ -2604,7 +2620,7 @@ int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, /* Make sure all the fields are supported */ supported_fields = hash_ctrl->supported_fields[proto].fields; if ((hash_fields & supported_fields) != hash_fields) { - ena_trc_err("proto %d doesn't support the required fields %x. supports only: %x\n", + ena_trc_err(ena_dev, "Proto %d doesn't support the required fields %x. supports only: %x\n", proto, hash_fields, supported_fields); } @@ -2645,14 +2661,14 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) { - ena_trc_dbg("Feature %d isn't supported\n", + ena_trc_dbg(ena_dev, "Feature %d isn't supported\n", ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG); return ENA_COM_UNSUPPORTED; } ret = ena_com_ind_tbl_convert_to_device(ena_dev); if (ret) { - ena_trc_err("Failed to convert host indirection table to device table\n"); + ena_trc_err(ena_dev, "Failed to convert host indirection table to device table\n"); return ret; } @@ -2669,7 +2685,7 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) &cmd.control_buffer.address, rss->rss_ind_tbl_dma_addr); if (unlikely(ret)) { - ena_trc_err("memory address set failed\n"); + ena_trc_err(ena_dev, "Memory address set failed\n"); return ret; } @@ -2683,7 +2699,7 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) sizeof(resp)); if (unlikely(ret)) - ena_trc_err("Failed to set indirect table. error: %d\n", ret); + ena_trc_err(ena_dev, "Failed to set indirect table. error: %d\n", ret); return ret; } @@ -2848,7 +2864,7 @@ int ena_com_set_host_attributes(struct ena_com_dev *ena_dev) &cmd.u.host_attr.debug_ba, host_attr->debug_area_dma_addr); if (unlikely(ret)) { - ena_trc_err("memory address set failed\n"); + ena_trc_err(ena_dev, "Memory address set failed\n"); return ret; } @@ -2856,7 +2872,7 @@ int ena_com_set_host_attributes(struct ena_com_dev *ena_dev) &cmd.u.host_attr.os_info_ba, host_attr->host_info_dma_addr); if (unlikely(ret)) { - ena_trc_err("memory address set failed\n"); + ena_trc_err(ena_dev, "Memory address set failed\n"); return ret; } @@ -2869,7 +2885,7 @@ int ena_com_set_host_attributes(struct ena_com_dev *ena_dev) sizeof(resp)); if (unlikely(ret)) - ena_trc_err("Failed to set host attributes: %d\n", ret); + ena_trc_err(ena_dev, "Failed to set host attributes: %d\n", ret); return ret; } @@ -2881,12 +2897,13 @@ bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev) ENA_ADMIN_INTERRUPT_MODERATION); } -static int ena_com_update_nonadaptive_moderation_interval(u32 coalesce_usecs, +static int ena_com_update_nonadaptive_moderation_interval(struct ena_com_dev *ena_dev, + u32 coalesce_usecs, u32 intr_delay_resolution, u32 *intr_moder_interval) { if (!intr_delay_resolution) { - ena_trc_err("Illegal interrupt delay granularity value\n"); + ena_trc_err(ena_dev, "Illegal interrupt delay granularity value\n"); return ENA_COM_FAULT; } @@ -2895,11 +2912,11 @@ static int ena_com_update_nonadaptive_moderation_interval(u32 coalesce_usecs, return 0; } - int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, u32 tx_coalesce_usecs) { - return ena_com_update_nonadaptive_moderation_interval(tx_coalesce_usecs, + return ena_com_update_nonadaptive_moderation_interval(ena_dev, + tx_coalesce_usecs, ena_dev->intr_delay_resolution, &ena_dev->intr_moder_tx_interval); } @@ -2907,7 +2924,8 @@ int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_de int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, u32 rx_coalesce_usecs) { - return ena_com_update_nonadaptive_moderation_interval(rx_coalesce_usecs, + return ena_com_update_nonadaptive_moderation_interval(ena_dev, + rx_coalesce_usecs, ena_dev->intr_delay_resolution, &ena_dev->intr_moder_rx_interval); } @@ -2923,12 +2941,12 @@ int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev) if (rc) { if (rc == ENA_COM_UNSUPPORTED) { - ena_trc_dbg("Feature %d isn't supported\n", + ena_trc_dbg(ena_dev, "Feature %d isn't supported\n", ENA_ADMIN_INTERRUPT_MODERATION); rc = 0; } else { - ena_trc_err("Failed to get interrupt moderation admin cmd. rc: %d\n", - rc); + ena_trc_err(ena_dev, + "Failed to get interrupt moderation admin cmd. rc: %d\n", rc); } /* no moderation supported, disable adaptive support */ @@ -2976,7 +2994,7 @@ int ena_com_config_dev_mode(struct ena_com_dev *ena_dev, (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc)); if (unlikely(ena_dev->tx_max_header_size == 0)) { - ena_trc_err("the size of the LLQ entry is smaller than needed\n"); + ena_trc_err(ena_dev, "The size of the LLQ entry is smaller than needed\n"); return -EINVAL; } diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h index e9601b1a8e..cd116e90e6 100644 --- a/drivers/net/ena/base/ena_com.h +++ b/drivers/net/ena/base/ena_com.h @@ -300,6 +300,7 @@ struct ena_com_dev { void __iomem *mem_bar; void *dmadev; void *bus; + ena_netdev *net_device; enum ena_admin_placement_policy_type tx_mem_queue_type; u32 tx_max_header_size; @@ -944,6 +945,26 @@ int ena_com_config_dev_mode(struct ena_com_dev *ena_dev, struct ena_admin_feature_llq_desc *llq_features, struct ena_llq_configurations *llq_default_config); +/* ena_com_io_sq_to_ena_dev - Extract ena_com_dev using contained field io_sq. + * @io_sq: IO submit queue struct + * + * @return - ena_com_dev struct extracted from io_sq + */ +static inline struct ena_com_dev *ena_com_io_sq_to_ena_dev(struct ena_com_io_sq *io_sq) +{ + return container_of(io_sq, struct ena_com_dev, io_sq_queues[io_sq->qid]); +} + +/* ena_com_io_cq_to_ena_dev - Extract ena_com_dev using contained field io_cq. + * @io_sq: IO submit queue struct + * + * @return - ena_com_dev struct extracted from io_sq + */ +static inline struct ena_com_dev *ena_com_io_cq_to_ena_dev(struct ena_com_io_cq *io_cq) +{ + return container_of(io_cq, struct ena_com_dev, io_cq_queues[io_cq->qid]); +} + static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev) { return ena_dev->adaptive_coalescing; diff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c index 5583a310a1..701e6721e3 100644 --- a/drivers/net/ena/base/ena_eth_com.c +++ b/drivers/net/ena/base/ena_eth_com.c @@ -57,12 +57,14 @@ static int ena_com_write_bounce_buffer_to_dev(struct ena_com_io_sq *io_sq, if (is_llq_max_tx_burst_exists(io_sq)) { if (unlikely(!io_sq->entries_in_tx_burst_left)) { - ena_trc_err("Error: trying to send more packets than tx burst allows\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Error: trying to send more packets than tx burst allows\n"); return ENA_COM_NO_SPACE; } io_sq->entries_in_tx_burst_left--; - ena_trc_dbg("decreasing entries_in_tx_burst_left of queue %d to %d\n", + ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq), + "Decreasing entries_in_tx_burst_left of queue %d to %d\n", io_sq->qid, io_sq->entries_in_tx_burst_left); } @@ -101,12 +103,14 @@ static int ena_com_write_header_to_bounce(struct ena_com_io_sq *io_sq, llq_info->descs_num_before_header * io_sq->desc_entry_size; if (unlikely((header_offset + header_len) > llq_info->desc_list_entry_size)) { - ena_trc_err("trying to write header larger than llq entry can accommodate\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Trying to write header larger than llq entry can accommodate\n"); return ENA_COM_FAULT; } if (unlikely(!bounce_buffer)) { - ena_trc_err("bounce buffer is NULL\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Bounce buffer is NULL\n"); return ENA_COM_FAULT; } @@ -124,7 +128,8 @@ static void *get_sq_desc_llq(struct ena_com_io_sq *io_sq) bounce_buffer = pkt_ctrl->curr_bounce_buf; if (unlikely(!bounce_buffer)) { - ena_trc_err("bounce buffer is NULL\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Bounce buffer is NULL\n"); return NULL; } @@ -149,7 +154,8 @@ static int ena_com_close_bounce_buffer(struct ena_com_io_sq *io_sq) rc = ena_com_write_bounce_buffer_to_dev(io_sq, pkt_ctrl->curr_bounce_buf); if (unlikely(rc)) { - ena_trc_err("failed to write bounce buffer to device\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Failed to write bounce buffer to device\n"); return rc; } @@ -182,7 +188,8 @@ static int ena_com_sq_update_llq_tail(struct ena_com_io_sq *io_sq) rc = ena_com_write_bounce_buffer_to_dev(io_sq, pkt_ctrl->curr_bounce_buf); if (unlikely(rc)) { - ena_trc_err("failed to write bounce buffer to device\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Failed to write bounce buffer to device\n"); return rc; } @@ -252,7 +259,8 @@ static u16 ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq, io_cq->cur_rx_pkt_cdesc_count = 0; io_cq->cur_rx_pkt_cdesc_start_idx = head_masked; - ena_trc_dbg("ena q_id: %d packets were completed. first desc idx %u descs# %d\n", + ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), + "ENA q_id: %d packets were completed. first desc idx %u descs# %d\n", io_cq->qid, *first_cdesc_idx, count); } else { io_cq->cur_rx_pkt_cdesc_count += count; @@ -335,8 +343,9 @@ static int ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *io_sq, } } -static void ena_com_rx_set_flags(struct ena_com_rx_ctx *ena_rx_ctx, - struct ena_eth_io_rx_cdesc_base *cdesc) +static void ena_com_rx_set_flags(struct ena_com_io_cq *io_cq, + struct ena_com_rx_ctx *ena_rx_ctx, + struct ena_eth_io_rx_cdesc_base *cdesc) { ena_rx_ctx->l3_proto = cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK; @@ -357,7 +366,8 @@ static void ena_com_rx_set_flags(struct ena_com_rx_ctx *ena_rx_ctx, (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT; - ena_trc_dbg("ena_rx_ctx->l3_proto %d ena_rx_ctx->l4_proto %d\nena_rx_ctx->l3_csum_err %d ena_rx_ctx->l4_csum_err %d\nhash frag %d frag: %d cdesc_status: %x\n", + ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), + "l3_proto %d l4_proto %d l3_csum_err %d l4_csum_err %d hash %d frag %d cdesc_status %x\n", ena_rx_ctx->l3_proto, ena_rx_ctx->l4_proto, ena_rx_ctx->l3_csum_err, @@ -386,23 +396,26 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, u64 addr_hi; ENA_WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_TX, - "wrong Q type"); + ena_com_io_sq_to_ena_dev(io_sq), "wrong Q type"); /* num_bufs +1 for potential meta desc */ if (unlikely(!ena_com_sq_have_enough_space(io_sq, num_bufs + 1))) { - ena_trc_dbg("Not enough space in the tx queue\n"); + ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq), + "Not enough space in the tx queue\n"); return ENA_COM_NO_MEM; } if (unlikely(header_len > io_sq->tx_max_header_size)) { - ena_trc_err("header size is too large %d max header: %d\n", + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Header size is too large %d max header: %d\n", header_len, io_sq->tx_max_header_size); return ENA_COM_INVAL; } if (unlikely(io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && !buffer_to_push)) { - ena_trc_err("push header wasn't provided on LLQ mode\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Push header wasn't provided on LLQ mode\n"); return ENA_COM_INVAL; } @@ -412,7 +425,8 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, rc = ena_com_create_and_store_tx_meta_desc(io_sq, ena_tx_ctx, &have_meta); if (unlikely(rc)) { - ena_trc_err("failed to create and store tx meta desc\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Failed to create and store tx meta desc\n"); return rc; } @@ -420,7 +434,8 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, if (unlikely(!num_bufs && !header_len)) { rc = ena_com_close_bounce_buffer(io_sq); if (rc) - ena_trc_err("failed to write buffers to LLQ\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Failed to write buffers to LLQ\n"); *nb_hw_desc = io_sq->tail - start_tail; return rc; } @@ -481,7 +496,8 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, if (likely(i != 0)) { rc = ena_com_sq_update_tail(io_sq); if (unlikely(rc)) { - ena_trc_err("failed to update sq tail\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Failed to update sq tail\n"); return rc; } @@ -513,13 +529,15 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, rc = ena_com_sq_update_tail(io_sq); if (unlikely(rc)) { - ena_trc_err("failed to update sq tail of the last descriptor\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Failed to update sq tail of the last descriptor\n"); return rc; } rc = ena_com_close_bounce_buffer(io_sq); if (rc) - ena_trc_err("failed when closing bounce buffer\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Failed when closing bounce buffer\n"); *nb_hw_desc = io_sq->tail - start_tail; return rc; @@ -537,7 +555,7 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq, u16 i = 0; ENA_WARN(io_cq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX, - "wrong Q type"); + ena_com_io_cq_to_ena_dev(io_cq), "wrong Q type"); nb_hw_desc = ena_com_cdesc_rx_pkt_get(io_cq, &cdesc_idx); if (nb_hw_desc == 0) { @@ -545,11 +563,13 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq, return 0; } - ena_trc_dbg("fetch rx packet: queue %d completed desc: %d\n", + ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), + "Fetch rx packet: queue %d completed desc: %d\n", io_cq->qid, nb_hw_desc); if (unlikely(nb_hw_desc > ena_rx_ctx->max_bufs)) { - ena_trc_err("Too many RX cdescs (%d) > MAX(%d)\n", + ena_trc_err(ena_com_io_cq_to_ena_dev(io_cq), + "Too many RX cdescs (%d) > MAX(%d)\n", nb_hw_desc, ena_rx_ctx->max_bufs); return ENA_COM_NO_SPACE; } @@ -573,13 +593,15 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq, /* Update SQ head ptr */ io_sq->next_to_comp += nb_hw_desc; - ena_trc_dbg("[%s][QID#%d] Updating SQ head to: %d\n", __func__, + ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), + "[%s][QID#%d] Updating SQ head to: %d\n", __func__, io_sq->qid, io_sq->next_to_comp); /* Get rx flags from the last pkt */ - ena_com_rx_set_flags(ena_rx_ctx, cdesc); + ena_com_rx_set_flags(io_cq, ena_rx_ctx, cdesc); ena_rx_ctx->descs = nb_hw_desc; + return 0; } @@ -590,7 +612,7 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq, struct ena_eth_io_rx_desc *desc; ENA_WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX, - "wrong Q type"); + ena_com_io_sq_to_ena_dev(io_sq), "wrong Q type"); if (unlikely(!ena_com_sq_have_enough_space(io_sq, 1))) return ENA_COM_NO_SPACE; @@ -610,6 +632,10 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq, desc->req_id = req_id; + ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq), + "[%s] Adding single RX desc, Queue: %u, req_id: %u\n", + __func__, io_sq->qid, req_id); + desc->buff_addr_lo = (u32)ena_buf->paddr; desc->buff_addr_hi = ((ena_buf->paddr & GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32); diff --git a/drivers/net/ena/base/ena_eth_com.h b/drivers/net/ena/base/ena_eth_com.h index 7dda16cd9f..0cfd18882e 100644 --- a/drivers/net/ena/base/ena_eth_com.h +++ b/drivers/net/ena/base/ena_eth_com.h @@ -143,7 +143,8 @@ static inline bool ena_com_is_doorbell_needed(struct ena_com_io_sq *io_sq, llq_info->descs_per_entry); } - ena_trc_dbg("queue: %d num_descs: %d num_entries_needed: %d\n", + ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq), + "Queue: %d num_descs: %d num_entries_needed: %d\n", io_sq->qid, num_descs, num_entries_needed); return num_entries_needed > io_sq->entries_in_tx_burst_left; @@ -154,14 +155,16 @@ static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq) u16 max_entries_in_tx_burst = io_sq->llq_info.max_entries_in_tx_burst; u16 tail = io_sq->tail; - ena_trc_dbg("write submission queue doorbell for queue: %d tail: %d\n", + ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq), + "Write submission queue doorbell for queue: %d tail: %d\n", io_sq->qid, tail); ENA_REG_WRITE32(io_sq->bus, tail, io_sq->db_addr); if (is_llq_max_tx_burst_exists(io_sq)) { - ena_trc_dbg("reset available entries in tx burst for queue %d to %d\n", - io_sq->qid, max_entries_in_tx_burst); + ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq), + "Reset available entries in tx burst for queue %d to %d\n", + io_sq->qid, max_entries_in_tx_burst); io_sq->entries_in_tx_burst_left = max_entries_in_tx_burst; } @@ -179,7 +182,8 @@ static inline int ena_com_update_dev_comp_head(struct ena_com_io_cq *io_cq) need_update = unreported_comp > (io_cq->q_depth / ENA_COMP_HEAD_THRESH); if (unlikely(need_update)) { - ena_trc_dbg("Write completion queue doorbell for queue %d: head: %d\n", + ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), + "Write completion queue doorbell for queue %d: head: %d\n", io_cq->qid, head); ENA_REG_WRITE32(io_cq->bus, head, io_cq->cq_head_db_reg); io_cq->last_head_update = head; @@ -243,7 +247,8 @@ static inline int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, *req_id = READ_ONCE16(cdesc->req_id); if (unlikely(*req_id >= io_cq->q_depth)) { - ena_trc_err("Invalid req id %d\n", cdesc->req_id); + ena_trc_err(ena_com_io_cq_to_ena_dev(io_cq), + "Invalid req id %d\n", cdesc->req_id); return ENA_COM_INVAL; } diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index ae68f860a5..df2fdd30f6 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -32,6 +32,7 @@ typedef uint32_t u32; typedef uint16_t u16; typedef uint8_t u8; +typedef struct rte_eth_dev ena_netdev; typedef uint64_t dma_addr_t; #ifndef ETIME #define ETIME ETIMEDOUT @@ -98,29 +99,33 @@ extern int ena_logtype_com; (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) #ifdef RTE_LIBRTE_ENA_COM_DEBUG -#define ena_trc_log(level, fmt, arg...) \ - rte_log(RTE_LOG_ ## level, ena_logtype_com, \ - "[ENA_COM: %s]" fmt, __func__, ##arg) - -#define ena_trc_dbg(format, arg...) ena_trc_log(DEBUG, format, ##arg) -#define ena_trc_info(format, arg...) ena_trc_log(INFO, format, ##arg) -#define ena_trc_warn(format, arg...) ena_trc_log(WARNING, format, ##arg) -#define ena_trc_err(format, arg...) ena_trc_log(ERR, format, ##arg) +#define ena_trc_log(dev, level, fmt, arg...) \ + ( \ + ENA_TOUCH(dev), \ + rte_log(RTE_LOG_ ## level, ena_logtype_com, \ + "[ENA_COM: %s]" fmt, __func__, ##arg) \ + ) + +#define ena_trc_dbg(dev, format, arg...) ena_trc_log(dev, DEBUG, format, ##arg) +#define ena_trc_info(dev, format, arg...) ena_trc_log(dev, INFO, format, ##arg) +#define ena_trc_warn(dev, format, arg...) \ + ena_trc_log(dev, WARNING, format, ##arg) +#define ena_trc_err(dev, format, arg...) ena_trc_log(dev, ERR, format, ##arg) #else -#define ena_trc_dbg(format, arg...) do { } while (0) -#define ena_trc_info(format, arg...) do { } while (0) -#define ena_trc_warn(format, arg...) do { } while (0) -#define ena_trc_err(format, arg...) do { } while (0) +#define ena_trc_dbg(dev, format, arg...) ENA_TOUCH(dev) +#define ena_trc_info(dev, format, arg...) ENA_TOUCH(dev) +#define ena_trc_warn(dev, format, arg...) ENA_TOUCH(dev) +#define ena_trc_err(dev, format, arg...) ENA_TOUCH(dev) #endif /* RTE_LIBRTE_ENA_COM_DEBUG */ -#define ENA_WARN(cond, format, arg...) \ -do { \ - if (unlikely(cond)) { \ - ena_trc_err( \ - "Warn failed on %s:%s:%d:" format, \ - __FILE__, __func__, __LINE__, ##arg); \ - } \ -} while (0) +#define ENA_WARN(cond, dev, format, arg...) \ + do { \ + if (unlikely(cond)) { \ + ena_trc_err(dev, \ + "Warn failed on %s:%s:%d:" format, \ + __FILE__, __func__, __LINE__, ##arg); \ + } \ + } while (0) /* Spinlock related methods */ #define ena_spinlock_t rte_spinlock_t From patchwork Tue May 11 06:45:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93132 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 526A7A0C41; Tue, 11 May 2021 08:46:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C3A2241120; Tue, 11 May 2021 08:46:20 +0200 (CEST) Received: from mail-lj1-f172.google.com (mail-lj1-f172.google.com [209.85.208.172]) by mails.dpdk.org (Postfix) with ESMTP id 9DFAF41106 for ; Tue, 11 May 2021 08:46:16 +0200 (CEST) Received: by mail-lj1-f172.google.com with SMTP id w15so23756146ljo.10 for ; Mon, 10 May 2021 23:46:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X7PvbP9j1NfG0NAlAEL4BaFTYvrtrKKvkhHPb1fM+OA=; b=QWhMrZkkIiEWnEm+EGsyrbnQKeY0J6r5aOnyAEJ8wwdq5fT0VYXYNbNpsx93cX6I2L U6l5AmzOaxXiFbCpft+PFUBQGkLnjFtLK55hHGBjAxEyxpEHxDnQHokBpCoRGlHL+7Zs PRTsWDCS+lA17Jm7tCANsSn+xe8Jv/H82zSSTvZ9q22RRWJMpvtM3WYHE2rwT+JMbeZN VN91Mu62gUoqrd6LkJXPHW24k/weQ2GSRnTO9v+n/LQGQhhJjQrURdziGZtWx1SQT/jt TSvWkHsDdKlaeXxseMvmPeWbp0LKVQB9bowX+Ao8gOdjLNNpf4ZJ7R72q7CtLuzxe3pg 2Wpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X7PvbP9j1NfG0NAlAEL4BaFTYvrtrKKvkhHPb1fM+OA=; b=q4q+9xJKouOUW38OaxcjWvUw2Yidh3XPkQKMv0xtwo4kACdEiuI/tqpyUOwZH5sN// T5Cv7jhATqIgcXXSaHMcjYalCp3PDpviL4BZ8xC5ZgrRerOdV1sfLkB51KLFuKEYyj7E uSYXF5WIAN8uOsTPThQwpCVCuwNFh9wdVXQHoQlkS3oQJTOadmtavMur2M1tqsc6wv+C GrAevO00YenASFTtkgoEK23Y4JaUchxrtZze6oWQPBDQPJJxu3fgIxQOBfkdZ/0mA/aB AgzWS0TL37ROL/GmI+l+aTR1KgvFCEwQkmgXIz7iVX5ONsnQBpDh/yHoTTagS2Oo2m7M 3QYg== X-Gm-Message-State: AOAM533IwVTKnrjP1SpaD499qJJtx5FXSt0cXNJaJzhDwlh3URCiwzlo 66qIJkfTSgKDi2o/ZMCoOEP52g== X-Google-Smtp-Source: ABdhPJxNMVQ3m07Vf3MILCU3cvtFxR6lqS/EbP6SOX+kIPFOsb28mh8eWqOogL7LeQG8MIHHah6pOw== X-Received: by 2002:a05:651c:140a:: with SMTP id u10mr20008612lje.384.1620715576230; Mon, 10 May 2021 23:46:16 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:15 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk Date: Tue, 11 May 2021 08:45:39 +0200 Message-Id: <20210511064554.10656-5-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 04/19] net/ena/base: style and comments improvements X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" List of changes: * Comment style was adjusted for the functions * The keys_num at "struct ena_admin_feature_rss_flow_hash_control" was renamed to the key_parts to better describe it's meaning * The RSS indirection table was called "REDIRECTION" -> changed to INDIRECTION * Change AENQ field "syndrom" -> "syndrome" * Calculate number of the RSS key parts or whole key by ussing the common way: sizeof of the first element of the RSS key * Add description of the "enum ena_admin_aq_feature_id" * Rename "map_rx_buf_bidirectional" field as "rx_buf_mirroring" * Other minor style fixes (remove extra spaces, add missing line break, improve indentation) * Remove unused macros ENA_ADMIN_EXTRA_PROPERTIES_* * Restructure the "if {} else if {} else" conditional statement for setting up the meta descriptor Fixes: 99ecfbf845b3 ("ena: import communication layer") Fixes: b68309be44c0 ("net/ena/base: update communication layer for the ENAv2") Fixes: b2b02edeb0d6 ("net/ena/base: upgrade HAL for new HW features") Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- v4: * Fix commit heading style. drivers/net/ena/base/ena_com.c | 26 +++--- .../net/ena/base/ena_defs/ena_admin_defs.h | 85 +++++++++---------- drivers/net/ena/base/ena_eth_com.c | 16 ++-- drivers/net/ena/ena_ethdev.c | 4 +- 4 files changed, 66 insertions(+), 65 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index 9931819bbb..9dc9f280c4 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -598,7 +598,7 @@ static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_c return ret; } -/** +/* * Set the LLQ configurations of the firmware * * The driver provides only the enabled feature values to the device, @@ -1092,7 +1092,7 @@ static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev) /* The key buffer is stored in the device in an array of * uint32 elements. */ - hash_key->keys_num = ENA_ADMIN_RSS_KEY_PARTS; + hash_key->key_parts = ENA_ADMIN_RSS_KEY_PARTS; } static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev) @@ -1165,7 +1165,7 @@ static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev, int ret; ret = ena_com_get_feature(ena_dev, &get_resp, - ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0); + ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG, 0); if (unlikely(ret)) return ret; @@ -1977,6 +1977,7 @@ int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr, sizeof(get_resp.u.dev_attr)); + ena_dev->supported_features = get_resp.u.dev_attr.supported_features; if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { @@ -2044,7 +2045,7 @@ int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, return rc; rc = ena_com_get_feature(ena_dev, &get_resp, - ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0); + ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG, 0); if (!rc) memcpy(&get_feat_ctx->ind_table, &get_resp.u.ind_table, sizeof(get_resp.u.ind_table)); @@ -2106,9 +2107,9 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data) timestamp = (u64)aenq_common->timestamp_low | ((u64)aenq_common->timestamp_high << 32); ENA_TOUCH(timestamp); /* In case debug is disabled */ - ena_trc_dbg(ena_dev, "AENQ! Group[%x] Syndrom[%x] timestamp: [%" ENA_PRIu64 "s]\n", + ena_trc_dbg(ena_dev, "AENQ! Group[%x] Syndrome[%x] timestamp: [%" ENA_PRIu64 "s]\n", aenq_common->group, - aenq_common->syndrom, + aenq_common->syndrome, timestamp); /* Handle specific event*/ @@ -2410,7 +2411,7 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, } memcpy(hash_key->key, key, key_len); rss->hash_init_val = init_val; - hash_key->keys_num = key_len / sizeof(u32); + hash_key->key_parts = key_len / sizeof(hash_key->key[0]); } break; case ENA_ADMIN_CRC32: @@ -2465,7 +2466,8 @@ int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key) ena_dev->rss.hash_key; if (key) - memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2); + memcpy(key, hash_key->key, + (size_t)(hash_key->key_parts) * sizeof(hash_key->key[0])); return 0; } @@ -2660,9 +2662,9 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) int ret; if (!ena_com_check_supported_feature_id(ena_dev, - ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) { + ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG)) { ena_trc_dbg(ena_dev, "Feature %d isn't supported\n", - ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG); + ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG); return ENA_COM_UNSUPPORTED; } @@ -2677,7 +2679,7 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; cmd.aq_common_descriptor.flags = ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; - cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG; + cmd.feat_common.feature_id = ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG; cmd.u.ind_table.size = rss->tbl_log_size; cmd.u.ind_table.inline_index = 0xFFFFFFFF; @@ -2715,7 +2717,7 @@ int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl) sizeof(struct ena_admin_rss_ind_table_entry); rc = ena_com_get_feature_ex(ena_dev, &get_resp, - ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, + ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG, rss->rss_ind_tbl_dma_addr, tbl_size, 0); if (unlikely(rc)) diff --git a/drivers/net/ena/base/ena_defs/ena_admin_defs.h b/drivers/net/ena/base/ena_defs/ena_admin_defs.h index 30e5eead71..40c2db717c 100644 --- a/drivers/net/ena/base/ena_defs/ena_admin_defs.h +++ b/drivers/net/ena/base/ena_defs/ena_admin_defs.h @@ -2,13 +2,9 @@ * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. * All rights reserved. */ - #ifndef _ENA_ADMIN_H_ #define _ENA_ADMIN_H_ -#define ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN 32 -#define ENA_ADMIN_EXTRA_PROPERTIES_COUNT 32 - #define ENA_ADMIN_RSS_KEY_PARTS 10 enum ena_admin_aq_opcode { @@ -33,6 +29,7 @@ enum ena_admin_aq_completion_status { ENA_ADMIN_RESOURCE_BUSY = 7, }; +/* subcommands for the set/get feature admin commands */ enum ena_admin_aq_feature_id { ENA_ADMIN_DEVICE_ATTRIBUTES = 1, ENA_ADMIN_MAX_QUEUES_NUM = 2, @@ -43,7 +40,7 @@ enum ena_admin_aq_feature_id { ENA_ADMIN_MAX_QUEUES_EXT = 7, ENA_ADMIN_RSS_HASH_FUNCTION = 10, ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11, - ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12, + ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG = 12, ENA_ADMIN_MTU = 14, ENA_ADMIN_RSS_HASH_INPUT = 18, ENA_ADMIN_INTERRUPT_MODERATION = 20, @@ -175,7 +172,7 @@ struct ena_admin_acq_common_desc { uint16_t extended_status; /* indicates to the driver which AQ entry has been consumed by the - * device and could be reused + * device and could be reused */ uint16_t sq_head_indx; }; @@ -220,8 +217,8 @@ struct ena_admin_aq_create_sq_cmd { */ uint8_t sq_caps_3; - /* associated completion queue id. This CQ must be created prior to - * SQ creation + /* associated completion queue id. This CQ must be created prior to SQ + * creation */ uint16_t cq_idx; @@ -360,7 +357,7 @@ struct ena_admin_aq_get_stats_cmd { uint16_t queue_idx; /* device id, value 0xFFFF means mine. only privileged device can get - * stats of other device + * stats of other device */ uint16_t device_id; }; @@ -442,8 +439,8 @@ struct ena_admin_get_set_feature_common_desc { uint8_t feature_id; /* The driver specifies the max feature version it supports and the - * device responds with the currently supported feature version. The - * field is zero based + * device responds with the currently supported feature version. The + * field is zero based */ uint8_t feature_version; @@ -455,7 +452,9 @@ struct ena_admin_device_attr_feature_desc { uint32_t device_version; - /* bitmap of ena_admin_aq_feature_id */ + /* bitmap of ena_admin_aq_feature_id, which represents supported + * subcommands for the set/get feature admin commands. + */ uint32_t supported_features; uint32_t reserved3; @@ -541,32 +540,30 @@ struct ena_admin_feature_llq_desc { uint32_t max_llq_depth; - /* specify the header locations the device supports. bitfield of - * enum ena_admin_llq_header_location. + /* specify the header locations the device supports. bitfield of enum + * ena_admin_llq_header_location. */ uint16_t header_location_ctrl_supported; /* the header location the driver selected to use. */ uint16_t header_location_ctrl_enabled; - /* if inline header is specified - this is the size of descriptor - * list entry. If header in a separate ring is specified - this is - * the size of header ring entry. bitfield of enum - * ena_admin_llq_ring_entry_size. specify the entry sizes the device - * supports + /* if inline header is specified - this is the size of descriptor list + * entry. If header in a separate ring is specified - this is the size + * of header ring entry. bitfield of enum ena_admin_llq_ring_entry_size. + * specify the entry sizes the device supports */ uint16_t entry_size_ctrl_supported; /* the entry size the driver selected to use. */ uint16_t entry_size_ctrl_enabled; - /* valid only if inline header is specified. First entry associated - * with the packet includes descriptors and header. Rest of the - * entries occupied by descriptors. This parameter defines the max - * number of descriptors precedding the header in the first entry. - * The field is bitfield of enum - * ena_admin_llq_num_descs_before_header and specify the values the - * device supports + /* valid only if inline header is specified. First entry associated with + * the packet includes descriptors and header. Rest of the entries + * occupied by descriptors. This parameter defines the max number of + * descriptors precedding the header in the first entry. The field is + * bitfield of enum ena_admin_llq_num_descs_before_header and specify + * the values the device supports */ uint16_t desc_num_before_header_supported; @@ -574,7 +571,7 @@ struct ena_admin_feature_llq_desc { uint16_t desc_num_before_header_enabled; /* valid only if inline was chosen. bitfield of enum - * ena_admin_llq_stride_ctrl + * ena_admin_llq_stride_ctrl */ uint16_t descriptors_stride_ctrl_supported; @@ -584,8 +581,8 @@ struct ena_admin_feature_llq_desc { /* reserved */ uint32_t reserved1; - /* accelerated low latency queues requirement. Driver needs to - * support those requirements in order to use accelerated LLQ + /* accelerated low latency queues requirement. driver needs to + * support those requirements in order to use accelerated llq */ struct ena_admin_accel_mode_req accel_mode; }; @@ -609,8 +606,8 @@ struct ena_admin_queue_ext_feature_fields { uint32_t max_tx_header_size; - /* Maximum Descriptors number, including meta descriptor, allowed for - * a single Tx packet + /* Maximum Descriptors number, including meta descriptor, allowed for a + * single Tx packet */ uint16_t max_per_packet_tx_descs; @@ -633,8 +630,8 @@ struct ena_admin_queue_feature_desc { uint32_t max_header_size; - /* Maximum Descriptors number, including meta descriptor, allowed for - * a single Tx packet + /* Maximum Descriptors number, including meta descriptor, allowed for a + * single Tx packet */ uint16_t max_packet_tx_descs; @@ -730,7 +727,7 @@ enum ena_admin_hash_functions { }; struct ena_admin_feature_rss_flow_hash_control { - uint32_t keys_num; + uint32_t key_parts; uint32_t reserved; @@ -872,7 +869,7 @@ struct ena_admin_host_info { /* 0 : mutable_rss_table_size * 1 : rx_offset * 2 : interrupt_moderation - * 3 : map_rx_buf_bidirectional + * 3 : rx_buf_mirroring * 4 : rss_configurable_function_key * 31:5 : reserved */ @@ -956,7 +953,7 @@ struct ena_admin_queue_ext_feature_desc { struct ena_admin_queue_ext_feature_fields max_queue_ext; uint32_t raw[10]; - } ; + }; }; struct ena_admin_get_feat_resp { @@ -1039,7 +1036,7 @@ struct ena_admin_set_feat_resp { struct ena_admin_aenq_common_desc { uint16_t group; - uint16_t syndrom; + uint16_t syndrome; /* 0 : phase * 7:1 : reserved - MBZ @@ -1063,7 +1060,7 @@ enum ena_admin_aenq_group { ENA_ADMIN_AENQ_GROUPS_NUM = 5, }; -enum ena_admin_aenq_notification_syndrom { +enum ena_admin_aenq_notification_syndrome { ENA_ADMIN_SUSPEND = 0, ENA_ADMIN_RESUME = 1, ENA_ADMIN_UPDATE_HINTS = 2, @@ -1197,8 +1194,8 @@ struct ena_admin_ena_mmio_req_read_less_resp { #define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1) #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2) -#define ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT 3 -#define ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK BIT(3) +#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3 +#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3) #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4) @@ -1652,14 +1649,14 @@ static inline void set_ena_admin_host_info_interrupt_moderation(struct ena_admin p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT) & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK; } -static inline uint32_t get_ena_admin_host_info_map_rx_buf_bidirectional(const struct ena_admin_host_info *p) +static inline uint32_t get_ena_admin_host_info_rx_buf_mirroring(const struct ena_admin_host_info *p) { - return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK) >> ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT; + return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK) >> ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT; } -static inline void set_ena_admin_host_info_map_rx_buf_bidirectional(struct ena_admin_host_info *p, uint32_t val) +static inline void set_ena_admin_host_info_rx_buf_mirroring(struct ena_admin_host_info *p, uint32_t val) { - p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT) & ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK; + p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT) & ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK; } static inline uint32_t get_ena_admin_host_info_rss_configurable_function_key(const struct ena_admin_host_info *p) diff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c index 701e6721e3..92a9a10a9e 100644 --- a/drivers/net/ena/base/ena_eth_com.c +++ b/drivers/net/ena/base/ena_eth_com.c @@ -331,16 +331,18 @@ static int ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *io_sq, *have_meta = true; return ena_com_create_meta(io_sq, ena_meta); - } else if (ena_com_meta_desc_changed(io_sq, ena_tx_ctx)) { + } + + if (ena_com_meta_desc_changed(io_sq, ena_tx_ctx)) { *have_meta = true; /* Cache the meta desc */ memcpy(&io_sq->cached_tx_meta, ena_meta, sizeof(struct ena_com_tx_meta)); return ena_com_create_meta(io_sq, ena_meta); - } else { - *have_meta = false; - return ENA_COM_OK; } + + *have_meta = false; + return ENA_COM_OK; } static void ena_com_rx_set_flags(struct ena_com_io_cq *io_cq, @@ -626,9 +628,9 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq, desc->length = ena_buf->len; desc->ctrl = ENA_ETH_IO_RX_DESC_FIRST_MASK | - ENA_ETH_IO_RX_DESC_LAST_MASK | - (io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK) | - ENA_ETH_IO_RX_DESC_COMP_REQ_MASK; + ENA_ETH_IO_RX_DESC_LAST_MASK | + ENA_ETH_IO_RX_DESC_COMP_REQ_MASK | + (io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK); desc->req_id = req_id; diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index f60e843b7f..f1ff4dad36 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -2973,7 +2973,7 @@ static void ena_notification(void *data, aenq_e->aenq_common_desc.group, ENA_ADMIN_NOTIFICATION); - switch (aenq_e->aenq_common_desc.syndrom) { + switch (aenq_e->aenq_common_desc.syndrome) { case ENA_ADMIN_UPDATE_HINTS: hints = (struct ena_admin_ena_hw_hints *) (&aenq_e->inline_data_w4); @@ -2981,7 +2981,7 @@ static void ena_notification(void *data, break; default: PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n", - aenq_e->aenq_common_desc.syndrom); + aenq_e->aenq_common_desc.syndrome); } } From patchwork Tue May 11 06:45:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93133 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9DD9FA0C41; Tue, 11 May 2021 08:46:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 20AC241123; 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[89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:17 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk , stable@dpdk.org Date: Tue, 11 May 2021 08:45:40 +0200 Message-Id: <20210511064554.10656-6-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 05/19] net/ena/base: fix issues from the static code scan X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" To silence error messages from the static code analysis, make the type conversions explicit where they're intended. Also fix the type for the DMA width value. Fixes: 99ecfbf845b3 ("ena: import communication layer") Cc: stable@dpdk.org Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- v4: * Add stable dpdk as cc. drivers/net/ena/base/ena_com.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index 9dc9f280c4..0cdeb1a2d9 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -1382,7 +1382,7 @@ int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, "Failed to submit command [%ld]\n", PTR_ERR(comp_ctx)); - return PTR_ERR(comp_ctx); + return (int)PTR_ERR(comp_ctx); } ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue); @@ -1602,7 +1602,7 @@ int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag) int ena_com_get_dma_width(struct ena_com_dev *ena_dev) { u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); - int width; + u32 width; if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) { ena_trc_err(ena_dev, "Reg read timeout occurred\n"); @@ -2280,7 +2280,7 @@ int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu) cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; cmd.aq_common_descriptor.flags = 0; cmd.feat_common.feature_id = ENA_ADMIN_MTU; - cmd.u.mtu.mtu = mtu; + cmd.u.mtu.mtu = (u32)mtu; ret = ena_com_execute_admin_command(admin_queue, (struct ena_admin_aq_entry *)&cmd, @@ -2691,7 +2691,7 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) return ret; } - cmd.control_buffer.length = (1ULL << rss->tbl_log_size) * + cmd.control_buffer.length = (u32)(1ULL << rss->tbl_log_size) * sizeof(struct ena_admin_rss_ind_table_entry); ret = ena_com_execute_admin_command(admin_queue, @@ -2713,7 +2713,7 @@ int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl) u32 tbl_size; int i, rc; - tbl_size = (1ULL << rss->tbl_log_size) * + tbl_size = (u32)(1ULL << rss->tbl_log_size) * sizeof(struct ena_admin_rss_ind_table_entry); rc = ena_com_get_feature_ex(ena_dev, &get_resp, From patchwork Tue May 11 06:45:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93134 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C0DD6A0C41; Tue, 11 May 2021 08:46:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9420F4112B; Tue, 11 May 2021 08:46:23 +0200 (CEST) Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) by mails.dpdk.org (Postfix) with ESMTP id 933D641113 for ; Tue, 11 May 2021 08:46:19 +0200 (CEST) Received: by mail-lf1-f44.google.com with SMTP id j10so27004893lfb.12 for ; Mon, 10 May 2021 23:46:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U++me9Uo+RxTcKEW87OLMRk/o2dg1jXQbeLFqWm2Jek=; b=NY7k7mu3SRUIkSuU3TQcqzJ6M7TrOsAmthc2vS9DBTIbiuPA4Ka9f4CzNT3Lez2Ms+ ku43MNmrpJtUhejKrHvH7+ehtGaFMiuARveIr0HX/dQePNmNGfowEqSMuLTOfat196yT 5bqj6HwTzCMYv0c9j/vWZKDTULh2ShzEo6brfiekrtmaYW7F9eEPeMVjB9D0d63k4YTK jEFd92lAxHVo7AZhjM5ZfNbWcdlXyTvTgV8JAhW6iMIN9GW6n8Z/e1iIKl6LWByTpwdD M7wku/GzuVld3xsg3s/BWclOSBBsdLtxlhAFSpacSG1hCy1pGH89Hksh8lAys3sPW9lL teeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U++me9Uo+RxTcKEW87OLMRk/o2dg1jXQbeLFqWm2Jek=; b=UWz0+eIhMYigHuJjtw2FRCMDJr2wG/MT56sDHqj6ZP+BgqWeWvEQzM87Tr+eH8qd4o H7kYC/3+syaXGNNAbR2HIiYFbWyzW79LfsOtYPJKPBYrgcINN01gXQdo9KNjdmSmN0JT UYxT74TWBMLXZbkpzsRoGsfyUGZPWePHIG12vyKQIiFrhWRuuvqAX9SFks3YBfqhI3EP B6zX64qkpki9kAHI/Y++V6bD080DvUwXtGe08Mu9MtU06ZlA2rB5v5dQ3qCIkOo+oLYX h9Kbi/YXWKnWzDi3GarEPrS6/qBPxRBMzq6CzB24H3fSWk8M1UURZLKykaJw1xWTD9WP rIQQ== X-Gm-Message-State: AOAM532MUae1WT6k1fDeamOOrjnHkXm9o0Qc6RrJbfAXbcmd/1fGxNUY ExaXvT2xAHMPBRfeLszeqI0PkQ== X-Google-Smtp-Source: ABdhPJx4XZyp4+ZMzPAkmqDhVHwZICbIiH+ElAWxblIWivQV5IlGvsPYNFyUwiOqUO0N0+BGkBUvPw== X-Received: by 2002:a05:6512:234d:: with SMTP id p13mr19930983lfu.470.1620715579253; Mon, 10 May 2021 23:46:19 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:18 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk , stable@dpdk.org Date: Tue, 11 May 2021 08:45:41 +0200 Message-Id: <20210511064554.10656-7-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 06/19] net/ena/base: destroy multiple "wait events" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Although the ENA DPDK PMD doesn't have to perform any actions for destroying the wait event, some other platforms have to. The macro "ENA_WAIT_EVENT_DESTROY" was renamed to "ENA_WAIT_EVENTS_DESTROY" and also whole implementation responsible for that was moved to a separate function for better readability. Fixes: 3adcba9a8987 ("net/ena: update HAL to the newer version") Cc: stable@dpdk.org Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- v4: * Revert changes to the "ENA_WAIT_EVENT_DESTROY". * Change name of the argument of "ENA_WAIT_EVENTS_DESTROY" to the "admin_queue". * Add stable dpdk as cc. drivers/net/ena/base/ena_com.c | 24 +++++++++++++++++------- drivers/net/ena/base/ena_plat_dpdk.h | 2 +- 2 files changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index 0cdeb1a2d9..d025c9cee1 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -1671,6 +1671,22 @@ int ena_com_validate_version(struct ena_com_dev *ena_dev) return 0; } +static void +ena_com_free_ena_admin_queue_comp_ctx(struct ena_com_dev *ena_dev, + struct ena_com_admin_queue *admin_queue) + +{ + if (!admin_queue->comp_ctx) + return; + + ENA_WAIT_EVENTS_DESTROY(admin_queue); + ENA_MEM_FREE(ena_dev->dmadev, + admin_queue->comp_ctx, + (admin_queue->q_depth * sizeof(struct ena_comp_ctx))); + + admin_queue->comp_ctx = NULL; +} + void ena_com_admin_destroy(struct ena_com_dev *ena_dev) { struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; @@ -1679,14 +1695,8 @@ void ena_com_admin_destroy(struct ena_com_dev *ena_dev) struct ena_com_aenq *aenq = &ena_dev->aenq; u16 size; - if (admin_queue->comp_ctx) { - ENA_WAIT_EVENT_DESTROY(admin_queue->comp_ctx->wait_event); - ENA_MEM_FREE(ena_dev->dmadev, - admin_queue->comp_ctx, - (admin_queue->q_depth * sizeof(struct ena_comp_ctx))); - } + ena_com_free_ena_admin_queue_comp_ctx(ena_dev, admin_queue); - admin_queue->comp_ctx = NULL; size = ADMIN_SQ_SIZE(admin_queue->q_depth); if (sq->entries) ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, sq->entries, diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index df2fdd30f6..ddf54f0ad5 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -299,7 +299,7 @@ extern rte_atomic32_t ena_alloc_cnt; #define ENA_TIME_EXPIRE(timeout) (timeout < rte_get_timer_cycles()) #define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles()) -#define ENA_WAIT_EVENT_DESTROY(waitqueue) ((void)(waitqueue)) +#define ENA_WAIT_EVENTS_DESTROY(admin_queue) ((void)(admin_queue)) #ifndef READ_ONCE #define READ_ONCE(var) (*((volatile typeof(var) *)(&(var)))) From patchwork Tue May 11 06:45:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93135 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 39ADEA0C41; Tue, 11 May 2021 08:47:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3197141134; Tue, 11 May 2021 08:46:25 +0200 (CEST) Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) by mails.dpdk.org (Postfix) with ESMTP id 0E00B41124 for ; Tue, 11 May 2021 08:46:21 +0200 (CEST) Received: by mail-lf1-f43.google.com with SMTP id a2so6042861lfc.9 for ; Mon, 10 May 2021 23:46:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; 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[89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:19 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk , Amit Bernstein Date: Tue, 11 May 2021 08:45:42 +0200 Message-Id: <20210511064554.10656-8-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 07/19] net/ena/base: remove indir table from ENA feat ctx X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The RSS indirection table shouldn't be included as a part of the device features context. If the driver has to acquire it, it can be done using the separate API whenever the RSS configuration is needed. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_com.c | 11 ----------- drivers/net/ena/base/ena_com.h | 1 - 2 files changed, 12 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index d025c9cee1..5ca36ab6d9 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -2054,17 +2054,6 @@ int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, else return rc; - rc = ena_com_get_feature(ena_dev, &get_resp, - ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG, 0); - if (!rc) - memcpy(&get_feat_ctx->ind_table, &get_resp.u.ind_table, - sizeof(get_resp.u.ind_table)); - else if (rc == ENA_COM_UNSUPPORTED) - memset(&get_feat_ctx->ind_table, 0x0, - sizeof(get_feat_ctx->ind_table)); - else - return rc; - return 0; } diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h index cd116e90e6..ca84e2e8bc 100644 --- a/drivers/net/ena/base/ena_com.h +++ b/drivers/net/ena/base/ena_com.h @@ -338,7 +338,6 @@ struct ena_com_dev_get_features_ctx { struct ena_admin_feature_offload_desc offload; struct ena_admin_ena_hw_hints hw_hints; struct ena_admin_feature_llq_desc llq; - struct ena_admin_feature_rss_ind_table ind_table; }; struct ena_com_create_io_ctx { From patchwork Tue May 11 06:45:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93136 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 039B5A0C41; Tue, 11 May 2021 08:47:15 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 69E684113F; Tue, 11 May 2021 08:46:27 +0200 (CEST) Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) by mails.dpdk.org (Postfix) with ESMTP id 622E541127 for ; Tue, 11 May 2021 08:46:22 +0200 (CEST) Received: by mail-lj1-f177.google.com with SMTP id w4so23778593ljw.9 for ; Mon, 10 May 2021 23:46:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OftqcSoM7GSchnu3STuHtE/G9PoTgF936ml4WKhFBT4=; b=rATiCieiLxXMDON2UmoTRhSUZk/dYeafnFcE3c3JRIyaFghSioi4beqv5GrX6PkIIi eOvlETUDILC3wIl1arawCV8XNQqF8aOLxSYt7OzoQx06B56PNKNMsI4EADZvZejfFKtg s9K+/wmy4EVCy9F8o3YYmB+zPFYAyceAHKAaRjnnJeMz7md9Qrrxibu4ELQopr58VQKe O0o5ojXUWmjcuixvIWi9tSPyeLl/EOaqvrCd0c/UPEqhRKHitUbDdyHrqB4L++ZEpZOY AptPG51XPW6FGOjawo4Sumi56JoJxVQ4t50scPGdgRRnxpqO7cVoiXNsUBJwoMdEolHC 8p6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OftqcSoM7GSchnu3STuHtE/G9PoTgF936ml4WKhFBT4=; b=Ee9MJS0Sp8cu/JWSS4KwoqKOcJJC8YyW3Wk4ssUxnvMCpISvrGLtjUA26Nywhl03Eo rcK+e2loDRDuDuCP2fow3gYZnkUgG6pOaNjDyS6or24S5/lPd8by4zTJduDSRWdG2ud8 juxGUfbeZwLy7ZEKxOiIG4QA1hBx4CYfOscfsrBUFZOAeD/75iIkjtsces6BrkE/GTa6 oCk2i7cDkap8k9DBbVMiFu6MBwDh6yD4awzQsItQZR6ASnsjH1S1ZAjdEddnbhXaTCyx P2a5j4uE7bkW6NyYcMJ+GMiMxj04L8kz0VepcXKSjJnTC+SxfOXaWfpvwb5wHfSuP/cI 98eg== X-Gm-Message-State: AOAM530SGaAczjlrgyXgqLAxyleK1yJDI9AiAc1Q88vxiYL5uaHC1l4F RdEL+kJvwvNkCyRvMbFIDfppJw== X-Google-Smtp-Source: ABdhPJzopgEJbDJzeiRHrd1m3gA7nTZa2vxy7Nk9GzL9nlMjYk9cCbqGrSOu6yVWX8OEK1zv7ZcOdg== X-Received: by 2002:a2e:9648:: with SMTP id z8mr23057215ljh.328.1620715582103; Mon, 10 May 2021 23:46:22 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:21 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk , Shay Agroskin Date: Tue, 11 May 2021 08:45:43 +0200 Message-Id: <20210511064554.10656-9-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 08/19] net/ena/base: remove mutable RSS from the host info X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This feature wasn't used by any of the drivers. Because of that, it was removed. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin --- drivers/net/ena/base/ena_defs/ena_admin_defs.h | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/net/ena/base/ena_defs/ena_admin_defs.h b/drivers/net/ena/base/ena_defs/ena_admin_defs.h index 40c2db717c..56768e1a1b 100644 --- a/drivers/net/ena/base/ena_defs/ena_admin_defs.h +++ b/drivers/net/ena/base/ena_defs/ena_admin_defs.h @@ -866,7 +866,7 @@ struct ena_admin_host_info { uint16_t reserved; - /* 0 : mutable_rss_table_size + /* 0 : reserved * 1 : rx_offset * 2 : interrupt_moderation * 3 : rx_buf_mirroring @@ -1189,7 +1189,6 @@ struct ena_admin_ena_mmio_req_read_less_resp { #define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) #define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8 #define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) -#define ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK BIT(0) #define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1) #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2 @@ -1619,16 +1618,6 @@ static inline void set_ena_admin_host_info_bus(struct ena_admin_host_info *p, ui p->bdf |= (val << ENA_ADMIN_HOST_INFO_BUS_SHIFT) & ENA_ADMIN_HOST_INFO_BUS_MASK; } -static inline uint32_t get_ena_admin_host_info_mutable_rss_table_size(const struct ena_admin_host_info *p) -{ - return p->driver_supported_features & ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK; -} - -static inline void set_ena_admin_host_info_mutable_rss_table_size(struct ena_admin_host_info *p, uint32_t val) -{ - p->driver_supported_features |= val & ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK; -} - static inline uint32_t get_ena_admin_host_info_rx_offset(const struct ena_admin_host_info *p) { return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK) >> ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT; From patchwork Tue May 11 06:45:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93137 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8ADE6A0C41; Tue, 11 May 2021 08:47:21 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 88D1D4111A; Tue, 11 May 2021 08:46:28 +0200 (CEST) Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) by mails.dpdk.org (Postfix) with ESMTP id B1C7E4112D for ; Tue, 11 May 2021 08:46:23 +0200 (CEST) Received: by mail-lf1-f52.google.com with SMTP id x19so27077382lfa.2 for ; Mon, 10 May 2021 23:46:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bEUI6vV9dHgqKL+43wC567npysK8dUD1d52yCAgs70s=; b=ICPO9OWe+bmTSwTY4/C1KP9SoUSn2ZgB8ETVd7aLQikeFVYVD58fDr1fKVvcTcGqzC W2dlH8eQwW9UC19yUeHE2Mc78BAYLQ4V9UFJvoa3jImvAuxkPHbimRt3w4Ou0kntDTfv nC2MgoxeORxo+8YxUONeREv6y2DjlfWhNopH+1NT/M7MzIefqsKZcGxQVS+G+BbmgNjy J/STwfqK7yZHSE3MiTpPM72X+bHqgws/eIzls1ptVJhYRmoP3PNWKExjw2lDrWxRijQq HguD1Am+Sn96EXqPspsMW05M/D/7cKFdUdNIq6RYFDyKg+JnAXJBpFNol64XMSYIFd7f Mnuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bEUI6vV9dHgqKL+43wC567npysK8dUD1d52yCAgs70s=; b=eAuvw81cdRaS5mlbyqLWuYRWV4FWlEfQWhDc06jkSknRcSwiqwAAakggHL+o7Uizaj ZB4We7Qj9xFO3E4wL+3lwfh02NMEPGcMl1rE8QYnGjflTPVNj8uCAPFleGTtRmgMBRHW iGWsxml2X457zBuAtzucVAQX3sioVO98kptsSZy59aAADXcw/QAGI4TCUwRTvp+kg3E8 /RYa39V2IrgZ1ztyWCjG+JUOWobldkzbe0HFAcAUw87NBLn6UtGk078w78XYDunKmqSa RfFFumZ1YXAA+fSZxGxRZXoRrjT0SGR6dqkzahVFsZ1hg8pbwnzfMnPcrjFOcgG8svEJ svoA== X-Gm-Message-State: AOAM532/1MNiH0wyhb5tWwoi5VvqdnuHmhAAjLQFcfMWcs/ln49UTYLt kwavr4n3qLXKUU1J/sAEkLHDjQ== X-Google-Smtp-Source: ABdhPJxOP/PsaTd/DTP1lVxnEAQtqFsmcnpMPh9inDqNSCfX5y+eamJkHj2kko4yAMSZmwtg7P2qZw== X-Received: by 2002:a05:6512:374b:: with SMTP id a11mr19352944lfs.377.1620715583373; Mon, 10 May 2021 23:46:23 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:22 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk , Amit Bernstein Date: Tue, 11 May 2021 08:45:44 +0200 Message-Id: <20210511064554.10656-10-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 09/19] net/ena/base: use rte prefetch0 write X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" As in the v20.11 rte_prefetch0_write API was added, it should be used in the platform file for the definition of the macro prefetchw, instead of using simply prefetch0. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Amit Bernstein --- v4: * Fix commit heading style. drivers/net/ena/base/ena_plat_dpdk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index ddf54f0ad5..9d1426da0b 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -291,7 +291,7 @@ extern rte_atomic32_t ena_alloc_cnt; #define might_sleep() #define prefetch(x) rte_prefetch0(x) -#define prefetchw(x) prefetch(x) +#define prefetchw(x) rte_prefetch0_write(x) #define lower_32_bits(x) ((uint32_t)(x)) #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16)) From patchwork Tue May 11 06:45:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93138 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 84FCDA0C41; Tue, 11 May 2021 08:47:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B935641143; Tue, 11 May 2021 08:46:29 +0200 (CEST) Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) by mails.dpdk.org (Postfix) with ESMTP id 2E7BC41131 for ; Tue, 11 May 2021 08:46:25 +0200 (CEST) Received: by mail-lf1-f47.google.com with SMTP id m11so10607155lfg.3 for ; Mon, 10 May 2021 23:46:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R2BPzNOlqsMnmqR95sxzbWtPtXDh74knm/Lqz6A19Zc=; b=EISqZXSHn1K7DHsHdZMpxPLA0Vkqu2fwpBcgm5VYPhNOqOrvDjOir+36My/5n8W/J3 od8Sd2zXNwO/35gSGDQiBgVVKimLmshbqEHAzcuBECBTBA0actA/3AsbJ1LzcL21tl1z TRbktRCqhEeviFUcAHNxmrnu/qf+40/oLNN9Tzdsx9ko8bgUSN+kKlTzPCxIbNNG2uME tvb21nSnQhKcJfVsky0/OU0pA/BjU3m8h9tgcC7LPA8pnhJVstD0s2jKfoxcPk19Q9eX N8oxmS7U+zVaeYlljTT86xCuUFatfNgtSw9un1acfVftz2oWx3WbUUx5pGUJAyPbEKZ6 NVYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R2BPzNOlqsMnmqR95sxzbWtPtXDh74knm/Lqz6A19Zc=; b=dGd/CbcLzuTB/5FEpPEKLIkXeX8IV/Ae/tbjZpqP1Teoz2xEdePKVoFLdAEwV75lyd S2ciJI11CsuPhuTHIJSbAjxey3sI4+Dnp+VpN4qOC45TZd9QppfbkuNEhWNGps+gOOKO 2kFImAAaYHZPtJR9iQ8Q8pns2udby1HJmflJO1sEYKC8myC8RJK2BH9VOCB96QNgpRB/ cT4mn5kDBeZtTlNITxASA8ERtOL3KKqp5U0x0QV4n3yFXM4VCiUvktSE56AyLb0G7pec WcwHSy49QkQqwzVaLtadjqhYaKz3MPUsUAx0mzvz5weZPu74gztKmRMqexJGoxpvkl0d jHIQ== X-Gm-Message-State: AOAM5336q/pgf5I5/VCK/5x2CNoUQ1/kxiqaOyjgJRSMvQ8/TFlw2Rfa 0ZGc+TDHMIHLEkZd3mM9fRDvZQ== X-Google-Smtp-Source: ABdhPJznqHfJV70xSFmaKu8FFNbuzkmLCDhPL0CyZtlZ3PjXcRbsLrBZr2Mjo1IDQn2skCqbktR80g== X-Received: by 2002:a05:6512:3056:: with SMTP id b22mr19175164lfb.526.1620715584773; Mon, 10 May 2021 23:46:24 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:24 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Amit Bernstein , Shay Agroskin , Michal Krawczyk Date: Tue, 11 May 2021 08:45:45 +0200 Message-Id: <20210511064554.10656-11-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 10/19] net/ena/base: adjust changes to lastest ena-com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Amit Bernstein 1. As memzone uses unique names, changed alloc coherent macro to use 64 bit size atomic variable to increase the memzone name space 2. "handle" param name change to be consistent with other macros 3. Variable definition displacement 4. Backslash alignment to column 80 Signed-off-by: Amit Bernstein Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin Reviewed-by: Michal Krawczyk --- v4: * Fix multiple checkpatch warnings. drivers/net/ena/base/ena_plat_dpdk.h | 256 +++++++++++++-------------- drivers/net/ena/ena_ethdev.c | 2 +- 2 files changed, 122 insertions(+), 136 deletions(-) diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index 9d1426da0b..13264d021b 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -34,10 +34,12 @@ typedef uint8_t u8; typedef struct rte_eth_dev ena_netdev; typedef uint64_t dma_addr_t; + #ifndef ETIME #define ETIME ETIMEDOUT #endif +#define ENA_PRIu64 PRIu64 #define ena_atomic32_t rte_atomic32_t #define ena_mem_handle_t const struct rte_memzone * @@ -76,7 +78,7 @@ typedef uint64_t dma_addr_t; #define __iomem #define US_PER_S 1000000 -#define ENA_GET_SYSTEM_USECS() \ +#define ENA_GET_SYSTEM_USECS() \ (rte_get_timer_cycles() * US_PER_S / rte_get_timer_hz()) extern int ena_logtype_com; @@ -95,20 +97,20 @@ extern int ena_logtype_com; #define BIT(nr) (1UL << (nr)) #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) #define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) -#define GENMASK_ULL(h, l) (((~0ULL) - (1ULL << (l)) + 1) & \ +#define GENMASK_ULL(h, l) (((~0ULL) - (1ULL << (l)) + 1) & \ (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) #ifdef RTE_LIBRTE_ENA_COM_DEBUG -#define ena_trc_log(dev, level, fmt, arg...) \ - ( \ - ENA_TOUCH(dev), \ - rte_log(RTE_LOG_ ## level, ena_logtype_com, \ - "[ENA_COM: %s]" fmt, __func__, ##arg) \ +#define ena_trc_log(dev, level, fmt, arg...) \ + ( \ + ENA_TOUCH(dev), \ + rte_log(RTE_LOG_ ## level, ena_logtype_com, \ + "[ENA_COM: %s]" fmt, __func__, ##arg) \ ) #define ena_trc_dbg(dev, format, arg...) ena_trc_log(dev, DEBUG, format, ##arg) #define ena_trc_info(dev, format, arg...) ena_trc_log(dev, INFO, format, ##arg) -#define ena_trc_warn(dev, format, arg...) \ +#define ena_trc_warn(dev, format, arg...) \ ena_trc_log(dev, WARNING, format, ##arg) #define ena_trc_err(dev, format, arg...) ena_trc_log(dev, ERR, format, ##arg) #else @@ -118,51 +120,51 @@ extern int ena_logtype_com; #define ena_trc_err(dev, format, arg...) ENA_TOUCH(dev) #endif /* RTE_LIBRTE_ENA_COM_DEBUG */ -#define ENA_WARN(cond, dev, format, arg...) \ - do { \ - if (unlikely(cond)) { \ - ena_trc_err(dev, \ - "Warn failed on %s:%s:%d:" format, \ - __FILE__, __func__, __LINE__, ##arg); \ - } \ +#define ENA_WARN(cond, dev, format, arg...) \ + do { \ + if (unlikely(cond)) { \ + ena_trc_err(dev, \ + "Warn failed on %s:%s:%d:" format, \ + __FILE__, __func__, __LINE__, ##arg); \ + } \ } while (0) /* Spinlock related methods */ #define ena_spinlock_t rte_spinlock_t -#define ENA_SPINLOCK_INIT(spinlock) rte_spinlock_init(&spinlock) -#define ENA_SPINLOCK_LOCK(spinlock, flags) \ - ({(void)flags; rte_spinlock_lock(&spinlock); }) -#define ENA_SPINLOCK_UNLOCK(spinlock, flags) \ +#define ENA_SPINLOCK_INIT(spinlock) rte_spinlock_init(&(spinlock)) +#define ENA_SPINLOCK_LOCK(spinlock, flags) \ + ({(void)flags; rte_spinlock_lock(&(spinlock)); }) +#define ENA_SPINLOCK_UNLOCK(spinlock, flags) \ ({(void)flags; rte_spinlock_unlock(&(spinlock)); }) -#define ENA_SPINLOCK_DESTROY(spinlock) ((void)spinlock) +#define ENA_SPINLOCK_DESTROY(spinlock) ((void)(spinlock)) -#define q_waitqueue_t \ - struct { \ - pthread_cond_t cond; \ - pthread_mutex_t mutex; \ +#define q_waitqueue_t \ + struct { \ + pthread_cond_t cond; \ + pthread_mutex_t mutex; \ } #define ena_wait_queue_t q_waitqueue_t -#define ENA_WAIT_EVENT_INIT(waitqueue) \ - do { \ - pthread_mutex_init(&(waitqueue).mutex, NULL); \ - pthread_cond_init(&(waitqueue).cond, NULL); \ +#define ENA_WAIT_EVENT_INIT(waitqueue) \ + do { \ + pthread_mutex_init(&(waitqueue).mutex, NULL); \ + pthread_cond_init(&(waitqueue).cond, NULL); \ } while (0) -#define ENA_WAIT_EVENT_WAIT(waitevent, timeout) \ - do { \ - struct timespec wait; \ - struct timeval now; \ - unsigned long timeout_us; \ - gettimeofday(&now, NULL); \ - wait.tv_sec = now.tv_sec + timeout / 1000000UL; \ - timeout_us = timeout % 1000000UL; \ - wait.tv_nsec = (now.tv_usec + timeout_us) * 1000UL; \ - pthread_mutex_lock(&waitevent.mutex); \ - pthread_cond_timedwait(&waitevent.cond, \ - &waitevent.mutex, &wait); \ - pthread_mutex_unlock(&waitevent.mutex); \ +#define ENA_WAIT_EVENT_WAIT(waitevent, timeout) \ + do { \ + struct timespec wait; \ + struct timeval now; \ + unsigned long timeout_us; \ + gettimeofday(&now, NULL); \ + wait.tv_sec = now.tv_sec + (timeout) / 1000000UL; \ + timeout_us = (timeout) % 1000000UL; \ + wait.tv_nsec = (now.tv_usec + timeout_us) * 1000UL; \ + pthread_mutex_lock(&(waitevent).mutex); \ + pthread_cond_timedwait(&(waitevent).cond, \ + &(waitevent).mutex, &wait); \ + pthread_mutex_unlock(&(waitevent).mutex); \ } while (0) #define ENA_WAIT_EVENT_SIGNAL(waitevent) pthread_cond_signal(&waitevent.cond) /* pthread condition doesn't need to be rearmed after usage */ @@ -174,104 +176,90 @@ extern int ena_logtype_com; #define ena_time_t uint64_t #define ENA_TIME_EXPIRE(timeout) (timeout < rte_get_timer_cycles()) -#define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ - (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles()) +#define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ + ((timeout_us) * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles()) /* * Each rte_memzone should have unique name. * To satisfy it, count number of allocations and add it to name. */ -extern rte_atomic32_t ena_alloc_cnt; - -#define ENA_MEM_ALLOC_COHERENT_ALIGNED( \ - dmadev, size, virt, phys, handle, alignment) \ - do { \ - const struct rte_memzone *mz = NULL; \ - ENA_TOUCH(dmadev); ENA_TOUCH(handle); \ - if (size > 0) { \ - char z_name[RTE_MEMZONE_NAMESIZE]; \ - snprintf(z_name, sizeof(z_name), \ - "ena_alloc_%d", \ - rte_atomic32_add_return(&ena_alloc_cnt, 1)); \ - mz = rte_memzone_reserve_aligned(z_name, size, \ - SOCKET_ID_ANY, \ - RTE_MEMZONE_IOVA_CONTIG, \ - alignment); \ - handle = mz; \ - } \ - if (mz == NULL) { \ - virt = NULL; \ - phys = 0; \ - } else { \ - memset(mz->addr, 0, size); \ - virt = mz->addr; \ - phys = mz->iova; \ - } \ +extern rte_atomic64_t ena_alloc_cnt; + +#define ENA_MEM_ALLOC_COHERENT_ALIGNED( \ + dmadev, size, virt, phys, mem_handle, alignment) \ + do { \ + const struct rte_memzone *mz = NULL; \ + ENA_TOUCH(dmadev); \ + if ((size) > 0) { \ + char z_name[RTE_MEMZONE_NAMESIZE]; \ + snprintf(z_name, sizeof(z_name), \ + "ena_alloc_%" PRIi64 "", \ + rte_atomic64_add_return(&ena_alloc_cnt, 1)); \ + mz = rte_memzone_reserve_aligned(z_name, (size), \ + SOCKET_ID_ANY, RTE_MEMZONE_IOVA_CONTIG,\ + alignment); \ + mem_handle = mz; \ + } \ + if (mz == NULL) { \ + virt = NULL; \ + phys = 0; \ + } else { \ + memset(mz->addr, 0, (size)); \ + virt = mz->addr; \ + phys = mz->iova; \ + } \ } while (0) -#define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, handle) \ - ENA_MEM_ALLOC_COHERENT_ALIGNED( \ - dmadev, \ - size, \ - virt, \ - phys, \ - handle, \ - RTE_CACHE_LINE_SIZE) -#define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, handle) \ - ({ ENA_TOUCH(size); ENA_TOUCH(phys); \ - ENA_TOUCH(dmadev); \ - rte_memzone_free(handle); }) - -#define ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED( \ - dmadev, size, virt, phys, mem_handle, node, dev_node, alignment) \ - do { \ - const struct rte_memzone *mz = NULL; \ - ENA_TOUCH(dmadev); ENA_TOUCH(dev_node); \ - if (size > 0) { \ - char z_name[RTE_MEMZONE_NAMESIZE]; \ - snprintf(z_name, sizeof(z_name), \ - "ena_alloc_%d", \ - rte_atomic32_add_return(&ena_alloc_cnt, 1)); \ - mz = rte_memzone_reserve_aligned(z_name, size, node, \ - RTE_MEMZONE_IOVA_CONTIG, alignment); \ - mem_handle = mz; \ - } \ - if (mz == NULL) { \ - virt = NULL; \ - phys = 0; \ - } else { \ - memset(mz->addr, 0, size); \ - virt = mz->addr; \ - phys = mz->iova; \ - } \ +#define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, mem_handle) \ + ENA_MEM_ALLOC_COHERENT_ALIGNED(dmadev, size, virt, phys, \ + mem_handle, RTE_CACHE_LINE_SIZE) +#define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, mem_handle) \ + ({ ENA_TOUCH(size); ENA_TOUCH(phys); ENA_TOUCH(dmadev); \ + rte_memzone_free(mem_handle); }) + +#define ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED( \ + dmadev, size, virt, phys, mem_handle, node, dev_node, alignment) \ + do { \ + const struct rte_memzone *mz = NULL; \ + ENA_TOUCH(dmadev); ENA_TOUCH(dev_node); \ + if ((size) > 0) { \ + char z_name[RTE_MEMZONE_NAMESIZE]; \ + snprintf(z_name, sizeof(z_name), \ + "ena_alloc_%" PRIi64 "", \ + rte_atomic64_add_return(&ena_alloc_cnt, 1)); \ + mz = rte_memzone_reserve_aligned(z_name, (size), \ + node, RTE_MEMZONE_IOVA_CONTIG, alignment); \ + mem_handle = mz; \ + } \ + if (mz == NULL) { \ + virt = NULL; \ + phys = 0; \ + } else { \ + memset(mz->addr, 0, (size)); \ + virt = mz->addr; \ + phys = mz->iova; \ + } \ } while (0) -#define ENA_MEM_ALLOC_COHERENT_NODE( \ - dmadev, size, virt, phys, mem_handle, node, dev_node) \ - ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED( \ - dmadev, \ - size, \ - virt, \ - phys, \ - mem_handle, \ - node, \ - dev_node, \ - RTE_CACHE_LINE_SIZE) -#define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) \ - do { \ - ENA_TOUCH(dmadev); ENA_TOUCH(dev_node); \ - virt = rte_zmalloc_socket(NULL, size, 0, node); \ +#define ENA_MEM_ALLOC_COHERENT_NODE( \ + dmadev, size, virt, phys, mem_handle, node, dev_node) \ + ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(dmadev, size, virt, phys, \ + mem_handle, node, dev_node, RTE_CACHE_LINE_SIZE) +#define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) \ + do { \ + ENA_TOUCH(dmadev); ENA_TOUCH(dev_node); \ + virt = rte_zmalloc_socket(NULL, size, 0, node); \ } while (0) #define ENA_MEM_ALLOC(dmadev, size) rte_zmalloc(NULL, size, 1) -#define ENA_MEM_FREE(dmadev, ptr, size) \ +#define ENA_MEM_FREE(dmadev, ptr, size) \ ({ ENA_TOUCH(dmadev); ENA_TOUCH(size); rte_free(ptr); }) #define ENA_DB_SYNC(mem_handle) ((void)mem_handle) -#define ENA_REG_WRITE32(bus, value, reg) \ +#define ENA_REG_WRITE32(bus, value, reg) \ ({ (void)(bus); rte_write32((value), (reg)); }) -#define ENA_REG_WRITE32_RELAXED(bus, value, reg) \ +#define ENA_REG_WRITE32_RELAXED(bus, value, reg) \ ({ (void)(bus); rte_write32_relaxed((value), (reg)); }) -#define ENA_REG_READ32(bus, reg) \ +#define ENA_REG_READ32(bus, reg) \ ({ (void)(bus); rte_read32_relaxed((reg)); }) #define ATOMIC32_INC(i32_ptr) rte_atomic32_inc(i32_ptr) @@ -297,8 +285,8 @@ extern rte_atomic32_t ena_alloc_cnt; #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16)) #define ENA_TIME_EXPIRE(timeout) (timeout < rte_get_timer_cycles()) -#define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ - (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles()) +#define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ + ((timeout_us) * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles()) #define ENA_WAIT_EVENTS_DESTROY(admin_queue) ((void)(admin_queue)) #ifndef READ_ONCE @@ -310,14 +298,14 @@ extern rte_atomic32_t ena_alloc_cnt; #define READ_ONCE32(var) READ_ONCE(var) /* The size must be 8 byte align */ -#define ENA_MEMCPY_TO_DEVICE_64(dst, src, size) \ - do { \ - int count, i; \ - uint64_t *to = (uint64_t *)(dst); \ - const uint64_t *from = (const uint64_t *)(src); \ - count = (size) / 8; \ - for (i = 0; i < count; i++, from++, to++) \ - rte_write64_relaxed(*from, to); \ +#define ENA_MEMCPY_TO_DEVICE_64(dst, src, size) \ + do { \ + int count, i; \ + uint64_t *to = (uint64_t *)(dst); \ + const uint64_t *from = (const uint64_t *)(src); \ + count = (size) / 8; \ + for (i = 0; i < count; i++, from++, to++) \ + rte_write64_relaxed(*from, to); \ } while(0) #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) @@ -330,7 +318,5 @@ void ena_rss_key_fill(void *key, size_t size); #define ENA_INTR_INITIAL_TX_INTERVAL_USECS_PLAT 0 -#define ENA_PRIu64 PRIu64 - #include "ena_includes.h" #endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */ diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index f1ff4dad36..3c9102cd19 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -85,7 +85,7 @@ struct ena_stats { * Each rte_memzone should have unique name. * To satisfy it, count number of allocation and add it to name. */ -rte_atomic32_t ena_alloc_cnt; +rte_atomic64_t ena_alloc_cnt; static const struct ena_stats ena_stats_global_strings[] = { ENA_STAT_GLOBAL_ENTRY(wd_expired), From patchwork Tue May 11 06:45:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93139 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B1B65A0C41; Tue, 11 May 2021 08:47:35 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9872141154; Tue, 11 May 2021 08:46:31 +0200 (CEST) Received: from mail-lj1-f179.google.com (mail-lj1-f179.google.com [209.85.208.179]) by mails.dpdk.org (Postfix) with ESMTP id A25244111A for ; Tue, 11 May 2021 08:46:26 +0200 (CEST) Received: by mail-lj1-f179.google.com with SMTP id v5so23765043ljg.12 for ; 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[89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:25 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, stable@dpdk.org, Shay Agroskin , Michal Krawczyk Date: Tue, 11 May 2021 08:45:46 +0200 Message-Id: <20210511064554.10656-12-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 11/19] net/ena: fix parsing of large LLQ header devarg X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Igor Chauskin The code incorrectly checked the return value of comparison when parsing the argument key name. The return value of strcmp should be compared to 0 to identify a match. Fixes: 8a7a73f26cc9 ("net/ena: support large LLQ headers") Cc: stable@dpdk.org Signed-off-by: Igor Chauskin Reviewed-by: Shay Agroskin Reviewed-by: Michal Krawczyk --- v4: * Add release notes. * Fix commit heading style. doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/ena/ena_ethdev.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index 6e4fcde1bc..755d5fcd32 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -209,6 +209,7 @@ New Features * Changed memcpy mapping to the dpdk-optimized version. * Updated ena_com (HAL) to the latest version. + * Fixed bugs when requesting large LLQ headers using the devargs. * **Added support of multiple data-units in cryptodev API.** diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 3c9102cd19..cb8ad5c3d0 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -2865,7 +2865,7 @@ static int ena_process_bool_devarg(const char *key, } /* Now, assign it to the proper adapter field. */ - if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR)) + if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0) adapter->use_large_llq_hdr = bool_value; return 0; From patchwork Tue May 11 06:45:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93140 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 472CAA0C41; Tue, 11 May 2021 08:47:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E54824115A; Tue, 11 May 2021 08:46:32 +0200 (CEST) Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) by mails.dpdk.org (Postfix) with ESMTP id EBC3641142 for ; Tue, 11 May 2021 08:46:27 +0200 (CEST) Received: by mail-lf1-f41.google.com with SMTP id x2so27019036lff.10 for ; Mon, 10 May 2021 23:46:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8qPrxRFwFGeW1O5g5Fpv0S1w/mScFeGzPp0onxAutk4=; b=j4NZG5jMXm/877oZkswOeiQpG37acvotTzv5NMiOmF3DPlIaGCmL9WFTEcD8+l3Ivb iXCoaLdfUtCFlZ4h33rB1zbFDvydxirCx7o8zLXI7CCU6QpFUgifGzfssIBJmTgoqWYi 0elIfbkjilfVjNiyKmovUoKyDCDtCjcAAq5JyMHTQaF9swsvHwC3DWnhepNbgbd9q3Ci Vc1Vl4VqX2S4q4GAJoW200Wj7wTJyqw981vj6hE4vM3SGJCjj/qI/XFI8i/dHuZoseNg bvi/8iLUv+3p6GGqjmjMUU2Kpa1xVbFKePe0sjyvd4BGiHkEtQDf/sXpSagdkR9ItM/R U9Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8qPrxRFwFGeW1O5g5Fpv0S1w/mScFeGzPp0onxAutk4=; b=Nl1GAKe7jVG/rOXyOmYO5y1NyBAQBww1VakPlmZaOXUjCE/Z6SLV4H83F9gRkSmC5K Jpi3kHxudldZs312AuCx1hmBsSAD14n6I1ZxB/F/EAKNR+b/wIfOJOqdwrPppoTKsxX+ DIigtIKW5tuECbv94endH6xdqlFEU8wkJv4locBUCk3s7le3tiOgXy0xPDjG0Cc0Vvjk 1ohdHHfqGVzQHaEPeYp7AAFt06YDvbu6VC1WXKK5vJ3HORoIqhyiayXGJv6y4c36+dV2 RGhEhZ8CoaUIpuDiX83RGBBifD2RXevA6kKHHEW/eACLp9TN06b20CguCqp0YEBjn8NW wZNA== X-Gm-Message-State: AOAM533subGysixXH1QvdKbiDDZ55+q2gzEFz5sGoZTfv9rPKKrZXZEb H6KnrqQMY4gncq2VOHqgyNVL8w== X-Google-Smtp-Source: ABdhPJwwIT0kfhsOUVs9i0haUu+0nGdp3upwFt20V9irP/xh++jh8suHnmp0wHB2gDmgZMW45steSA== X-Received: by 2002:a05:6512:3455:: with SMTP id j21mr11455222lfr.235.1620715587621; Mon, 10 May 2021 23:46:27 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:26 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk , stable@dpdk.org, Shay Agroskin Date: Tue, 11 May 2021 08:45:47 +0200 Message-Id: <20210511064554.10656-13-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 12/19] net/ena: terminate devargs allowed keys with null X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" As the documentation of rte_kvargs_parse() states, the valid_keys argument must be NULL terminated. Lack of this feature may cause segmentation fault if the passed devarg will be different then the supported value. Fixes: 8a7a73f26cc9 ("net/ena: support large LLQ headers") Cc: stable@dpdk.org Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin Acked-by: Ferruh Yigit --- v4: * Fix commit heading style. drivers/net/ena/ena_ethdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index cb8ad5c3d0..6092288239 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -2876,6 +2876,7 @@ static int ena_parse_devargs(struct ena_adapter *adapter, { static const char * const allowed_args[] = { ENA_DEVARG_LARGE_LLQ_HDR, + NULL, }; struct rte_kvargs *kvlist; int rc; From patchwork Tue May 11 06:45:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93141 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BE411A0C41; Tue, 11 May 2021 08:47:47 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5E4614115F; Tue, 11 May 2021 08:46:34 +0200 (CEST) Received: from mail-lj1-f174.google.com (mail-lj1-f174.google.com [209.85.208.174]) by mails.dpdk.org (Postfix) with ESMTP id 689B14003E for ; Tue, 11 May 2021 08:46:29 +0200 (CEST) Received: by mail-lj1-f174.google.com with SMTP id y9so23789011ljn.6 for ; Mon, 10 May 2021 23:46:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HU9l+3uNdV5SIRC8MoZiQGNy8s2234T1R11FXkSGrww=; b=AfZkK8+zIWscRW+OtXRZt7iE3PKrcO1mp5/HkW/zOEDbzpxDB8FYT9Ory+Wb9KR1kr JeFBP+6PWWWyBAIayyKXqirKFrsu+na/GR+0ZIHGXrOpQ8zml36KhTnMfHuhAKoPeLnP ycwHpNFSn6BduoA+Z4xIQANJpXlovmmhQPeTUpeW0rveNZtjUBSZJyK7oLvSgS1h/X8f Xb1caOeDC/WGme3a5+Nm/OwOUzWyCcIusbeFe6dXG05BN78x33NRgEvaXpyISxdQZThn I+Cd6UoHVe63AIJuoudthleDEdf9Yn9fG3C1zsHI8CeQ5bKo4sENUfoQe/nx2g3ylsyU ETpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HU9l+3uNdV5SIRC8MoZiQGNy8s2234T1R11FXkSGrww=; b=cIHBIMzNigLbse3kmPmPqf43rNjXPJdlN96XJj5MrfDtj7wg7m1w+PltEPakhhwqDK jouszPL1fV9BqOd1v17tvOobWpjk4QGMWfiZdsL/2Zo00kAqhDrZgnlZUNdR0POTOiR3 cV8MPI0hxnEL4izWkuej+LzfI7EqwiN3MtVfudiSirl3OxwXIsaNggrqJjuDf3TjSxlE bynpUuMy5cYw4mSbtpjaq0A+kOnETsdjgHz0OSI94kP1tKz4ZZQOKbb6Vt8hyn0rH6qP T6GuMuyn/Eu73+BGlV26h2pLv+efOYA5SXQY0knjzOVr5yqYGxVtcZBPtVVC2mt+5cSQ /zkw== X-Gm-Message-State: AOAM531IsAvGWyHmW+agQ1RlRUxjFA0CT/oY2F4d8h6hKQumBBSpe7FG ONGrvnSAsv60ajUuKfX0joeDzQ== X-Google-Smtp-Source: ABdhPJw15/PfucEbUsiXFmTLizWol1588AFm8N0uaSYowSLr2ssgpvmh9MoB/EtW71TPQ7LzPWM35Q== X-Received: by 2002:a2e:161a:: with SMTP id w26mr23118370ljd.436.1620715589106; Mon, 10 May 2021 23:46:29 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:28 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk , stable@dpdk.org, Amit Bernstein Date: Tue, 11 May 2021 08:45:48 +0200 Message-Id: <20210511064554.10656-14-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 13/19] net/ena: indicate Rx RSS hash presence X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" To make it possible to the app to determine if the hash was calculated for the packet or not, the PKT_RX_RSS_HASH should be set in the mbuf's ol_flags. As the PMD wasn't setting that, the application couldn't check if there is a hash in a proper way. The hash is valid only if it's UDP or TCP and the IP packet wasn't fragmented. Fixes: e5df9f33db00 ("net/ena: fix passing RSS hash to mbuf") Cc: stable@dpdk.org Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Amit Bernstein --- v4: * Add release notes. * Always announce DEV_RX_OFFLOAD_RSS_HASH if RSS is enabled. doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/ena/ena_ethdev.c | 12 ++++++++++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index 755d5fcd32..389a7a05ac 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -210,6 +210,7 @@ New Features * Changed memcpy mapping to the dpdk-optimized version. * Updated ena_com (HAL) to the latest version. * Fixed bugs when requesting large LLQ headers using the devargs. + * Added indication of the RSS hash presence in the mbuf. * **Added support of multiple data-units in cryptodev API.** diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 6092288239..9a43ab50fe 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -51,6 +51,8 @@ #define ENA_MIN_RING_DESC 128 +#define ENA_PTYPE_HAS_HASH (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP) + enum ethtool_stringset { ETH_SS_TEST = 0, ETH_SS_STATS, @@ -314,6 +316,11 @@ static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, else ol_flags |= PKT_RX_L4_CKSUM_GOOD; + if (likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) { + ol_flags |= PKT_RX_RSS_HASH; + mbuf->hash.rss = ena_rx_ctx->hash; + } + mbuf->ol_flags = ol_flags; mbuf->packet_type = packet_type; } @@ -1960,6 +1967,9 @@ static int ena_dev_configure(struct rte_eth_dev *dev) adapter->state = ENA_ADAPTER_STATE_CONFIG; + if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) + dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; + adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads; adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads; return 0; @@ -2245,8 +2255,6 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, ++rx_ring->rx_stats.bad_csum; } - mbuf->hash.rss = ena_rx_ctx.hash; - rx_pkts[completed] = mbuf; rx_ring->rx_stats.bytes += mbuf->pkt_len; } From patchwork Tue May 11 06:45:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93142 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6C049A0C41; Tue, 11 May 2021 08:47:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D759641167; Tue, 11 May 2021 08:46:35 +0200 (CEST) Received: from mail-lj1-f172.google.com (mail-lj1-f172.google.com [209.85.208.172]) by mails.dpdk.org (Postfix) with ESMTP id BB83B4110B for ; Tue, 11 May 2021 08:46:30 +0200 (CEST) Received: by mail-lj1-f172.google.com with SMTP id b7so23792978ljr.4 for ; Mon, 10 May 2021 23:46:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gAOAdq/3nI0xT6ujf76EsSvcMe11nEit/A1336hWGkU=; b=PI8ViRXr71NytgsuSgoryzTq4Q/MqPEX+Cqi1hurLclYPHui6V0Z+540PwZ94BKO3u FFZPOjUofU2sF5bAokG6K2ereWvZU1EwDbxIhxaFcUF5p4Dx8KK0HSZdupMIMdvt8ZZe kJFUcq6w9gBo/omuT2Uxqkzk1ehw95sBcyMRbqrWL5LrwS1grjzK4534Ia4pzNQZSWGb bfl8efsstXGpcKkGJbr4l15fUTzVy0IBcZ5qTxT2rKq7/GUmtwCPKqfzWVPC2pNs4p4a nSU1olftmxsnf1cGomaG2y2idVHF7HTA5+5tGZ1+z4hKH5kE8xcFFBB7BzsqKXvm3v4x 8Zew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gAOAdq/3nI0xT6ujf76EsSvcMe11nEit/A1336hWGkU=; b=d+C3OJ2zmup9P4F2JDvG2RTbN9DsDo+Vja0OhKN2QCvYo++RrQZJH8Xj8ZwkbwY8Ho 9OIXPOildB9UjejrR2Tcndx8cc6593dksDECIeKIIaIyZbIayZLBPPcN+zScR31eRT4g Bk2/21jh8nxf6w8/MWC8QgxltxluvrhNn6sQhmrpxTx07K0MWz2VhBPfVqtvexZYmG2+ ZmfsM6BwYgGHaASHihWNvyWcaC15DpmcqLMl1FdY7LO+wvpYHu85IifQfGvvnFyr0DCw WzgsOP5uJrLchtXpJtRPJglw5az3d3jg+BQ/aAZQ+DrkZSLBm6ItdR1uqscxJLPED/Sy HZTw== X-Gm-Message-State: AOAM533lwvm/Q+3hvome3QfDOqTSrz9faP66piV5+0BEDiXG3azUV1sR B/Ec0SDX4M3xfKx9/dG9pfrccw== X-Google-Smtp-Source: ABdhPJxHySoS7uJCctlpM4x65J03LK3thXF1vlaaORiXtfzkntRcdHYnlLseXkbxQcMgzy22MUykvQ== X-Received: by 2002:a2e:8512:: with SMTP id j18mr23893599lji.196.1620715590445; Mon, 10 May 2021 23:46:30 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:29 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Stanislaw Kardach , Michal Krawczyk , Shay Agroskin Date: Tue, 11 May 2021 08:45:49 +0200 Message-Id: <20210511064554.10656-15-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 14/19] net/ena: remove endian swap functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Stanislaw Kardach swap*_*_le() functions are not used anywhere and besides there are rte alternatives already present. Fixes: 1173fca25af9 ("ena: add polling-mode driver") Signed-off-by: Stanislaw Kardach Reviewed-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin --- drivers/net/ena/ena_platform.h | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/net/ena/ena_platform.h b/drivers/net/ena/ena_platform.h index d3e40e0e9e..748928b2d9 100644 --- a/drivers/net/ena/ena_platform.h +++ b/drivers/net/ena/ena_platform.h @@ -6,18 +6,6 @@ #ifndef __ENA_PLATFORM_H__ #define __ENA_PLATFORM_H__ -#define swap16_to_le(x) (x) - -#define swap32_to_le(x) (x) - -#define swap64_to_le(x) (x) - -#define swap16_from_le(x) (x) - -#define swap32_from_le(x) (x) - -#define swap64_from_le(x) (x) - #define ena_assert_msg(cond, msg) \ do { \ if (unlikely(!(cond))) { \ From patchwork Tue May 11 06:45:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93143 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 17D79A0C41; Tue, 11 May 2021 08:48:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 09434410FE; Tue, 11 May 2021 08:46:37 +0200 (CEST) Received: from mail-lj1-f180.google.com (mail-lj1-f180.google.com [209.85.208.180]) by mails.dpdk.org (Postfix) with ESMTP id 17F6641157 for ; Tue, 11 May 2021 08:46:32 +0200 (CEST) Received: by mail-lj1-f180.google.com with SMTP id b7so23793033ljr.4 for ; Mon, 10 May 2021 23:46:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rz71/71Hu/SeU0B7hSRScwyLgKXuMWaMpT9AOXXeDm4=; b=uE1RfGNPFn2yii6117P9/BYOJnM0Mi73IP9TvSA69jn1llccFBJ+MKiq78pqnzgWja RQuE1n9J+00kegjOsg+94q2sjMAja/hbd+UwseFUC1NY72L2BQChYd3gsBsD6xYUR2mN T09ytvCuX/2jDAJ1xH9tC9WHi/L96nufDTYg/oiK+nAnEvnZuk9uvVLP8jKOUMKF354y SOykmHZx4QM7WcUegY8LNJT+tLQgwME+OQGkGKrEwBxez3+NNoWWQhObNKCAFNIs/avx GpODquPeXU92PYTFmWkqZsRR1y0EzUjmRFkL4nPFAaQy5LhVtrLkGqRTXIRjO9zgh3/z Hd8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rz71/71Hu/SeU0B7hSRScwyLgKXuMWaMpT9AOXXeDm4=; b=NWuSEYE4zSgsLfDWvdhWW9ORKiIcgJZczur69Ub0jS1KSK6QLrnr6WP6VG3dmqShAV CPFca1UQAT9GFsOXZA36wuHHm9kC1K/py9FXh7dNN8qc/C8ScQAkKgsQayDL2xfjx+1E GUetq7ZuTWhPSjDtHTqnygrgff6LUfoa5zJRZzDWD+r+afPH8M3D5fbgdHBc++o2rHDT LndxGVN3w+FL6JSN7BTcq7zFBIOy5kBL5QhFSO7CQ61KpLiveoMWtU/fC0zuEwIlO1P0 Ns96v9JYXAxFhmA4I+UxR0I/mSLA17UJiGU1Sb9VjPHont9ooh9ecTUKhrN9fQyjT20/ c1MQ== X-Gm-Message-State: AOAM531LDJDmIEypp+XLr/MV8tN9DLAC4Lq2YbiJh1ChAh9AlTqlw9PI vO7CLJJrEo7Bqrmhvy4ls0da4g== X-Google-Smtp-Source: ABdhPJxRSem6ArsOhajSdZkJvymNxtNgsef7Z/yo4xWeWa88mtDqletHtAPDaJRj9gllFftOo4W1Nw== X-Received: by 2002:a2e:9896:: with SMTP id b22mr23193302ljj.329.1620715591773; Mon, 10 May 2021 23:46:31 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:31 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Stanislaw Kardach , Michal Krawczyk , Shay Agroskin Date: Tue, 11 May 2021 08:45:50 +0200 Message-Id: <20210511064554.10656-16-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 15/19] net/ena: handle spurious wakeups in ENA wait event X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Stanislaw Kardach pthread_cond_timedwait() may spuriously wakeup according to POSIX. Therefore it is required to check whether predicate is actually true before finishing the waiting loop. Signed-off-by: Stanislaw Kardach Reviewed-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin --- v4: * Replace rte_panic with the error log. drivers/net/ena/base/ena_plat_dpdk.h | 73 ++++++++++++++++++---------- 1 file changed, 46 insertions(+), 27 deletions(-) diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index 13264d021b..f66df95591 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -77,6 +77,14 @@ typedef uint64_t dma_addr_t; #define mmiowb rte_io_wmb #define __iomem +#ifndef READ_ONCE +#define READ_ONCE(var) (*((volatile typeof(var) *)(&(var)))) +#endif + +#define READ_ONCE8(var) READ_ONCE(var) +#define READ_ONCE16(var) READ_ONCE(var) +#define READ_ONCE32(var) READ_ONCE(var) + #define US_PER_S 1000000 #define ENA_GET_SYSTEM_USECS() \ (rte_get_timer_cycles() * US_PER_S / rte_get_timer_hz()) @@ -138,40 +146,59 @@ extern int ena_logtype_com; ({(void)flags; rte_spinlock_unlock(&(spinlock)); }) #define ENA_SPINLOCK_DESTROY(spinlock) ((void)(spinlock)) -#define q_waitqueue_t \ - struct { \ - pthread_cond_t cond; \ - pthread_mutex_t mutex; \ - } +typedef struct { + pthread_cond_t cond; + pthread_mutex_t mutex; + uint8_t flag; +} ena_wait_event_t; -#define ena_wait_queue_t q_waitqueue_t - -#define ENA_WAIT_EVENT_INIT(waitqueue) \ +#define ENA_WAIT_EVENT_INIT(waitevent) \ do { \ - pthread_mutex_init(&(waitqueue).mutex, NULL); \ - pthread_cond_init(&(waitqueue).cond, NULL); \ + ena_wait_event_t *_we = &(waitevent); \ + pthread_mutex_init(&_we->mutex, NULL); \ + pthread_cond_init(&_we->cond, NULL); \ + _we->flag = 0; \ } while (0) #define ENA_WAIT_EVENT_WAIT(waitevent, timeout) \ do { \ + ena_wait_event_t *_we = &(waitevent); \ + typeof(timeout) _tmo = (timeout); \ + int ret = 0; \ struct timespec wait; \ struct timeval now; \ unsigned long timeout_us; \ gettimeofday(&now, NULL); \ - wait.tv_sec = now.tv_sec + (timeout) / 1000000UL; \ - timeout_us = (timeout) % 1000000UL; \ + wait.tv_sec = now.tv_sec + _tmo / 1000000UL; \ + timeout_us = _tmo % 1000000UL; \ wait.tv_nsec = (now.tv_usec + timeout_us) * 1000UL; \ - pthread_mutex_lock(&(waitevent).mutex); \ - pthread_cond_timedwait(&(waitevent).cond, \ - &(waitevent).mutex, &wait); \ - pthread_mutex_unlock(&(waitevent).mutex); \ + pthread_mutex_lock(&_we->mutex); \ + while (ret == 0 && !_we->flag) { \ + ret = pthread_cond_timedwait(&_we->cond, \ + &_we->mutex, &wait); \ + } \ + /* Asserts only if not working on ena_wait_event_t */ \ + if (unlikely(ret != 0 && ret != ETIMEDOUT)) \ + ena_trc_err(NULL, \ + "Invalid wait event. pthread ret: %d\n", ret); \ + else if (unlikely(ret == ETIMEDOUT)) \ + ena_trc_err(NULL, \ + "Timeout waiting for " #waitevent "\n"); \ + _we->flag = 0; \ + pthread_mutex_unlock(&_we->mutex); \ + } while (0) +#define ENA_WAIT_EVENT_SIGNAL(waitevent) \ + do { \ + ena_wait_event_t *_we = &(waitevent); \ + pthread_mutex_lock(&_we->mutex); \ + _we->flag = 1; \ + pthread_cond_signal(&_we->cond); \ + pthread_mutex_unlock(&_we->mutex); \ } while (0) -#define ENA_WAIT_EVENT_SIGNAL(waitevent) pthread_cond_signal(&waitevent.cond) /* pthread condition doesn't need to be rearmed after usage */ #define ENA_WAIT_EVENT_CLEAR(...) -#define ENA_WAIT_EVENT_DESTROY(waitqueue) ((void)(waitqueue)) +#define ENA_WAIT_EVENT_DESTROY(waitevent) ((void)(waitevent)) -#define ena_wait_event_t ena_wait_queue_t #define ENA_MIGHT_SLEEP() #define ena_time_t uint64_t @@ -289,14 +316,6 @@ extern rte_atomic64_t ena_alloc_cnt; ((timeout_us) * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles()) #define ENA_WAIT_EVENTS_DESTROY(admin_queue) ((void)(admin_queue)) -#ifndef READ_ONCE -#define READ_ONCE(var) (*((volatile typeof(var) *)(&(var)))) -#endif - -#define READ_ONCE8(var) READ_ONCE(var) -#define READ_ONCE16(var) READ_ONCE(var) -#define READ_ONCE32(var) READ_ONCE(var) - /* The size must be 8 byte align */ #define ENA_MEMCPY_TO_DEVICE_64(dst, src, size) \ do { \ From patchwork Tue May 11 06:45:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93144 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 031FAA0C41; Tue, 11 May 2021 08:48:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 31BDD41171; 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[89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:32 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Stanislaw Kardach , Michal Krawczyk , Shay Agroskin Date: Tue, 11 May 2021 08:45:51 +0200 Message-Id: <20210511064554.10656-17-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 16/19] net/ena: make ethdev references SMP safe X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Stanislaw Kardach rte_pci_device and rte_eth_dev are process-local structures. Therefore ena_adapter::pdev and ena_adapter::rte_dev cannot be used universally. Switch this to extracting those structures via rte_eth_devices indexing and remove pdev since it's not used outside of init. Signed-off-by: Stanislaw Kardach Reviewed-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin --- v4: * Remove access to the "rte_eth_devices" and instead pass rte_eth_dev as an argument to all the primary process callbacks. * Fix commit heading style. drivers/net/ena/ena_ethdev.c | 72 ++++++++++++++++++------------------ drivers/net/ena/ena_ethdev.h | 5 +-- 2 files changed, 38 insertions(+), 39 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 9a43ab50fe..055fa6d514 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -164,6 +164,7 @@ static const struct rte_pci_id pci_id_ena_map[] = { static struct ena_aenq_handlers aenq_handlers; static int ena_device_init(struct ena_com_dev *ena_dev, + struct rte_pci_device *pdev, struct ena_com_dev_get_features_ctx *get_feat_ctx, bool *wd_state); static int ena_dev_configure(struct rte_eth_dev *dev); @@ -457,11 +458,11 @@ static void ena_config_host_info(struct ena_com_dev *ena_dev) } /* This function calculates the number of xstats based on the current config */ -static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev) +static unsigned int ena_xstats_calc_num(struct rte_eth_dev_data *data) { return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI + - (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) + - (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX); + (data->nb_tx_queues * ENA_STATS_ARRAY_TX) + + (data->nb_rx_queues * ENA_STATS_ARRAY_RX); } static void ena_config_debug_area(struct ena_adapter *adapter) @@ -469,7 +470,7 @@ static void ena_config_debug_area(struct ena_adapter *adapter) u32 debug_area_size; int rc, ss_count; - ss_count = ena_xstats_calc_num(adapter->rte_dev); + ss_count = ena_xstats_calc_num(adapter->edev_data); /* allocate 32 bytes for each string and 64bit for the value */ debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; @@ -518,7 +519,7 @@ static int ena_close(struct rte_eth_dev *dev) rte_intr_disable(intr_handle); rte_intr_callback_unregister(intr_handle, ena_interrupt_handler_rte, - adapter); + dev); /* * MAC is not allocated dynamically. Setting NULL should prevent from @@ -593,7 +594,7 @@ static int ena_rss_reta_update(struct rte_eth_dev *dev, } PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries for port %d\n", - __func__, reta_size, adapter->rte_dev->data->port_id); + __func__, reta_size, dev->data->port_id); return 0; } @@ -637,7 +638,7 @@ static int ena_rss_reta_query(struct rte_eth_dev *dev, static int ena_rss_init_default(struct ena_adapter *adapter) { struct ena_com_dev *ena_dev = &adapter->ena_dev; - uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues; + uint16_t nb_rx_queues = adapter->edev_data->nb_rx_queues; int rc, i; u32 val; @@ -675,8 +676,7 @@ static int ena_rss_init_default(struct ena_adapter *adapter) PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n"); goto err_fill_indir; } - PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n", - adapter->rte_dev->data->port_id); + PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n", adapter->port_id); return 0; @@ -847,10 +847,10 @@ static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter) { uint32_t max_frame_len = adapter->max_mtu; - if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads & + if (adapter->edev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) max_frame_len = - adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len; + adapter->edev_data->dev_conf.rxmode.max_rx_pkt_len; return max_frame_len; } @@ -1070,8 +1070,8 @@ static int ena_start(struct rte_eth_dev *dev) if (rc) goto err_start_tx; - if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode & - ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) { + if (adapter->edev_data->dev_conf.rxmode.mq_mode & + ETH_MQ_RX_RSS_FLAG && adapter->edev_data->nb_rx_queues > 0) { rc = ena_rss_init_default(adapter); if (rc) goto err_rss_init; @@ -1084,7 +1084,7 @@ static int ena_start(struct rte_eth_dev *dev) ticks = rte_get_timer_hz(); rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(), - ena_timer_wd_callback, adapter); + ena_timer_wd_callback, dev); ++adapter->dev_stats.dev_start; adapter->state = ENA_ADAPTER_STATE_RUNNING; @@ -1511,6 +1511,7 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) } static int ena_device_init(struct ena_com_dev *ena_dev, + struct rte_pci_device *pdev, struct ena_com_dev_get_features_ctx *get_feat_ctx, bool *wd_state) { @@ -1528,9 +1529,7 @@ static int ena_device_init(struct ena_com_dev *ena_dev, /* The PCIe configuration space revision id indicate if mmio reg * read is disabled. */ - readless_supported = - !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id - & ENA_MMIO_DISABLE_REG_READ); + readless_supported = !(pdev->id.class_id & ENA_MMIO_DISABLE_REG_READ); ena_com_set_mmio_read_mode(ena_dev, readless_supported); /* reset device */ @@ -1601,12 +1600,13 @@ static int ena_device_init(struct ena_com_dev *ena_dev, static void ena_interrupt_handler_rte(void *cb_arg) { - struct ena_adapter *adapter = cb_arg; + struct rte_eth_dev *dev = cb_arg; + struct ena_adapter *adapter = dev->data->dev_private; struct ena_com_dev *ena_dev = &adapter->ena_dev; ena_com_admin_q_comp_intr_handler(ena_dev); if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) - ena_com_aenq_intr_handler(ena_dev, adapter); + ena_com_aenq_intr_handler(ena_dev, dev); } static void check_for_missing_keep_alive(struct ena_adapter *adapter) @@ -1639,8 +1639,8 @@ static void check_for_admin_com_state(struct ena_adapter *adapter) static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, void *arg) { - struct ena_adapter *adapter = arg; - struct rte_eth_dev *dev = adapter->rte_dev; + struct rte_eth_dev *dev = arg; + struct ena_adapter *adapter = dev->data->dev_private; check_for_missing_keep_alive(adapter); check_for_admin_com_state(adapter); @@ -1781,11 +1781,10 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) memset(adapter, 0, sizeof(struct ena_adapter)); ena_dev = &adapter->ena_dev; - adapter->rte_eth_dev_data = eth_dev->data; - adapter->rte_dev = eth_dev; + adapter->edev_data = eth_dev->data; + adapter->port_id = eth_dev->data->port_id; pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); - adapter->pdev = pci_dev; PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d", pci_dev->addr.domain, @@ -1805,7 +1804,8 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) } ena_dev->reg_bar = adapter->regs; - ena_dev->dmadev = adapter->pdev; + /* This is a dummy pointer for ena_com functions. */ + ena_dev->dmadev = adapter; adapter->id_number = adapters_found; @@ -1819,7 +1819,7 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) } /* device specific initialization routine */ - rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state); + rc = ena_device_init(ena_dev, pci_dev, &get_feat_ctx, &wd_state); if (rc) { PMD_INIT_LOG(CRIT, "Failed to init ENA device"); goto err; @@ -1902,7 +1902,7 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) rte_intr_callback_register(intr_handle, ena_interrupt_handler_rte, - adapter); + eth_dev); rte_intr_enable(intr_handle); ena_com_set_admin_polling_mode(ena_dev, false); ena_com_admin_aenq_enable(ena_dev); @@ -2681,7 +2681,7 @@ static int ena_xstats_get_names(struct rte_eth_dev *dev, struct rte_eth_xstat_name *xstats_names, unsigned int n) { - unsigned int xstats_count = ena_xstats_calc_num(dev); + unsigned int xstats_count = ena_xstats_calc_num(dev->data); unsigned int stat, i, count = 0; if (n < xstats_count || !xstats_names) @@ -2730,7 +2730,7 @@ static int ena_xstats_get(struct rte_eth_dev *dev, unsigned int n) { struct ena_adapter *adapter = dev->data->dev_private; - unsigned int xstats_count = ena_xstats_calc_num(dev); + unsigned int xstats_count = ena_xstats_calc_num(dev->data); unsigned int stat, i, count = 0; int stat_offset; void *stats_begin; @@ -2955,14 +2955,12 @@ RTE_LOG_REGISTER(ena_logtype_com, pmd.net.ena.com, NOTICE); static void ena_update_on_link_change(void *adapter_data, struct ena_admin_aenq_entry *aenq_e) { - struct rte_eth_dev *eth_dev; - struct ena_adapter *adapter; + struct rte_eth_dev *eth_dev = adapter_data; + struct ena_adapter *adapter = eth_dev->data->dev_private; struct ena_admin_aenq_link_change_desc *aenq_link_desc; uint32_t status; - adapter = adapter_data; aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; - eth_dev = adapter->rte_dev; status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc); adapter->link_status = status; @@ -2971,10 +2969,11 @@ static void ena_update_on_link_change(void *adapter_data, rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL); } -static void ena_notification(void *data, +static void ena_notification(void *adapter_data, struct ena_admin_aenq_entry *aenq_e) { - struct ena_adapter *adapter = data; + struct rte_eth_dev *eth_dev = adapter_data; + struct ena_adapter *adapter = eth_dev->data->dev_private; struct ena_admin_ena_hw_hints *hints; if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION) @@ -2997,7 +2996,8 @@ static void ena_notification(void *data, static void ena_keep_alive(void *adapter_data, __rte_unused struct ena_admin_aenq_entry *aenq_e) { - struct ena_adapter *adapter = adapter_data; + struct rte_eth_dev *eth_dev = adapter_data; + struct ena_adapter *adapter = eth_dev->data->dev_private; struct ena_admin_aenq_keep_alive_desc *desc; uint64_t rx_drops; uint64_t tx_drops; diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index ae235897ee..925e71f642 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -210,9 +210,8 @@ struct ena_offloads { /* board specific private data structure */ struct ena_adapter { /* OS defined structs */ - struct rte_pci_device *pdev; - struct rte_eth_dev_data *rte_eth_dev_data; - struct rte_eth_dev *rte_dev; + struct rte_eth_dev_data *edev_data; + int port_id; struct ena_com_dev ena_dev __rte_cache_aligned; From patchwork Tue May 11 06:45:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93145 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EF501A0C41; Tue, 11 May 2021 08:48:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5EB9F4117F; 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[89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:33 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Stanislaw Kardach , Michal Krawczyk , Shay Agroskin Date: Tue, 11 May 2021 08:45:52 +0200 Message-Id: <20210511064554.10656-18-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 17/19] net/ena: disable dev ops not supported in SMP X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Stanislaw Kardach For dev_ops not supported in SMP, either return -EPERM or return without doing anything. In both cases log a warning. Signed-off-by: Stanislaw Kardach Reviewed-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin --- v4: * Fix commit heading style. drivers/net/ena/ena_ethdev.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 055fa6d514..21bea98007 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -535,6 +535,12 @@ ena_dev_reset(struct rte_eth_dev *dev) { int rc = 0; + /* Cannot release memory in secondary process */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) { + PMD_DRV_LOG(WARNING, "dev_reset not supported in secondary.\n"); + return -EPERM; + } + ena_destroy_device(dev); rc = eth_ena_dev_init(dev); if (rc) @@ -1058,6 +1064,12 @@ static int ena_start(struct rte_eth_dev *dev) uint64_t ticks; int rc = 0; + /* Cannot allocate memory in secondary process */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) { + PMD_DRV_LOG(WARNING, "dev_start not supported in secondary.\n"); + return -EPERM; + } + rc = ena_check_valid_conf(adapter); if (rc) return rc; @@ -1104,6 +1116,12 @@ static int ena_stop(struct rte_eth_dev *dev) struct ena_com_dev *ena_dev = &adapter->ena_dev; int rc; + /* Cannot free memory in secondary process */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) { + PMD_DRV_LOG(WARNING, "dev_stop not supported in secondary.\n"); + return -EPERM; + } + rte_timer_stop_sync(&adapter->timer_wd); ena_queue_stop_all(dev, ENA_RING_TYPE_TX); ena_queue_stop_all(dev, ENA_RING_TYPE_RX); From patchwork Tue May 11 06:45:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93146 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5353EA0C41; Tue, 11 May 2021 08:48:19 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CC41E41187; Tue, 11 May 2021 08:46:41 +0200 (CEST) Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) by mails.dpdk.org (Postfix) with ESMTP id 39B744116A for ; Tue, 11 May 2021 08:46:36 +0200 (CEST) Received: by mail-lf1-f48.google.com with SMTP id a2so6043743lfc.9 for ; Mon, 10 May 2021 23:46:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=incR0NTCFG47GrErbWDRkiNmTglIzII58kgCssj2WvQ=; b=Tk0f73W1XV3UNzpQjy5je6jBOxIAIBIlUYSsRczQ6tgn6tFG51ByxdZMxFBWlFn7zk WnY9IgAn9YJLbgOy2nRYSw52CHZypKEMqGajbvAm5ymSwaouguD7h4TOrfirtswNBRSE sM3+P99+AfYmYwZzFOJqWEO4y84Cdl0/26yxB0+5l2DZQzufXORovS94Ug4qMxT4SvdA 4fMk3a6Un0QvuHy7bl9BJozLPCDHXvEnLtOeCAiEMxDFAVAMXojG1SEvVSXhTn8crQcJ 0EpjTkBCi/UGUyPxrJUSGVMw/Hwtz7q4Igl4BjG02zdJLE2D+18vwwytslQ49NVmsRrX 6qdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=incR0NTCFG47GrErbWDRkiNmTglIzII58kgCssj2WvQ=; b=rMOp4K829foEjY8PkQKxZEoM9FTfnFuvaLR6rrPYCGT7+DJRAD9ALlgzDVDmHqJcaM XyayNYpQWBG4dZvm4i4PPGpCryIQ22jp6bC9gbZGEsCiosYsWfzngQepF/weVYk+t9WD AqZwroA+cm5Ieqc2i9Qncb+H3SmrBAJaRF50ZbJfDY/gxI3SWbyoPbcIUt7lR8odXmB1 kBh3Tb+L3vUr0dZTjlu5KNwy6p0QEKygZnTs0wwPTYMe3wyDlGF3NSj94Wte/RtWLbLk GLMWWqivWSk5bm6p+lHm0f9s9lB7CK77nP2Bwq55PdtaS5YxvpxSsHTvTW6dzIZXs631 u4Qg== X-Gm-Message-State: AOAM533ZmuJ6hzvP4vuGUYR6pa+3gCzBIiRGlHepZCWFetRN+xwh/iE6 LLjbq65kzy/iVTfYEiadpfRnCg== X-Google-Smtp-Source: ABdhPJztxfv4cKbudpx4Z5aeXalzJGeUHCo3mko3D7CjNYrBR7xGlZbIwZNjROo/5BrO0ZXPnUb3Fg== X-Received: by 2002:a05:6512:1190:: with SMTP id g16mr20747129lfr.342.1620715595903; Mon, 10 May 2021 23:46:35 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:35 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Stanislaw Kardach , stable@dpdk.org, Michal Krawczyk , Shay Agroskin Date: Tue, 11 May 2021 08:45:53 +0200 Message-Id: <20210511064554.10656-19-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 18/19] net/ena: report default ring size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Stanislaw Kardach Remove invalid ring size alignment logic and add default rx and tx port ring sizes to the device info spec. The logic in lines 1297 and 1371 is invalid. The RTE_ETH_DEV_FALLBACK_RX_RINGSIZE (and the TX counterpart) is a value that rte_eth_rx_queue_setup() will set if dev_info.default_rxportconf.ring_size is 0 and user provided 0 in nb_rx_desc argument. However the current code treats it as a hint for the PMD to change the ring size to internal defaults. Additionally since the ENA_DEFAULT_RING_SIZE is defined, report it in the device capabilities so that both rte_ethdev code and the user can utilize it for device configuration. Fixes: ea93d37eb49d ("net/ena: add HW queues depth setup") Cc: stable@dpdk.org Signed-off-by: Stanislaw Kardach Reviewed-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin --- v4: * Add release notes. doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/ena/ena_ethdev.c | 9 +++------ 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index 389a7a05ac..f6c566f05c 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -211,6 +211,7 @@ New Features * Updated ena_com (HAL) to the latest version. * Fixed bugs when requesting large LLQ headers using the devargs. * Added indication of the RSS hash presence in the mbuf. + * Fixed bug when the default ring size was set. * **Added support of multiple data-units in cryptodev API.** diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 21bea98007..cb2c93052a 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -1300,9 +1300,6 @@ static int ena_tx_queue_setup(struct rte_eth_dev *dev, return -EINVAL; } - if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE) - nb_desc = adapter->max_tx_ring_size; - txq->port_id = dev->data->port_id; txq->next_to_clean = 0; txq->next_to_use = 0; @@ -1374,9 +1371,6 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev, return ENA_COM_FAULT; } - if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE) - nb_desc = adapter->max_rx_ring_size; - if (!rte_is_power_of_2(nb_desc)) { PMD_DRV_LOG(ERR, "Unsupported size of RX queue: %d is not a power of 2.\n", @@ -2096,6 +2090,9 @@ static int ena_infos_get(struct rte_eth_dev *dev, dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, adapter->max_tx_sgl_size); + dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE; + dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE; + return 0; } From patchwork Tue May 11 06:45:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93147 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DCD74A0C41; Tue, 11 May 2021 08:48:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0C63D4116D; Tue, 11 May 2021 08:46:43 +0200 (CEST) Received: from mail-lj1-f178.google.com (mail-lj1-f178.google.com [209.85.208.178]) by mails.dpdk.org (Postfix) with ESMTP id 8DC4141118 for ; Tue, 11 May 2021 08:46:37 +0200 (CEST) Received: by mail-lj1-f178.google.com with SMTP id q186so4150451ljq.8 for ; Mon, 10 May 2021 23:46:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EcflCy6t4J5LfmF/kDYFL/oYnE+x9aPtqOYrdAH9oZY=; b=fnzhqFPtoOt2FtPbaME6+WuA8e7HKcGilOtI85RdtP4W4T9cM1jRN77AcDgUwLcC+5 eHX33Xb4I3TEe3XGFSHUVSHP7dWbGZIGcZB0ygOkextmaTmHQ9AkUFhtkCnbTJxWJ9V4 MdUUAQfQ23p/4ZDIKzOjGgYasFNSzwaVCRBH0FGkpjuHBKqzLAoATe+bS7wxu/LmH+ty SEV7Bu10I9j5wazbrDZ5oGRAqOCo5JWAfZqypBs3UW2+c1lATwMd6Nnx2FxbHpQOwrU2 fbjpeVqRuQFGI7hAN+dD/IfUp/EVc7BtTt+IX5N3hIm3xoGjgKu7swZCxRaVOroMCJ42 NCgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EcflCy6t4J5LfmF/kDYFL/oYnE+x9aPtqOYrdAH9oZY=; b=iwvTGO6KRbciT3eYjdqqOWGi76TtYj/oW8TyUUkvv58CNdUtSVKTO34uMu6Y/9ITvZ R1qCj6BBQSEKeVhQA9NXiQ3a7Pp139o5pXwWZ6T3AOhYRUo3a12p3Qoh+J2dmExZ6G2j Us2W6I2tEGNr/OBS56UEuGkIavO+w3A3hp+uJc3hvwrpXAmB/QfOw3vmmmyPon1l0GAD QBgPyYaY71Lpu7RG2UczLxGMnvGsmi9hU+b8vWNAw7RmCweBXuuRSs0gBFCiYZU+qwWc KEc/khDnuk8hC6V3zyU6EXWG1qkGcXtRRL3St/4gZbk+6Nu7wCVqmz4NaiZ7lnI0nMkZ 82Cg== X-Gm-Message-State: AOAM530GBRHzYRiS94B3FkcGLIMBMqvermZ0O74siJndd9pdRlsut1vw ywu3cv6+AKW/8V3r+dIxeG70Qg== X-Google-Smtp-Source: ABdhPJwsDgbazVR7Um9yBlA/rA9TLT2gvQIgyhMJ6mmzs7lU4UiQajG9O8iPCtv6T8qFYT/204iADw== X-Received: by 2002:a2e:584b:: with SMTP id x11mr22092178ljd.476.1620715597247; Mon, 10 May 2021 23:46:37 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id v20sm2496776lfd.92.2021.05.10.23.46.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 23:46:36 -0700 (PDT) From: Michal Krawczyk To: ferruh.yigit@intel.com Cc: dev@dpdk.org, ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk Date: Tue, 11 May 2021 08:45:54 +0200 Message-Id: <20210511064554.10656-20-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210511064554.10656-1-mk@semihalf.com> References: <87e65a42-4ae5-1a81-8f8e-74759fc14999@intel.com> <20210511064554.10656-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 19/19] net/ena: update version to v2.3.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This version update contains: * memcpy mapping to the dpdk-optimized version. * ena_com (HAL) update to the latest version (from 18.09.2020). * Bug fixes for the large LLQ headers and devargs parsing. * Mbuf RSS hash presence indication. * Bug fix for the default ring size. * Fix for the SMP mode (although ENA is not fully MP aware, yet). Signed-off-by: Michal Krawczyk --- v4: * Remove release notes update from this commit. * Squash this patch with the geration date and commit ID update of the HAL. * Update commit log regarding the SMP fixes. v3: * Fix typo in the commit log (double "the") drivers/net/ena/base/ena_defs/ena_gen_info.h | 4 ++-- drivers/net/ena/ena_ethdev.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ena/base/ena_defs/ena_gen_info.h b/drivers/net/ena/base/ena_defs/ena_gen_info.h index 54bbfda11f..49895108d5 100644 --- a/drivers/net/ena/base/ena_defs/ena_gen_info.h +++ b/drivers/net/ena/base/ena_defs/ena_gen_info.h @@ -2,5 +2,5 @@ * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. * All rights reserved. */ -#define ENA_GEN_DATE "Sun Apr 26 13:45:21 DST 2020" -#define ENA_GEN_COMMIT "37aa7c3" +#define ENA_GEN_DATE "Fri Sep 18 17:09:00 IDT 2020" +#define ENA_GEN_COMMIT "0f80d82" diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index cb2c93052a..0caa5d9ee7 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -27,8 +27,8 @@ #include #define DRV_MODULE_VER_MAJOR 2 -#define DRV_MODULE_VER_MINOR 2 -#define DRV_MODULE_VER_SUBMINOR 1 +#define DRV_MODULE_VER_MINOR 3 +#define DRV_MODULE_VER_SUBMINOR 0 #define ENA_IO_TXQ_IDX(q) (2 * (q)) #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)