From patchwork Mon Jun 28 02:57:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: fengchengwen X-Patchwork-Id: 94882 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 51B59A0C40; Mon, 28 Jun 2021 05:01:38 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 51B3D410EE; Mon, 28 Jun 2021 05:01:31 +0200 (CEST) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id D0AD4410E8 for ; Mon, 28 Jun 2021 05:01:28 +0200 (CEST) Received: from dggemv711-chm.china.huawei.com (unknown [172.30.72.55]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4GCsk53XnlzZkgG; Mon, 28 Jun 2021 10:58:21 +0800 (CST) Received: from dggpeml500024.china.huawei.com (7.185.36.10) by dggemv711-chm.china.huawei.com (10.1.198.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Mon, 28 Jun 2021 11:01:19 +0800 Received: from localhost.localdomain (10.67.165.24) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Mon, 28 Jun 2021 11:01:17 +0800 From: Chengwen Feng To: , , CC: , , , , , , , Date: Mon, 28 Jun 2021 10:57:50 +0800 Message-ID: <1624849071-56826-2-git-send-email-fengchengwen@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1624849071-56826-1-git-send-email-fengchengwen@huawei.com> References: <1624849071-56826-1-git-send-email-fengchengwen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 1/2] build: fix SVE compile error with gcc8.3 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" If the target machine has SVE feature (e.g. "-march=armv8.2-a+sve'), and the compiler are gcc8.3, it will compile error: In file included from ../dpdk-next-net/lib/eal/common/ eal_common_options.c:38: ../dpdk-next-net/lib/eal/arm/include/rte_vect.h:13:10: fatal error: arm_sve.h: No such file or directory #include ^~~~~~~~~~~ compilation terminated. The root cause is that gcc8.3 supports SVE (the macro __ARM_FEATURE_SVE was 1), but it doesn't support SVE ACLE [1]. The solution: a) Detect compiler whether support SVE ACLE, if support then define RTE_HAS_SVE_ACLE macro. b) Use the RTE_HAS_SVE_ACLE macro to include SVE header file. [1] ACLE: Arm C Language Extensions, the SVE ACLE header file is , user should include it when writing ACLE SVE code. Fixes: 67b68824a82d ("lpm/arm: support SVE") Signed-off-by: Chengwen Feng Acked-by: Ruifeng Wang --- config/arm/meson.build | 6 ++++++ lib/eal/arm/include/rte_vect.h | 2 +- lib/lpm/rte_lpm.h | 2 +- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index e83a56e..7342626 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -488,3 +488,9 @@ if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != '' compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL', 'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2'] endif + +# Check whether SVE ACLE is supported and set the corresponding flag which will used with SVE ACLE code. +if (cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and + cc.check_header('arm_sve.h')) + dpdk_conf.set('RTE_HAS_SVE_ACLE', 1) +endif diff --git a/lib/eal/arm/include/rte_vect.h b/lib/eal/arm/include/rte_vect.h index 093e912..4b705ba 100644 --- a/lib/eal/arm/include/rte_vect.h +++ b/lib/eal/arm/include/rte_vect.h @@ -9,7 +9,7 @@ #include "generic/rte_vect.h" #include "rte_debug.h" #include "arm_neon.h" -#ifdef __ARM_FEATURE_SVE +#ifdef RTE_HAS_SVE_ACLE #include #endif diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h index 28b5768..5eb14c1 100644 --- a/lib/lpm/rte_lpm.h +++ b/lib/lpm/rte_lpm.h @@ -402,7 +402,7 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv); #if defined(RTE_ARCH_ARM) -#ifdef __ARM_FEATURE_SVE +#ifdef RTE_HAS_SVE_ACLE #include "rte_lpm_sve.h" #else #include "rte_lpm_neon.h" From patchwork Mon Jun 28 02:57:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: fengchengwen X-Patchwork-Id: 94880 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AE9ADA0C40; Mon, 28 Jun 2021 05:01:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2A47040692; Mon, 28 Jun 2021 05:01:27 +0200 (CEST) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id A9F714068A for ; Mon, 28 Jun 2021 05:01:25 +0200 (CEST) Received: from dggemv703-chm.china.huawei.com (unknown [172.30.72.55]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4GCsk06ChLzZnFG; Mon, 28 Jun 2021 10:58:16 +0800 (CST) Received: from dggpeml500024.china.huawei.com (7.185.36.10) by dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Mon, 28 Jun 2021 11:01:19 +0800 Received: from localhost.localdomain (10.67.165.24) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Mon, 28 Jun 2021 11:01:17 +0800 From: Chengwen Feng To: , , CC: , , , , , , , Date: Mon, 28 Jun 2021 10:57:51 +0800 Message-ID: <1624849071-56826-3-git-send-email-fengchengwen@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1624849071-56826-1-git-send-email-fengchengwen@huawei.com> References: <1624849071-56826-1-git-send-email-fengchengwen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 2/2] net/hns3: fix SVE code compile error with gcc8.3 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" If the target machine has SVE feature (e.g. '-march=armv8.2-a+sve'), and compiler are gcc8.3, it will compile error, the error is arm_sve.h no such file or directory. The solution: a. If RTE_HAS_SVE_ACLE defined (it means the minimum instruction set support SVE ACLE) then compiles it. b. Else if the compiler support SVE ACLE then compiles it. c. Otherwise don't compile it. Fixes: 8c25b02b082a ("net/hns3: fix enabling SVE Rx/Tx") Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx") Cc: stable@dpdk.org Signed-off-by: Chengwen Feng Acked-by: Ruifeng Wang --- drivers/net/hns3/hns3_rxtx.c | 2 +- drivers/net/hns3/meson.build | 20 +++++++++++++++++++- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index cb9eccf..a86e105 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2811,7 +2811,7 @@ hns3_get_default_vec_support(void) static bool hns3_get_sve_support(void) { -#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE) +#if defined(RTE_HAS_SVE_ACLE) if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256) return false; if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE)) diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build index 53c7df7..a99e0db 100644 --- a/drivers/net/hns3/meson.build +++ b/drivers/net/hns3/meson.build @@ -35,7 +35,25 @@ deps += ['hash'] if arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64') sources += files('hns3_rxtx_vec.c') - if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' + + # compile SVE when: + # a. support SVE in minimum instruction set baseline + # b. it's not minimum instruction set, but compiler support + if dpdk_conf.has('RTE_HAS_SVE_ACLE') sources += files('hns3_rxtx_vec_sve.c') + elif cc.has_argument('-march=armv8.2-a+sve') and cc.check_header('arm_sve.h') + cflags += ['-DRTE_HAS_SVE_ACLE=1'] + sve_cflags = [] + foreach flag: cflags + if not (flag.startswith('-march=') or flag.startswith('-mcpu=') or flag.startswith('-mtune=')) + sve_cflags += flag + endif + endforeach + hns3_sve_lib = static_library('hns3_sve_lib', + 'hns3_rxtx_vec_sve.c', + dependencies: [static_rte_ethdev], + include_directories: includes, + c_args: [sve_cflags, '-march=armv8.2-a+sve']) + objs += hns3_sve_lib.extract_objects('hns3_rxtx_vec_sve.c') endif endif