From patchwork Fri Sep 10 08:54:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Yang X-Patchwork-Id: 98573 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3EDF2A0547; Fri, 10 Sep 2021 10:59:14 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2B9FE410FE; Fri, 10 Sep 2021 10:59:14 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 9A73D4067E for ; Fri, 10 Sep 2021 10:59:12 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10102"; a="201225032" X-IronPort-AV: E=Sophos;i="5.85,282,1624345200"; d="scan'208";a="201225032" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2021 01:59:09 -0700 X-IronPort-AV: E=Sophos;i="5.85,282,1624345200"; d="scan'208";a="504988081" Received: from intel-npg-odc-srv01.cd.intel.com ([10.240.178.191]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2021 01:59:07 -0700 From: Steve Yang To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, Steve Yang Date: Fri, 10 Sep 2021 08:54:57 +0000 Message-Id: <20210910085458.61835-2-stevex.yang@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210910085458.61835-1-stevex.yang@intel.com> References: <20210910085458.61835-1-stevex.yang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v1 1/2] net/ice: add L4 support for QinQ switch filter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add L4 support for QinQ switch filter as following flow patterns: eth / vlan / vlan / ipv4 / udp eth / vlan / vlan / ipv4 / tcp eth / vlan / vlan / ipv6 / udp eth / vlan / vlan / ipv6 / tcp Signed-off-by: Steve Yang --- drivers/net/ice/ice_generic_flow.c | 4 ++++ drivers/net/ice/ice_switch_filter.c | 20 ++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/net/ice/ice_generic_flow.c b/drivers/net/ice/ice_generic_flow.c index c2fa75f165..9e03c2856c 100644 --- a/drivers/net/ice/ice_generic_flow.c +++ b/drivers/net/ice/ice_generic_flow.c @@ -2134,11 +2134,15 @@ static struct ice_ptype_match ice_ptype_map[] = { {pattern_eth_arp, ICE_PTYPE_MAC_PAY}, {pattern_eth_vlan_ipv4, ICE_PTYPE_IPV4_PAY}, {pattern_eth_qinq_ipv4, ICE_PTYPE_IPV4_PAY}, + {pattern_eth_qinq_ipv4_udp, ICE_PTYPE_IPV4_UDP_PAY}, + {pattern_eth_qinq_ipv4_tcp, ICE_PTYPE_IPV4_TCP_PAY}, {pattern_eth_vlan_ipv4_udp, ICE_PTYPE_IPV4_UDP_PAY}, {pattern_eth_vlan_ipv4_tcp, ICE_PTYPE_IPV4_TCP_PAY}, {pattern_eth_vlan_ipv4_sctp, ICE_PTYPE_IPV4_SCTP_PAY}, {pattern_eth_vlan_ipv6, ICE_PTYPE_IPV6_PAY}, {pattern_eth_qinq_ipv6, ICE_PTYPE_IPV6_PAY}, + {pattern_eth_qinq_ipv6_udp, ICE_PTYPE_IPV6_UDP_PAY}, + {pattern_eth_qinq_ipv6_tcp, ICE_PTYPE_IPV6_TCP_PAY}, {pattern_eth_vlan_ipv6_udp, ICE_PTYPE_IPV6_UDP_PAY}, {pattern_eth_vlan_ipv6_tcp, ICE_PTYPE_IPV6_TCP_PAY}, {pattern_eth_vlan_ipv6_sctp, ICE_PTYPE_IPV6_SCTP_PAY}, diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c index f222cb9cb0..bbd2805c37 100644 --- a/drivers/net/ice/ice_switch_filter.c +++ b/drivers/net/ice/ice_switch_filter.c @@ -44,6 +44,12 @@ ICE_INSET_IPV4_PROTO | ICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS) #define ICE_SW_INSET_MAC_QINQ_IPV4 ( \ ICE_SW_INSET_MAC_QINQ | ICE_SW_INSET_MAC_IPV4) +#define ICE_SW_INSET_MAC_QINQ_IPV4_TCP ( \ + ICE_SW_INSET_MAC_QINQ_IPV4 | \ + ICE_INSET_TCP_DST_PORT | ICE_INSET_TCP_SRC_PORT) +#define ICE_SW_INSET_MAC_QINQ_IPV4_UDP ( \ + ICE_SW_INSET_MAC_QINQ_IPV4 | \ + ICE_INSET_UDP_DST_PORT | ICE_INSET_UDP_SRC_PORT) #define ICE_SW_INSET_MAC_IPV4_TCP ( \ ICE_INSET_DMAC | ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \ ICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS | \ @@ -58,6 +64,12 @@ ICE_INSET_IPV6_NEXT_HDR) #define ICE_SW_INSET_MAC_QINQ_IPV6 ( \ ICE_SW_INSET_MAC_QINQ | ICE_SW_INSET_MAC_IPV6) +#define ICE_SW_INSET_MAC_QINQ_IPV6_TCP ( \ + ICE_SW_INSET_MAC_QINQ_IPV6 | \ + ICE_INSET_TCP_DST_PORT | ICE_INSET_TCP_SRC_PORT) +#define ICE_SW_INSET_MAC_QINQ_IPV6_UDP ( \ + ICE_SW_INSET_MAC_QINQ_IPV6 | \ + ICE_INSET_UDP_DST_PORT | ICE_INSET_UDP_SRC_PORT) #define ICE_SW_INSET_MAC_IPV6_TCP ( \ ICE_INSET_DMAC | ICE_INSET_IPV6_DST | ICE_INSET_IPV6_SRC | \ ICE_INSET_IPV6_HOP_LIMIT | ICE_INSET_IPV6_TC | \ @@ -216,7 +228,11 @@ ice_pattern_match_item ice_switch_pattern_dist_list[] = { {pattern_eth_ipv4_pfcp, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv6_pfcp, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_qinq_ipv4, ICE_SW_INSET_MAC_QINQ_IPV4, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_qinq_ipv4_tcp, ICE_SW_INSET_MAC_QINQ_IPV4_TCP, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_qinq_ipv4_udp, ICE_SW_INSET_MAC_QINQ_IPV4_UDP, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_qinq_ipv6, ICE_SW_INSET_MAC_QINQ_IPV6, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_qinq_ipv6_tcp, ICE_SW_INSET_MAC_QINQ_IPV6_TCP, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_qinq_ipv6_udp, ICE_SW_INSET_MAC_QINQ_IPV6_UDP, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_qinq_pppoes, ICE_SW_INSET_MAC_PPPOE, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_qinq_pppoes_proto, ICE_SW_INSET_MAC_PPPOE_PROTO, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_qinq_pppoes_ipv4, ICE_SW_INSET_MAC_PPPOE_IPV4, ICE_INSET_NONE, ICE_INSET_NONE}, @@ -295,7 +311,11 @@ ice_pattern_match_item ice_switch_pattern_perm_list[] = { {pattern_eth_ipv4_pfcp, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv6_pfcp, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_qinq_ipv4, ICE_SW_INSET_MAC_QINQ_IPV4, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_qinq_ipv4_tcp, ICE_SW_INSET_MAC_QINQ_IPV4_TCP, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_qinq_ipv4_udp, ICE_SW_INSET_MAC_QINQ_IPV4_UDP, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_qinq_ipv6, ICE_SW_INSET_MAC_QINQ_IPV6, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_qinq_ipv6_tcp, ICE_SW_INSET_MAC_QINQ_IPV6_TCP, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_qinq_ipv6_udp, ICE_SW_INSET_MAC_QINQ_IPV6_UDP, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_qinq_pppoes, ICE_SW_INSET_MAC_PPPOE, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_qinq_pppoes_proto, ICE_SW_INSET_MAC_PPPOE_PROTO, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_qinq_pppoes_ipv4, ICE_SW_INSET_MAC_PPPOE_IPV4, ICE_INSET_NONE, ICE_INSET_NONE}, From patchwork Fri Sep 10 08:54:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Yang X-Patchwork-Id: 98574 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7EDCFA0547; Fri, 10 Sep 2021 10:59:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3743C41121; Fri, 10 Sep 2021 10:59:16 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id E21824067E for ; Fri, 10 Sep 2021 10:59:13 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10102"; a="201225040" X-IronPort-AV: E=Sophos;i="5.85,282,1624345200"; d="scan'208";a="201225040" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2021 01:59:13 -0700 X-IronPort-AV: E=Sophos;i="5.85,282,1624345200"; d="scan'208";a="504988104" Received: from intel-npg-odc-srv01.cd.intel.com ([10.240.178.191]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2021 01:59:11 -0700 From: Steve Yang To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, Steve Yang Date: Fri, 10 Sep 2021 08:54:58 +0000 Message-Id: <20210910085458.61835-3-stevex.yang@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210910085458.61835-1-stevex.yang@intel.com> References: <20210910085458.61835-1-stevex.yang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v1 2/2] net/ice/base: support L4 for QinQ switch filter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds more dummy packet types for QinQ packet, it enables tcp/udp layer of ipv4/ipv6 for QinQ payload, so we can use L4 dst/src port as input set for switch filter. For Example: flow create 0 ingress pattern eth / vlan tci is 2 / vlan tci is 1 \ / ipv4 src is 10.1.1.1 / tcp src is 400 / end actions vf id 1 / end Signed-off-by: Steve Yang --- drivers/net/ice/base/ice_switch.c | 173 +++++++++++++++++++++++++++++- 1 file changed, 168 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 9179f66c20..5da8d650da 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -1660,7 +1660,7 @@ static const struct ice_dummy_pkt_offsets dummy_qinq_ipv4_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, { ICE_VLAN_EX, 12 }, { ICE_VLAN_IN, 16 }, - { ICE_ETYPE_OL, 20 }, + { ICE_ETYPE_OL, 20 }, { ICE_IPV4_OFOS, 22 }, { ICE_PROTOCOL_LAST, 0 }, }; @@ -1674,6 +1674,35 @@ static const u8 dummy_qinq_ipv4_pkt[] = { 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */ 0x08, 0x00, /* ICE_ETYPE_OL 20 */ + 0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_OFOS 22 */ + 0x00, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, /* 2 bytes for 4 byte alignment */ +}; + +static const +struct ice_dummy_pkt_offsets dummy_qinq_ipv4_udp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_VLAN_EX, 12 }, + { ICE_VLAN_IN, 16 }, + { ICE_ETYPE_OL, 20 }, + { ICE_IPV4_OFOS, 22 }, + { ICE_UDP_ILOS, 42 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_qinq_ipv4_udp_pkt[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */ + 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */ + 0x08, 0x00, /* ICE_ETYPE_OL 20 */ + 0x45, 0x00, 0x00, 0x1c, /* ICE_IPV4_OFOS 22 */ 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, @@ -1686,11 +1715,46 @@ static const u8 dummy_qinq_ipv4_pkt[] = { 0x00, 0x00, /* 2 bytes for 4 byte alignment */ }; +static const +struct ice_dummy_pkt_offsets dummy_qinq_ipv4_tcp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_VLAN_EX, 12 }, + { ICE_VLAN_IN, 16 }, + { ICE_ETYPE_OL, 20 }, + { ICE_IPV4_OFOS, 22 }, + { ICE_TCP_IL, 42 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_qinq_ipv4_tcp_pkt[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */ + 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */ + 0x08, 0x00, /* ICE_ETYPE_OL 20 */ + + 0x45, 0x00, 0x00, 0x28, /* ICE_IPV4_OFOS 22 */ + 0x00, 0x01, 0x00, 0x00, + 0x00, 0x06, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 42 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x50, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, /* 2 bytes for 4 byte alignment */ +}; + static const struct ice_dummy_pkt_offsets dummy_qinq_ipv6_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, { ICE_VLAN_EX, 12 }, { ICE_VLAN_IN, 16 }, - { ICE_ETYPE_OL, 20 }, + { ICE_ETYPE_OL, 20 }, { ICE_IPV6_OFOS, 22 }, { ICE_PROTOCOL_LAST, 0 }, }; @@ -1705,7 +1769,41 @@ static const u8 dummy_qinq_ipv6_pkt[] = { 0x86, 0xDD, /* ICE_ETYPE_OL 20 */ 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 22 */ - 0x00, 0x10, 0x11, 0x00, /* Next header UDP */ + 0x00, 0x00, 0x3b, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, /* 2 bytes for 4 byte alignment */ +}; + +static const +struct ice_dummy_pkt_offsets dummy_qinq_ipv6_udp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_VLAN_EX, 12 }, + { ICE_VLAN_IN, 16 }, + { ICE_ETYPE_OL, 20 }, + { ICE_IPV6_OFOS, 22 }, + { ICE_UDP_ILOS, 62 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_qinq_ipv6_udp_pkt[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */ + 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */ + 0x86, 0xDD, /* ICE_ETYPE_OL 20 */ + + 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 22 */ + 0x00, 0x08, 0x11, 0x00, /* Next header UDP */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1716,9 +1814,46 @@ static const u8 dummy_qinq_ipv6_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 62 */ - 0x00, 0x10, 0x00, 0x00, + 0x00, 0x08, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, /* needed for ESP packets */ + 0x00, 0x00, /* 2 bytes for 4 byte alignment */ +}; + +static const +struct ice_dummy_pkt_offsets dummy_qinq_ipv6_tcp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_VLAN_EX, 12 }, + { ICE_VLAN_IN, 16 }, + { ICE_ETYPE_OL, 20 }, + { ICE_IPV6_OFOS, 22 }, + { ICE_TCP_IL, 62 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_qinq_ipv6_tcp_pkt[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */ + 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */ + 0x86, 0xDD, /* ICE_ETYPE_OL 20 */ + + 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 22 */ + 0x00, 0x14, 0x06, 0x00, /* Next header TCP */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 62 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 2 bytes for 4 byte alignment */ @@ -7918,12 +8053,40 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, if ((tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ || tun_type == ICE_NON_TUN_QINQ) && ipv6) { + if (tcp) { + *pkt = dummy_qinq_ipv6_tcp_pkt; + *pkt_len = sizeof(dummy_qinq_ipv6_tcp_pkt); + *offsets = dummy_qinq_ipv6_tcp_packet_offsets; + return; + } + + if (udp) { + *pkt = dummy_qinq_ipv6_udp_pkt; + *pkt_len = sizeof(dummy_qinq_ipv6_udp_pkt); + *offsets = dummy_qinq_ipv6_udp_packet_offsets; + return; + } + *pkt = dummy_qinq_ipv6_pkt; *pkt_len = sizeof(dummy_qinq_ipv6_pkt); *offsets = dummy_qinq_ipv6_packet_offsets; return; } else if (tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ || tun_type == ICE_NON_TUN_QINQ) { + if (tcp) { + *pkt = dummy_qinq_ipv4_tcp_pkt; + *pkt_len = sizeof(dummy_qinq_ipv4_tcp_pkt); + *offsets = dummy_qinq_ipv4_tcp_packet_offsets; + return; + } + + if (udp) { + *pkt = dummy_qinq_ipv4_udp_pkt; + *pkt_len = sizeof(dummy_qinq_ipv4_udp_pkt); + *offsets = dummy_qinq_ipv4_udp_packet_offsets; + return; + } + *pkt = dummy_qinq_ipv4_pkt; *pkt_len = sizeof(dummy_qinq_ipv4_pkt); *offsets = dummy_qinq_ipv4_packet_offsets;