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The initiated DMA is performed without CPU being involved in the actual DMA transaction. This is achieved via using the QDMA controller of DPAA SoC. Signed-off-by: Gagandeep Singh --- MAINTAINERS | 11 ++++++ doc/guides/dmadevs/dpaa.rst | 54 ++++++++++++++++++++++++++ doc/guides/dmadevs/index.rst | 1 + doc/guides/rel_notes/release_21_11.rst | 3 ++ drivers/bus/dpaa/dpaa_bus.c | 22 +++++++++++ drivers/bus/dpaa/rte_dpaa_bus.h | 5 +++ drivers/common/dpaax/dpaa_list.h | 2 + drivers/dma/dpaa/dpaa_qdma.c | 29 ++++++++++++++ drivers/dma/dpaa/dpaa_qdma_logs.h | 46 ++++++++++++++++++++++ drivers/dma/dpaa/meson.build | 14 +++++++ drivers/dma/dpaa/version.map | 4 ++ drivers/dma/meson.build | 1 + 12 files changed, 192 insertions(+) create mode 100644 doc/guides/dmadevs/dpaa.rst create mode 100644 drivers/dma/dpaa/dpaa_qdma.c create mode 100644 drivers/dma/dpaa/dpaa_qdma_logs.h create mode 100644 drivers/dma/dpaa/meson.build create mode 100644 drivers/dma/dpaa/version.map diff --git a/MAINTAINERS b/MAINTAINERS index e157e12f88..0f333b7baa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1377,6 +1377,17 @@ F: drivers/raw/dpaa2_qdma/ F: doc/guides/rawdevs/dpaa2_qdma.rst + +Dmadev Drivers +-------------- + +NXP DPAA DMA +M: Gagandeep Singh +M: Nipun Gupta +F: drivers/dma/dpaa/ +F: doc/guides/dmadevs/dpaa.rst + + Packet processing ----------------- diff --git a/doc/guides/dmadevs/dpaa.rst b/doc/guides/dmadevs/dpaa.rst new file mode 100644 index 0000000000..885a8bb8aa --- /dev/null +++ b/doc/guides/dmadevs/dpaa.rst @@ -0,0 +1,54 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright 2021 NXP + +NXP DPAA DMA Driver +===================== + +The DPAA DMA is an implementation of the dmadev APIs, that provide means +to initiate a DMA transaction from CPU. The initiated DMA is performed +without CPU being involved in the actual DMA transaction. This is achieved +via using the QDMA controller of DPAA SoC. + +The QDMA controller transfers blocks of data between one source and one +destination. The blocks of data transferred can be represented in memory +as contiguous or noncontiguous using scatter/gather table(s). + +More information can be found at `NXP Official Website +`_. + +Supported DPAA SoCs +-------------------- + +- LS1046A +- LS1043A + +Prerequisites +------------- + +See :doc:`../platform/dpaa` for setup information + +- Follow the DPDK :ref:`Getting Started Guide for Linux ` to setup the basic DPDK environment. + +.. note:: + + Some part of dpaa bus code (qbman and fman - library) routines are + dual licensed (BSD & GPLv2), however they are used as BSD in DPDK in userspace. + +Compilation +------------ + +For builds using ``meson`` and ``ninja``, the driver will be built when the +target platform is dpaa-based. No additional compilation steps are necessary. + +Initialization +-------------- + +On EAL initialization, DPAA DMA devices will be detected on DPAA bus and +will be probed and populated into their device list. + + +Platform Requirement +~~~~~~~~~~~~~~~~~~~~ + +DPAA DMA driver for DPDK can only work on NXP SoCs as listed in the +``Supported DPAA SoCs``. diff --git a/doc/guides/dmadevs/index.rst b/doc/guides/dmadevs/index.rst index c2aa6058e6..6b6406f590 100644 --- a/doc/guides/dmadevs/index.rst +++ b/doc/guides/dmadevs/index.rst @@ -12,6 +12,7 @@ an application through DMA API. :numbered: cnxk + dpaa hisilicon idxd ioat diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst index 01923e2deb..ba6ad7bf16 100644 --- a/doc/guides/rel_notes/release_21_11.rst +++ b/doc/guides/rel_notes/release_21_11.rst @@ -20,6 +20,9 @@ DPDK Release 21.11 ninja -C build doc xdg-open build/doc/guides/html/rel_notes/release_21_11.html +* **Added NXP DPAA DMA driver.** + + * Added a new dmadev driver for NXP DPAA platform. New Features ------------ diff --git a/drivers/bus/dpaa/dpaa_bus.c b/drivers/bus/dpaa/dpaa_bus.c index 9a53fdc1fb..737ac8d8c5 100644 --- a/drivers/bus/dpaa/dpaa_bus.c +++ b/drivers/bus/dpaa/dpaa_bus.c @@ -250,6 +250,28 @@ dpaa_create_device_list(void) rte_dpaa_bus.device_count += i; + /* Creating QDMA Device */ + for (i = 0; i < RTE_DPAA_QDMA_DEVICES; i++) { + dev = calloc(1, sizeof(struct rte_dpaa_device)); + if (!dev) { + DPAA_BUS_LOG(ERR, "Failed to allocate QDMA device"); + ret = -1; + goto cleanup; + } + + dev->device_type = FSL_DPAA_QDMA; + dev->id.dev_id = rte_dpaa_bus.device_count + i; + + memset(dev->name, 0, RTE_ETH_NAME_MAX_LEN); + sprintf(dev->name, "dpaa_qdma-%d", i+1); + DPAA_BUS_LOG(INFO, "%s qdma device added", dev->name); + dev->device.name = dev->name; + dev->device.devargs = dpaa_devargs_lookup(dev); + + dpaa_add_to_device_list(dev); + } + rte_dpaa_bus.device_count += i; + return 0; cleanup: diff --git a/drivers/bus/dpaa/rte_dpaa_bus.h b/drivers/bus/dpaa/rte_dpaa_bus.h index 97d189f9b0..31a5ea3fca 100644 --- a/drivers/bus/dpaa/rte_dpaa_bus.h +++ b/drivers/bus/dpaa/rte_dpaa_bus.h @@ -58,6 +58,9 @@ dpaa_seqn(struct rte_mbuf *mbuf) /** Device driver supports link state interrupt */ #define RTE_DPAA_DRV_INTR_LSC 0x0008 +/** Number of supported QDMA devices */ +#define RTE_DPAA_QDMA_DEVICES 1 + #define RTE_DEV_TO_DPAA_CONST(ptr) \ container_of(ptr, const struct rte_dpaa_device, device) @@ -73,6 +76,7 @@ TAILQ_HEAD(rte_dpaa_driver_list, rte_dpaa_driver); enum rte_dpaa_type { FSL_DPAA_ETH = 1, FSL_DPAA_CRYPTO, + FSL_DPAA_QDMA }; struct rte_dpaa_bus { @@ -95,6 +99,7 @@ struct rte_dpaa_device { union { struct rte_eth_dev *eth_dev; struct rte_cryptodev *crypto_dev; + struct rte_dma_dev *dmadev; }; struct rte_dpaa_driver *driver; struct dpaa_device_id id; diff --git a/drivers/common/dpaax/dpaa_list.h b/drivers/common/dpaax/dpaa_list.h index e94575982b..319a3562ab 100644 --- a/drivers/common/dpaax/dpaa_list.h +++ b/drivers/common/dpaax/dpaa_list.h @@ -35,6 +35,8 @@ do { \ const struct list_head *__p298 = (p); \ ((__p298->next == __p298) && (__p298->prev == __p298)); \ }) +#define list_first_entry(ptr, type, member) \ + list_entry((ptr)->next, type, member) #define list_add(p, l) \ do { \ struct list_head *__p298 = (p); \ diff --git a/drivers/dma/dpaa/dpaa_qdma.c b/drivers/dma/dpaa/dpaa_qdma.c new file mode 100644 index 0000000000..29a6ec2fb3 --- /dev/null +++ b/drivers/dma/dpaa/dpaa_qdma.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2021 NXP + */ + +#include + +static int +dpaa_qdma_probe(__rte_unused struct rte_dpaa_driver *dpaa_drv, + __rte_unused struct rte_dpaa_device *dpaa_dev) +{ + return 0; +} + +static int +dpaa_qdma_remove(__rte_unused struct rte_dpaa_device *dpaa_dev) +{ + return 0; +} + +static struct rte_dpaa_driver rte_dpaa_qdma_pmd; + +static struct rte_dpaa_driver rte_dpaa_qdma_pmd = { + .drv_type = FSL_DPAA_QDMA, + .probe = dpaa_qdma_probe, + .remove = dpaa_qdma_remove, +}; + +RTE_PMD_REGISTER_DPAA(dpaa_qdma, rte_dpaa_qdma_pmd); +RTE_LOG_REGISTER_DEFAULT(dpaa_qdma_logtype, INFO); diff --git a/drivers/dma/dpaa/dpaa_qdma_logs.h b/drivers/dma/dpaa/dpaa_qdma_logs.h new file mode 100644 index 0000000000..01d4a508fc --- /dev/null +++ b/drivers/dma/dpaa/dpaa_qdma_logs.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2021 NXP + */ + +#ifndef __DPAA_QDMA_LOGS_H__ +#define __DPAA_QDMA_LOGS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +extern int dpaa_qdma_logtype; + +#define DPAA_QDMA_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, dpaa_qdma_logtype, "dpaa_qdma: " \ + fmt "\n", ## args) + +#define DPAA_QDMA_DEBUG(fmt, args...) \ + rte_log(RTE_LOG_DEBUG, dpaa_qdma_logtype, "dpaa_qdma: %s(): " \ + fmt "\n", __func__, ## args) + +#define DPAA_QDMA_FUNC_TRACE() DPAA_QDMA_DEBUG(">>") + +#define DPAA_QDMA_INFO(fmt, args...) \ + DPAA_QDMA_LOG(INFO, fmt, ## args) +#define DPAA_QDMA_ERR(fmt, args...) \ + DPAA_QDMA_LOG(ERR, fmt, ## args) +#define DPAA_QDMA_WARN(fmt, args...) \ + DPAA_QDMA_LOG(WARNING, fmt, ## args) + +/* DP Logs, toggled out at compile time if level lower than current level */ +#define DPAA_QDMA_DP_LOG(level, fmt, args...) \ + RTE_LOG_DP(level, PMD, "dpaa_qdma: " fmt "\n", ## args) + +#define DPAA_QDMA_DP_DEBUG(fmt, args...) \ + DPAA_QDMA_DP_LOG(DEBUG, fmt, ## args) +#define DPAA_QDMA_DP_INFO(fmt, args...) \ + DPAA_QDMA_DP_LOG(INFO, fmt, ## args) +#define DPAA_QDMA_DP_WARN(fmt, args...) \ + DPAA_QDMA_DP_LOG(WARNING, fmt, ## args) + +#ifdef __cplusplus +} +#endif + +#endif /* __DPAA_QDMA_LOGS_H__ */ diff --git a/drivers/dma/dpaa/meson.build b/drivers/dma/dpaa/meson.build new file mode 100644 index 0000000000..9ab0862ede --- /dev/null +++ b/drivers/dma/dpaa/meson.build @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2021 NXP + +if not is_linux + build = false + reason = 'only supported on linux' +endif + +deps += ['dmadev', 'bus_dpaa'] +sources = files('dpaa_qdma.c') + +if cc.has_argument('-Wno-pointer-arith') + cflags += '-Wno-pointer-arith' +endif diff --git a/drivers/dma/dpaa/version.map b/drivers/dma/dpaa/version.map new file mode 100644 index 0000000000..7bab7bea48 --- /dev/null +++ b/drivers/dma/dpaa/version.map @@ -0,0 +1,4 @@ +DPDK_22 { + + local: *; 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Signed-off-by: Gagandeep Singh --- drivers/dma/dpaa/dpaa_qdma.c | 469 ++++++++++++++++++++++++++++++++++- drivers/dma/dpaa/dpaa_qdma.h | 236 ++++++++++++++++++ 2 files changed, 703 insertions(+), 2 deletions(-) create mode 100644 drivers/dma/dpaa/dpaa_qdma.h diff --git a/drivers/dma/dpaa/dpaa_qdma.c b/drivers/dma/dpaa/dpaa_qdma.c index 29a6ec2fb3..c3255dc0c7 100644 --- a/drivers/dma/dpaa/dpaa_qdma.c +++ b/drivers/dma/dpaa/dpaa_qdma.c @@ -3,17 +3,482 @@ */ #include +#include + +#include "dpaa_qdma.h" +#include "dpaa_qdma_logs.h" + +static inline int +ilog2(int x) +{ + int log = 0; + + x >>= 1; + + while (x) { + log++; + x >>= 1; + } + return log; +} + +static u32 +qdma_readl(void *addr) +{ + return QDMA_IN(addr); +} + +static void +qdma_writel(u32 val, void *addr) +{ + QDMA_OUT(addr, val); +} + +static void +*dma_pool_alloc(int size, int aligned, dma_addr_t *phy_addr) +{ + void *virt_addr; + + virt_addr = rte_malloc("dma pool alloc", size, aligned); + if (!virt_addr) + return NULL; + + *phy_addr = rte_mem_virt2iova(virt_addr); + + return virt_addr; +} + +static void +dma_pool_free(void *addr) +{ + rte_free(addr); +} + +static void +fsl_qdma_free_chan_resources(struct fsl_qdma_chan *fsl_chan) +{ + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue; + struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma; + struct fsl_qdma_comp *comp_temp, *_comp_temp; + int id; + + if (--fsl_queue->count) + goto finally; + + id = (fsl_qdma->block_base - fsl_queue->block_base) / + fsl_qdma->block_offset; + + while (rte_atomic32_read(&wait_task[id]) == 1) + rte_delay_us(QDMA_DELAY); + + list_for_each_entry_safe(comp_temp, _comp_temp, + &fsl_queue->comp_used, list) { + list_del(&comp_temp->list); + dma_pool_free(comp_temp->virt_addr); + dma_pool_free(comp_temp->desc_virt_addr); + rte_free(comp_temp); + } + + list_for_each_entry_safe(comp_temp, _comp_temp, + &fsl_queue->comp_free, list) { + list_del(&comp_temp->list); + dma_pool_free(comp_temp->virt_addr); + dma_pool_free(comp_temp->desc_virt_addr); + rte_free(comp_temp); + } + +finally: + fsl_qdma->desc_allocated--; +} + +static struct fsl_qdma_queue +*fsl_qdma_alloc_queue_resources(struct fsl_qdma_engine *fsl_qdma) +{ + struct fsl_qdma_queue *queue_head, *queue_temp; + int len, i, j; + int queue_num; + int blocks; + unsigned int queue_size[FSL_QDMA_QUEUE_MAX]; + + queue_num = fsl_qdma->n_queues; + blocks = fsl_qdma->num_blocks; + + len = sizeof(*queue_head) * queue_num * blocks; + queue_head = rte_zmalloc("qdma: queue head", len, 0); + if (!queue_head) + return NULL; + + for (i = 0; i < FSL_QDMA_QUEUE_MAX; i++) + queue_size[i] = QDMA_QUEUE_SIZE; + + for (j = 0; j < blocks; j++) { + for (i = 0; i < queue_num; i++) { + if (queue_size[i] > FSL_QDMA_CIRCULAR_DESC_SIZE_MAX || + queue_size[i] < FSL_QDMA_CIRCULAR_DESC_SIZE_MIN) { + DPAA_QDMA_ERR("Get wrong queue-sizes.\n"); + goto fail; + } + queue_temp = queue_head + i + (j * queue_num); + + queue_temp->cq = + dma_pool_alloc(sizeof(struct fsl_qdma_format) * + queue_size[i], + sizeof(struct fsl_qdma_format) * + queue_size[i], &queue_temp->bus_addr); + + if (!queue_temp->cq) + goto fail; + + memset(queue_temp->cq, 0x0, queue_size[i] * + sizeof(struct fsl_qdma_format)); + + queue_temp->block_base = fsl_qdma->block_base + + FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j); + queue_temp->n_cq = queue_size[i]; + queue_temp->id = i; + queue_temp->count = 0; + queue_temp->pending = 0; + queue_temp->virt_head = queue_temp->cq; + + } + } + return queue_head; + +fail: + for (j = 0; j < blocks; j++) { + for (i = 0; i < queue_num; i++) { + queue_temp = queue_head + i + (j * queue_num); + dma_pool_free(queue_temp->cq); + } + } + rte_free(queue_head); + + return NULL; +} + +static struct +fsl_qdma_queue *fsl_qdma_prep_status_queue(void) +{ + struct fsl_qdma_queue *status_head; + unsigned int status_size; + + status_size = QDMA_STATUS_SIZE; + if (status_size > FSL_QDMA_CIRCULAR_DESC_SIZE_MAX || + status_size < FSL_QDMA_CIRCULAR_DESC_SIZE_MIN) { + DPAA_QDMA_ERR("Get wrong status_size.\n"); + return NULL; + } + + status_head = rte_zmalloc("qdma: status head", sizeof(*status_head), 0); + if (!status_head) + return NULL; + + /* + * Buffer for queue command + */ + status_head->cq = dma_pool_alloc(sizeof(struct fsl_qdma_format) * + status_size, + sizeof(struct fsl_qdma_format) * + status_size, + &status_head->bus_addr); + + if (!status_head->cq) { + rte_free(status_head); + return NULL; + } + + memset(status_head->cq, 0x0, status_size * + sizeof(struct fsl_qdma_format)); + status_head->n_cq = status_size; + status_head->virt_head = status_head->cq; + + return status_head; +} + +static int +fsl_qdma_halt(struct fsl_qdma_engine *fsl_qdma) +{ + void *ctrl = fsl_qdma->ctrl_base; + void *block; + int i, count = RETRIES; + unsigned int j; + u32 reg; + + /* Disable the command queue and wait for idle state. */ + reg = qdma_readl(ctrl + FSL_QDMA_DMR); + reg |= FSL_QDMA_DMR_DQD; + qdma_writel(reg, ctrl + FSL_QDMA_DMR); + for (j = 0; j < fsl_qdma->num_blocks; j++) { + block = fsl_qdma->block_base + + FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j); + for (i = 0; i < FSL_QDMA_QUEUE_NUM_MAX; i++) + qdma_writel(0, block + FSL_QDMA_BCQMR(i)); + } + while (true) { + reg = qdma_readl(ctrl + FSL_QDMA_DSR); + if (!(reg & FSL_QDMA_DSR_DB)) + break; + if (count-- < 0) + return -EBUSY; + rte_delay_us(100); + } + + for (j = 0; j < fsl_qdma->num_blocks; j++) { + block = fsl_qdma->block_base + + FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j); + + /* Disable status queue. */ + qdma_writel(0, block + FSL_QDMA_BSQMR); + + /* + * clear the command queue interrupt detect register for + * all queues. + */ + qdma_writel(0xffffffff, block + FSL_QDMA_BCQIDR(0)); + } + + return 0; +} + +static int +fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma) +{ + struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue; + struct fsl_qdma_queue *temp; + void *ctrl = fsl_qdma->ctrl_base; + void *block; + u32 i, j; + u32 reg; + int ret, val; + + /* Try to halt the qDMA engine first. */ + ret = fsl_qdma_halt(fsl_qdma); + if (ret) { + DPAA_QDMA_ERR("DMA halt failed!"); + return ret; + } + + for (j = 0; j < fsl_qdma->num_blocks; j++) { + block = fsl_qdma->block_base + + FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j); + for (i = 0; i < fsl_qdma->n_queues; i++) { + temp = fsl_queue + i + (j * fsl_qdma->n_queues); + /* + * Initialize Command Queue registers to + * point to the first + * command descriptor in memory. + * Dequeue Pointer Address Registers + * Enqueue Pointer Address Registers + */ + + qdma_writel(lower_32_bits(temp->bus_addr), + block + FSL_QDMA_BCQDPA_SADDR(i)); + qdma_writel(upper_32_bits(temp->bus_addr), + block + FSL_QDMA_BCQEDPA_SADDR(i)); + qdma_writel(lower_32_bits(temp->bus_addr), + block + FSL_QDMA_BCQEPA_SADDR(i)); + qdma_writel(upper_32_bits(temp->bus_addr), + block + FSL_QDMA_BCQEEPA_SADDR(i)); + + /* Initialize the queue mode. */ + reg = FSL_QDMA_BCQMR_EN; + reg |= FSL_QDMA_BCQMR_CD_THLD(ilog2(temp->n_cq) - 4); + reg |= FSL_QDMA_BCQMR_CQ_SIZE(ilog2(temp->n_cq) - 6); + qdma_writel(reg, block + FSL_QDMA_BCQMR(i)); + } + + /* + * Workaround for erratum: ERR010812. + * We must enable XOFF to avoid the enqueue rejection occurs. + * Setting SQCCMR ENTER_WM to 0x20. + */ + + qdma_writel(FSL_QDMA_SQCCMR_ENTER_WM, + block + FSL_QDMA_SQCCMR); + + /* + * Initialize status queue registers to point to the first + * command descriptor in memory. + * Dequeue Pointer Address Registers + * Enqueue Pointer Address Registers + */ + + qdma_writel( + upper_32_bits(fsl_qdma->status[j]->bus_addr), + block + FSL_QDMA_SQEEPAR); + qdma_writel( + lower_32_bits(fsl_qdma->status[j]->bus_addr), + block + FSL_QDMA_SQEPAR); + qdma_writel( + upper_32_bits(fsl_qdma->status[j]->bus_addr), + block + FSL_QDMA_SQEDPAR); + qdma_writel( + lower_32_bits(fsl_qdma->status[j]->bus_addr), + block + FSL_QDMA_SQDPAR); + /* Desiable status queue interrupt. */ + + qdma_writel(0x0, block + FSL_QDMA_BCQIER(0)); + qdma_writel(0x0, block + FSL_QDMA_BSQICR); + qdma_writel(0x0, block + FSL_QDMA_CQIER); + + /* Initialize the status queue mode. */ + reg = FSL_QDMA_BSQMR_EN; + val = ilog2(fsl_qdma->status[j]->n_cq) - 6; + reg |= FSL_QDMA_BSQMR_CQ_SIZE(val); + qdma_writel(reg, block + FSL_QDMA_BSQMR); + } + + reg = qdma_readl(ctrl + FSL_QDMA_DMR); + reg &= ~FSL_QDMA_DMR_DQD; + qdma_writel(reg, ctrl + FSL_QDMA_DMR); + + return 0; +} + +static void +dma_release(void *fsl_chan) +{ + ((struct fsl_qdma_chan *)fsl_chan)->free = true; + fsl_qdma_free_chan_resources((struct fsl_qdma_chan *)fsl_chan); +} + +static int +dpaa_qdma_init(struct rte_dma_dev *dmadev) +{ + struct fsl_qdma_engine *fsl_qdma = dmadev->data->dev_private; + struct fsl_qdma_chan *fsl_chan; + uint64_t phys_addr; + unsigned int len; + int ccsr_qdma_fd; + int regs_size; + int ret; + u32 i; + + fsl_qdma->desc_allocated = 0; + fsl_qdma->n_chans = VIRT_CHANNELS; + fsl_qdma->n_queues = QDMA_QUEUES; + fsl_qdma->num_blocks = QDMA_BLOCKS; + fsl_qdma->block_offset = QDMA_BLOCK_OFFSET; + + len = sizeof(*fsl_chan) * fsl_qdma->n_chans; + fsl_qdma->chans = rte_zmalloc("qdma: fsl chans", len, 0); + if (!fsl_qdma->chans) + return -1; + + len = sizeof(struct fsl_qdma_queue *) * fsl_qdma->num_blocks; + fsl_qdma->status = rte_zmalloc("qdma: fsl status", len, 0); + if (!fsl_qdma->status) { + rte_free(fsl_qdma->chans); + return -1; + } + + for (i = 0; i < fsl_qdma->num_blocks; i++) { + rte_atomic32_init(&wait_task[i]); + fsl_qdma->status[i] = fsl_qdma_prep_status_queue(); + if (!fsl_qdma->status[i]) + goto err; + } + + ccsr_qdma_fd = open("/dev/mem", O_RDWR); + if (unlikely(ccsr_qdma_fd < 0)) { + DPAA_QDMA_ERR("Can not open /dev/mem for qdma CCSR map"); + goto err; + } + + regs_size = fsl_qdma->block_offset * (fsl_qdma->num_blocks + 2); + phys_addr = QDMA_CCSR_BASE; + fsl_qdma->ctrl_base = mmap(NULL, regs_size, PROT_READ | + PROT_WRITE, MAP_SHARED, + ccsr_qdma_fd, phys_addr); + + close(ccsr_qdma_fd); + if (fsl_qdma->ctrl_base == MAP_FAILED) { + DPAA_QDMA_ERR("Can not map CCSR base qdma: Phys: %08" PRIx64 + "size %d\n", phys_addr, regs_size); + goto err; + } + + fsl_qdma->status_base = fsl_qdma->ctrl_base + QDMA_BLOCK_OFFSET; + fsl_qdma->block_base = fsl_qdma->status_base + QDMA_BLOCK_OFFSET; + + fsl_qdma->queue = fsl_qdma_alloc_queue_resources(fsl_qdma); + if (!fsl_qdma->queue) { + munmap(fsl_qdma->ctrl_base, regs_size); + goto err; + } + + for (i = 0; i < fsl_qdma->n_chans; i++) { + struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i]; + + fsl_chan->qdma = fsl_qdma; + fsl_chan->queue = fsl_qdma->queue + i % (fsl_qdma->n_queues * + fsl_qdma->num_blocks); + fsl_chan->free = true; + } + + ret = fsl_qdma_reg_init(fsl_qdma); + if (ret) { + DPAA_QDMA_ERR("Can't Initialize the qDMA engine.\n"); + munmap(fsl_qdma->ctrl_base, regs_size); + goto err; + } + + return 0; + +err: + rte_free(fsl_qdma->chans); + rte_free(fsl_qdma->status); + + return -1; +} static int dpaa_qdma_probe(__rte_unused struct rte_dpaa_driver *dpaa_drv, - __rte_unused struct rte_dpaa_device *dpaa_dev) + struct rte_dpaa_device *dpaa_dev) { + struct rte_dma_dev *dmadev; + int ret; + + dmadev = rte_dma_pmd_allocate(dpaa_dev->device.name, + rte_socket_id(), + sizeof(struct fsl_qdma_engine)); + if (!dmadev) { + DPAA_QDMA_ERR("Unable to allocate dmadevice"); + return -EINVAL; + } + + dpaa_dev->dmadev = dmadev; + + /* Invoke PMD device initialization function */ + ret = dpaa_qdma_init(dmadev); + if (ret) { + (void)rte_dma_pmd_release(dpaa_dev->device.name); + return ret; + } + + dmadev->state = RTE_DMA_DEV_READY; return 0; } static int -dpaa_qdma_remove(__rte_unused struct rte_dpaa_device *dpaa_dev) +dpaa_qdma_remove(struct rte_dpaa_device *dpaa_dev) { + struct rte_dma_dev *dmadev = dpaa_dev->dmadev; + struct fsl_qdma_engine *fsl_qdma = dmadev->data->dev_private; + int i = 0, max = QDMA_QUEUES * QDMA_BLOCKS; + + for (i = 0; i < max; i++) { + struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i]; + + if (fsl_chan->free == false) + dma_release(fsl_chan); + } + + rte_free(fsl_qdma->status); + rte_free(fsl_qdma->chans); + + (void)rte_dma_pmd_release(dpaa_dev->device.name); + return 0; } diff --git a/drivers/dma/dpaa/dpaa_qdma.h b/drivers/dma/dpaa/dpaa_qdma.h new file mode 100644 index 0000000000..c05620b740 --- /dev/null +++ b/drivers/dma/dpaa/dpaa_qdma.h @@ -0,0 +1,236 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2021 NXP + */ + +#ifndef _DPAA_QDMA_H_ +#define _DPAA_QDMA_H_ + +#include + +#define CORE_NUMBER 4 +#define RETRIES 5 + +#define FSL_QDMA_DMR 0x0 +#define FSL_QDMA_DSR 0x4 +#define FSL_QDMA_DEIER 0xe00 +#define FSL_QDMA_DEDR 0xe04 +#define FSL_QDMA_DECFDW0R 0xe10 +#define FSL_QDMA_DECFDW1R 0xe14 +#define FSL_QDMA_DECFDW2R 0xe18 +#define FSL_QDMA_DECFDW3R 0xe1c +#define FSL_QDMA_DECFQIDR 0xe30 +#define FSL_QDMA_DECBR 0xe34 + +#define FSL_QDMA_BCQMR(x) (0xc0 + 0x100 * (x)) +#define FSL_QDMA_BCQSR(x) (0xc4 + 0x100 * (x)) +#define FSL_QDMA_BCQEDPA_SADDR(x) (0xc8 + 0x100 * (x)) +#define FSL_QDMA_BCQDPA_SADDR(x) (0xcc + 0x100 * (x)) +#define FSL_QDMA_BCQEEPA_SADDR(x) (0xd0 + 0x100 * (x)) +#define FSL_QDMA_BCQEPA_SADDR(x) (0xd4 + 0x100 * (x)) +#define FSL_QDMA_BCQIER(x) (0xe0 + 0x100 * (x)) +#define FSL_QDMA_BCQIDR(x) (0xe4 + 0x100 * (x)) + +#define FSL_QDMA_SQEDPAR 0x808 +#define FSL_QDMA_SQDPAR 0x80c +#define FSL_QDMA_SQEEPAR 0x810 +#define FSL_QDMA_SQEPAR 0x814 +#define FSL_QDMA_BSQMR 0x800 +#define FSL_QDMA_BSQSR 0x804 +#define FSL_QDMA_BSQICR 0x828 +#define FSL_QDMA_CQMR 0xa00 +#define FSL_QDMA_CQDSCR1 0xa08 +#define FSL_QDMA_CQDSCR2 0xa0c +#define FSL_QDMA_CQIER 0xa10 +#define FSL_QDMA_CQEDR 0xa14 +#define FSL_QDMA_SQCCMR 0xa20 + +#define FSL_QDMA_SQICR_ICEN + +#define FSL_QDMA_CQIDR_CQT 0xff000000 +#define FSL_QDMA_CQIDR_SQPE 0x800000 +#define FSL_QDMA_CQIDR_SQT 0x8000 + +#define FSL_QDMA_BCQIER_CQTIE 0x8000 +#define FSL_QDMA_BCQIER_CQPEIE 0x800000 +#define FSL_QDMA_BSQICR_ICEN 0x80000000 +#define FSL_QDMA_BSQICR_ICST(x) ((x) << 16) +#define FSL_QDMA_CQIER_MEIE 0x80000000 +#define FSL_QDMA_CQIER_TEIE 0x1 +#define FSL_QDMA_SQCCMR_ENTER_WM 0x200000 + +#define FSL_QDMA_QUEUE_MAX 8 + +#define FSL_QDMA_BCQMR_EN 0x80000000 +#define FSL_QDMA_BCQMR_EI 0x40000000 +#define FSL_QDMA_BCQMR_EI_BE 0x40 +#define FSL_QDMA_BCQMR_CD_THLD(x) ((x) << 20) +#define FSL_QDMA_BCQMR_CQ_SIZE(x) ((x) << 16) + +#define FSL_QDMA_BCQSR_QF 0x10000 +#define FSL_QDMA_BCQSR_XOFF 0x1 +#define FSL_QDMA_BCQSR_QF_XOFF_BE 0x1000100 + +#define FSL_QDMA_BSQMR_EN 0x80000000 +#define FSL_QDMA_BSQMR_DI 0x40000000 +#define FSL_QDMA_BSQMR_DI_BE 0x40 +#define FSL_QDMA_BSQMR_CQ_SIZE(x) ((x) << 16) + +#define FSL_QDMA_BSQSR_QE 0x20000 +#define FSL_QDMA_BSQSR_QE_BE 0x200 +#define FSL_QDMA_BSQSR_QF 0x10000 + +#define FSL_QDMA_DMR_DQD 0x40000000 +#define FSL_QDMA_DSR_DB 0x80000000 + +#define FSL_QDMA_COMMAND_BUFFER_SIZE 64 +#define FSL_QDMA_DESCRIPTOR_BUFFER_SIZE 32 +#define FSL_QDMA_CIRCULAR_DESC_SIZE_MIN 64 +#define FSL_QDMA_CIRCULAR_DESC_SIZE_MAX 16384 +#define FSL_QDMA_QUEUE_NUM_MAX 8 + +#define FSL_QDMA_CMD_RWTTYPE 0x4 +#define FSL_QDMA_CMD_LWC 0x2 + +#define FSL_QDMA_CMD_RWTTYPE_OFFSET 28 +#define FSL_QDMA_CMD_NS_OFFSET 27 +#define FSL_QDMA_CMD_DQOS_OFFSET 24 +#define FSL_QDMA_CMD_WTHROTL_OFFSET 20 +#define FSL_QDMA_CMD_DSEN_OFFSET 19 +#define FSL_QDMA_CMD_LWC_OFFSET 16 + +#define QDMA_CCDF_STATUS 20 +#define QDMA_CCDF_OFFSET 20 +#define QDMA_CCDF_MASK GENMASK(28, 20) +#define QDMA_CCDF_FOTMAT BIT(29) +#define QDMA_CCDF_SER BIT(30) + +#define QDMA_SG_FIN BIT(30) +#define QDMA_SG_EXT BIT(31) +#define QDMA_SG_LEN_MASK GENMASK(29, 0) + +#define QDMA_BIG_ENDIAN 1 +#define COMP_TIMEOUT 100000 +#define COMMAND_QUEUE_OVERFLLOW 10 + +/* qdma engine attribute */ +#define QDMA_QUEUE_SIZE 64 +#define QDMA_STATUS_SIZE 64 +#define QDMA_CCSR_BASE 0x8380000 +#define VIRT_CHANNELS 32 +#define QDMA_BLOCK_OFFSET 0x10000 +#define QDMA_BLOCKS 4 +#define QDMA_QUEUES 8 +#define QDMA_DELAY 1000 + +#ifdef QDMA_BIG_ENDIAN +#define QDMA_IN(addr) be32_to_cpu(rte_read32(addr)) +#define QDMA_OUT(addr, val) rte_write32(be32_to_cpu(val), addr) +#define QDMA_IN_BE(addr) rte_read32(addr) +#define QDMA_OUT_BE(addr, val) rte_write32(val, addr) +#else +#define QDMA_IN(addr) rte_read32(addr) +#define QDMA_OUT(addr, val) rte_write32(val, addr) +#define QDMA_IN_BE(addr) be32_to_cpu(rte_write32(addr)) +#define QDMA_OUT_BE(addr, val) rte_write32(be32_to_cpu(val), addr) +#endif + +#define FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma_engine, x) \ + (((fsl_qdma_engine)->block_offset) * (x)) + +typedef void (*dma_call_back)(void *params); + +/* qDMA Command Descriptor Formats */ +struct fsl_qdma_format { + __le32 status; /* ser, status */ + __le32 cfg; /* format, offset */ + union { + struct { + __le32 addr_lo; /* low 32-bits of 40-bit address */ + u8 addr_hi; /* high 8-bits of 40-bit address */ + u8 __reserved1[2]; + u8 cfg8b_w1; /* dd, queue */ + }; + __le64 data; + }; +}; + +/* qDMA Source Descriptor Format */ +struct fsl_qdma_sdf { + __le32 rev3; + __le32 cfg; /* rev4, bit[0-11] - ssd, bit[12-23] sss */ + __le32 rev5; + __le32 cmd; +}; + +/* qDMA Destination Descriptor Format */ +struct fsl_qdma_ddf { + __le32 rev1; + __le32 cfg; /* rev2, bit[0-11] - dsd, bit[12-23] - dss */ + __le32 rev3; + __le32 cmd; +}; + +enum dma_status { + DMA_COMPLETE, + DMA_IN_PROGRESS, + DMA_IN_PREPAR, + DMA_PAUSED, + DMA_ERROR, +}; + +struct fsl_qdma_chan { + struct fsl_qdma_engine *qdma; + struct fsl_qdma_queue *queue; + bool free; + struct list_head list; +}; + +struct fsl_qdma_list { + struct list_head dma_list; +}; + +struct fsl_qdma_queue { + struct fsl_qdma_format *virt_head; + struct list_head comp_used; + struct list_head comp_free; + dma_addr_t bus_addr; + u32 n_cq; + u32 id; + u32 count; + u32 pending; + struct fsl_qdma_format *cq; + void *block_base; +}; + +struct fsl_qdma_comp { + dma_addr_t bus_addr; + dma_addr_t desc_bus_addr; + void *virt_addr; + int index; + void *desc_virt_addr; + struct fsl_qdma_chan *qchan; + dma_call_back call_back_func; + void *params; + struct list_head list; +}; + +struct fsl_qdma_engine { + int desc_allocated; + void *ctrl_base; + void *status_base; + void *block_base; + u32 n_chans; + u32 n_queues; + int error_irq; + struct fsl_qdma_queue *queue; + struct fsl_qdma_queue **status; + struct fsl_qdma_chan *chans; + u32 num_blocks; + u8 free_block_id; + u32 vchan_map[4]; + int block_offset; +}; + +static rte_atomic32_t wait_task[CORE_NUMBER]; + +#endif /* _DPAA_QDMA_H_ */ From patchwork Tue Nov 9 04:39:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gagandeep Singh X-Patchwork-Id: 104029 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4BB1BA0C4B; Tue, 9 Nov 2021 05:40:02 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org 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X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 41ade81e-553b-4382-6377-08d9a33af3e0 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB6960.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2021 04:39:44.7114 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Au7PpXLLbRhSFrZev6AISViZM3g3bJDzRUSLkNlkGeND+TQsUNKKv6IyAnr/rZtX X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB5630 Subject: [dpdk-dev] [PATCH v4 3/5] dma/dpaa: support basic operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch support basic DMA operations which includes device capability and channel setup. Signed-off-by: Gagandeep Singh --- drivers/dma/dpaa/dpaa_qdma.c | 204 +++++++++++++++++++++++++++++++++++ drivers/dma/dpaa/dpaa_qdma.h | 6 ++ 2 files changed, 210 insertions(+) diff --git a/drivers/dma/dpaa/dpaa_qdma.c b/drivers/dma/dpaa/dpaa_qdma.c index c3255dc0c7..e59cd36872 100644 --- a/drivers/dma/dpaa/dpaa_qdma.c +++ b/drivers/dma/dpaa/dpaa_qdma.c @@ -8,6 +8,19 @@ #include "dpaa_qdma.h" #include "dpaa_qdma_logs.h" +static inline void +qdma_desc_addr_set64(struct fsl_qdma_format *ccdf, u64 addr) +{ + ccdf->addr_hi = upper_32_bits(addr); + ccdf->addr_lo = rte_cpu_to_le_32(lower_32_bits(addr)); +} + +static inline void +qdma_csgf_set_len(struct fsl_qdma_format *csgf, int len) +{ + csgf->cfg = rte_cpu_to_le_32(len & QDMA_SG_LEN_MASK); +} + static inline int ilog2(int x) { @@ -91,6 +104,77 @@ fsl_qdma_free_chan_resources(struct fsl_qdma_chan *fsl_chan) fsl_qdma->desc_allocated--; } +/* + * Pre-request command descriptor and compound S/G for enqueue. + */ +static int +fsl_qdma_pre_request_enqueue_comp_sd_desc( + struct fsl_qdma_queue *queue, + int size, int aligned) +{ + struct fsl_qdma_comp *comp_temp, *_comp_temp; + struct fsl_qdma_sdf *sdf; + struct fsl_qdma_ddf *ddf; + struct fsl_qdma_format *csgf_desc; + int i; + + for (i = 0; i < (int)(queue->n_cq + COMMAND_QUEUE_OVERFLLOW); i++) { + comp_temp = rte_zmalloc("qdma: comp temp", + sizeof(*comp_temp), 0); + if (!comp_temp) + return -ENOMEM; + + comp_temp->virt_addr = + dma_pool_alloc(size, aligned, &comp_temp->bus_addr); + if (!comp_temp->virt_addr) { + rte_free(comp_temp); + goto fail; + } + + comp_temp->desc_virt_addr = + dma_pool_alloc(size, aligned, &comp_temp->desc_bus_addr); + if (!comp_temp->desc_virt_addr) { + rte_free(comp_temp->virt_addr); + rte_free(comp_temp); + goto fail; + } + + memset(comp_temp->virt_addr, 0, FSL_QDMA_COMMAND_BUFFER_SIZE); + memset(comp_temp->desc_virt_addr, 0, + FSL_QDMA_DESCRIPTOR_BUFFER_SIZE); + + csgf_desc = (struct fsl_qdma_format *)comp_temp->virt_addr + 1; + sdf = (struct fsl_qdma_sdf *)comp_temp->desc_virt_addr; + ddf = (struct fsl_qdma_ddf *)comp_temp->desc_virt_addr + 1; + /* Compound Command Descriptor(Frame List Table) */ + qdma_desc_addr_set64(csgf_desc, comp_temp->desc_bus_addr); + /* It must be 32 as Compound S/G Descriptor */ + qdma_csgf_set_len(csgf_desc, 32); + /* Descriptor Buffer */ + sdf->cmd = rte_cpu_to_le_32(FSL_QDMA_CMD_RWTTYPE << + FSL_QDMA_CMD_RWTTYPE_OFFSET); + ddf->cmd = rte_cpu_to_le_32(FSL_QDMA_CMD_RWTTYPE << + FSL_QDMA_CMD_RWTTYPE_OFFSET); + ddf->cmd |= rte_cpu_to_le_32(FSL_QDMA_CMD_LWC << + FSL_QDMA_CMD_LWC_OFFSET); + + list_add_tail(&comp_temp->list, &queue->comp_free); + } + + return 0; + +fail: + list_for_each_entry_safe(comp_temp, _comp_temp, + &queue->comp_free, list) { + list_del(&comp_temp->list); + rte_free(comp_temp->virt_addr); + rte_free(comp_temp->desc_virt_addr); + rte_free(comp_temp); + } + + return -ENOMEM; +} + static struct fsl_qdma_queue *fsl_qdma_alloc_queue_resources(struct fsl_qdma_engine *fsl_qdma) { @@ -335,6 +419,84 @@ fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma) return 0; } +static int +fsl_qdma_alloc_chan_resources(struct fsl_qdma_chan *fsl_chan) +{ + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue; + struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma; + int ret; + + if (fsl_queue->count++) + goto finally; + + INIT_LIST_HEAD(&fsl_queue->comp_free); + INIT_LIST_HEAD(&fsl_queue->comp_used); + + ret = fsl_qdma_pre_request_enqueue_comp_sd_desc(fsl_queue, + FSL_QDMA_COMMAND_BUFFER_SIZE, 64); + if (ret) { + DPAA_QDMA_ERR( + "failed to alloc dma buffer for comp descriptor\n"); + goto exit; + } + +finally: + return fsl_qdma->desc_allocated++; + +exit: + return -ENOMEM; +} + +static int +dpaa_info_get(const struct rte_dma_dev *dev, struct rte_dma_info *dev_info, + uint32_t info_sz) +{ +#define DPAADMA_MAX_DESC 64 +#define DPAADMA_MIN_DESC 64 + + RTE_SET_USED(dev); + RTE_SET_USED(info_sz); + + dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM | + RTE_DMA_CAPA_MEM_TO_DEV | + RTE_DMA_CAPA_DEV_TO_DEV | + RTE_DMA_CAPA_DEV_TO_MEM | + RTE_DMA_CAPA_SILENT | + RTE_DMA_CAPA_OPS_COPY; + dev_info->max_vchans = 1; + dev_info->max_desc = DPAADMA_MAX_DESC; + dev_info->min_desc = DPAADMA_MIN_DESC; + + return 0; +} + +static int +dpaa_get_channel(struct fsl_qdma_engine *fsl_qdma, uint16_t vchan) +{ + u32 i, start, end; + int ret; + + start = fsl_qdma->free_block_id * QDMA_QUEUES; + fsl_qdma->free_block_id++; + + end = start + 1; + for (i = start; i < end; i++) { + struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i]; + + if (fsl_chan->free) { + fsl_chan->free = false; + ret = fsl_qdma_alloc_chan_resources(fsl_chan); + if (ret) + return ret; + + fsl_qdma->vchan_map[vchan] = i; + return 0; + } + } + + return -1; +} + static void dma_release(void *fsl_chan) { @@ -342,6 +504,45 @@ dma_release(void *fsl_chan) fsl_qdma_free_chan_resources((struct fsl_qdma_chan *)fsl_chan); } +static int +dpaa_qdma_configure(__rte_unused struct rte_dma_dev *dmadev, + __rte_unused const struct rte_dma_conf *dev_conf, + __rte_unused uint32_t conf_sz) +{ + return 0; +} + +static int +dpaa_qdma_start(__rte_unused struct rte_dma_dev *dev) +{ + return 0; +} + +static int +dpaa_qdma_close(__rte_unused struct rte_dma_dev *dev) +{ + return 0; +} + +static int +dpaa_qdma_queue_setup(struct rte_dma_dev *dmadev, + uint16_t vchan, + __rte_unused const struct rte_dma_vchan_conf *conf, + __rte_unused uint32_t conf_sz) +{ + struct fsl_qdma_engine *fsl_qdma = dmadev->data->dev_private; + + return dpaa_get_channel(fsl_qdma, vchan); +} + +static struct rte_dma_dev_ops dpaa_qdma_ops = { + .dev_info_get = dpaa_info_get, + .dev_configure = dpaa_qdma_configure, + .dev_start = dpaa_qdma_start, + .dev_close = dpaa_qdma_close, + .vchan_setup = dpaa_qdma_queue_setup, +}; + static int dpaa_qdma_init(struct rte_dma_dev *dmadev) { @@ -448,6 +649,9 @@ dpaa_qdma_probe(__rte_unused struct rte_dpaa_driver *dpaa_drv, } dpaa_dev->dmadev = dmadev; + dmadev->dev_ops = &dpaa_qdma_ops; + dmadev->device = &dpaa_dev->device; + dmadev->fp_obj->dev_private = dmadev->data->dev_private; /* Invoke PMD device initialization function */ ret = dpaa_qdma_init(dmadev); diff --git a/drivers/dma/dpaa/dpaa_qdma.h b/drivers/dma/dpaa/dpaa_qdma.h index c05620b740..f046167108 100644 --- a/drivers/dma/dpaa/dpaa_qdma.h +++ b/drivers/dma/dpaa/dpaa_qdma.h @@ -10,6 +10,12 @@ #define CORE_NUMBER 4 #define RETRIES 5 +#ifndef GENMASK +#define BITS_PER_LONG (__SIZEOF_LONG__ * 8) +#define GENMASK(h, l) \ + (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) +#endif + #define FSL_QDMA_DMR 0x0 #define FSL_QDMA_DSR 0x4 #define FSL_QDMA_DEIER 0xe00 From patchwork Tue Nov 9 04:39:09 2021 Content-Type: text/plain; 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Signed-off-by: Gagandeep Singh --- doc/guides/dmadevs/dpaa.rst | 11 ++ drivers/dma/dpaa/dpaa_qdma.c | 334 +++++++++++++++++++++++++++++++++++ drivers/dma/dpaa/dpaa_qdma.h | 4 + 3 files changed, 349 insertions(+) diff --git a/doc/guides/dmadevs/dpaa.rst b/doc/guides/dmadevs/dpaa.rst index 885a8bb8aa..4fbd8a25fb 100644 --- a/doc/guides/dmadevs/dpaa.rst +++ b/doc/guides/dmadevs/dpaa.rst @@ -46,6 +46,17 @@ Initialization On EAL initialization, DPAA DMA devices will be detected on DPAA bus and will be probed and populated into their device list. +Features +-------- + +The DPAA DMA implements following features in the dmadev API: + +- Supports 1 virtual channel. +- Supports all 4 DMA transfers: MEM_TO_MEM, MEM_TO_DEV, + DEV_TO_MEM, DEV_TO_DEV. +- Supports DMA silent mode. +- Supports issuing DMA of data within memory without hogging CPU while + performing DMA operation. Platform Requirement ~~~~~~~~~~~~~~~~~~~~ diff --git a/drivers/dma/dpaa/dpaa_qdma.c b/drivers/dma/dpaa/dpaa_qdma.c index e59cd36872..ebe6211f08 100644 --- a/drivers/dma/dpaa/dpaa_qdma.c +++ b/drivers/dma/dpaa/dpaa_qdma.c @@ -15,12 +15,50 @@ qdma_desc_addr_set64(struct fsl_qdma_format *ccdf, u64 addr) ccdf->addr_lo = rte_cpu_to_le_32(lower_32_bits(addr)); } +static inline u64 +qdma_ccdf_get_queue(const struct fsl_qdma_format *ccdf) +{ + return ccdf->cfg8b_w1 & 0xff; +} + +static inline int +qdma_ccdf_get_offset(const struct fsl_qdma_format *ccdf) +{ + return (rte_le_to_cpu_32(ccdf->cfg) & QDMA_CCDF_MASK) + >> QDMA_CCDF_OFFSET; +} + +static inline void +qdma_ccdf_set_format(struct fsl_qdma_format *ccdf, int offset) +{ + ccdf->cfg = rte_cpu_to_le_32(QDMA_CCDF_FOTMAT | offset); +} + +static inline int +qdma_ccdf_get_status(const struct fsl_qdma_format *ccdf) +{ + return (rte_le_to_cpu_32(ccdf->status) & QDMA_CCDF_MASK) + >> QDMA_CCDF_STATUS; +} + +static inline void +qdma_ccdf_set_ser(struct fsl_qdma_format *ccdf, int status) +{ + ccdf->status = rte_cpu_to_le_32(QDMA_CCDF_SER | status); +} + static inline void qdma_csgf_set_len(struct fsl_qdma_format *csgf, int len) { csgf->cfg = rte_cpu_to_le_32(len & QDMA_SG_LEN_MASK); } +static inline void +qdma_csgf_set_f(struct fsl_qdma_format *csgf, int len) +{ + csgf->cfg = rte_cpu_to_le_32(QDMA_SG_FIN | (len & QDMA_SG_LEN_MASK)); +} + static inline int ilog2(int x) { @@ -47,6 +85,18 @@ qdma_writel(u32 val, void *addr) QDMA_OUT(addr, val); } +static u32 +qdma_readl_be(void *addr) +{ + return QDMA_IN_BE(addr); +} + +static void +qdma_writel_be(u32 val, void *addr) +{ + QDMA_OUT_BE(addr, val); +} + static void *dma_pool_alloc(int size, int aligned, dma_addr_t *phy_addr) { @@ -104,6 +154,32 @@ fsl_qdma_free_chan_resources(struct fsl_qdma_chan *fsl_chan) fsl_qdma->desc_allocated--; } +static void +fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp, + dma_addr_t dst, dma_addr_t src, u32 len) +{ + struct fsl_qdma_format *csgf_src, *csgf_dest; + + /* Note: command table (fsl_comp->virt_addr) is getting filled + * directly in cmd descriptors of queues while enqueuing the descriptor + * please refer fsl_qdma_enqueue_desc + * frame list table (virt_addr) + 1) and source, + * destination descriptor table + * (fsl_comp->desc_virt_addr and fsl_comp->desc_virt_addr+1) move to + * the control path to fsl_qdma_pre_request_enqueue_comp_sd_desc + */ + csgf_src = (struct fsl_qdma_format *)fsl_comp->virt_addr + 2; + csgf_dest = (struct fsl_qdma_format *)fsl_comp->virt_addr + 3; + + /* Status notification is enqueued to status queue. */ + qdma_desc_addr_set64(csgf_src, src); + qdma_csgf_set_len(csgf_src, len); + qdma_desc_addr_set64(csgf_dest, dst); + qdma_csgf_set_len(csgf_dest, len); + /* This entry is the last entry. */ + qdma_csgf_set_f(csgf_dest, len); +} + /* * Pre-request command descriptor and compound S/G for enqueue. */ @@ -175,6 +251,26 @@ fsl_qdma_pre_request_enqueue_comp_sd_desc( return -ENOMEM; } +/* + * Request a command descriptor for enqueue. + */ +static struct fsl_qdma_comp * +fsl_qdma_request_enqueue_desc(struct fsl_qdma_chan *fsl_chan) +{ + struct fsl_qdma_queue *queue = fsl_chan->queue; + struct fsl_qdma_comp *comp_temp; + + if (!list_empty(&queue->comp_free)) { + comp_temp = list_first_entry(&queue->comp_free, + struct fsl_qdma_comp, + list); + list_del(&comp_temp->list); + return comp_temp; + } + + return NULL; +} + static struct fsl_qdma_queue *fsl_qdma_alloc_queue_resources(struct fsl_qdma_engine *fsl_qdma) { @@ -324,6 +420,54 @@ fsl_qdma_halt(struct fsl_qdma_engine *fsl_qdma) return 0; } +static int +fsl_qdma_queue_transfer_complete(struct fsl_qdma_engine *fsl_qdma, + void *block, int id, const uint16_t nb_cpls, + uint16_t *last_idx, + enum rte_dma_status_code *status) +{ + struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue; + struct fsl_qdma_queue *fsl_status = fsl_qdma->status[id]; + struct fsl_qdma_queue *temp_queue; + struct fsl_qdma_format *status_addr; + struct fsl_qdma_comp *fsl_comp = NULL; + u32 reg, i; + int count = 0; + + while (count < nb_cpls) { + reg = qdma_readl_be(block + FSL_QDMA_BSQSR); + if (reg & FSL_QDMA_BSQSR_QE_BE) + return count; + + status_addr = fsl_status->virt_head; + + i = qdma_ccdf_get_queue(status_addr) + + id * fsl_qdma->n_queues; + temp_queue = fsl_queue + i; + fsl_comp = list_first_entry(&temp_queue->comp_used, + struct fsl_qdma_comp, + list); + list_del(&fsl_comp->list); + + reg = qdma_readl_be(block + FSL_QDMA_BSQMR); + reg |= FSL_QDMA_BSQMR_DI_BE; + + qdma_desc_addr_set64(status_addr, 0x0); + fsl_status->virt_head++; + if (fsl_status->virt_head == fsl_status->cq + fsl_status->n_cq) + fsl_status->virt_head = fsl_status->cq; + qdma_writel_be(reg, block + FSL_QDMA_BSQMR); + *last_idx = fsl_comp->index; + if (status != NULL) + status[count] = RTE_DMA_STATUS_SUCCESSFUL; + + list_add_tail(&fsl_comp->list, &temp_queue->comp_free); + count++; + + } + return count; +} + static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma) { @@ -419,6 +563,66 @@ fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma) return 0; } +static void * +fsl_qdma_prep_memcpy(void *fsl_chan, dma_addr_t dst, + dma_addr_t src, size_t len, + void *call_back, + void *param) +{ + struct fsl_qdma_comp *fsl_comp; + + fsl_comp = + fsl_qdma_request_enqueue_desc((struct fsl_qdma_chan *)fsl_chan); + if (!fsl_comp) + return NULL; + + fsl_comp->qchan = fsl_chan; + fsl_comp->call_back_func = call_back; + fsl_comp->params = param; + + fsl_qdma_comp_fill_memcpy(fsl_comp, dst, src, len); + return (void *)fsl_comp; +} + +static int +fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan, + struct fsl_qdma_comp *fsl_comp, + uint64_t flags) +{ + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue; + void *block = fsl_queue->block_base; + struct fsl_qdma_format *ccdf; + u32 reg; + + /* retrieve and store the register value in big endian + * to avoid bits swap + */ + reg = qdma_readl_be(block + + FSL_QDMA_BCQSR(fsl_queue->id)); + if (reg & (FSL_QDMA_BCQSR_QF_XOFF_BE)) + return -1; + + /* filling descriptor command table */ + ccdf = (struct fsl_qdma_format *)fsl_queue->virt_head; + qdma_desc_addr_set64(ccdf, fsl_comp->bus_addr + 16); + qdma_ccdf_set_format(ccdf, qdma_ccdf_get_offset(fsl_comp->virt_addr)); + qdma_ccdf_set_ser(ccdf, qdma_ccdf_get_status(fsl_comp->virt_addr)); + fsl_comp->index = fsl_queue->virt_head - fsl_queue->cq; + fsl_queue->virt_head++; + + if (fsl_queue->virt_head == fsl_queue->cq + fsl_queue->n_cq) + fsl_queue->virt_head = fsl_queue->cq; + + list_add_tail(&fsl_comp->list, &fsl_queue->comp_used); + + if (flags == RTE_DMA_OP_FLAG_SUBMIT) { + reg = qdma_readl_be(block + FSL_QDMA_BCQMR(fsl_queue->id)); + reg |= FSL_QDMA_BCQMR_EI_BE; + qdma_writel_be(reg, block + FSL_QDMA_BCQMR(fsl_queue->id)); + } + return fsl_comp->index; +} + static int fsl_qdma_alloc_chan_resources(struct fsl_qdma_chan *fsl_chan) { @@ -535,6 +739,132 @@ dpaa_qdma_queue_setup(struct rte_dma_dev *dmadev, return dpaa_get_channel(fsl_qdma, vchan); } +static int +dpaa_qdma_submit(void *dev_private, uint16_t vchan) +{ + struct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private; + struct fsl_qdma_chan *fsl_chan = + &fsl_qdma->chans[fsl_qdma->vchan_map[vchan]]; + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue; + void *block = fsl_queue->block_base; + u32 reg; + + while (fsl_queue->pending) { + reg = qdma_readl_be(block + FSL_QDMA_BCQMR(fsl_queue->id)); + reg |= FSL_QDMA_BCQMR_EI_BE; + qdma_writel_be(reg, block + FSL_QDMA_BCQMR(fsl_queue->id)); + fsl_queue->pending--; + } + + return 0; +} + +static int +dpaa_qdma_enqueue(void *dev_private, uint16_t vchan, + rte_iova_t src, rte_iova_t dst, + uint32_t length, uint64_t flags) +{ + struct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private; + struct fsl_qdma_chan *fsl_chan = + &fsl_qdma->chans[fsl_qdma->vchan_map[vchan]]; + int ret; + + void *fsl_comp = NULL; + + fsl_comp = fsl_qdma_prep_memcpy(fsl_chan, + (dma_addr_t)dst, (dma_addr_t)src, + length, NULL, NULL); + if (!fsl_comp) { + DPAA_QDMA_DP_DEBUG("fsl_comp is NULL\n"); + return -1; + } + ret = fsl_qdma_enqueue_desc(fsl_chan, fsl_comp, flags); + + return ret; +} + +static uint16_t +dpaa_qdma_dequeue_status(void *dev_private, uint16_t vchan, + const uint16_t nb_cpls, uint16_t *last_idx, + enum rte_dma_status_code *st) +{ + struct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private; + int id = (int)((fsl_qdma->vchan_map[vchan]) / QDMA_QUEUES); + void *block; + int intr; + void *status = fsl_qdma->status_base; + + intr = qdma_readl_be(status + FSL_QDMA_DEDR); + if (intr) { + DPAA_QDMA_ERR("DMA transaction error! %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW0R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW0R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW1R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW1R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW2R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW2R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW3R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW3R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFQIDR); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFQIDR %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECBR); + DPAA_QDMA_INFO("reg FSL_QDMA_DECBR %x\n", intr); + qdma_writel(0xffffffff, + status + FSL_QDMA_DEDR); + intr = qdma_readl(status + FSL_QDMA_DEDR); + } + + block = fsl_qdma->block_base + + FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id); + + intr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id, nb_cpls, + last_idx, st); + + return intr; +} + + +static uint16_t +dpaa_qdma_dequeue(void *dev_private, + uint16_t vchan, const uint16_t nb_cpls, + uint16_t *last_idx, bool *has_error) +{ + struct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private; + int id = (int)((fsl_qdma->vchan_map[vchan]) / QDMA_QUEUES); + void *block; + int intr; + void *status = fsl_qdma->status_base; + + intr = qdma_readl_be(status + FSL_QDMA_DEDR); + if (intr) { + DPAA_QDMA_ERR("DMA transaction error! %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW0R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW0R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW1R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW1R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW2R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW2R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW3R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW3R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFQIDR); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFQIDR %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECBR); + DPAA_QDMA_INFO("reg FSL_QDMA_DECBR %x\n", intr); + qdma_writel(0xffffffff, + status + FSL_QDMA_DEDR); + intr = qdma_readl(status + FSL_QDMA_DEDR); + *has_error = true; + } + + block = fsl_qdma->block_base + + FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id); + + intr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id, nb_cpls, + last_idx, NULL); + + return intr; +} + static struct rte_dma_dev_ops dpaa_qdma_ops = { .dev_info_get = dpaa_info_get, .dev_configure = dpaa_qdma_configure, @@ -652,6 +982,10 @@ dpaa_qdma_probe(__rte_unused struct rte_dpaa_driver *dpaa_drv, dmadev->dev_ops = &dpaa_qdma_ops; dmadev->device = &dpaa_dev->device; dmadev->fp_obj->dev_private = dmadev->data->dev_private; + dmadev->fp_obj->copy = dpaa_qdma_enqueue; + dmadev->fp_obj->submit = dpaa_qdma_submit; + dmadev->fp_obj->completed = dpaa_qdma_dequeue; + dmadev->fp_obj->completed_status = dpaa_qdma_dequeue_status; /* Invoke PMD device initialization function */ ret = dpaa_qdma_init(dmadev); diff --git a/drivers/dma/dpaa/dpaa_qdma.h b/drivers/dma/dpaa/dpaa_qdma.h index f046167108..6d0ac58317 100644 --- a/drivers/dma/dpaa/dpaa_qdma.h +++ b/drivers/dma/dpaa/dpaa_qdma.h @@ -7,6 +7,10 @@ #include +#ifndef BIT +#define BIT(nr) (1UL << (nr)) +#endif + #define CORE_NUMBER 4 #define RETRIES 5 From patchwork Tue Nov 9 04:39:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gagandeep Singh X-Patchwork-Id: 104031 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8D38BA0C4B; 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queue_temp->pending = 0; queue_temp->virt_head = queue_temp->cq; - + queue_temp->stats = (struct rte_dma_stats){0}; } } return queue_head; @@ -619,6 +619,9 @@ fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan, reg = qdma_readl_be(block + FSL_QDMA_BCQMR(fsl_queue->id)); reg |= FSL_QDMA_BCQMR_EI_BE; qdma_writel_be(reg, block + FSL_QDMA_BCQMR(fsl_queue->id)); + fsl_queue->stats.submitted++; + } else { + fsl_queue->pending++; } return fsl_comp->index; } @@ -754,6 +757,7 @@ dpaa_qdma_submit(void *dev_private, uint16_t vchan) reg |= FSL_QDMA_BCQMR_EI_BE; qdma_writel_be(reg, block + FSL_QDMA_BCQMR(fsl_queue->id)); fsl_queue->pending--; + fsl_queue->stats.submitted++; } return 0; @@ -793,6 +797,9 @@ dpaa_qdma_dequeue_status(void *dev_private, uint16_t vchan, void *block; int intr; void *status = fsl_qdma->status_base; + struct fsl_qdma_chan *fsl_chan = + &fsl_qdma->chans[fsl_qdma->vchan_map[vchan]]; + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue; intr = qdma_readl_be(status + FSL_QDMA_DEDR); if (intr) { @@ -812,6 +819,7 @@ dpaa_qdma_dequeue_status(void *dev_private, uint16_t vchan, qdma_writel(0xffffffff, status + FSL_QDMA_DEDR); intr = qdma_readl(status + FSL_QDMA_DEDR); + fsl_queue->stats.errors++; } block = fsl_qdma->block_base + @@ -819,6 +827,7 @@ dpaa_qdma_dequeue_status(void *dev_private, uint16_t vchan, intr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id, nb_cpls, last_idx, st); + fsl_queue->stats.completed += intr; return intr; } @@ -834,6 +843,9 @@ dpaa_qdma_dequeue(void *dev_private, void *block; int intr; void *status = fsl_qdma->status_base; + struct fsl_qdma_chan *fsl_chan = + &fsl_qdma->chans[fsl_qdma->vchan_map[vchan]]; + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue; intr = qdma_readl_be(status + FSL_QDMA_DEDR); if (intr) { @@ -854,6 +866,7 @@ dpaa_qdma_dequeue(void *dev_private, status + FSL_QDMA_DEDR); intr = qdma_readl(status + FSL_QDMA_DEDR); *has_error = true; + fsl_queue->stats.errors++; } block = fsl_qdma->block_base + @@ -861,16 +874,52 @@ dpaa_qdma_dequeue(void *dev_private, intr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id, nb_cpls, last_idx, NULL); + fsl_queue->stats.completed += intr; return intr; } +static int +dpaa_qdma_stats_get(const struct rte_dma_dev *dmadev, uint16_t vchan, + struct rte_dma_stats *rte_stats, uint32_t size) +{ + struct fsl_qdma_engine *fsl_qdma = dmadev->data->dev_private; + struct fsl_qdma_chan *fsl_chan = + &fsl_qdma->chans[fsl_qdma->vchan_map[vchan]]; + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue; + struct rte_dma_stats *stats = &fsl_queue->stats; + + if (size < sizeof(rte_stats)) + return -EINVAL; + if (rte_stats == NULL) + return -EINVAL; + + *rte_stats = *stats; + + return 0; +} + +static int +dpaa_qdma_stats_reset(struct rte_dma_dev *dmadev, uint16_t vchan) +{ + struct fsl_qdma_engine *fsl_qdma = dmadev->data->dev_private; + struct fsl_qdma_chan *fsl_chan = + &fsl_qdma->chans[fsl_qdma->vchan_map[vchan]]; + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue; + + fsl_queue->stats = (struct rte_dma_stats){0}; + + return 0; +} + static struct rte_dma_dev_ops dpaa_qdma_ops = { .dev_info_get = dpaa_info_get, .dev_configure = dpaa_qdma_configure, .dev_start = dpaa_qdma_start, .dev_close = dpaa_qdma_close, .vchan_setup = dpaa_qdma_queue_setup, + .stats_get = dpaa_qdma_stats_get, + .stats_reset = dpaa_qdma_stats_reset, }; static int diff --git a/drivers/dma/dpaa/dpaa_qdma.h b/drivers/dma/dpaa/dpaa_qdma.h index 6d0ac58317..bf49b2d5d9 100644 --- a/drivers/dma/dpaa/dpaa_qdma.h +++ b/drivers/dma/dpaa/dpaa_qdma.h @@ -210,6 +210,7 @@ struct fsl_qdma_queue { u32 pending; struct fsl_qdma_format *cq; void *block_base; + struct rte_dma_stats stats; }; struct fsl_qdma_comp {