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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT065.mail.protection.outlook.com (10.13.174.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4669.10 via Frontend Transport; Tue, 9 Nov 2021 12:36:31 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 9 Nov 2021 12:36:29 +0000 From: Matan Azrad To: Viacheslav Ovsiienko CC: , Thomas Monjalon , Michael Baum , , Michael Baum Date: Tue, 9 Nov 2021 14:36:08 +0200 Message-ID: <20211109123612.2301442-2-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211109123612.2301442-1-matan@nvidia.com> References: <20211108172113.2241853-1-matan@nvidia.com> <20211109123612.2301442-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4ec0e973-81d4-4014-03ab-08d9a37d8f0a X-MS-TrafficTypeDiagnostic: CY4PR1201MB0263: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:348; 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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(36906005)(26005)(336012)(70586007)(8676002)(6286002)(47076005)(356005)(6862004)(508600001)(2616005)(6666004)(107886003)(2906002)(1076003)(37006003)(426003)(54906003)(4326008)(5660300002)(7636003)(86362001)(316002)(16526019)(82310400003)(70206006)(6636002)(36860700001)(55016002)(83380400001)(186003)(8936002)(7696005)(36756003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2021 12:36:31.4644 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ec0e973-81d4-4014-03ab-08d9a37d8f0a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1201MB0263 Subject: [dpdk-dev] [PATCH v3 1/5] common/mlx5: glue MR registration with IOVA X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Michael Baum Add support for rdma-core API to register IOVA MR. The API gets the process VA, size, and IOVA and returns a memory region with space pointed by a specific IOVA. So any access in this MR should come with an address that is relative to the IOVA specified in the API. Fixes: cc07a42da250 ("vdpa/mlx5: prepare memory regions") Cc: stable@dpdk.org Signed-off-by: Michael Baum Signed-off-by: Matan Azrad --- drivers/common/mlx5/linux/meson.build | 2 ++ drivers/common/mlx5/linux/mlx5_glue.c | 18 ++++++++++++++++++ drivers/common/mlx5/linux/mlx5_glue.h | 3 +++ 3 files changed, 23 insertions(+) diff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build index 2dcd27b778..7909f23e21 100644 --- a/drivers/common/mlx5/linux/meson.build +++ b/drivers/common/mlx5/linux/meson.build @@ -200,6 +200,8 @@ has_sym_args = [ 'MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR' ], [ 'HAVE_MLX5_DR_ALLOW_DUPLICATE', 'infiniband/mlx5dv.h', 'mlx5dv_dr_domain_allow_duplicate_rules' ], + [ 'HAVE_MLX5_IBV_REG_MR_IOVA', 'infiniband/verbs.h', + 'ibv_reg_mr_iova' ], ] config = configuration_data() foreach arg:has_sym_args diff --git a/drivers/common/mlx5/linux/mlx5_glue.c b/drivers/common/mlx5/linux/mlx5_glue.c index 037ca961a0..bc6622053f 100644 --- a/drivers/common/mlx5/linux/mlx5_glue.c +++ b/drivers/common/mlx5/linux/mlx5_glue.c @@ -224,6 +224,23 @@ mlx5_glue_reg_mr(struct ibv_pd *pd, void *addr, size_t length, int access) return ibv_reg_mr(pd, addr, length, access); } +static struct ibv_mr * +mlx5_glue_reg_mr_iova(struct ibv_pd *pd, void *addr, size_t length, + uint64_t iova, int access) +{ +#ifdef HAVE_MLX5_IBV_REG_MR_IOVA + return ibv_reg_mr_iova(pd, addr, length, iova, access); +#else + (void)pd; + (void)addr; + (void)length; + (void)iova; + (void)access; + errno = ENOTSUP; + return NULL; +#endif +} + static struct ibv_mr * mlx5_glue_alloc_null_mr(struct ibv_pd *pd) { @@ -1412,6 +1429,7 @@ const struct mlx5_glue *mlx5_glue = &(const struct mlx5_glue) { .destroy_qp = mlx5_glue_destroy_qp, .modify_qp = mlx5_glue_modify_qp, .reg_mr = mlx5_glue_reg_mr, + .reg_mr_iova = mlx5_glue_reg_mr_iova, .alloc_null_mr = mlx5_glue_alloc_null_mr, .dereg_mr = mlx5_glue_dereg_mr, .create_counter_set = mlx5_glue_create_counter_set, diff --git a/drivers/common/mlx5/linux/mlx5_glue.h b/drivers/common/mlx5/linux/mlx5_glue.h index f39ef2dac7..4e6d31f263 100644 --- a/drivers/common/mlx5/linux/mlx5_glue.h +++ b/drivers/common/mlx5/linux/mlx5_glue.h @@ -197,6 +197,9 @@ struct mlx5_glue { int attr_mask); struct ibv_mr *(*reg_mr)(struct ibv_pd *pd, void *addr, size_t length, int access); + struct ibv_mr *(*reg_mr_iova)(struct ibv_pd *pd, void *addr, + size_t length, uint64_t iova, + int access); struct ibv_mr *(*alloc_null_mr)(struct ibv_pd *pd); int (*dereg_mr)(struct ibv_mr *mr); struct ibv_counter_set *(*create_counter_set) From patchwork Tue Nov 9 12:36:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matan Azrad X-Patchwork-Id: 104063 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 02A2EA034F; Tue, 9 Nov 2021 13:36:44 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 883A841109; Tue, 9 Nov 2021 13:36:39 +0100 (CET) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2079.outbound.protection.outlook.com [40.107.220.79]) by mails.dpdk.org (Postfix) with ESMTP id 5D2D24111F; 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Tue, 9 Nov 2021 12:36:31 +0000 From: Matan Azrad To: Viacheslav Ovsiienko CC: , Thomas Monjalon , , Michael Baum Date: Tue, 9 Nov 2021 14:36:09 +0200 Message-ID: <20211109123612.2301442-3-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211109123612.2301442-1-matan@nvidia.com> References: <20211108172113.2241853-1-matan@nvidia.com> <20211109123612.2301442-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b371fd2c-9824-4587-63f8-08d9a37d91aa X-MS-TrafficTypeDiagnostic: BY5PR12MB4068: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: veSPd7EqTWkr/NpSc7fadSMWK5PxU174VzWhpB3K92BYFBIoYJ8chhjR7QIBYr3YFarcyIiMN5PBvyKcQkJunH2xgsQVqrZbwaA8c9sPdq6UXDAWmDNxiVVkPojj4GtqKI+t7Ir7t59d3T7zjQL+dEOt/U8fE1nPTuMxFmcT6w2CgsrRSIUhw+QvFK8Psw45Rcnp3hpFSZWiZFL1Nx04hXHz0ypi29o6x+TlbIfuznnVZqy2Amf+8q0wBdOy5QbagpqI1Iefx1VgfIIHlkYN57ObqXKh/2SYil63jzWRwnUeGxNjpUJSa2I6v+vbKop+g3zpkM2EYsC+qRXXsQhzEgYpqjqDbievz3lQGhxbQdhWTy45p4L148xU4P2tk8Hum/9R6OQCWYgZaUOQGgxv23O2m7n9t8N8I/qs5NknGLIhUu2EGqLQSA+G1afYz3vhKKNLA5yi3dn4Fo4V/qBt/KAzVqb7lB+P9qF2OjhzSnbzZjaFmZn3IKnXZ6twjpbQomq3rQq766yoM+ddUMk3WrB9diQC8ffzgJRI5bsMjhCDQh9+WDKOoHVR8cDxfqgNYNc5IBN9bHqn3WMt5964R/gPpGayFkVeEWxppBENBtJE/2JOVc9knoylIWTw3ZJh4xjPQWjSRTIIH11a4h+Z8R/VGnXeMmObT0PvCkW4VrQkbnIcneK/eKSF9FcrSO9bu0fql3EuoUzUEDUxz+QPyA== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(2616005)(6286002)(4326008)(47076005)(426003)(6666004)(36756003)(83380400001)(336012)(55016002)(356005)(36860700001)(6862004)(107886003)(1076003)(2906002)(82310400003)(26005)(7636003)(86362001)(5660300002)(36906005)(6636002)(16526019)(7696005)(508600001)(70586007)(70206006)(8676002)(54906003)(37006003)(186003)(316002)(8936002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2021 12:36:35.8629 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b371fd2c-9824-4587-63f8-08d9a37d91aa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4068 Subject: [dpdk-dev] [PATCH v3 2/5] common/mlx5: add wrapped MR create API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The mlx5 PMD uses the kernel mlx5 driver to map physical memory to the HW. Using the Verbs API ibv_reg_mr, a mkey can be created for that. In this case, the mkey is signed on the user ID of the kernel driver. Using the DevX API, a mkey also can be created, but it should point an umem object (represents the specific buffer mapping) created by the kernel. In this case, the mkey is signed on the user ID of the process DevX context. In FW DevX control commands which get mkey as a parameter, there is a security check on the user ID and Verbs mkeys are rejected. Unfortunately, also when using DevX mkey, there is an error in the FW command on umem validation because the umem is not designed to be used for any mkey parameters. As a workaround to the kernel driver/FW issue, it is needed to use a wrapped MR, which is an indirect mkey(created by the DevX API) pointing to direct mkey created by the kernel for any DevX command uses an MR. Add an API to create and destroy this wrapped MR. Fixes: 5382d28c2110 ("net/mlx5: accelerate DV flow counter transactions") Fixes: 9d39e57f21ac ("vdpa/mlx5: support live migration") Cc: stable@dpdk.org Signed-off-by: Michael Baum Signed-off-by: Matan Azrad --- drivers/common/mlx5/linux/mlx5_common_os.c | 56 ++++++++++++++++++++ drivers/common/mlx5/mlx5_common.h | 18 +++++++ drivers/common/mlx5/version.map | 3 ++ drivers/common/mlx5/windows/mlx5_common_os.c | 40 ++++++++++++++ 4 files changed, 117 insertions(+) diff --git a/drivers/common/mlx5/linux/mlx5_common_os.c b/drivers/common/mlx5/linux/mlx5_common_os.c index b516564b79..0d3e24e04e 100644 --- a/drivers/common/mlx5/linux/mlx5_common_os.c +++ b/drivers/common/mlx5/linux/mlx5_common_os.c @@ -744,3 +744,59 @@ mlx5_get_device_guid(const struct rte_pci_addr *dev, uint8_t *guid, size_t len) fclose(id_file); return ret; } + +/* + * Create direct mkey using the kernel ibv_reg_mr API and wrap it with a new + * indirect mkey created by the DevX API. + * This mkey should be used for DevX commands requesting mkey as a parameter. + */ +int +mlx5_os_wrapped_mkey_create(void *ctx, void *pd, uint32_t pdn, void *addr, + size_t length, struct mlx5_pmd_wrapped_mr *pmd_mr) +{ + struct mlx5_klm klm = { + .byte_count = length, + .address = (uintptr_t)addr, + }; + struct mlx5_devx_mkey_attr mkey_attr = { + .pd = pdn, + .klm_array = &klm, + .klm_num = 1, + }; + struct mlx5_devx_obj *mkey; + struct ibv_mr *ibv_mr = mlx5_glue->reg_mr(pd, addr, length, + IBV_ACCESS_LOCAL_WRITE | + (haswell_broadwell_cpu ? 0 : + IBV_ACCESS_RELAXED_ORDERING)); + + if (!ibv_mr) { + rte_errno = errno; + return -rte_errno; + } + klm.mkey = ibv_mr->lkey; + mkey_attr.addr = (uintptr_t)addr; + mkey_attr.size = length; + mkey = mlx5_devx_cmd_mkey_create(ctx, &mkey_attr); + if (!mkey) { + claim_zero(mlx5_glue->dereg_mr(ibv_mr)); + return -rte_errno; + } + pmd_mr->addr = addr; + pmd_mr->len = length; + pmd_mr->obj = (void *)ibv_mr; + pmd_mr->imkey = mkey; + pmd_mr->lkey = mkey->id; + return 0; +} + +void +mlx5_os_wrapped_mkey_destroy(struct mlx5_pmd_wrapped_mr *pmd_mr) +{ + if (!pmd_mr) + return; + if (pmd_mr->imkey) + claim_zero(mlx5_devx_cmd_destroy(pmd_mr->imkey)); + if (pmd_mr->obj) + claim_zero(mlx5_glue->dereg_mr(pmd_mr->obj)); + memset(pmd_mr, 0, sizeof(*pmd_mr)); +} diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h index 661d3ab235..e8809844af 100644 --- a/drivers/common/mlx5/mlx5_common.h +++ b/drivers/common/mlx5/mlx5_common.h @@ -509,4 +509,22 @@ mlx5_devx_uar_release(struct mlx5_uar *uar); int mlx5_os_open_device(struct mlx5_common_device *cdev, uint32_t classes); int mlx5_os_pd_create(struct mlx5_common_device *cdev); +/* mlx5 PMD wrapped MR struct. */ +struct mlx5_pmd_wrapped_mr { + uint32_t lkey; + void *addr; + size_t len; + void *obj; /* verbs mr object or devx umem object. */ + void *imkey; /* DevX indirect mkey object. */ +}; + +__rte_internal +int +mlx5_os_wrapped_mkey_create(void *ctx, void *pd, uint32_t pdn, void *addr, + size_t length, struct mlx5_pmd_wrapped_mr *pmd_mr); + +__rte_internal +void +mlx5_os_wrapped_mkey_destroy(struct mlx5_pmd_wrapped_mr *pmd_mr); + #endif /* RTE_PMD_MLX5_COMMON_H_ */ diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index 2335edf39d..8a62dc2782 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -134,6 +134,9 @@ INTERNAL { mlx5_os_umem_dereg; mlx5_os_umem_reg; + mlx5_os_wrapped_mkey_create; + mlx5_os_wrapped_mkey_destroy; + mlx5_realloc; mlx5_translate_port_name; # WINDOWS_NO_EXPORT diff --git a/drivers/common/mlx5/windows/mlx5_common_os.c b/drivers/common/mlx5/windows/mlx5_common_os.c index ea478d7395..0d03344343 100644 --- a/drivers/common/mlx5/windows/mlx5_common_os.c +++ b/drivers/common/mlx5/windows/mlx5_common_os.c @@ -390,3 +390,43 @@ mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, mlx5_dereg_mr_t *dereg_mr_cb) *reg_mr_cb = mlx5_os_reg_mr; *dereg_mr_cb = mlx5_os_dereg_mr; } + +/* + * In Windows, no need to wrap the MR, no known issue for it in kernel. + * Use the regular function to create direct MR. + */ +int +mlx5_os_wrapped_mkey_create(void *ctx, void *pd, uint32_t pdn, void *addr, + size_t length, struct mlx5_pmd_wrapped_mr *wpmd_mr) +{ + struct mlx5_pmd_mr pmd_mr = {0}; + int ret = mlx5_os_reg_mr(pd, addr, length, &pmd_mr); + + (void)pdn; + (void)ctx; + if (ret != 0) + return -1; + wpmd_mr->addr = addr; + wpmd_mr->len = length; + wpmd_mr->obj = pmd_mr.obj; + wpmd_mr->imkey = pmd_mr.mkey; + wpmd_mr->lkey = pmd_mr.mkey->id; + return 0; +} + +void +mlx5_os_wrapped_mkey_destroy(struct mlx5_pmd_wrapped_mr *wpmd_mr) +{ + struct mlx5_pmd_mr pmd_mr; + + if (!wpmd_mr) + return; + pmd_mr.addr = wpmd_mr->addr; + pmd_mr.len = wpmd_mr->len; + pmd_mr.obj = wpmd_mr->obj; + pmd_mr.mkey = wpmd_mr->imkey; + pmd_mr.lkey = wpmd_mr->lkey; + mlx5_os_dereg_mr(&pmd_mr); + memset(wpmd_mr, 0, sizeof(*wpmd_mr)); +} + From patchwork Tue Nov 9 12:36:10 2021 Content-Type: text/plain; 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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT065.mail.protection.outlook.com (10.13.174.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4669.10 via Frontend Transport; Tue, 9 Nov 2021 12:36:36 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 9 Nov 2021 12:36:33 +0000 From: Matan Azrad To: Viacheslav Ovsiienko CC: , Thomas Monjalon , , Michael Baum Date: Tue, 9 Nov 2021 14:36:10 +0200 Message-ID: <20211109123612.2301442-4-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211109123612.2301442-1-matan@nvidia.com> References: <20211108172113.2241853-1-matan@nvidia.com> <20211109123612.2301442-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d610061d-d8f4-4b10-5fac-08d9a37d9226 X-MS-TrafficTypeDiagnostic: MWHPR12MB1423: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:38; 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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(336012)(2906002)(36756003)(6286002)(83380400001)(4326008)(86362001)(2616005)(54906003)(37006003)(16526019)(26005)(6862004)(5660300002)(186003)(107886003)(426003)(6666004)(7696005)(7636003)(55016002)(316002)(82310400003)(36906005)(1076003)(8936002)(508600001)(8676002)(70586007)(36860700001)(70206006)(6636002)(47076005)(356005)(14143004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2021 12:36:36.6654 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d610061d-d8f4-4b10-5fac-08d9a37d9226 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1423 Subject: [dpdk-dev] [PATCH v3 3/5] vdpa/mlx5: workaround dirty bitmap MR creation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Due to kernel driver/FW issues in direct MKEY creation using the DevX API, this patch replaces the dirty bitmap MR creation to use wrapped mkey instead. Fixes: 9d39e57f21ac ("vdpa/mlx5: support live migration") Cc: stable@dpdk.org Signed-off-by: Michael Baum Signed-off-by: Matan Azrad --- drivers/vdpa/mlx5/mlx5_vdpa.h | 1 + drivers/vdpa/mlx5/mlx5_vdpa_lm.c | 38 +++++++------------------------ drivers/vdpa/mlx5/mlx5_vdpa_mem.c | 2 ++ 3 files changed, 11 insertions(+), 30 deletions(-) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h index 62498f87fd..15212a2b30 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.h +++ b/drivers/vdpa/mlx5/mlx5_vdpa.h @@ -147,6 +147,7 @@ struct mlx5_vdpa_priv { struct mlx5_vdpa_steer steer; struct mlx5dv_var *var; void *virtq_db_addr; + struct mlx5_pmd_wrapped_mr lm_mr; SLIST_HEAD(mr_list, mlx5_vdpa_query_mr) mr_list; struct mlx5_vdpa_virtq virtqs[]; }; diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_lm.c b/drivers/vdpa/mlx5/mlx5_vdpa_lm.c index 3e8d9eb9a2..e65e4faa47 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_lm.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_lm.c @@ -36,38 +36,22 @@ int mlx5_vdpa_dirty_bitmap_set(struct mlx5_vdpa_priv *priv, uint64_t log_base, uint64_t log_size) { - struct mlx5_devx_mkey_attr mkey_attr = { - .addr = (uintptr_t)log_base, - .size = log_size, - .pd = priv->cdev->pdn, - .pg_access = 1, - }; struct mlx5_devx_virtq_attr attr = { .type = MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS, .dirty_bitmap_addr = log_base, .dirty_bitmap_size = log_size, }; - struct mlx5_vdpa_query_mr *mr = rte_malloc(__func__, sizeof(*mr), 0); int i; + int ret = mlx5_os_wrapped_mkey_create(priv->cdev->ctx, priv->cdev->pd, + priv->cdev->pdn, + (void *)(uintptr_t)log_base, + log_size, &priv->lm_mr); - if (!mr) { - DRV_LOG(ERR, "Failed to allocate mem for lm mr."); + if (!ret) { + DRV_LOG(ERR, "Failed to allocate wrapped MR for lm."); return -1; } - mr->umem = mlx5_glue->devx_umem_reg(priv->cdev->ctx, - (void *)(uintptr_t)log_base, - log_size, IBV_ACCESS_LOCAL_WRITE); - if (!mr->umem) { - DRV_LOG(ERR, "Failed to register umem for lm mr."); - goto err; - } - mkey_attr.umem_id = mr->umem->umem_id; - mr->mkey = mlx5_devx_cmd_mkey_create(priv->cdev->ctx, &mkey_attr); - if (!mr->mkey) { - DRV_LOG(ERR, "Failed to create Mkey for lm."); - goto err; - } - attr.dirty_bitmap_mkey = mr->mkey->id; + attr.dirty_bitmap_mkey = priv->lm_mr.lkey; for (i = 0; i < priv->nr_virtqs; ++i) { attr.queue_index = i; if (!priv->virtqs[i].virtq) { @@ -78,15 +62,9 @@ mlx5_vdpa_dirty_bitmap_set(struct mlx5_vdpa_priv *priv, uint64_t log_base, goto err; } } - mr->is_indirect = 0; - SLIST_INSERT_HEAD(&priv->mr_list, mr, next); return 0; err: - if (mr->mkey) - mlx5_devx_cmd_destroy(mr->mkey); - if (mr->umem) - mlx5_glue->devx_umem_dereg(mr->umem); - rte_free(mr); + mlx5_os_wrapped_mkey_destroy(&priv->lm_mr); return -1; } diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_mem.c b/drivers/vdpa/mlx5/mlx5_vdpa_mem.c index f551a094cd..d7707bbd91 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_mem.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_mem.c @@ -31,6 +31,8 @@ mlx5_vdpa_mem_dereg(struct mlx5_vdpa_priv *priv) entry = next; } SLIST_INIT(&priv->mr_list); + if (priv->lm_mr.addr) + mlx5_os_wrapped_mkey_destroy(&priv->lm_mr); if (priv->null_mr) { claim_zero(mlx5_glue->dereg_mr(priv->null_mr)); priv->null_mr = NULL; From patchwork Tue Nov 9 12:36:11 2021 Content-Type: text/plain; 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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT065.mail.protection.outlook.com (10.13.174.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4669.10 via Frontend Transport; Tue, 9 Nov 2021 12:36:37 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 9 Nov 2021 12:36:34 +0000 From: Matan Azrad To: Viacheslav Ovsiienko CC: , Thomas Monjalon , Michael Baum , , Michael Baum Date: Tue, 9 Nov 2021 14:36:11 +0200 Message-ID: <20211109123612.2301442-5-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211109123612.2301442-1-matan@nvidia.com> References: <20211108172113.2241853-1-matan@nvidia.com> <20211109123612.2301442-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b7b754c3-002a-4253-4b55-08d9a37d928f X-MS-TrafficTypeDiagnostic: MWHPR12MB1423: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:130; 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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(336012)(2906002)(36756003)(6286002)(83380400001)(4326008)(86362001)(2616005)(54906003)(37006003)(16526019)(26005)(6862004)(5660300002)(186003)(107886003)(426003)(6666004)(7696005)(7636003)(55016002)(316002)(82310400003)(36906005)(1076003)(8936002)(508600001)(8676002)(70586007)(36860700001)(70206006)(6636002)(47076005)(356005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2021 12:36:37.3690 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b7b754c3-002a-4253-4b55-08d9a37d928f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1423 Subject: [dpdk-dev] [PATCH v3 4/5] vdpa/mlx5: workaround guest MR registrations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Michael Baum Due to kernel issue in direct MKEY creation using the DevX API, this patch replaces the virtio MR creation to use Verbs API. Fixes: cc07a42da250 ("vdpa/mlx5: prepare memory regions") Cc: stable@dpdk.org Signed-off-by: Michael Baum Signed-off-by: Matan Azrad --- drivers/vdpa/mlx5/mlx5_vdpa.h | 8 +++--- drivers/vdpa/mlx5/mlx5_vdpa_mem.c | 41 +++++++++---------------------- 2 files changed, 16 insertions(+), 33 deletions(-) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h index 15212a2b30..22617924ea 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.h +++ b/drivers/vdpa/mlx5/mlx5_vdpa.h @@ -59,10 +59,10 @@ struct mlx5_vdpa_event_qp { struct mlx5_vdpa_query_mr { SLIST_ENTRY(mlx5_vdpa_query_mr) next; - void *addr; - uint64_t length; - struct mlx5dv_devx_umem *umem; - struct mlx5_devx_obj *mkey; + union { + struct ibv_mr *mr; + struct mlx5_devx_obj *mkey; + }; int is_indirect; }; diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_mem.c b/drivers/vdpa/mlx5/mlx5_vdpa_mem.c index d7707bbd91..b1b9053bff 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_mem.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_mem.c @@ -23,9 +23,10 @@ mlx5_vdpa_mem_dereg(struct mlx5_vdpa_priv *priv) entry = SLIST_FIRST(&priv->mr_list); while (entry) { next = SLIST_NEXT(entry, next); - claim_zero(mlx5_devx_cmd_destroy(entry->mkey)); - if (!entry->is_indirect) - claim_zero(mlx5_glue->devx_umem_dereg(entry->umem)); + if (entry->is_indirect) + claim_zero(mlx5_devx_cmd_destroy(entry->mkey)); + else + claim_zero(mlx5_glue->dereg_mr(entry->mr)); SLIST_REMOVE(&priv->mr_list, entry, mlx5_vdpa_query_mr, next); rte_free(entry); entry = next; @@ -202,7 +203,6 @@ mlx5_vdpa_mem_register(struct mlx5_vdpa_priv *priv) goto error; } DRV_LOG(DEBUG, "Dump fill Mkey = %u.", priv->null_mr->lkey); - memset(&mkey_attr, 0, sizeof(mkey_attr)); for (i = 0; i < mem->nregions; i++) { reg = &mem->regions[i]; entry = rte_zmalloc(__func__, sizeof(*entry), 0); @@ -211,28 +211,15 @@ mlx5_vdpa_mem_register(struct mlx5_vdpa_priv *priv) DRV_LOG(ERR, "Failed to allocate mem entry memory."); goto error; } - entry->umem = mlx5_glue->devx_umem_reg(priv->cdev->ctx, - (void *)(uintptr_t)reg->host_user_addr, - reg->size, IBV_ACCESS_LOCAL_WRITE); - if (!entry->umem) { - DRV_LOG(ERR, "Failed to register Umem by Devx."); - ret = -errno; - goto error; - } - mkey_attr.addr = (uintptr_t)(reg->guest_phys_addr); - mkey_attr.size = reg->size; - mkey_attr.umem_id = entry->umem->umem_id; - mkey_attr.pd = priv->cdev->pdn; - mkey_attr.pg_access = 1; - entry->mkey = mlx5_devx_cmd_mkey_create(priv->cdev->ctx, - &mkey_attr); - if (!entry->mkey) { + entry->mr = mlx5_glue->reg_mr_iova(priv->cdev->pd, + (void *)(uintptr_t)(reg->host_user_addr), + reg->size, reg->guest_phys_addr, + IBV_ACCESS_LOCAL_WRITE); + if (!entry->mr) { DRV_LOG(ERR, "Failed to create direct Mkey."); ret = -rte_errno; goto error; } - entry->addr = (void *)(uintptr_t)(reg->host_user_addr); - entry->length = reg->size; entry->is_indirect = 0; if (i > 0) { uint64_t sadd; @@ -262,12 +249,13 @@ mlx5_vdpa_mem_register(struct mlx5_vdpa_priv *priv) for (k = 0; k < reg->size; k += klm_size) { klm_array[klm_index].byte_count = k + klm_size > reg->size ? reg->size - k : klm_size; - klm_array[klm_index].mkey = entry->mkey->id; + klm_array[klm_index].mkey = entry->mr->lkey; klm_array[klm_index].address = reg->guest_phys_addr + k; klm_index++; } SLIST_INSERT_HEAD(&priv->mr_list, entry, next); } + memset(&mkey_attr, 0, sizeof(mkey_attr)); mkey_attr.addr = (uintptr_t)(mem->regions[0].guest_phys_addr); mkey_attr.size = mem_size; mkey_attr.pd = priv->cdev->pdn; @@ -295,13 +283,8 @@ mlx5_vdpa_mem_register(struct mlx5_vdpa_priv *priv) priv->gpa_mkey_index = entry->mkey->id; return 0; error: - if (entry) { - if (entry->mkey) - mlx5_devx_cmd_destroy(entry->mkey); - if (entry->umem) - mlx5_glue->devx_umem_dereg(entry->umem); + if (entry) rte_free(entry); - } mlx5_vdpa_mem_dereg(priv); rte_errno = -ret; return ret; From patchwork Tue Nov 9 12:36:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matan Azrad X-Patchwork-Id: 104066 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AF789A034F; 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Tue, 9 Nov 2021 12:36:36 +0000 From: Matan Azrad To: Viacheslav Ovsiienko CC: , Thomas Monjalon , Michael Baum , Date: Tue, 9 Nov 2021 14:36:12 +0200 Message-ID: <20211109123612.2301442-6-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211109123612.2301442-1-matan@nvidia.com> References: <20211108172113.2241853-1-matan@nvidia.com> <20211109123612.2301442-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 13126b01-5492-4acd-7876-08d9a37d936f X-MS-TrafficTypeDiagnostic: MW2PR12MB2395: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:246; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: pL0uaFvZROcxqY7bEsixWiBLMBWPzUMvuNN4mV5kJS2R+JmfgZJUL5xgj4mwGBtuVLdXgZxoZrTjMQ/rFzUjxjFwQ2+glOEkBWd8tktqKzfyVuhFJuJAm05C4lOPS8Kolc39BE9HvqcwuERgctva+3ifyo26m6nbRXs4d1vYkzNCtWSAQY8b8a3JV+S3CY2zXmivftQN99X/uDvbrxGKaAr5yf6WP04Ni6w12Y/qpl6vShrIXKj7VjLbdJ8r6AmqCjRCAwB7emT7AH5MtilnIPuavvTdD1u15qCxTw4iGLuKlF5cx+C4PtKPLQz8r3wUjLf5WzSga1YCFKe8oUaYpCriLno0/LBVD1CgnwDH6j5WOH85pHs8q2UZgKbWmQAxfgWrKqglQTIzZKdeuyAloYwfu+NROOuN8yqeCRfy5L2M339M3pVfZytF8K0MVDeQfnj0CVhCnd23EWkBHJ6QW2a4xfA1U++5NjIoBwJTc3VdNgfI9QGN5ECNwnczuIUQVW4kW3tKhPza1+WEFCQa/q9cYiNBASHg4Wz9sV5aJriwatw0zfWW0h6smVycUTNUWpk6m62jxyZmbWl26TOPtq5LofqVF5FfZxJeidZKEdOmBAvlvHeJAW9vTpOYISHwBzydNrqp38pKL6AgTxujBv84W5CPZiFJuTxyKOgeQMyifXDafuVjdKpEY916M9nXlsIZTYir+FpiXo4OOA8T3w== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(316002)(36860700001)(36906005)(83380400001)(6666004)(37006003)(54906003)(82310400003)(7636003)(2616005)(70586007)(2906002)(8676002)(8936002)(70206006)(6636002)(508600001)(426003)(26005)(55016002)(36756003)(336012)(86362001)(5660300002)(7696005)(16526019)(186003)(4326008)(6862004)(6286002)(356005)(47076005)(1076003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2021 12:36:38.8421 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 13126b01-5492-4acd-7876-08d9a37d936f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR12MB2395 Subject: [dpdk-dev] [PATCH v3 5/5] net/mlx5: workaround MR creation for flow counter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Michael Baum Due to kernel driver / FW issues in direct MKEY creation using the DevX API, this patch replaces the counter MR creation to use wrapped mkey API. Fixes: 5382d28c2110 ("net/mlx5: accelerate DV flow counter transactions") Cc: stable@dpdk.org Signed-off-by: Michael Baum Signed-off-by: Matan Azrad --- drivers/net/mlx5/mlx5.c | 8 +------- drivers/net/mlx5/mlx5.h | 5 +---- drivers/net/mlx5/mlx5_flow.c | 25 ++++++------------------- 3 files changed, 8 insertions(+), 30 deletions(-) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index f5990dd757..2a3efb3588 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -522,7 +522,6 @@ mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh) static void mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh) { - struct mlx5_hca_attr *attr = &sh->cdev->config.hca_attr; int i; memset(&sh->cmng, 0, sizeof(sh->cmng)); @@ -535,10 +534,6 @@ mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh) TAILQ_INIT(&sh->cmng.counters[i]); rte_spinlock_init(&sh->cmng.csl[i]); } - if (sh->devx && !haswell_broadwell_cpu) { - sh->cmng.relaxed_ordering_write = attr->relaxed_ordering_write; - sh->cmng.relaxed_ordering_read = attr->relaxed_ordering_read; - } } /** @@ -553,8 +548,7 @@ mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng) uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data; LIST_REMOVE(mng, next); - claim_zero(mlx5_devx_cmd_destroy(mng->dm)); - claim_zero(mlx5_os_umem_dereg(mng->umem)); + mlx5_os_wrapped_mkey_destroy(&mng->wm); mlx5_free(mem); } diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index c2a13b6de4..bdadd6e024 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -462,8 +462,7 @@ struct mlx5_flow_counter_pool { struct mlx5_counter_stats_mem_mng { LIST_ENTRY(mlx5_counter_stats_mem_mng) next; struct mlx5_counter_stats_raw *raws; - struct mlx5_devx_obj *dm; - void *umem; + struct mlx5_pmd_wrapped_mr wm; }; /* Raw memory structure for the counter statistics values of a pool. */ @@ -494,8 +493,6 @@ struct mlx5_flow_counter_mng { uint8_t pending_queries; uint16_t pool_index; uint8_t query_thread_on; - bool relaxed_ordering_read; - bool relaxed_ordering_write; bool counter_fallback; /* Use counter fallback management. */ LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 2f30a35525..40625688b0 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -7775,7 +7775,6 @@ mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, static int mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) { - struct mlx5_devx_mkey_attr mkey_attr; struct mlx5_counter_stats_mem_mng *mem_mng; volatile struct flow_counter_stats *raw_data; int raws_n = MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES; @@ -7785,6 +7784,7 @@ mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) sizeof(struct mlx5_counter_stats_mem_mng); size_t pgsize = rte_mem_page_size(); uint8_t *mem; + int ret; int i; if (pgsize == (size_t)-1) { @@ -7799,23 +7799,10 @@ mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) } mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1; size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n; - mem_mng->umem = mlx5_os_umem_reg(sh->cdev->ctx, mem, size, - IBV_ACCESS_LOCAL_WRITE); - if (!mem_mng->umem) { - rte_errno = errno; - mlx5_free(mem); - return -rte_errno; - } - memset(&mkey_attr, 0, sizeof(mkey_attr)); - mkey_attr.addr = (uintptr_t)mem; - mkey_attr.size = size; - mkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem); - mkey_attr.pd = sh->cdev->pdn; - mkey_attr.relaxed_ordering_write = sh->cmng.relaxed_ordering_write; - mkey_attr.relaxed_ordering_read = sh->cmng.relaxed_ordering_read; - mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->cdev->ctx, &mkey_attr); - if (!mem_mng->dm) { - mlx5_os_umem_dereg(mem_mng->umem); + ret = mlx5_os_wrapped_mkey_create(sh->cdev->ctx, sh->cdev->pd, + sh->cdev->pdn, mem, size, + &mem_mng->wm); + if (ret) { rte_errno = errno; mlx5_free(mem); return -rte_errno; @@ -7934,7 +7921,7 @@ mlx5_flow_query_alarm(void *arg) ret = mlx5_devx_cmd_flow_counter_query(pool->min_dcs, 0, MLX5_COUNTERS_PER_POOL, NULL, NULL, - pool->raw_hw->mem_mng->dm->id, + pool->raw_hw->mem_mng->wm.lkey, (void *)(uintptr_t) pool->raw_hw->data, sh->devx_comp,