From patchwork Wed Jan 19 09:43:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Bhansali X-Patchwork-Id: 106067 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7981AA04A4; Wed, 19 Jan 2022 10:43:45 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DB1F5410E1; Wed, 19 Jan 2022 10:43:44 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B54C14013F for ; Wed, 19 Jan 2022 10:43:43 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20J1t0Wr020606; Wed, 19 Jan 2022 01:43:40 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=1ttvCv+ChTPme2NF5sXq/otjqF2FTTaqL8tA/SHk//I=; b=P3VfkgkMfg5A9yTzIZ9JUT4AqWDbmlr2i3+sthWjn0Gw7WcmfruUsfkkZYjNlq7olzWf RR193OoZRFD6oWWnXPgfw1eJu5sHfxmg+g4Pky/fCYpE82wfhK6AZIBvn6LmVk9ljsT2 Kq0LH2MzAegaKFFag6O+VbkaoTVb70M44l4vuyJDnkhBYkE+1HhTktr3nxNpO4j5K03u v8p6LtNVOsmAgy/eL2tyQAQSGZwh+k9QwMLXgFow5+We5LCwe9C53zSufd4e4VVsXqb2 b8UyTCVhhz42FlEjpdtO6lich7LkUzkzmhBB87DMc3b4EyNHkqBYJslza6H/vd77Gnbw 1Q== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3dp9d61bn5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 19 Jan 2022 01:43:40 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 19 Jan 2022 01:43:38 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 19 Jan 2022 01:43:38 -0800 Received: from localhost.localdomain (unknown [10.28.48.107]) by maili.marvell.com (Postfix) with ESMTP id F13403F704C; Wed, 19 Jan 2022 01:43:35 -0800 (PST) From: Rahul Bhansali To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Rahul Bhansali Subject: [PATCH v2 1/2] common/cnxk: get head-tail of Rx and Tx queues Date: Wed, 19 Jan 2022 15:13:26 +0530 Message-ID: <20220119094327.1488398-1-rbhansali@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Proofpoint-GUID: 6FPWH0BsqEwWFwbFCZOIHGsbRC3Ajeym X-Proofpoint-ORIG-GUID: 6FPWH0BsqEwWFwbFCZOIHGsbRC3Ajeym X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-19_06,2022-01-18_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adds roc APIs roc_nix_cq_head_tail_get, roc_nix_sq_head_tail_get to get head-tail of receive and transmit queue respectively. Signed-off-by: Rahul Bhansali Acked-by: Ray Kinsella --- v2 changes: - No change drivers/common/cnxk/roc_nix.h | 4 +++ drivers/common/cnxk/roc_nix_queue.c | 53 +++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 2 ++ 3 files changed, 59 insertions(+) -- 2.25.1 diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 69a5e8e7b4..d79abfef9f 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -795,8 +795,12 @@ int __roc_api roc_nix_rq_ena_dis(struct roc_nix_rq *rq, bool enable); int __roc_api roc_nix_rq_fini(struct roc_nix_rq *rq); int __roc_api roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq); int __roc_api roc_nix_cq_fini(struct roc_nix_cq *cq); +void __roc_api roc_nix_cq_head_tail_get(struct roc_nix *roc_nix, uint16_t qid, + uint32_t *head, uint32_t *tail); int __roc_api roc_nix_sq_init(struct roc_nix *roc_nix, struct roc_nix_sq *sq); int __roc_api roc_nix_sq_fini(struct roc_nix_sq *sq); +void __roc_api roc_nix_sq_head_tail_get(struct roc_nix *roc_nix, uint16_t qid, + uint32_t *head, uint32_t *tail); /* PTP */ int __roc_api roc_nix_ptp_rx_ena_dis(struct roc_nix *roc_nix, int enable); diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index c638cd43e4..67f83acdf2 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -969,3 +969,56 @@ roc_nix_sq_fini(struct roc_nix_sq *sq) return rc; } + +void +roc_nix_cq_head_tail_get(struct roc_nix *roc_nix, uint16_t qid, uint32_t *head, + uint32_t *tail) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + uint64_t reg, val; + int64_t *addr; + + if (head == NULL || tail == NULL) + return; + + reg = (((uint64_t)qid) << 32); + addr = (int64_t *)(nix->base + NIX_LF_CQ_OP_STATUS); + val = roc_atomic64_add_nosync(reg, addr); + if (val & + (BIT_ULL(NIX_CQ_OP_STAT_OP_ERR) | BIT_ULL(NIX_CQ_OP_STAT_CQ_ERR))) + val = 0; + + *tail = (uint32_t)(val & 0xFFFFF); + *head = (uint32_t)((val >> 20) & 0xFFFFF); +} + +void +roc_nix_sq_head_tail_get(struct roc_nix *roc_nix, uint16_t qid, uint32_t *head, + uint32_t *tail) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct roc_nix_sq *sq = nix->sqs[qid]; + uint16_t sqes_per_sqb, sqb_cnt; + uint64_t reg, val; + int64_t *addr; + + if (head == NULL || tail == NULL) + return; + + reg = (((uint64_t)qid) << 32); + addr = (int64_t *)(nix->base + NIX_LF_SQ_OP_STATUS); + val = roc_atomic64_add_nosync(reg, addr); + if (val & BIT_ULL(NIX_CQ_OP_STAT_OP_ERR)) { + val = 0; + return; + } + + *tail = (uint32_t)((val >> 28) & 0x3F); + *head = (uint32_t)((val >> 20) & 0x3F); + sqb_cnt = (uint16_t)(val & 0xFFFF); + + sqes_per_sqb = 1 << sq->sqes_per_sqb_log2; + + /* Update tail index as per used sqb count */ + *tail += (sqes_per_sqb * (sqb_cnt - 1)); +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 07c6720f0c..a9dba47e0e 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -107,6 +107,7 @@ INTERNAL { roc_nix_bpf_timeunit_get; roc_nix_cq_dump; roc_nix_cq_fini; + roc_nix_cq_head_tail_get; roc_nix_cq_init; roc_nix_cqe_dump; roc_nix_dev_fini; @@ -222,6 +223,7 @@ INTERNAL { roc_nix_rx_queue_intr_enable; roc_nix_sq_dump; roc_nix_sq_fini; + roc_nix_sq_head_tail_get; roc_nix_sq_init; roc_nix_stats_get; roc_nix_stats_queue_get; From patchwork Wed Jan 19 09:43:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Bhansali X-Patchwork-Id: 106068 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 18FC0A04A4; Wed, 19 Jan 2022 10:43:52 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 103FC410F6; Wed, 19 Jan 2022 10:43:49 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 0114541142 for ; Wed, 19 Jan 2022 10:43:46 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20J1tFha021222 for ; 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Wed, 19 Jan 2022 01:43:44 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 19 Jan 2022 01:43:44 -0800 Received: from localhost.localdomain (unknown [10.28.48.107]) by maili.marvell.com (Postfix) with ESMTP id DF0613F704C; Wed, 19 Jan 2022 01:43:41 -0800 (PST) From: Rahul Bhansali To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rahul Bhansali Subject: [PATCH v2 2/2] net/cnxk: ethdev Rx/Tx queue status callbacks Date: Wed, 19 Jan 2022 15:13:27 +0530 Message-ID: <20220119094327.1488398-2-rbhansali@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220119094327.1488398-1-rbhansali@marvell.com> References: <20220119094327.1488398-1-rbhansali@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: QGFAw03ninMQwutl2Ts45YOAiowqBrDB X-Proofpoint-ORIG-GUID: QGFAw03ninMQwutl2Ts45YOAiowqBrDB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-19_06,2022-01-18_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Provides ethdev callback support of rx_queue_count, rx_descriptor_status and tx_descriptor_status. Signed-off-by: Rahul Bhansali --- v2 changes: - Updated doc/guides/nics/features/cnxk* for "Rx descriptor status" and "Tx descriptor status" doc/guides/nics/features/cnxk.ini | 2 + doc/guides/nics/features/cnxk_vec.ini | 2 + doc/guides/nics/features/cnxk_vf.ini | 2 + drivers/net/cnxk/cnxk_ethdev.c | 3 ++ drivers/net/cnxk/cnxk_ethdev.h | 5 +++ drivers/net/cnxk/cnxk_ethdev_ops.c | 60 +++++++++++++++++++++++++++ 6 files changed, 74 insertions(+) -- 2.25.1 diff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini index 1623a1803e..0eba334eb4 100644 --- a/doc/guides/nics/features/cnxk.ini +++ b/doc/guides/nics/features/cnxk.ini @@ -37,6 +37,8 @@ Inner L4 checksum = Y Packet type parsing = Y Timesync = Y Timestamp offload = Y +Rx descriptor status = Y +Tx descriptor status = Y Basic stats = Y Stats per queue = Y Extended stats = Y diff --git a/doc/guides/nics/features/cnxk_vec.ini b/doc/guides/nics/features/cnxk_vec.ini index 4b7c2bce4d..df5f358a3e 100644 --- a/doc/guides/nics/features/cnxk_vec.ini +++ b/doc/guides/nics/features/cnxk_vec.ini @@ -33,6 +33,8 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Rx descriptor status = Y +Tx descriptor status = Y Basic stats = Y Stats per queue = Y Extended stats = Y diff --git a/doc/guides/nics/features/cnxk_vf.ini b/doc/guides/nics/features/cnxk_vf.ini index 0523be434d..a78fbcada0 100644 --- a/doc/guides/nics/features/cnxk_vf.ini +++ b/doc/guides/nics/features/cnxk_vf.ini @@ -29,6 +29,8 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Rx descriptor status = Y +Tx descriptor status = Y Basic stats = Y Stats per queue = Y Extended stats = Y diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 74f625553d..183fd241d8 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1595,6 +1595,9 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev) int rc, max_entries; eth_dev->dev_ops = &cnxk_eth_dev_ops; + eth_dev->rx_queue_count = cnxk_nix_rx_queue_count; + eth_dev->rx_descriptor_status = cnxk_nix_rx_descriptor_status; + eth_dev->tx_descriptor_status = cnxk_nix_tx_descriptor_status; /* Alloc security context */ sec_ctx = plt_zmalloc(sizeof(struct rte_security_ctx), 0); diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 5bfda3d815..43814a81fc 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -559,6 +559,11 @@ void cnxk_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid, void cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid, struct rte_eth_txq_info *qinfo); +/* Queue status */ +int cnxk_nix_rx_descriptor_status(void *rxq, uint16_t offset); +int cnxk_nix_tx_descriptor_status(void *txq, uint16_t offset); +uint32_t cnxk_nix_rx_queue_count(void *rxq); + /* Lookup configuration */ const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev); void *cnxk_nix_fastpath_lookup_mem_get(void); diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c index 34e4809650..f20f201db2 100644 --- a/drivers/net/cnxk/cnxk_ethdev_ops.c +++ b/drivers/net/cnxk/cnxk_ethdev_ops.c @@ -695,6 +695,66 @@ cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid, memcpy(&qinfo->conf, &txq_sp->qconf.conf.tx, sizeof(qinfo->conf)); } +uint32_t +cnxk_nix_rx_queue_count(void *rxq) +{ + struct cnxk_eth_rxq_sp *rxq_sp = cnxk_eth_rxq_to_sp(rxq); + struct roc_nix *nix = &rxq_sp->dev->nix; + uint32_t head, tail; + + roc_nix_cq_head_tail_get(nix, rxq_sp->qid, &head, &tail); + return (tail - head) % (rxq_sp->qconf.nb_desc); +} + +static inline int +nix_offset_has_packet(uint32_t head, uint32_t tail, uint16_t offset, bool is_rx) +{ + /* Check given offset(queue index) has packet filled/xmit by HW + * in case of Rx or Tx. + * Also, checks for wrap around case. + */ + return ((tail > head && offset <= tail && offset >= head) || + (head > tail && (offset >= head || offset <= tail))) ? + is_rx : + !is_rx; +} + +int +cnxk_nix_rx_descriptor_status(void *rxq, uint16_t offset) +{ + struct cnxk_eth_rxq_sp *rxq_sp = cnxk_eth_rxq_to_sp(rxq); + struct roc_nix *nix = &rxq_sp->dev->nix; + uint32_t head, tail; + + if (rxq_sp->qconf.nb_desc <= offset) + return -EINVAL; + + roc_nix_cq_head_tail_get(nix, rxq_sp->qid, &head, &tail); + + if (nix_offset_has_packet(head, tail, offset, 1)) + return RTE_ETH_RX_DESC_DONE; + else + return RTE_ETH_RX_DESC_AVAIL; +} + +int +cnxk_nix_tx_descriptor_status(void *txq, uint16_t offset) +{ + struct cnxk_eth_txq_sp *txq_sp = cnxk_eth_txq_to_sp(txq); + struct roc_nix *nix = &txq_sp->dev->nix; + uint32_t head = 0, tail = 0; + + if (txq_sp->qconf.nb_desc <= offset) + return -EINVAL; + + roc_nix_sq_head_tail_get(nix, txq_sp->qid, &head, &tail); + + if (nix_offset_has_packet(head, tail, offset, 0)) + return RTE_ETH_TX_DESC_DONE; + else + return RTE_ETH_TX_DESC_FULL; +} + /* It is a NOP for cnxk as HW frees the buffer on xmit */ int cnxk_nix_tx_done_cleanup(void *txq, uint32_t free_cnt)