From patchwork Fri Jan 28 02:11:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 106653 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E6F7FA00C4; Fri, 28 Jan 2022 03:29:11 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A6ED842761; Fri, 28 Jan 2022 03:29:11 +0100 (CET) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 1D9F440141; Fri, 28 Jan 2022 03:29:09 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643336950; x=1674872950; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=P8zh0ex+GZntcQ2X3iJbiecS4ggScwCYExPrOwQ+jmY=; b=aGu1zfPWoHoOMjpsH7ew5i2FDC5J7wj7WvVbbvnJ5xAjTFl2uie+QFAV 1UHepEPaywYBO0f7J6y7/2KiF/DuV9WHIOvjpuHJaPAeZ8fQEiPBE3pAK jpNiwemq7kB9EcmRcW+VN+oonDohJtuBnBLHdxVzFnX+zlwadTugfFB6X SW0Gr9YaHgH6ZA5ZhKLy1LpAkL/8OYNuOzJGL9wUNQyjHZaQVY7HEpU2Q djZRtNntkEPR9QqqjqBgFH5MHqJif1jWfedaH4DFLVqNpVewiYvSM9vGn r7ml/29GMECpxJEviM3TuATL7KArvkwhVk03f29UUYFrPMUFPqfE0x4gI A==; X-IronPort-AV: E=McAfee;i="6200,9189,10240"; a="230600735" X-IronPort-AV: E=Sophos;i="5.88,322,1635231600"; d="scan'208";a="230600735" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jan 2022 18:29:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,322,1635231600"; d="scan'208";a="564031479" Received: from unknown (HELO npg-dpdk-simeisu-cvl-119d218.sh.intel.com) ([10.67.119.218]) by orsmga001.jf.intel.com with ESMTP; 27 Jan 2022 18:29:07 -0800 From: Simei Su To: qi.z.zhang@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, Simei Su , stable@dpdk.org Subject: [PATCH v2] net/ice: fix missing clock initialization Date: Fri, 28 Jan 2022 10:11:29 +0800 Message-Id: <20220128021129.430189-1-simei.su@intel.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20220124051823.32879-1-simei.su@intel.com> References: <20220124051823.32879-1-simei.su@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Rx PHY timer init value is not same as primary timer init value when power up which will lead Rx timestamp always have big gap compared with PTP timestamp. This patch adds PHC init time in initializing PTP hardware clock. Fixes: 646dcbe6c701 ("net/ice: support IEEE 1588 PTP") Cc: stable@dpdk.org Signed-off-by: Simei Su --- v2: * Rename commit title. drivers/net/ice/ice_ethdev.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index d01acb8..dbf822e 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -5661,6 +5661,8 @@ ice_timesync_enable(struct rte_eth_dev *dev) struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); struct ice_adapter *ad = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + uint64_t start_time; + struct timespec system_time; int ret; if (dev->data->dev_started && !(dev->data->dev_conf.rxmode.offloads & @@ -5682,6 +5684,15 @@ ice_timesync_enable(struct rte_eth_dev *dev) "Failed to write PHC increment time value"); return -1; } + + clock_gettime(CLOCK_MONOTONIC, &system_time); + start_time = system_time.tv_sec * NSEC_PER_SEC + + system_time.tv_nsec; + ret = ice_ptp_init_time(hw, start_time); + if (ret) { + PMD_DRV_LOG(ERR, "Failed to write PHC initial time"); + return -1; + } } /* Initialize cycle counters for system time/RX/TX timestamp */