From patchwork Thu Mar 24 02:26:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 108828 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 959CBA0507; Thu, 24 Mar 2022 03:49:04 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3E18D41151; Thu, 24 Mar 2022 03:49:04 +0100 (CET) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 76B83410FC for ; Thu, 24 Mar 2022 03:49:02 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648090142; x=1679626142; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=iaESPSACR9KhTGQYhab/ExWfgJogFM7zn+POopL/ZGE=; b=W/AILvjqbPUxm1mhr5jOeUJ66roEvfOUIu87PEkArF23x/4klo/cJUgb t7lYJslz4YYE3ZIpFd5PI47MVvjPxQIQcVD+CpZksxJU/m/CplbB7utO8 d5Gd2MY539ItCz9m2Man+IPypfiL9ETv7nSBJMIY/6Gx5/d3CFPCttc7s HGDe9FXmaWK5GouBEYmnW6mHGwyG7HpI4gb8RzfOrhBl/eSwOIx0CrFrG e8DKfRtjrt1CZNVZ91PPq1J3nOA6brxki/wXJN1dhLJXUgeEmvQwnAu8C o8mHTAuLkFT0ayQqhgMOXxQ9E2/3DVnKsrl0kgOb+EnKZAXdHXrbMlrox Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10295"; a="321468717" X-IronPort-AV: E=Sophos;i="5.90,206,1643702400"; d="scan'208";a="321468717" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2022 19:49:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,206,1643702400"; d="scan'208";a="649685400" Received: from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181]) by orsmga004.jf.intel.com with ESMTP; 23 Mar 2022 19:48:59 -0700 From: Wenjun Wu To: dev@dpdk.org, qi.z.zhang@intel.com, qiming.yang@intel.com Cc: Wenjun Wu Subject: [PATCH] net/ice: fix error set of queue number Date: Thu, 24 Mar 2022 10:26:43 +0800 Message-Id: <20220324022643.61254-1-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The queue number actually applied should be the maximum integer power of 2 less than or equal to min(vsi->nb_qps, ICE_MAX_Q_PER_TC), so we need to get the most significant 1 bit. However the return value of function rte_bsf32 is the least significant 1 bit. This patch replaces the function rte_bsf32 with the function rte_fls_u32 and adds necessary boundary check. Signed-off-by: Wenjun Wu --- drivers/net/ice/ice_ethdev.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 13adcf90ed..73e550f5fb 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -808,7 +808,7 @@ ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi, struct ice_aqc_vsi_props *info, uint8_t enabled_tcmap) { - uint16_t bsf, qp_idx; + uint16_t fls, qp_idx; /* default tc 0 now. Multi-TC supporting need to be done later. * Configure TC and queue mapping parameters, for enabled TC, @@ -820,15 +820,15 @@ ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi, } vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC); - bsf = rte_bsf32(vsi->nb_qps); + fls = (vsi->nb_qps == 0) ? 0 : rte_fls_u32(vsi->nb_qps) - 1; /* Adjust the queue number to actual queues that can be applied */ - vsi->nb_qps = 0x1 << bsf; + vsi->nb_qps = (vsi->nb_qps == 0) ? 0 : 0x1 << fls; qp_idx = 0; /* Set tc and queue mapping with VSI */ info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx << ICE_AQ_VSI_TC_Q_OFFSET_S) | - (bsf << ICE_AQ_VSI_TC_Q_NUM_S)); + (fls << ICE_AQ_VSI_TC_Q_NUM_S)); /* Associate queue number with VSI */ info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);