From patchwork Thu Mar 24 05:12:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 108835 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3C17AA04FF; Thu, 24 Mar 2022 06:34:44 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0CB4741151; Thu, 24 Mar 2022 06:34:44 +0100 (CET) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id 8DF8E410FC for ; Thu, 24 Mar 2022 06:34:42 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648100082; x=1679636082; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=TREOHkZ+m07Lk6wARUoLk7NMouUok3UyDcoe05ZMdTQ=; b=ny9hHnE+u2JK3fvEWoyu34s8ttXKque5Xhn1XUNRRp9LJC5BFvTvP/Ka BkyoLetOE33nquxB2p04g5ZZdj8Pk/4knw5JFN6foOqU/OJrwdOWNQuga YJFRUxvli1vPmtm880vSymI7ga8wi/Z5HgzROzA1l968V9lp1PrIvYBy6 9EZXoJgUnL6/R65kc3w0OS8sa5kdvBF/OkwMYyDOmqniSzQ30hobaJYdO n1437+GYEnTr0363r2ckqHSmxTxc/18vPmu8qM6x7FFAScW+MVl0xRnUX IYk7hYfLnUdNQ3ASCsMKG6I8LlqO2/qxab97WO1VWG+UEEnLnZyz5LmNM w==; X-IronPort-AV: E=McAfee;i="6200,9189,10295"; a="258478944" X-IronPort-AV: E=Sophos;i="5.90,206,1643702400"; d="scan'208";a="258478944" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2022 22:34:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,206,1643702400"; d="scan'208";a="717687579" Received: from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181]) by orsmga005.jf.intel.com with ESMTP; 23 Mar 2022 22:34:40 -0700 From: Wenjun Wu To: dev@dpdk.org, qiming.yang@intel.com, qi.z.zhang@intel.com Cc: Wenjun Wu Subject: [PATCH v1] net/ice: support 256 queues Date: Thu, 24 Mar 2022 13:12:32 +0800 Message-Id: <20220324051232.170169-1-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org 256 queues can be allowed now. This patch improves the code to support 256 queues for per PF. Signed-off-by: Wenjun Wu Acked-by: Qi Zhang --- drivers/net/ice/ice_ethdev.c | 8 ++++---- drivers/net/ice/ice_ethdev.h | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 13adcf90ed..73e550f5fb 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -808,7 +808,7 @@ ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi, struct ice_aqc_vsi_props *info, uint8_t enabled_tcmap) { - uint16_t bsf, qp_idx; + uint16_t fls, qp_idx; /* default tc 0 now. Multi-TC supporting need to be done later. * Configure TC and queue mapping parameters, for enabled TC, @@ -820,15 +820,15 @@ ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi, } vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC); - bsf = rte_bsf32(vsi->nb_qps); + fls = (vsi->nb_qps == 0) ? 0 : rte_fls_u32(vsi->nb_qps) - 1; /* Adjust the queue number to actual queues that can be applied */ - vsi->nb_qps = 0x1 << bsf; + vsi->nb_qps = (vsi->nb_qps == 0) ? 0 : 0x1 << fls; qp_idx = 0; /* Set tc and queue mapping with VSI */ info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx << ICE_AQ_VSI_TC_Q_OFFSET_S) | - (bsf << ICE_AQ_VSI_TC_Q_NUM_S)); + (fls << ICE_AQ_VSI_TC_Q_NUM_S)); /* Associate queue number with VSI */ info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG); diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h index 3ed580d438..09cfb60b0f 100644 --- a/drivers/net/ice/ice_ethdev.h +++ b/drivers/net/ice/ice_ethdev.h @@ -21,8 +21,8 @@ #define ICE_ADMINQ_BUF_SZ 4096 #define ICE_SBIOQ_BUF_SZ 4096 #define ICE_MAILBOXQ_BUF_SZ 4096 -/* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ -#define ICE_MAX_Q_PER_TC 64 +/* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64, 128, 256 */ +#define ICE_MAX_Q_PER_TC 256 #define ICE_NUM_DESC_DEFAULT 512 #define ICE_BUF_SIZE_MIN 1024 #define ICE_FRAME_SIZE_MAX 9728