From patchwork Thu Apr 7 10:56:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109352 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EADDEA0508; Thu, 7 Apr 2022 04:58:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DA373410DD; Thu, 7 Apr 2022 04:58:05 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 444FA4014F for ; Thu, 7 Apr 2022 04:58:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300284; x=1680836284; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=J4Wo64ItQBH4N6CEJHCXCjbSj6gRI5z9jkTbPzFPbys=; b=enX7W0FXR0p4LZzlZ9aB+KvafVVrNCR8pSg4yfgGjty+bd9uLsHHoSs6 94NfdPSYwgm0O+6hLR5sonxH0axNEzyLrRsCuHm3iOJJjxHaO9aVENdey OpF0IQITGS7ZUr7Hy8h13e0AgTKladxtgqImGnVlTxdZ20DENtqt/s5sv ROujxnPbh21+EEZayKqaG/wx/UAgBC1Zv5JBL/YOawdI/KWSbEuUaENtX ZTQJn9n9bzz8RxgbmQNjNeuXu4ijQA2Nau/c6pm3SwZaHDkSktaTkxWxG KeiGHLlNtjc1EFKXlTf2T9k0x8inFsZLiwRmtt17hSG2jo7NxtS2zcQlA w==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="321907391" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="321907391" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:03 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850392" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:01 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Kevin Liu Subject: [PATCH 01/39] net/ice: enable RSS RETA ops for DCF hardware Date: Thu, 7 Apr 2022 10:56:28 +0000 Message-Id: <20220407105706.18889-2-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Steve Yang RSS RETA should be updated and queried by application, Add related ops ('.reta_update', '.reta_query') for DCF. Signed-off-by: Steve Yang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_dcf.c | 2 +- drivers/net/ice/ice_dcf.h | 1 + drivers/net/ice/ice_dcf_ethdev.c | 77 ++++++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c index 7f0c074b01..070d1b71ac 100644 --- a/drivers/net/ice/ice_dcf.c +++ b/drivers/net/ice/ice_dcf.c @@ -790,7 +790,7 @@ ice_dcf_configure_rss_key(struct ice_dcf_hw *hw) return err; } -static int +int ice_dcf_configure_rss_lut(struct ice_dcf_hw *hw) { struct virtchnl_rss_lut *rss_lut; diff --git a/drivers/net/ice/ice_dcf.h b/drivers/net/ice/ice_dcf.h index 6ec766ebda..b2c6aa2684 100644 --- a/drivers/net/ice/ice_dcf.h +++ b/drivers/net/ice/ice_dcf.h @@ -122,6 +122,7 @@ int ice_dcf_send_aq_cmd(void *dcf_hw, struct ice_aq_desc *desc, int ice_dcf_handle_vsi_update_event(struct ice_dcf_hw *hw); int ice_dcf_init_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw); void ice_dcf_uninit_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw); +int ice_dcf_configure_rss_lut(struct ice_dcf_hw *hw); int ice_dcf_init_rss(struct ice_dcf_hw *hw); int ice_dcf_configure_queues(struct ice_dcf_hw *hw); int ice_dcf_config_irq_map(struct ice_dcf_hw *hw); diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index 59610e058f..1ac66ed990 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -761,6 +761,81 @@ ice_dcf_dev_flow_ops_get(struct rte_eth_dev *dev, return 0; } +static int +ice_dcf_dev_rss_reta_update(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) +{ + struct ice_dcf_adapter *adapter = dev->data->dev_private; + struct ice_dcf_hw *hw = &adapter->real_hw; + uint8_t *lut; + uint16_t i, idx, shift; + int ret; + + if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF)) + return -ENOTSUP; + + if (reta_size != hw->vf_res->rss_lut_size) { + PMD_DRV_LOG(ERR, "The size of hash lookup table configured " + "(%d) doesn't match the number of hardware can " + "support (%d)", reta_size, hw->vf_res->rss_lut_size); + return -EINVAL; + } + + lut = rte_zmalloc("rss_lut", reta_size, 0); + if (!lut) { + PMD_DRV_LOG(ERR, "No memory can be allocated"); + return -ENOMEM; + } + /* store the old lut table temporarily */ + rte_memcpy(lut, hw->rss_lut, reta_size); + + for (i = 0; i < reta_size; i++) { + idx = i / RTE_ETH_RETA_GROUP_SIZE; + shift = i % RTE_ETH_RETA_GROUP_SIZE; + if (reta_conf[idx].mask & (1ULL << shift)) + lut[i] = reta_conf[idx].reta[shift]; + } + + rte_memcpy(hw->rss_lut, lut, reta_size); + /* send virtchnnl ops to configure rss*/ + ret = ice_dcf_configure_rss_lut(hw); + if (ret) /* revert back */ + rte_memcpy(hw->rss_lut, lut, reta_size); + rte_free(lut); + + return ret; +} + +static int +ice_dcf_dev_rss_reta_query(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) +{ + struct ice_dcf_adapter *adapter = dev->data->dev_private; + struct ice_dcf_hw *hw = &adapter->real_hw; + uint16_t i, idx, shift; + + if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF)) + return -ENOTSUP; + + if (reta_size != hw->vf_res->rss_lut_size) { + PMD_DRV_LOG(ERR, "The size of hash lookup table configured " + "(%d) doesn't match the number of hardware can " + "support (%d)", reta_size, hw->vf_res->rss_lut_size); + return -EINVAL; + } + + for (i = 0; i < reta_size; i++) { + idx = i / RTE_ETH_RETA_GROUP_SIZE; + shift = i % RTE_ETH_RETA_GROUP_SIZE; + if (reta_conf[idx].mask & (1ULL << shift)) + reta_conf[idx].reta[shift] = hw->rss_lut[i]; + } + + return 0; +} + #define ICE_DCF_32_BIT_WIDTH (CHAR_BIT * 4) #define ICE_DCF_48_BIT_WIDTH (CHAR_BIT * 6) #define ICE_DCF_48_BIT_MASK RTE_LEN2MASK(ICE_DCF_48_BIT_WIDTH, uint64_t) @@ -1107,6 +1182,8 @@ static const struct eth_dev_ops ice_dcf_eth_dev_ops = { .udp_tunnel_port_add = ice_dcf_dev_udp_tunnel_port_add, .udp_tunnel_port_del = ice_dcf_dev_udp_tunnel_port_del, .tm_ops_get = ice_dcf_tm_ops_get, + .reta_update = ice_dcf_dev_rss_reta_update, + .reta_query = ice_dcf_dev_rss_reta_query, }; static int From patchwork Thu Apr 7 10:56:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109353 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EFC4FA0508; Thu, 7 Apr 2022 04:58:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DC9E0410DC; Thu, 7 Apr 2022 04:58:13 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 1BE274014F for ; Thu, 7 Apr 2022 04:58:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300292; x=1680836292; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mrR24+g49ndVilfIC2X4RY0fJTgOXLiccIJAdDUJoA8=; b=kefFdvF0nwrk8F/BgOXDYqdDMQKHgvMpdPZNvHzvWXIcchXhkOTCho3H AMuNu5buI+ZfwP79nwEubffZOC4t2FNz3liDksFHayn5Ql9fpzIiL9nE9 9Xfho8fpOFgHIWRlXNYKWOf0lSdRudpp+XnuUZuYBkhblcxlG7pcn+Wbz A4cbG3hmirEICAOXzG0560eSfZsMMtb5JWZW0flhLcEQiJo6uXdnFtgsy QAJqV4HsW4hx3Ttz0QVvaoJK1+T/69DlFah1HnShmlm6BKEiqF7Amt9ZC mrG61V9613czR1LEFpehG6YvovqKlbgQ7AtO3hrf9tqmrecJG6nqbwRUs g==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="321907403" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="321907403" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:11 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850428" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:09 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Kevin Liu Subject: [PATCH 02/39] net/ice: enable RSS HASH ops for DCF hardware Date: Thu, 7 Apr 2022 10:56:29 +0000 Message-Id: <20220407105706.18889-3-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Steve Yang RSS HASH should be updated and queried by application, Add related ops ('.rss_hash_update', '.rss_hash_conf_get') for DCF. Because DCF doesn't support configure RSS HASH, only HASH key can be updated within ops '.rss_hash_update'. Signed-off-by: Steve Yang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_dcf.c | 2 +- drivers/net/ice/ice_dcf.h | 1 + drivers/net/ice/ice_dcf_ethdev.c | 51 ++++++++++++++++++++++++++++++++ 3 files changed, 53 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c index 070d1b71ac..89c0203ba3 100644 --- a/drivers/net/ice/ice_dcf.c +++ b/drivers/net/ice/ice_dcf.c @@ -758,7 +758,7 @@ ice_dcf_uninit_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw) hw->ets_config = NULL; } -static int +int ice_dcf_configure_rss_key(struct ice_dcf_hw *hw) { struct virtchnl_rss_key *rss_key; diff --git a/drivers/net/ice/ice_dcf.h b/drivers/net/ice/ice_dcf.h index b2c6aa2684..f0b45af5ae 100644 --- a/drivers/net/ice/ice_dcf.h +++ b/drivers/net/ice/ice_dcf.h @@ -122,6 +122,7 @@ int ice_dcf_send_aq_cmd(void *dcf_hw, struct ice_aq_desc *desc, int ice_dcf_handle_vsi_update_event(struct ice_dcf_hw *hw); int ice_dcf_init_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw); void ice_dcf_uninit_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw); +int ice_dcf_configure_rss_key(struct ice_dcf_hw *hw); int ice_dcf_configure_rss_lut(struct ice_dcf_hw *hw); int ice_dcf_init_rss(struct ice_dcf_hw *hw); int ice_dcf_configure_queues(struct ice_dcf_hw *hw); diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index 1ac66ed990..ccad7fc304 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -836,6 +836,55 @@ ice_dcf_dev_rss_reta_query(struct rte_eth_dev *dev, return 0; } +static int +ice_dcf_dev_rss_hash_update(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct ice_dcf_adapter *adapter = dev->data->dev_private; + struct ice_dcf_hw *hw = &adapter->real_hw; + + if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF)) + return -ENOTSUP; + + /* HENA setting, it is enabled by default, no change */ + if (!rss_conf->rss_key || rss_conf->rss_key_len == 0) { + PMD_DRV_LOG(DEBUG, "No key to be configured"); + return 0; + } else if (rss_conf->rss_key_len != hw->vf_res->rss_key_size) { + PMD_DRV_LOG(ERR, "The size of hash key configured " + "(%d) doesn't match the size of hardware can " + "support (%d)", rss_conf->rss_key_len, + hw->vf_res->rss_key_size); + return -EINVAL; + } + + rte_memcpy(hw->rss_key, rss_conf->rss_key, rss_conf->rss_key_len); + + return ice_dcf_configure_rss_key(hw); +} + +static int +ice_dcf_dev_rss_hash_conf_get(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct ice_dcf_adapter *adapter = dev->data->dev_private; + struct ice_dcf_hw *hw = &adapter->real_hw; + + if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF)) + return -ENOTSUP; + + /* Just set it to default value now. */ + rss_conf->rss_hf = ICE_RSS_OFFLOAD_ALL; + + if (!rss_conf->rss_key) + return 0; + + rss_conf->rss_key_len = hw->vf_res->rss_key_size; + rte_memcpy(rss_conf->rss_key, hw->rss_key, rss_conf->rss_key_len); + + return 0; +} + #define ICE_DCF_32_BIT_WIDTH (CHAR_BIT * 4) #define ICE_DCF_48_BIT_WIDTH (CHAR_BIT * 6) #define ICE_DCF_48_BIT_MASK RTE_LEN2MASK(ICE_DCF_48_BIT_WIDTH, uint64_t) @@ -1184,6 +1233,8 @@ static const struct eth_dev_ops ice_dcf_eth_dev_ops = { .tm_ops_get = ice_dcf_tm_ops_get, .reta_update = ice_dcf_dev_rss_reta_update, .reta_query = ice_dcf_dev_rss_reta_query, + .rss_hash_update = ice_dcf_dev_rss_hash_update, + .rss_hash_conf_get = ice_dcf_dev_rss_hash_conf_get, }; static int From patchwork Thu Apr 7 10:56:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109355 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 04011A0508; Thu, 7 Apr 2022 04:58:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3618242852; Thu, 7 Apr 2022 04:58:20 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id E02AC42835 for ; Thu, 7 Apr 2022 04:58:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300298; x=1680836298; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5FnmNbyjznWNp/QvhpWMhZ+N23zqp246e9Z1lWhhsmg=; b=ddyrZsA1xjTOMATOizL9q0wyovQn+1ru04tLJ5+Sb7Wx8YMA2zNsd06V 67EyoLLrKuvhUFaFSEFhxXAAwbYclRE8vXojUn9nfMT3KlgUJn72RAu0x M+yWOeOo8E9BGMGWJ+cInN7+5TRpA++NHdwc4aLRuopAN1RIQEUEdhDM/ 5VsUJuevoXnHNuhR6f1gRBOQetLDWKRqWDPOlZp1meu8Stk4vD5kg14+C I3QO8f2OcpsPH9VPBTWDfRSha8FGFDSQoSDy4omvvTjjXOWGWVOHJW7gu Seo659QVOldWcXy5E3Jql6ycK7CHqJN45EenWuZwrhMDI/bBE/wJ9V2qj A==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738309" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738309" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:16 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850452" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:14 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Robin Zhang , Kevin Liu Subject: [PATCH 03/39] net/ice: cleanup Tx buffers Date: Thu, 7 Apr 2022 10:56:30 +0000 Message-Id: <20220407105706.18889-4-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Robin Zhang Add support for ops rte_eth_tx_done_cleanup in dcf Signed-off-by: Robin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_dcf_ethdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index ccad7fc304..d8b5961514 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -1235,6 +1235,7 @@ static const struct eth_dev_ops ice_dcf_eth_dev_ops = { .reta_query = ice_dcf_dev_rss_reta_query, .rss_hash_update = ice_dcf_dev_rss_hash_update, .rss_hash_conf_get = ice_dcf_dev_rss_hash_conf_get, + .tx_done_cleanup = ice_tx_done_cleanup, }; static int From patchwork Thu Apr 7 10:56:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109356 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3586DA0508; Thu, 7 Apr 2022 04:58:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2921C42868; Thu, 7 Apr 2022 04:58:23 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 35E8842868 for ; Thu, 7 Apr 2022 04:58:21 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300301; x=1680836301; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uhH6sbpPFSDqWF8L5yx2JMPlQrbIgO+TzDOmyZdVXeM=; b=SB4q32mB8U22//ChnvIpvjGlBijC/RveQEFtR/t8YFTfzG3vVbpaiASb 43BpT2C/Xid/EqkO5M/xbxfm1muIGeLtgTaHeuF4BPKCwK00A/+RVtbzT j0/8vLXg5mUlqx1/OJSTkqalkMhqQc/Etr48hfSQJCMUpv+acLyZ1dQAd 3b1E2ZJRhfCKZ6gn2P5XfywXXTwWIaQlu6SFZxH/7gEYImSBfEl9v/UW6 oqB6tBlyyhnfMuKS5g4uUwLkFSmu3qcTwM8TJ8ucU5vytz9usuY2ID7kq hj0fQSLYy7dKYjF6CvhkSmkipa9+G+iyfKWUY1Kv/0wrzrpqGi1RpTEq7 A==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738318" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738318" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:20 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850462" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:18 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Jie Wang , Kevin Liu Subject: [PATCH 04/39] net/ice: add ops MTU-SET to dcf Date: Thu, 7 Apr 2022 10:56:31 +0000 Message-Id: <20220407105706.18889-5-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Jie Wang add API "mtu_set" to dcf, and it can configure the port mtu through cmdline. Signed-off-by: Jie Wang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_dcf_ethdev.c | 14 ++++++++++++++ drivers/net/ice/ice_dcf_ethdev.h | 6 ++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index d8b5961514..06d752fd61 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -1081,6 +1081,19 @@ ice_dcf_link_update(struct rte_eth_dev *dev, return rte_eth_linkstatus_set(dev, &new_link); } +static int +ice_dcf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu __rte_unused) +{ + /* mtu setting is forbidden if port is start */ + if (dev->data->dev_started != 0) { + PMD_DRV_LOG(ERR, "port %d must be stopped before configuration", + dev->data->port_id); + return -EBUSY; + } + + return 0; +} + bool ice_dcf_adminq_need_retry(struct ice_adapter *ad) { @@ -1236,6 +1249,7 @@ static const struct eth_dev_ops ice_dcf_eth_dev_ops = { .rss_hash_update = ice_dcf_dev_rss_hash_update, .rss_hash_conf_get = ice_dcf_dev_rss_hash_conf_get, .tx_done_cleanup = ice_tx_done_cleanup, + .mtu_set = ice_dcf_dev_mtu_set, }; static int diff --git a/drivers/net/ice/ice_dcf_ethdev.h b/drivers/net/ice/ice_dcf_ethdev.h index 11a1305038..f2faf26f58 100644 --- a/drivers/net/ice/ice_dcf_ethdev.h +++ b/drivers/net/ice/ice_dcf_ethdev.h @@ -15,6 +15,12 @@ #define ICE_DCF_MAX_RINGS 1 +#define ICE_DCF_FRAME_SIZE_MAX 9728 +#define ICE_DCF_VLAN_TAG_SIZE 4 +#define ICE_DCF_ETH_OVERHEAD \ + (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_DCF_VLAN_TAG_SIZE * 2) +#define ICE_DCF_ETH_MAX_LEN (RTE_ETHER_MTU + ICE_DCF_ETH_OVERHEAD) + struct ice_dcf_queue { uint64_t dummy; }; From patchwork Thu Apr 7 10:56:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109357 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 75206A0508; Thu, 7 Apr 2022 04:58:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 19FC7427EB; Thu, 7 Apr 2022 04:58:27 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id DB53D4286D for ; Thu, 7 Apr 2022 04:58:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300305; x=1680836305; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HAg21Ie7KGkUTfzVHs6REN3QEDKJCuyvy8CYzTL9F7A=; b=AkxkhWh5rQyECR92QFBadI43OoFgJv1hCs3g52/4rs9982nU0ukSLr5s oddmlnttRyGBaGW10ZUZmAN6RC9ShMPD5kQWSt2ndt0kVYWnc2tWOdEu/ cav/bU5+SZlABlrCK3qm7WqHaI1FwQkROHlQI3QmmW8WrlPPesAS/3GHU 28RAQEI+gKze4v8RRoIIWfQ2X1wCUc92B06mTAJiGz3NpgYZ8T+jAA52M Z3umAEUc7c55UTNsThn6Wo2XWeb2ksD3xSpfoeXHVTre2+iUldQkNjnr9 LOT1Sch2my+8aZggRqx/Iy0RB5mgJtoIDwSx6TCaQRRJvgJt0VpyeOylA A==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738319" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738319" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:24 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850473" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:22 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Jie Wang , Kevin Liu Subject: [PATCH 05/39] net/ice: add ops dev-supported-ptypes-get to dcf Date: Thu, 7 Apr 2022 10:56:32 +0000 Message-Id: <20220407105706.18889-6-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Jie Wang add API "dev_supported_ptypes_get" to dcf, that dcf pmd can get ptypes through the new API. Signed-off-by: Jie Wang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_dcf_ethdev.c | 80 +++++++++++++++++++------------- 1 file changed, 49 insertions(+), 31 deletions(-) diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index 06d752fd61..6a577a6582 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -1218,38 +1218,56 @@ ice_dcf_dev_reset(struct rte_eth_dev *dev) return ret; } +static const uint32_t * +ice_dcf_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) +{ + static const uint32_t ptypes[] = { + RTE_PTYPE_L2_ETHER, + RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, + RTE_PTYPE_L4_FRAG, + RTE_PTYPE_L4_ICMP, + RTE_PTYPE_L4_NONFRAG, + RTE_PTYPE_L4_SCTP, + RTE_PTYPE_L4_TCP, + RTE_PTYPE_L4_UDP, + RTE_PTYPE_UNKNOWN + }; + return ptypes; +} + static const struct eth_dev_ops ice_dcf_eth_dev_ops = { - .dev_start = ice_dcf_dev_start, - .dev_stop = ice_dcf_dev_stop, - .dev_close = ice_dcf_dev_close, - .dev_reset = ice_dcf_dev_reset, - .dev_configure = ice_dcf_dev_configure, - .dev_infos_get = ice_dcf_dev_info_get, - .rx_queue_setup = ice_rx_queue_setup, - .tx_queue_setup = ice_tx_queue_setup, - .rx_queue_release = ice_dev_rx_queue_release, - .tx_queue_release = ice_dev_tx_queue_release, - .rx_queue_start = ice_dcf_rx_queue_start, - .tx_queue_start = ice_dcf_tx_queue_start, - .rx_queue_stop = ice_dcf_rx_queue_stop, - .tx_queue_stop = ice_dcf_tx_queue_stop, - .link_update = ice_dcf_link_update, - .stats_get = ice_dcf_stats_get, - .stats_reset = ice_dcf_stats_reset, - .promiscuous_enable = ice_dcf_dev_promiscuous_enable, - .promiscuous_disable = ice_dcf_dev_promiscuous_disable, - .allmulticast_enable = ice_dcf_dev_allmulticast_enable, - .allmulticast_disable = ice_dcf_dev_allmulticast_disable, - .flow_ops_get = ice_dcf_dev_flow_ops_get, - .udp_tunnel_port_add = ice_dcf_dev_udp_tunnel_port_add, - .udp_tunnel_port_del = ice_dcf_dev_udp_tunnel_port_del, - .tm_ops_get = ice_dcf_tm_ops_get, - .reta_update = ice_dcf_dev_rss_reta_update, - .reta_query = ice_dcf_dev_rss_reta_query, - .rss_hash_update = ice_dcf_dev_rss_hash_update, - .rss_hash_conf_get = ice_dcf_dev_rss_hash_conf_get, - .tx_done_cleanup = ice_tx_done_cleanup, - .mtu_set = ice_dcf_dev_mtu_set, + .dev_start = ice_dcf_dev_start, + .dev_stop = ice_dcf_dev_stop, + .dev_close = ice_dcf_dev_close, + .dev_reset = ice_dcf_dev_reset, + .dev_configure = ice_dcf_dev_configure, + .dev_infos_get = ice_dcf_dev_info_get, + .dev_supported_ptypes_get = ice_dcf_dev_supported_ptypes_get, + .rx_queue_setup = ice_rx_queue_setup, + .tx_queue_setup = ice_tx_queue_setup, + .rx_queue_release = ice_dev_rx_queue_release, + .tx_queue_release = ice_dev_tx_queue_release, + .rx_queue_start = ice_dcf_rx_queue_start, + .tx_queue_start = ice_dcf_tx_queue_start, + .rx_queue_stop = ice_dcf_rx_queue_stop, + .tx_queue_stop = ice_dcf_tx_queue_stop, + .link_update = ice_dcf_link_update, + .stats_get = ice_dcf_stats_get, + .stats_reset = ice_dcf_stats_reset, + .promiscuous_enable = ice_dcf_dev_promiscuous_enable, + .promiscuous_disable = ice_dcf_dev_promiscuous_disable, + .allmulticast_enable = ice_dcf_dev_allmulticast_enable, + .allmulticast_disable = ice_dcf_dev_allmulticast_disable, + .flow_ops_get = ice_dcf_dev_flow_ops_get, + .udp_tunnel_port_add = ice_dcf_dev_udp_tunnel_port_add, + .udp_tunnel_port_del = ice_dcf_dev_udp_tunnel_port_del, + .tm_ops_get = ice_dcf_tm_ops_get, + .reta_update = ice_dcf_dev_rss_reta_update, + .reta_query = ice_dcf_dev_rss_reta_query, + .rss_hash_update = ice_dcf_dev_rss_hash_update, + .rss_hash_conf_get = ice_dcf_dev_rss_hash_conf_get, + .tx_done_cleanup = ice_tx_done_cleanup, + .mtu_set = ice_dcf_dev_mtu_set, }; static int From patchwork Thu Apr 7 10:56:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109358 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4F5DAA0508; Thu, 7 Apr 2022 04:58:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 113E642870; Thu, 7 Apr 2022 04:58:31 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 1CF9A42870 for ; Thu, 7 Apr 2022 04:58:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300309; x=1680836309; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WOQHVMy6I/PNV1SH4Kmb0apkriJ+8tFdVGNa6R1TKVo=; b=O7NTBzxW23r6cJxED4GTgEiMoVwNtmXvq8lWCcd8fHap/UQgg9+tYYen AmNq+bnzPi5sCnV5JJs/gmJwMly8SOvjLiL2qGGFNBb+bpiOXvrZMVagL tC5fLacp3ISKfpVzgMTa6Qzh+9lxvVRhg2E9dmQdMdTlLgFC7xROafrb1 xSaaLE6QZqaz55jzNe4D/q2A+jFhwLlh7SW3Xtp0fHRqxX2QiRLnG727H m9InubEeBE9LsbVnPLj3emLMPJrZdimjKocibp/MRZN0lL8kLl3BMFZlT zmRtU9AnkIEuXsA5gYOhtljoePHeLfZsS6CHH+HVDCbxoDc7dlZFvV71m g==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738333" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738333" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:28 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850478" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:25 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Alvin Zhang , Kevin Liu Subject: [PATCH 06/39] net/ice: support dcf promisc configuration Date: Thu, 7 Apr 2022 10:56:33 +0000 Message-Id: <20220407105706.18889-7-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alvin Zhang Support configuration of unicast and multicast promisc on dcf. Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_dcf_ethdev.c | 77 ++++++++++++++++++++++++++++++-- drivers/net/ice/ice_dcf_ethdev.h | 3 ++ 2 files changed, 76 insertions(+), 4 deletions(-) diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index 6a577a6582..87d281ee93 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -727,27 +727,95 @@ ice_dcf_dev_info_get(struct rte_eth_dev *dev, } static int -ice_dcf_dev_promiscuous_enable(__rte_unused struct rte_eth_dev *dev) +dcf_config_promisc(struct ice_dcf_adapter *adapter, + bool enable_unicast, + bool enable_multicast) { + struct ice_dcf_hw *hw = &adapter->real_hw; + struct virtchnl_promisc_info promisc; + struct dcf_virtchnl_cmd args; + int err; + + promisc.flags = 0; + promisc.vsi_id = hw->vsi_res->vsi_id; + + if (enable_unicast) + promisc.flags |= FLAG_VF_UNICAST_PROMISC; + + if (enable_multicast) + promisc.flags |= FLAG_VF_MULTICAST_PROMISC; + + memset(&args, 0, sizeof(args)); + args.v_op = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE; + args.req_msg = (uint8_t *)&promisc; + args.req_msglen = sizeof(promisc); + + err = ice_dcf_execute_virtchnl_cmd(hw, &args); + if (err) { + PMD_DRV_LOG(ERR, + "fail to execute command VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE"); + return err; + } + + adapter->promisc_unicast_enabled = enable_unicast; + adapter->promisc_multicast_enabled = enable_multicast; return 0; } +static int +ice_dcf_dev_promiscuous_enable(__rte_unused struct rte_eth_dev *dev) +{ + struct ice_dcf_adapter *adapter = dev->data->dev_private; + + if (adapter->promisc_unicast_enabled) { + PMD_DRV_LOG(INFO, "promiscuous has been enabled"); + return 0; + } + + return dcf_config_promisc(adapter, true, + adapter->promisc_multicast_enabled); +} + static int ice_dcf_dev_promiscuous_disable(__rte_unused struct rte_eth_dev *dev) { - return 0; + struct ice_dcf_adapter *adapter = dev->data->dev_private; + + if (!adapter->promisc_unicast_enabled) { + PMD_DRV_LOG(INFO, "promiscuous has been disabled"); + return 0; + } + + return dcf_config_promisc(adapter, false, + adapter->promisc_multicast_enabled); } static int ice_dcf_dev_allmulticast_enable(__rte_unused struct rte_eth_dev *dev) { - return 0; + struct ice_dcf_adapter *adapter = dev->data->dev_private; + + if (adapter->promisc_multicast_enabled) { + PMD_DRV_LOG(INFO, "allmulticast has been enabled"); + return 0; + } + + return dcf_config_promisc(adapter, adapter->promisc_unicast_enabled, + true); } static int ice_dcf_dev_allmulticast_disable(__rte_unused struct rte_eth_dev *dev) { - return 0; + struct ice_dcf_adapter *adapter = dev->data->dev_private; + + if (!adapter->promisc_multicast_enabled) { + PMD_DRV_LOG(INFO, "allmulticast has been disabled"); + return 0; + } + + return dcf_config_promisc(adapter, adapter->promisc_unicast_enabled, + false); } static int @@ -1299,6 +1367,7 @@ ice_dcf_dev_init(struct rte_eth_dev *eth_dev) return -1; } + dcf_config_promisc(adapter, false, false); return 0; } diff --git a/drivers/net/ice/ice_dcf_ethdev.h b/drivers/net/ice/ice_dcf_ethdev.h index f2faf26f58..22e450527b 100644 --- a/drivers/net/ice/ice_dcf_ethdev.h +++ b/drivers/net/ice/ice_dcf_ethdev.h @@ -33,6 +33,9 @@ struct ice_dcf_adapter { struct ice_adapter parent; /* Must be first */ struct ice_dcf_hw real_hw; + bool promisc_unicast_enabled; + bool promisc_multicast_enabled; + int num_reprs; struct ice_dcf_repr_info *repr_infos; }; From patchwork Thu Apr 7 10:56:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109359 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DAA26A0508; Thu, 7 Apr 2022 04:58:48 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 088D6410EF; Thu, 7 Apr 2022 04:58:36 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id B68B642874 for ; Thu, 7 Apr 2022 04:58:33 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; 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06 Apr 2022 19:58:30 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Kevin Liu , Alvin Zhang Subject: [PATCH 07/39] net/ice: support dcf MAC configuration Date: Thu, 7 Apr 2022 10:56:34 +0000 Message-Id: <20220407105706.18889-8-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Below PMD ops are supported in this patch: .mac_addr_add = dcf_dev_add_mac_addr .mac_addr_remove = dcf_dev_del_mac_addr .set_mc_addr_list = dcf_set_mc_addr_list .mac_addr_set = dcf_dev_set_default_mac_addr Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_dcf.c | 9 +- drivers/net/ice/ice_dcf.h | 4 +- drivers/net/ice/ice_dcf_ethdev.c | 218 ++++++++++++++++++++++++++++++- drivers/net/ice/ice_dcf_ethdev.h | 5 +- 4 files changed, 226 insertions(+), 10 deletions(-) diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c index 89c0203ba3..55ae68c456 100644 --- a/drivers/net/ice/ice_dcf.c +++ b/drivers/net/ice/ice_dcf.c @@ -1089,10 +1089,11 @@ ice_dcf_query_stats(struct ice_dcf_hw *hw, } int -ice_dcf_add_del_all_mac_addr(struct ice_dcf_hw *hw, bool add) +ice_dcf_add_del_all_mac_addr(struct ice_dcf_hw *hw, + struct rte_ether_addr *addr, + bool add, uint8_t type) { struct virtchnl_ether_addr_list *list; - struct rte_ether_addr *addr; struct dcf_virtchnl_cmd args; int len, err = 0; @@ -1105,7 +1106,6 @@ ice_dcf_add_del_all_mac_addr(struct ice_dcf_hw *hw, bool add) } len = sizeof(struct virtchnl_ether_addr_list); - addr = hw->eth_dev->data->mac_addrs; len += sizeof(struct virtchnl_ether_addr); list = rte_zmalloc(NULL, len, 0); @@ -1116,9 +1116,10 @@ ice_dcf_add_del_all_mac_addr(struct ice_dcf_hw *hw, bool add) rte_memcpy(list->list[0].addr, addr->addr_bytes, sizeof(addr->addr_bytes)); + PMD_DRV_LOG(DEBUG, "add/rm mac:" RTE_ETHER_ADDR_PRT_FMT, RTE_ETHER_ADDR_BYTES(addr)); - + list->list[0].type = type; list->vsi_id = hw->vsi_res->vsi_id; list->num_elements = 1; diff --git a/drivers/net/ice/ice_dcf.h b/drivers/net/ice/ice_dcf.h index f0b45af5ae..78df202a77 100644 --- a/drivers/net/ice/ice_dcf.h +++ b/drivers/net/ice/ice_dcf.h @@ -131,7 +131,9 @@ int ice_dcf_switch_queue(struct ice_dcf_hw *hw, uint16_t qid, bool rx, bool on); int ice_dcf_disable_queues(struct ice_dcf_hw *hw); int ice_dcf_query_stats(struct ice_dcf_hw *hw, struct virtchnl_eth_stats *pstats); -int ice_dcf_add_del_all_mac_addr(struct ice_dcf_hw *hw, bool add); +int ice_dcf_add_del_all_mac_addr(struct ice_dcf_hw *hw, + struct rte_ether_addr *addr, bool add, + uint8_t type); int ice_dcf_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete); void ice_dcf_tm_conf_init(struct rte_eth_dev *dev); diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index 87d281ee93..0d944f9fd2 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -26,6 +26,12 @@ #include "ice_dcf_ethdev.h" #include "ice_rxtx.h" +#define DCF_NUM_MACADDR_MAX 64 + +static int dcf_add_del_mc_addr_list(struct ice_dcf_hw *hw, + struct rte_ether_addr *mc_addrs, + uint32_t mc_addrs_num, bool add); + static int ice_dcf_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, struct rte_eth_udp_tunnel *udp_tunnel); @@ -561,12 +567,22 @@ ice_dcf_dev_start(struct rte_eth_dev *dev) return ret; } - ret = ice_dcf_add_del_all_mac_addr(hw, true); + ret = ice_dcf_add_del_all_mac_addr(hw, hw->eth_dev->data->mac_addrs, + true, VIRTCHNL_ETHER_ADDR_PRIMARY); if (ret) { PMD_DRV_LOG(ERR, "Failed to add mac addr"); return ret; } + if (dcf_ad->mc_addrs_num) { + /* flush previous addresses */ + ret = dcf_add_del_mc_addr_list(hw, dcf_ad->mc_addrs, + dcf_ad->mc_addrs_num, true); + if (ret) + return ret; + } + + dev->data->dev_link.link_status = RTE_ETH_LINK_UP; return 0; @@ -625,7 +641,16 @@ ice_dcf_dev_stop(struct rte_eth_dev *dev) rte_intr_efd_disable(intr_handle); rte_intr_vec_list_free(intr_handle); - ice_dcf_add_del_all_mac_addr(&dcf_ad->real_hw, false); + ice_dcf_add_del_all_mac_addr(&dcf_ad->real_hw, + dcf_ad->real_hw.eth_dev->data->mac_addrs, + false, VIRTCHNL_ETHER_ADDR_PRIMARY); + + if (dcf_ad->mc_addrs_num) + /* flush previous addresses */ + (void)dcf_add_del_mc_addr_list(&dcf_ad->real_hw, + dcf_ad->mc_addrs, + dcf_ad->mc_addrs_num, false); + dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN; ad->pf.adapter_stopped = 1; hw->tm_conf.committed = false; @@ -655,7 +680,7 @@ ice_dcf_dev_info_get(struct rte_eth_dev *dev, struct ice_dcf_adapter *adapter = dev->data->dev_private; struct ice_dcf_hw *hw = &adapter->real_hw; - dev_info->max_mac_addrs = 1; + dev_info->max_mac_addrs = DCF_NUM_MACADDR_MAX; dev_info->max_rx_queues = hw->vsi_res->num_queue_pairs; dev_info->max_tx_queues = hw->vsi_res->num_queue_pairs; dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN; @@ -818,6 +843,189 @@ ice_dcf_dev_allmulticast_disable(__rte_unused struct rte_eth_dev *dev) false); } +static int +dcf_dev_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr, + __rte_unused uint32_t index, + __rte_unused uint32_t pool) +{ + struct ice_dcf_adapter *adapter = dev->data->dev_private; + int err; + + if (rte_is_zero_ether_addr(addr)) { + PMD_DRV_LOG(ERR, "Invalid Ethernet Address"); + return -EINVAL; + } + + err = ice_dcf_add_del_all_mac_addr(&adapter->real_hw, addr, true, + VIRTCHNL_ETHER_ADDR_EXTRA); + if (err) { + PMD_DRV_LOG(ERR, "fail to add MAC address"); + return err; + } + + return 0; +} + +static void +dcf_dev_del_mac_addr(struct rte_eth_dev *dev, uint32_t index) +{ + struct ice_dcf_adapter *adapter = dev->data->dev_private; + struct rte_ether_addr *addr = &dev->data->mac_addrs[index]; + int err; + + err = ice_dcf_add_del_all_mac_addr(&adapter->real_hw, addr, false, + VIRTCHNL_ETHER_ADDR_EXTRA); + if (err) + PMD_DRV_LOG(ERR, "fail to remove MAC address"); +} + +static int +dcf_add_del_mc_addr_list(struct ice_dcf_hw *hw, + struct rte_ether_addr *mc_addrs, + uint32_t mc_addrs_num, bool add) +{ + struct virtchnl_ether_addr_list *list; + struct dcf_virtchnl_cmd args; + uint32_t i; + int len, err = 0; + + len = sizeof(struct virtchnl_ether_addr_list); + len += sizeof(struct virtchnl_ether_addr) * mc_addrs_num; + + list = rte_zmalloc(NULL, len, 0); + if (!list) { + PMD_DRV_LOG(ERR, "fail to allocate memory"); + return -ENOMEM; + } + + for (i = 0; i < mc_addrs_num; i++) { + memcpy(list->list[i].addr, mc_addrs[i].addr_bytes, + sizeof(list->list[i].addr)); + list->list[i].type = VIRTCHNL_ETHER_ADDR_EXTRA; + } + + list->vsi_id = hw->vsi_res->vsi_id; + list->num_elements = mc_addrs_num; + + memset(&args, 0, sizeof(args)); + args.v_op = add ? VIRTCHNL_OP_ADD_ETH_ADDR : + VIRTCHNL_OP_DEL_ETH_ADDR; + args.req_msg = (uint8_t *)list; + args.req_msglen = len; + err = ice_dcf_execute_virtchnl_cmd(hw, &args); + if (err) + PMD_DRV_LOG(ERR, "fail to execute command %s", + add ? "OP_ADD_ETHER_ADDRESS" : + "OP_DEL_ETHER_ADDRESS"); + rte_free(list); + return err; +} + +static int +dcf_set_mc_addr_list(struct rte_eth_dev *dev, + struct rte_ether_addr *mc_addrs, + uint32_t mc_addrs_num) +{ + struct ice_dcf_adapter *adapter = dev->data->dev_private; + struct ice_dcf_hw *hw = &adapter->real_hw; + uint32_t i; + int ret; + + + if (mc_addrs_num > DCF_NUM_MACADDR_MAX) { + PMD_DRV_LOG(ERR, + "can't add more than a limited number (%u) of addresses.", + (uint32_t)DCF_NUM_MACADDR_MAX); + return -EINVAL; + } + + for (i = 0; i < mc_addrs_num; i++) { + if (!rte_is_multicast_ether_addr(&mc_addrs[i])) { + const uint8_t *mac = mc_addrs[i].addr_bytes; + + PMD_DRV_LOG(ERR, + "Invalid mac: %02x:%02x:%02x:%02x:%02x:%02x", + mac[0], mac[1], mac[2], mac[3], mac[4], + mac[5]); + return -EINVAL; + } + } + + if (adapter->mc_addrs_num) { + /* flush previous addresses */ + ret = dcf_add_del_mc_addr_list(hw, adapter->mc_addrs, + adapter->mc_addrs_num, false); + if (ret) + return ret; + } + if (!mc_addrs_num) { + adapter->mc_addrs_num = 0; + return 0; + } + + /* add new ones */ + ret = dcf_add_del_mc_addr_list(hw, mc_addrs, mc_addrs_num, true); + if (ret) { + /* if adding mac address list fails, should add the + * previous addresses back. + */ + if (adapter->mc_addrs_num) + (void)dcf_add_del_mc_addr_list(hw, adapter->mc_addrs, + adapter->mc_addrs_num, + true); + return ret; + } + adapter->mc_addrs_num = mc_addrs_num; + memcpy(adapter->mc_addrs, + mc_addrs, mc_addrs_num * sizeof(*mc_addrs)); + + return 0; +} + +static int +dcf_dev_set_default_mac_addr(struct rte_eth_dev *dev, + struct rte_ether_addr *mac_addr) +{ + struct ice_dcf_adapter *adapter = dev->data->dev_private; + struct ice_dcf_hw *hw = &adapter->real_hw; + struct rte_ether_addr *old_addr; + int ret; + + old_addr = hw->eth_dev->data->mac_addrs; + if (rte_is_same_ether_addr(old_addr, mac_addr)) + return 0; + + ret = ice_dcf_add_del_all_mac_addr(&adapter->real_hw, old_addr, false, + VIRTCHNL_ETHER_ADDR_PRIMARY); + if (ret) + PMD_DRV_LOG(ERR, "Fail to delete old MAC:" + " %02X:%02X:%02X:%02X:%02X:%02X", + old_addr->addr_bytes[0], + old_addr->addr_bytes[1], + old_addr->addr_bytes[2], + old_addr->addr_bytes[3], + old_addr->addr_bytes[4], + old_addr->addr_bytes[5]); + + ret = ice_dcf_add_del_all_mac_addr(&adapter->real_hw, mac_addr, true, + VIRTCHNL_ETHER_ADDR_PRIMARY); + if (ret) + PMD_DRV_LOG(ERR, "Fail to add new MAC:" + " %02X:%02X:%02X:%02X:%02X:%02X", + mac_addr->addr_bytes[0], + mac_addr->addr_bytes[1], + mac_addr->addr_bytes[2], + mac_addr->addr_bytes[3], + mac_addr->addr_bytes[4], + mac_addr->addr_bytes[5]); + + if (ret) + return -EIO; + + rte_ether_addr_copy(mac_addr, hw->eth_dev->data->mac_addrs); + return 0; +} + static int ice_dcf_dev_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops) @@ -1326,6 +1534,10 @@ static const struct eth_dev_ops ice_dcf_eth_dev_ops = { .promiscuous_disable = ice_dcf_dev_promiscuous_disable, .allmulticast_enable = ice_dcf_dev_allmulticast_enable, .allmulticast_disable = ice_dcf_dev_allmulticast_disable, + .mac_addr_add = dcf_dev_add_mac_addr, + .mac_addr_remove = dcf_dev_del_mac_addr, + .set_mc_addr_list = dcf_set_mc_addr_list, + .mac_addr_set = dcf_dev_set_default_mac_addr, .flow_ops_get = ice_dcf_dev_flow_ops_get, .udp_tunnel_port_add = ice_dcf_dev_udp_tunnel_port_add, .udp_tunnel_port_del = ice_dcf_dev_udp_tunnel_port_del, diff --git a/drivers/net/ice/ice_dcf_ethdev.h b/drivers/net/ice/ice_dcf_ethdev.h index 22e450527b..27f6402786 100644 --- a/drivers/net/ice/ice_dcf_ethdev.h +++ b/drivers/net/ice/ice_dcf_ethdev.h @@ -14,7 +14,7 @@ #include "ice_dcf.h" #define ICE_DCF_MAX_RINGS 1 - +#define DCF_NUM_MACADDR_MAX 64 #define ICE_DCF_FRAME_SIZE_MAX 9728 #define ICE_DCF_VLAN_TAG_SIZE 4 #define ICE_DCF_ETH_OVERHEAD \ @@ -35,7 +35,8 @@ struct ice_dcf_adapter { bool promisc_unicast_enabled; bool promisc_multicast_enabled; - + uint32_t mc_addrs_num; + struct rte_ether_addr mc_addrs[DCF_NUM_MACADDR_MAX]; int num_reprs; struct ice_dcf_repr_info *repr_infos; }; From patchwork Thu Apr 7 10:56:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109360 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A4CAEA0508; Thu, 7 Apr 2022 04:58:56 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 62D4842878; Thu, 7 Apr 2022 04:58:39 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 3CE174287C for ; Thu, 7 Apr 2022 04:58:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; 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06 Apr 2022 19:58:34 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Alvin Zhang , Kevin Liu Subject: [PATCH 08/39] net/ice: support dcf VLAN filter and offload configuration Date: Thu, 7 Apr 2022 10:56:35 +0000 Message-Id: <20220407105706.18889-9-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alvin Zhang Below PMD ops are supported in this patch: .vlan_filter_set = dcf_dev_vlan_filter_set .vlan_offload_set = dcf_dev_vlan_offload_set Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_dcf_ethdev.c | 101 +++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index 0d944f9fd2..e58cdf47d2 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -1026,6 +1026,105 @@ dcf_dev_set_default_mac_addr(struct rte_eth_dev *dev, return 0; } +static int +dcf_add_del_vlan(struct ice_dcf_hw *hw, uint16_t vlanid, bool add) +{ + struct virtchnl_vlan_filter_list *vlan_list; + uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) + + sizeof(uint16_t)]; + struct dcf_virtchnl_cmd args; + int err; + + vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer; + vlan_list->vsi_id = hw->vsi_res->vsi_id; + vlan_list->num_elements = 1; + vlan_list->vlan_id[0] = vlanid; + + memset(&args, 0, sizeof(args)); + args.v_op = add ? VIRTCHNL_OP_ADD_VLAN : VIRTCHNL_OP_DEL_VLAN; + args.req_msg = cmd_buffer; + args.req_msglen = sizeof(cmd_buffer); + err = ice_dcf_execute_virtchnl_cmd(hw, &args); + if (err) + PMD_DRV_LOG(ERR, "fail to execute command %s", + add ? "OP_ADD_VLAN" : "OP_DEL_VLAN"); + + return err; +} + +static int +dcf_enable_vlan_strip(struct ice_dcf_hw *hw) +{ + struct dcf_virtchnl_cmd args; + int ret; + + memset(&args, 0, sizeof(args)); + args.v_op = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING; + ret = ice_dcf_execute_virtchnl_cmd(hw, &args); + if (ret) + PMD_DRV_LOG(ERR, + "Failed to execute command of OP_ENABLE_VLAN_STRIPPING"); + + return ret; +} + +static int +dcf_disable_vlan_strip(struct ice_dcf_hw *hw) +{ + struct dcf_virtchnl_cmd args; + int ret; + + memset(&args, 0, sizeof(args)); + args.v_op = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING; + ret = ice_dcf_execute_virtchnl_cmd(hw, &args); + if (ret) + PMD_DRV_LOG(ERR, + "Failed to execute command of OP_DISABLE_VLAN_STRIPPING"); + + return ret; +} + +static int +dcf_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) +{ + struct ice_dcf_adapter *adapter = dev->data->dev_private; + struct ice_dcf_hw *hw = &adapter->real_hw; + int err; + + if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN)) + return -ENOTSUP; + + err = dcf_add_del_vlan(hw, vlan_id, on); + if (err) + return -EIO; + return 0; +} + +static int +dcf_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask) +{ + struct ice_dcf_adapter *adapter = dev->data->dev_private; + struct ice_dcf_hw *hw = &adapter->real_hw; + struct rte_eth_conf *dev_conf = &dev->data->dev_conf; + int err; + + if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN)) + return -ENOTSUP; + + /* Vlan stripping setting */ + if (mask & RTE_ETH_VLAN_STRIP_MASK) { + /* Enable or disable VLAN stripping */ + if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) + err = dcf_enable_vlan_strip(hw); + else + err = dcf_disable_vlan_strip(hw); + + if (err) + return -EIO; + } + return 0; +} + static int ice_dcf_dev_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops) @@ -1538,6 +1637,8 @@ static const struct eth_dev_ops ice_dcf_eth_dev_ops = { .mac_addr_remove = dcf_dev_del_mac_addr, .set_mc_addr_list = dcf_set_mc_addr_list, .mac_addr_set = dcf_dev_set_default_mac_addr, + .vlan_filter_set = dcf_dev_vlan_filter_set, + .vlan_offload_set = dcf_dev_vlan_offload_set, .flow_ops_get = ice_dcf_dev_flow_ops_get, .udp_tunnel_port_add = ice_dcf_dev_udp_tunnel_port_add, .udp_tunnel_port_del = ice_dcf_dev_udp_tunnel_port_del, From patchwork Thu Apr 7 10:56:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109361 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 042ECA0508; Thu, 7 Apr 2022 04:59:03 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4BCFB42835; Thu, 7 Apr 2022 04:58:43 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 721C44287F for ; Thu, 7 Apr 2022 04:58:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300321; x=1680836321; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=czQYGmqdwsiJjeNH0C2rD08JOg7Y4c6jT9LjqLzrkTE=; b=BFxa32t8tzs2bLifxh9am+SPti3+5UhnTU7fZuDGrkZplWyLp9KCSPUU 5otf2CbGTU8oxv6PQoujzvn1CyKcpNdMzzImmU4NL7a6VrPkce5Y7/ctf RPpq0T/mTUHnPi7hsMTJ+0By6j/5BevD/i6p7ncz+WeERzmmLaKm5TEXo 6XJX5Rm12YVgHgTzmDpW8NYt+VSzrUx/Z2XAZMrxsqWoFo3zeJejGjxKw ONveJ6nNCCtnMManKD/CWlZM6T2LQeBdauIPn6Oe7z080zvqvERBoqiXi xV6134Wr7GzG+JgcyKv+q+TN2EGT0mQQhb3G0Xzzd9Vk96CXfjFrCUJhc Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738347" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738347" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:41 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850523" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:38 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Alvin Zhang , Kevin Liu Subject: [PATCH 09/39] net/ice: support DCF new VLAN capabilities Date: Thu, 7 Apr 2022 10:56:36 +0000 Message-Id: <20220407105706.18889-10-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alvin Zhang The new VLAN virtchnl opcodes introduce new capabilities like VLAN filtering, stripping and insertion. The DCF needs to query the VLAN capabilities based on current device configuration firstly. DCF is able to configure inner VLAN filter when port VLAN is enabled base on negotiation; and DCF is able to configure outer VLAN (0x8100) if port VLAN is disabled to be compatible with legacy mode. When port VLAN is updated by DCF, the DCF needs to reset to query the new VLAN capabilities. Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_dcf.c | 27 +++++ drivers/net/ice/ice_dcf.h | 1 + drivers/net/ice/ice_dcf_ethdev.c | 171 ++++++++++++++++++++++++++++--- 3 files changed, 182 insertions(+), 17 deletions(-) diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c index 55ae68c456..885d58c0f4 100644 --- a/drivers/net/ice/ice_dcf.c +++ b/drivers/net/ice/ice_dcf.c @@ -587,6 +587,29 @@ ice_dcf_get_supported_rxdid(struct ice_dcf_hw *hw) return 0; } +static int +dcf_get_vlan_offload_caps_v2(struct ice_dcf_hw *hw) +{ + struct virtchnl_vlan_caps vlan_v2_caps; + struct dcf_virtchnl_cmd args; + int ret; + + memset(&args, 0, sizeof(args)); + args.v_op = VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS; + args.rsp_msgbuf = (uint8_t *)&vlan_v2_caps; + args.rsp_buflen = sizeof(vlan_v2_caps); + + ret = ice_dcf_execute_virtchnl_cmd(hw, &args); + if (ret) { + PMD_DRV_LOG(ERR, + "Failed to execute command of VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS"); + return ret; + } + + rte_memcpy(&hw->vlan_v2_caps, &vlan_v2_caps, sizeof(vlan_v2_caps)); + return 0; +} + int ice_dcf_init_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw) { @@ -701,6 +724,10 @@ ice_dcf_init_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw) rte_intr_enable(pci_dev->intr_handle); ice_dcf_enable_irq0(hw); + if ((hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) && + dcf_get_vlan_offload_caps_v2(hw)) + goto err_rss; + return 0; err_rss: diff --git a/drivers/net/ice/ice_dcf.h b/drivers/net/ice/ice_dcf.h index 78df202a77..32e6031bd9 100644 --- a/drivers/net/ice/ice_dcf.h +++ b/drivers/net/ice/ice_dcf.h @@ -107,6 +107,7 @@ struct ice_dcf_hw { uint16_t nb_msix; uint16_t rxq_map[16]; struct virtchnl_eth_stats eth_stats_offset; + struct virtchnl_vlan_caps vlan_v2_caps; /* Link status */ bool link_up; diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index e58cdf47d2..d4bfa182a4 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -1026,6 +1026,46 @@ dcf_dev_set_default_mac_addr(struct rte_eth_dev *dev, return 0; } +static int +dcf_add_del_vlan_v2(struct ice_dcf_hw *hw, uint16_t vlanid, bool add) +{ + struct virtchnl_vlan_supported_caps *supported_caps = + &hw->vlan_v2_caps.filtering.filtering_support; + struct virtchnl_vlan *vlan_setting; + struct virtchnl_vlan_filter_list_v2 vlan_filter; + struct dcf_virtchnl_cmd args; + uint32_t filtering_caps; + int err; + + if (supported_caps->outer) { + filtering_caps = supported_caps->outer; + vlan_setting = &vlan_filter.filters[0].outer; + } else { + filtering_caps = supported_caps->inner; + vlan_setting = &vlan_filter.filters[0].inner; + } + + if (!(filtering_caps & VIRTCHNL_VLAN_ETHERTYPE_8100)) + return -ENOTSUP; + + memset(&vlan_filter, 0, sizeof(vlan_filter)); + vlan_filter.vport_id = hw->vsi_res->vsi_id; + vlan_filter.num_elements = 1; + vlan_setting->tpid = RTE_ETHER_TYPE_VLAN; + vlan_setting->tci = vlanid; + + memset(&args, 0, sizeof(args)); + args.v_op = add ? VIRTCHNL_OP_ADD_VLAN_V2 : VIRTCHNL_OP_DEL_VLAN_V2; + args.req_msg = (uint8_t *)&vlan_filter; + args.req_msglen = sizeof(vlan_filter); + err = ice_dcf_execute_virtchnl_cmd(hw, &args); + if (err) + PMD_DRV_LOG(ERR, "fail to execute command %s", + add ? "OP_ADD_VLAN_V2" : "OP_DEL_VLAN_V2"); + + return err; +} + static int dcf_add_del_vlan(struct ice_dcf_hw *hw, uint16_t vlanid, bool add) { @@ -1052,6 +1092,116 @@ dcf_add_del_vlan(struct ice_dcf_hw *hw, uint16_t vlanid, bool add) return err; } +static int +dcf_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) +{ + struct ice_dcf_adapter *adapter = dev->data->dev_private; + struct ice_dcf_hw *hw = &adapter->real_hw; + int err; + + if (hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) { + err = dcf_add_del_vlan_v2(hw, vlan_id, on); + if (err) + return -EIO; + return 0; + } + + if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN)) + return -ENOTSUP; + + err = dcf_add_del_vlan(hw, vlan_id, on); + if (err) + return -EIO; + return 0; +} + +static void +dcf_iterate_vlan_filters_v2(struct rte_eth_dev *dev, bool enable) +{ + struct rte_vlan_filter_conf *vfc = &dev->data->vlan_filter_conf; + struct ice_dcf_adapter *adapter = dev->data->dev_private; + struct ice_dcf_hw *hw = &adapter->real_hw; + uint32_t i, j; + uint64_t ids; + + for (i = 0; i < RTE_DIM(vfc->ids); i++) { + if (vfc->ids[i] == 0) + continue; + + ids = vfc->ids[i]; + for (j = 0; ids != 0 && j < 64; j++, ids >>= 1) { + if (ids & 1) + dcf_add_del_vlan_v2(hw, 64 * i + j, enable); + } + } +} + +static int +dcf_config_vlan_strip_v2(struct ice_dcf_hw *hw, bool enable) +{ + struct virtchnl_vlan_supported_caps *stripping_caps = + &hw->vlan_v2_caps.offloads.stripping_support; + struct virtchnl_vlan_setting vlan_strip; + struct dcf_virtchnl_cmd args; + uint32_t *ethertype; + int ret; + + if ((stripping_caps->outer & VIRTCHNL_VLAN_ETHERTYPE_8100) && + (stripping_caps->outer & VIRTCHNL_VLAN_TOGGLE)) + ethertype = &vlan_strip.outer_ethertype_setting; + else if ((stripping_caps->inner & VIRTCHNL_VLAN_ETHERTYPE_8100) && + (stripping_caps->inner & VIRTCHNL_VLAN_TOGGLE)) + ethertype = &vlan_strip.inner_ethertype_setting; + else + return -ENOTSUP; + + memset(&vlan_strip, 0, sizeof(vlan_strip)); + vlan_strip.vport_id = hw->vsi_res->vsi_id; + *ethertype = VIRTCHNL_VLAN_ETHERTYPE_8100; + + memset(&args, 0, sizeof(args)); + args.v_op = enable ? VIRTCHNL_OP_ENABLE_VLAN_STRIPPING_V2 : + VIRTCHNL_OP_DISABLE_VLAN_STRIPPING_V2; + args.req_msg = (uint8_t *)&vlan_strip; + args.req_msglen = sizeof(vlan_strip); + ret = ice_dcf_execute_virtchnl_cmd(hw, &args); + if (ret) + PMD_DRV_LOG(ERR, "fail to execute command %s", + enable ? "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING_V2" : + "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING_V2"); + + return ret; +} + +static int +dcf_dev_vlan_offload_set_v2(struct rte_eth_dev *dev, int mask) +{ + struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; + struct ice_dcf_adapter *adapter = dev->data->dev_private; + struct ice_dcf_hw *hw = &adapter->real_hw; + bool enable; + int err; + + if (mask & RTE_ETH_VLAN_FILTER_MASK) { + enable = !!(rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER); + + dcf_iterate_vlan_filters_v2(dev, enable); + } + + if (mask & RTE_ETH_VLAN_STRIP_MASK) { + enable = !!(rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP); + + err = dcf_config_vlan_strip_v2(hw, enable); + /* If not support, the stripping is already disabled by PF */ + if (err == -ENOTSUP && !enable) + err = 0; + if (err) + return -EIO; + } + + return 0; +} + static int dcf_enable_vlan_strip(struct ice_dcf_hw *hw) { @@ -1084,30 +1234,17 @@ dcf_disable_vlan_strip(struct ice_dcf_hw *hw) return ret; } -static int -dcf_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) -{ - struct ice_dcf_adapter *adapter = dev->data->dev_private; - struct ice_dcf_hw *hw = &adapter->real_hw; - int err; - - if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN)) - return -ENOTSUP; - - err = dcf_add_del_vlan(hw, vlan_id, on); - if (err) - return -EIO; - return 0; -} - static int dcf_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask) { + struct rte_eth_conf *dev_conf = &dev->data->dev_conf; struct ice_dcf_adapter *adapter = dev->data->dev_private; struct ice_dcf_hw *hw = &adapter->real_hw; - struct rte_eth_conf *dev_conf = &dev->data->dev_conf; int err; + if (hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) + return dcf_dev_vlan_offload_set_v2(dev, mask); + if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN)) return -ENOTSUP; From patchwork Thu Apr 7 10:56:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109362 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BE7F1A0508; Thu, 7 Apr 2022 04:59:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4EF6F42883; Thu, 7 Apr 2022 04:58:45 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id DC4264287D for ; Thu, 7 Apr 2022 04:58:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300324; x=1680836324; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=soZEOlPaZDYWJK582B374G4S5rjpEAf/cO/hHvnfTro=; b=SY75HlzAEpey62evWrb96GDrUGzMb9RHWNpSjLIPt+QrLufuQohb0xNR ttRaP31Rz1SDx/ydC52RAWp5rgj/D0THenM23VHScGyKcoT1rZ2eS80C5 k5eyu9lKbG43+SIQ5ssi055waLRBg6wDiAyQNYNSJspTRsqnIfDuwrnyf Ibq+FKA3XGwq+73wYlxL5hjCdYs3KcSyohtxGIpozTfbnipKwTYmk0KLi t/amim0eOvTytyu3X1+t6/w+2N5wCL3WLdHOoD0Ra9ouJ0mXF1maozyUS i/KHAtacFHfSKYWmaE3iOnYhW0zkKZalZy77xKSPg7Tb/T/jUJWJ3z2Ie A==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738349" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738349" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:43 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850535" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:41 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Dapeng Yu , Kevin Liu Subject: [PATCH 10/39] net/ice: enable CVL DCF device reset API Date: Thu, 7 Apr 2022 10:56:37 +0000 Message-Id: <20220407105706.18889-11-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Dapeng Yu Enable CVL DCF device reset API. Signed-off-by: Dapeng Yu Signed-off-by: Kevin Liu --- drivers/net/ice/ice_dcf.c | 24 ++++++++++++++++++++++++ drivers/net/ice/ice_dcf.h | 1 + 2 files changed, 25 insertions(+) diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c index 885d58c0f4..9c2f13cf72 100644 --- a/drivers/net/ice/ice_dcf.c +++ b/drivers/net/ice/ice_dcf.c @@ -1163,3 +1163,27 @@ ice_dcf_add_del_all_mac_addr(struct ice_dcf_hw *hw, rte_free(list); return err; } + +int +ice_dcf_cap_reset(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw) +{ + int ret; + + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + + ice_dcf_disable_irq0(hw); + rte_intr_disable(intr_handle); + rte_intr_callback_unregister(intr_handle, ice_dcf_dev_interrupt_handler, + hw); + ret = ice_dcf_mode_disable(hw); + if (ret) + goto err; + ret = ice_dcf_get_vf_resource(hw); +err: + rte_intr_callback_register(intr_handle, ice_dcf_dev_interrupt_handler, + hw); + rte_intr_enable(intr_handle); + ice_dcf_enable_irq0(hw); + return ret; +} diff --git a/drivers/net/ice/ice_dcf.h b/drivers/net/ice/ice_dcf.h index 32e6031bd9..8cf17e7700 100644 --- a/drivers/net/ice/ice_dcf.h +++ b/drivers/net/ice/ice_dcf.h @@ -137,6 +137,7 @@ int ice_dcf_add_del_all_mac_addr(struct ice_dcf_hw *hw, uint8_t type); int ice_dcf_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete); +int ice_dcf_cap_reset(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw); void ice_dcf_tm_conf_init(struct rte_eth_dev *dev); void ice_dcf_tm_conf_uninit(struct rte_eth_dev *dev); int ice_dcf_replay_vf_bw(struct ice_dcf_hw *hw, uint16_t vf_id); From patchwork Thu Apr 7 10:56:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109363 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 62550A0508; Thu, 7 Apr 2022 04:59:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 533214285E; Thu, 7 Apr 2022 04:58:48 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id A887E410DD for ; Thu, 7 Apr 2022 04:58:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300326; x=1680836326; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ej+hNt6aRetaFtO6hTS6hPkvkACq5l0iXPnR186tnes=; b=ZiZ4kQYPLPBVsugu6DbLuzRwda57PF981crE3tU3xN1G9ss6snXjZNp0 wBQhLvxjji18KmzZNfhhn452hm0Ypnxlz65dBotJ7B0/idhn7aPna3WCS 6GjVpwWyXktFzRsTfSmcqdu2kHe0IdIc8wexawBAkgrNCmPLFixKRi2Ui 8ekbKFDUQJJ2tjhPv9C8huqoxgMclJDo7WD0+xS3s4zRhchkPKbiVfO8h WcbiJX6Y4RD/b6hbEwhnC4FmrNtaELgUpNAwUslmEgzdrXGM24cOyQNqD LVpiI5kb6VB/e4QFL37TKCL/zV/N7LW70E6oTlU7sxGR2jBYMPPJ9xyzp Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738353" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738353" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:46 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850559" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:43 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Junfeng Guo , Kevin Liu Subject: [PATCH 11/39] net/ice/base: add VXLAN support for switch filter Date: Thu, 7 Apr 2022 10:56:38 +0000 Message-Id: <20220407105706.18889-12-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Junfeng Guo 1. Add profile rule for VXLAN on Switch Filter, including pattern_eth_ipv4_udp_vxlan_any pattern_eth_ipv6_udp_vxlan_any pattern_eth_ipv4_udp_vxlan_eth_ipv4 pattern_eth_ipv4_udp_vxlan_eth_ipv6 pattern_eth_ipv6_udp_vxlan_eth_ipv4 pattern_eth_ipv6_udp_vxlan_eth_ipv6 2. Add common rule for VXLAN on Switch Filter, including +-----------------+-----------------------------------------------------+ | Pattern | Input Set | +-----------------+-----------------------------------------------------+ | ipv4_vxlan_ipv4 | vni, inner dmac, inner dst/src ip, outer dst/src ip | | ipv4_vxlan_ipv6 | vni, inner dmac, inner dst/src ip | | ipv6_vxlan_ipv4 | vni, inner dmac, inner dst/src ip | | ipv6_vxlan_ipv6 | vni, inner dmac, inner dst/src ip | +-----------------+-----------------------------------------------------+ Signed-off-by: Junfeng Guo Signed-off-by: Kevin Liu --- drivers/net/ice/base/ice_protocol_type.h | 6 + drivers/net/ice/base/ice_switch.c | 213 ++++++++++++++++++++++- drivers/net/ice/base/ice_switch.h | 12 ++ 3 files changed, 230 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index 0e6e5990be..d6332c5690 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -112,6 +112,12 @@ enum ice_sw_tunnel_type { ICE_SW_TUN_IPV6_NAT_T, ICE_SW_TUN_IPV4_L2TPV3, ICE_SW_TUN_IPV6_L2TPV3, + ICE_SW_TUN_PROFID_IPV4_VXLAN, + ICE_SW_TUN_PROFID_IPV4_VXLAN_IPV4, + ICE_SW_TUN_PROFID_IPV4_VXLAN_IPV6, + ICE_SW_TUN_PROFID_IPV6_VXLAN, + ICE_SW_TUN_PROFID_IPV6_VXLAN_IPV4, + ICE_SW_TUN_PROFID_IPV6_VXLAN_IPV6, ICE_SW_TUN_PROFID_IPV6_ESP, ICE_SW_TUN_PROFID_IPV6_AH, ICE_SW_TUN_PROFID_MAC_IPV6_L2TPV3, diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index d4cc664ad7..b0c50c8f40 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -228,6 +228,117 @@ static const u8 dummy_udp_tun_udp_packet[] = { 0x00, 0x08, 0x00, 0x00, }; +static const +struct ice_dummy_pkt_offsets dummy_udp_tun_ipv6_tcp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_UDP_OF, 34 }, + { ICE_VXLAN, 42 }, + { ICE_GENEVE, 42 }, + { ICE_VXLAN_GPE, 42 }, + { ICE_MAC_IL, 50 }, + { ICE_IPV6_IL, 64 }, + { ICE_TCP_IL, 104 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_udp_tun_ipv6_tcp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_OL 12 */ + + 0x45, 0x00, 0x00, 0x5a, /* ICE_IPV4_OFOS 14 */ + 0x00, 0x01, 0x00, 0x00, + 0x40, 0x11, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x12, 0xb5, /* ICE_UDP_OF 34 */ + 0x00, 0x46, 0x00, 0x00, + + 0x00, 0x00, 0x65, 0x58, /* ICE_VXLAN 42 */ + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x86, 0xdd, + + 0x60, 0x00, 0x00, 0x00, /* ICE_IPV4_IL 64 */ + 0x00, 0x00, 0x06, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 104 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x50, 0x02, 0x20, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const +struct ice_dummy_pkt_offsets dummy_udp_tun_ipv6_udp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_UDP_OF, 34 }, + { ICE_VXLAN, 42 }, + { ICE_GENEVE, 42 }, + { ICE_VXLAN_GPE, 42 }, + { ICE_MAC_IL, 50 }, + { ICE_IPV6_IL, 64 }, + { ICE_UDP_ILOS, 104 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_udp_tun_ipv6_udp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_OL 12 */ + + 0x45, 0x00, 0x00, 0x4e, /* ICE_IPV4_OFOS 14 */ + 0x00, 0x01, 0x00, 0x00, + 0x00, 0x11, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x12, 0xb5, /* ICE_UDP_OF 34 */ + 0x00, 0x3a, 0x00, 0x00, + + 0x00, 0x00, 0x65, 0x58, /* ICE_VXLAN 42 */ + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x86, 0xdd, + + 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_IL 64 */ + 0x00, 0x58, 0x11, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 104 */ + 0x00, 0x08, 0x00, 0x00, +}; + /* offset info for MAC + IPv4 + UDP dummy packet */ static const struct ice_dummy_pkt_offsets dummy_udp_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, @@ -2001,6 +2112,10 @@ static enum ice_sw_tunnel_type ice_get_tun_type_for_recipe(u8 rid, bool vlan) u8 gre_profile[12] = {13, 14, 15, 19, 20, 21, 28, 29, 30, 31, 32, 33}; u8 pppoe_profile[7] = {34, 35, 36, 37, 38, 39, 40}; u8 non_tun_profile[6] = {4, 5, 6, 7, 8, 9}; + bool ipv4_vxlan_ipv4_valid = false; + bool ipv4_vxlan_ipv6_valid = false; + bool ipv6_vxlan_ipv4_valid = false; + bool ipv6_vxlan_ipv6_valid = false; enum ice_sw_tunnel_type tun_type; u16 i, j, k, profile_num = 0; bool non_tun_valid = false; @@ -2022,8 +2137,17 @@ static enum ice_sw_tunnel_type ice_get_tun_type_for_recipe(u8 rid, bool vlan) } for (i = 0; i < 12; i++) { - if (vxlan_profile[i] == j) + if (vxlan_profile[i] == j) { vxlan_valid = true; + if (i < 3) + ipv4_vxlan_ipv4_valid = true; + else if (i < 6) + ipv6_vxlan_ipv4_valid = true; + else if (i < 9) + ipv4_vxlan_ipv6_valid = true; + else if (i < 12) + ipv6_vxlan_ipv6_valid = true; + } } for (i = 0; i < 7; i++) { @@ -2083,6 +2207,20 @@ static enum ice_sw_tunnel_type ice_get_tun_type_for_recipe(u8 rid, bool vlan) break; } } + if (tun_type == ICE_SW_TUN_VXLAN) { + if (ipv4_vxlan_ipv4_valid && ipv4_vxlan_ipv6_valid) + tun_type = ICE_SW_TUN_PROFID_IPV4_VXLAN; + else if (ipv6_vxlan_ipv4_valid && ipv6_vxlan_ipv6_valid) + tun_type = ICE_SW_TUN_PROFID_IPV6_VXLAN; + else if (ipv4_vxlan_ipv4_valid) + tun_type = ICE_SW_TUN_PROFID_IPV4_VXLAN_IPV4; + else if (ipv4_vxlan_ipv6_valid) + tun_type = ICE_SW_TUN_PROFID_IPV4_VXLAN_IPV6; + else if (ipv6_vxlan_ipv4_valid) + tun_type = ICE_SW_TUN_PROFID_IPV6_VXLAN_IPV4; + else if (ipv6_vxlan_ipv6_valid) + tun_type = ICE_SW_TUN_PROFID_IPV6_VXLAN_IPV6; + } if (profile_num == 1 && (flag_valid || non_tun_valid || pppoe_valid)) { for (j = 0; j < ICE_MAX_NUM_PROFILES; j++) { @@ -7496,6 +7634,12 @@ static bool ice_tun_type_match_word(enum ice_sw_tunnel_type tun_type, u16 *mask) case ICE_SW_TUN_VXLAN_GPE: case ICE_SW_TUN_GENEVE: case ICE_SW_TUN_VXLAN: + case ICE_SW_TUN_PROFID_IPV4_VXLAN: + case ICE_SW_TUN_PROFID_IPV4_VXLAN_IPV4: + case ICE_SW_TUN_PROFID_IPV4_VXLAN_IPV6: + case ICE_SW_TUN_PROFID_IPV6_VXLAN: + case ICE_SW_TUN_PROFID_IPV6_VXLAN_IPV4: + case ICE_SW_TUN_PROFID_IPV6_VXLAN_IPV6: case ICE_SW_TUN_NVGRE: case ICE_SW_TUN_UDP: case ICE_ALL_TUNNELS: @@ -7613,6 +7757,42 @@ ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo, case ICE_SW_TUN_PPPOE_IPV6_UDP: ice_set_bit(ICE_PROFID_PPPOE_IPV6_UDP, bm); return; + case ICE_SW_TUN_PROFID_IPV4_VXLAN: + ice_set_bit(ICE_PROFID_IPV4_TUN_M_IPV4_TCP, bm); + ice_set_bit(ICE_PROFID_IPV4_TUN_M_IPV4_UDP, bm); + ice_set_bit(ICE_PROFID_IPV4_TUN_M_IPV4_OTHER, bm); + ice_set_bit(ICE_PROFID_IPV4_TUN_M_IPV6_TCP, bm); + ice_set_bit(ICE_PROFID_IPV4_TUN_M_IPV6_UDP, bm); + ice_set_bit(ICE_PROFID_IPV4_TUN_M_IPV6_OTHER, bm); + return; + case ICE_SW_TUN_PROFID_IPV4_VXLAN_IPV4: + ice_set_bit(ICE_PROFID_IPV4_TUN_M_IPV4_TCP, bm); + ice_set_bit(ICE_PROFID_IPV4_TUN_M_IPV4_UDP, bm); + ice_set_bit(ICE_PROFID_IPV4_TUN_M_IPV4_OTHER, bm); + return; + case ICE_SW_TUN_PROFID_IPV4_VXLAN_IPV6: + ice_set_bit(ICE_PROFID_IPV4_TUN_M_IPV6_TCP, bm); + ice_set_bit(ICE_PROFID_IPV4_TUN_M_IPV6_UDP, bm); + ice_set_bit(ICE_PROFID_IPV4_TUN_M_IPV6_OTHER, bm); + return; + case ICE_SW_TUN_PROFID_IPV6_VXLAN: + ice_set_bit(ICE_PROFID_IPV6_TUN_M_IPV4_TCP, bm); + ice_set_bit(ICE_PROFID_IPV6_TUN_M_IPV4_UDP, bm); + ice_set_bit(ICE_PROFID_IPV6_TUN_M_IPV4_OTHER, bm); + ice_set_bit(ICE_PROFID_IPV6_TUN_M_IPV6_TCP, bm); + ice_set_bit(ICE_PROFID_IPV6_TUN_M_IPV6_UDP, bm); + ice_set_bit(ICE_PROFID_IPV6_TUN_M_IPV6_OTHER, bm); + return; + case ICE_SW_TUN_PROFID_IPV6_VXLAN_IPV4: + ice_set_bit(ICE_PROFID_IPV6_TUN_M_IPV4_TCP, bm); + ice_set_bit(ICE_PROFID_IPV6_TUN_M_IPV4_UDP, bm); + ice_set_bit(ICE_PROFID_IPV6_TUN_M_IPV4_OTHER, bm); + return; + case ICE_SW_TUN_PROFID_IPV6_VXLAN_IPV6: + ice_set_bit(ICE_PROFID_IPV6_TUN_M_IPV6_TCP, bm); + ice_set_bit(ICE_PROFID_IPV6_TUN_M_IPV6_UDP, bm); + ice_set_bit(ICE_PROFID_IPV6_TUN_M_IPV6_OTHER, bm); + return; case ICE_SW_TUN_PROFID_IPV6_ESP: case ICE_SW_TUN_IPV6_ESP: ice_set_bit(ICE_PROFID_IPV6_ESP, bm); @@ -7780,6 +7960,12 @@ bool ice_is_prof_rule(enum ice_sw_tunnel_type type) { switch (type) { case ICE_SW_TUN_AND_NON_TUN: + case ICE_SW_TUN_PROFID_IPV4_VXLAN: + case ICE_SW_TUN_PROFID_IPV4_VXLAN_IPV4: + case ICE_SW_TUN_PROFID_IPV4_VXLAN_IPV6: + case ICE_SW_TUN_PROFID_IPV6_VXLAN: + case ICE_SW_TUN_PROFID_IPV6_VXLAN_IPV4: + case ICE_SW_TUN_PROFID_IPV6_VXLAN_IPV6: case ICE_SW_TUN_PROFID_IPV6_ESP: case ICE_SW_TUN_PROFID_IPV6_AH: case ICE_SW_TUN_PROFID_MAC_IPV6_L2TPV3: @@ -8396,8 +8582,27 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, return; } + if (tun_type == ICE_SW_TUN_PROFID_IPV4_VXLAN_IPV6 || + tun_type == ICE_SW_TUN_PROFID_IPV6_VXLAN_IPV6) { + if (tcp) { + *pkt = dummy_udp_tun_ipv6_tcp_packet; + *pkt_len = sizeof(dummy_udp_tun_ipv6_tcp_packet); + *offsets = dummy_udp_tun_ipv6_tcp_packet_offsets; + return; + } + + *pkt = dummy_udp_tun_ipv6_udp_packet; + *pkt_len = sizeof(dummy_udp_tun_ipv6_udp_packet); + *offsets = dummy_udp_tun_ipv6_udp_packet_offsets; + return; + } + if (tun_type == ICE_SW_TUN_VXLAN || tun_type == ICE_SW_TUN_GENEVE || tun_type == ICE_SW_TUN_VXLAN_GPE || tun_type == ICE_SW_TUN_UDP || + tun_type == ICE_SW_TUN_PROFID_IPV4_VXLAN || + tun_type == ICE_SW_TUN_PROFID_IPV4_VXLAN_IPV4 || + tun_type == ICE_SW_TUN_PROFID_IPV6_VXLAN || + tun_type == ICE_SW_TUN_PROFID_IPV6_VXLAN_IPV4 || tun_type == ICE_SW_TUN_GENEVE_VLAN || tun_type == ICE_SW_TUN_VXLAN_VLAN) { if (tcp) { @@ -8613,6 +8818,12 @@ ice_fill_adv_packet_tun(struct ice_hw *hw, enum ice_sw_tunnel_type tun_type, case ICE_SW_TUN_AND_NON_TUN: case ICE_SW_TUN_VXLAN_GPE: case ICE_SW_TUN_VXLAN: + case ICE_SW_TUN_PROFID_IPV4_VXLAN: + case ICE_SW_TUN_PROFID_IPV4_VXLAN_IPV4: + case ICE_SW_TUN_PROFID_IPV4_VXLAN_IPV6: + case ICE_SW_TUN_PROFID_IPV6_VXLAN: + case ICE_SW_TUN_PROFID_IPV6_VXLAN_IPV4: + case ICE_SW_TUN_PROFID_IPV6_VXLAN_IPV6: case ICE_SW_TUN_VXLAN_VLAN: case ICE_SW_TUN_UDP: if (!ice_get_open_tunnel_port(hw, TNL_VXLAN, &open_port)) diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index a2b3c80107..efb9399b77 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -20,6 +20,18 @@ #define ICE_PROFID_IPV4_UDP 5 #define ICE_PROFID_IPV6_TCP 7 #define ICE_PROFID_IPV6_UDP 8 +#define ICE_PROFID_IPV4_TUN_M_IPV4_TCP 10 +#define ICE_PROFID_IPV4_TUN_M_IPV4_UDP 11 +#define ICE_PROFID_IPV4_TUN_M_IPV4_OTHER 12 +#define ICE_PROFID_IPV6_TUN_M_IPV4_TCP 16 +#define ICE_PROFID_IPV6_TUN_M_IPV4_UDP 17 +#define ICE_PROFID_IPV6_TUN_M_IPV4_OTHER 18 +#define ICE_PROFID_IPV4_TUN_M_IPV6_TCP 22 +#define ICE_PROFID_IPV4_TUN_M_IPV6_UDP 23 +#define ICE_PROFID_IPV4_TUN_M_IPV6_OTHER 24 +#define ICE_PROFID_IPV6_TUN_M_IPV6_TCP 25 +#define ICE_PROFID_IPV6_TUN_M_IPV6_UDP 26 +#define ICE_PROFID_IPV6_TUN_M_IPV6_OTHER 27 #define ICE_PROFID_PPPOE_PAY 34 #define ICE_PROFID_PPPOE_IPV4_TCP 35 #define ICE_PROFID_PPPOE_IPV4_UDP 36 From patchwork Thu Apr 7 10:56:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109364 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7BE58A0508; Thu, 7 Apr 2022 04:59:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CADCA42886; Thu, 7 Apr 2022 04:58:51 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 5126342886 for ; Thu, 7 Apr 2022 04:58:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300329; x=1680836329; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GypuUfHl5KQvgLq0XITj/gqSyLC9O1aub31sne0FyNQ=; b=WiKCxrDP+BfypISXz3Hev1owU1ygSoTdMFCltpouPrqimxTPvDMR2Q7h h4lc48zplZWweDm6w8yFHRd7vHQeILLW/EOzAlbhu9Z+9/TXeaTyVUHJy vp6gtJA9yArsKZS9FN6VncRVF7f1A0DTjTgySryBrCy4iPMMvbAmUYsn4 Yxlzn/EgKkQxTCvk6b9GLyisAfAttBaqXnj/R6Fsp+doyu0n3+XFedtAd s+VgWD1bCnCI2YEdkoWG/d3iH0qvleHLnF8fyd0gTl21oqWUf8JheTZ8s OpNXkuRZyUDeFmQjH3KE446V5kg7GOl/YQdJDM1ie8sj8nhWSViH7KJFu A==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738358" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738358" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:48 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850572" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:46 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Junfeng Guo , Kevin Liu Subject: [PATCH 12/39] net/ice: add VXLAN support for switch filter Date: Thu, 7 Apr 2022 10:56:39 +0000 Message-Id: <20220407105706.18889-13-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Junfeng Guo 1. Add profile rule for VXLAN on Switch Filter, including pattern_eth_ipv4_udp_vxlan_any pattern_eth_ipv6_udp_vxlan_any pattern_eth_ipv4_udp_vxlan_eth_ipv4 pattern_eth_ipv4_udp_vxlan_eth_ipv6 pattern_eth_ipv6_udp_vxlan_eth_ipv4 pattern_eth_ipv6_udp_vxlan_eth_ipv6 2. Add common rule for VXLAN on Switch Filter, including +-----------------+-----------------------------------------------------+ | Pattern | Input Set | +-----------------+-----------------------------------------------------+ | ipv4_vxlan_ipv4 | vni, inner dmac, inner dst/src ip, outer dst/src ip | | ipv4_vxlan_ipv6 | vni, inner dmac, inner dst/src ip | | ipv6_vxlan_ipv4 | vni, inner dmac, inner dst/src ip | | ipv6_vxlan_ipv6 | vni, inner dmac, inner dst/src ip | +-----------------+-----------------------------------------------------+ Signed-off-by: Junfeng Guo Signed-off-by: Kevin Liu --- drivers/net/ice/ice_generic_flow.c | 20 ++++++++++ drivers/net/ice/ice_generic_flow.h | 4 ++ drivers/net/ice/ice_switch_filter.c | 59 +++++++++++++++++++++++++++-- 3 files changed, 80 insertions(+), 3 deletions(-) diff --git a/drivers/net/ice/ice_generic_flow.c b/drivers/net/ice/ice_generic_flow.c index 53b1c0b69a..1433094ed4 100644 --- a/drivers/net/ice/ice_generic_flow.c +++ b/drivers/net/ice/ice_generic_flow.c @@ -375,6 +375,26 @@ enum rte_flow_item_type pattern_eth_ipv4_udp_vxlan_ipv4_icmp[] = { RTE_FLOW_ITEM_TYPE_END, }; +/* IPv4 VXLAN ANY */ +enum rte_flow_item_type pattern_eth_ipv4_udp_vxlan_any[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_VXLAN, + RTE_FLOW_ITEM_TYPE_ANY, + RTE_FLOW_ITEM_TYPE_END, +}; + +/* IPv6 VXLAN ANY */ +enum rte_flow_item_type pattern_eth_ipv6_udp_vxlan_any[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV6, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_VXLAN, + RTE_FLOW_ITEM_TYPE_ANY, + RTE_FLOW_ITEM_TYPE_END, +}; + /* IPv4 VXLAN MAC IPv4 */ enum rte_flow_item_type pattern_eth_ipv4_udp_vxlan_eth_ipv4[] = { RTE_FLOW_ITEM_TYPE_ETH, diff --git a/drivers/net/ice/ice_generic_flow.h b/drivers/net/ice/ice_generic_flow.h index 11f51a5c15..def7e2d6d6 100644 --- a/drivers/net/ice/ice_generic_flow.h +++ b/drivers/net/ice/ice_generic_flow.h @@ -175,6 +175,10 @@ extern enum rte_flow_item_type pattern_eth_ipv6_icmp6[]; extern enum rte_flow_item_type pattern_eth_vlan_ipv6_icmp6[]; extern enum rte_flow_item_type pattern_eth_qinq_ipv6_icmp6[]; +/* IPv4/IPv6 VXLAN ANY */ +extern enum rte_flow_item_type pattern_eth_ipv4_udp_vxlan_any[]; +extern enum rte_flow_item_type pattern_eth_ipv6_udp_vxlan_any[]; + /* IPv4 VXLAN IPv4 */ extern enum rte_flow_item_type pattern_eth_ipv4_udp_vxlan_ipv4[]; extern enum rte_flow_item_type pattern_eth_ipv4_udp_vxlan_ipv4_udp[]; diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c index 36c9bffb73..e90e109eca 100644 --- a/drivers/net/ice/ice_switch_filter.c +++ b/drivers/net/ice/ice_switch_filter.c @@ -85,6 +85,19 @@ #define ICE_SW_INSET_DIST_VXLAN_IPV4 ( \ ICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | ICE_INSET_DMAC | \ ICE_INSET_VXLAN_VNI) +#define ICE_SW_INSET_DIST_IPV4_VXLAN_IPV4 ( \ + ICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \ + ICE_INSET_DMAC | ICE_INSET_VXLAN_VNI | \ + ICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST) +#define ICE_SW_INSET_DIST_IPV4_VXLAN_IPV6 ( \ + ICE_INSET_DMAC | ICE_INSET_VXLAN_VNI | \ + ICE_INSET_IPV6_SRC | ICE_INSET_IPV6_DST) +#define ICE_SW_INSET_DIST_IPV6_VXLAN_IPV4 ( \ + ICE_INSET_DMAC | ICE_INSET_VXLAN_VNI | \ + ICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST) +#define ICE_SW_INSET_DIST_IPV6_VXLAN_IPV6 ( \ + ICE_INSET_DMAC | ICE_INSET_VXLAN_VNI | \ + ICE_INSET_IPV6_SRC | ICE_INSET_IPV6_DST) #define ICE_SW_INSET_DIST_NVGRE_IPV4_TCP ( \ ICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \ ICE_INSET_TCP_SRC_PORT | ICE_INSET_TCP_DST_PORT | \ @@ -112,6 +125,9 @@ ICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \ ICE_INSET_UDP_SRC_PORT | ICE_INSET_UDP_DST_PORT | \ ICE_INSET_IPV4_TOS) +#define ICE_SW_INSET_PERM_TUNNEL_IPV6 ( \ + ICE_INSET_IPV6_SRC | ICE_INSET_IPV6_DST | \ + ICE_INSET_IPV6_NEXT_HDR | ICE_INSET_IPV6_TC) #define ICE_SW_INSET_MAC_PPPOE ( \ ICE_INSET_VLAN_OUTER | ICE_INSET_VLAN_INNER | \ ICE_INSET_DMAC | ICE_INSET_ETHERTYPE | ICE_INSET_PPPOE_SESSION) @@ -217,9 +233,14 @@ ice_pattern_match_item ice_switch_pattern_dist_list[] = { {pattern_eth_ipv6, ICE_SW_INSET_MAC_IPV6, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv6_udp, ICE_SW_INSET_MAC_IPV6_UDP, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv6_tcp, ICE_SW_INSET_MAC_IPV6_TCP, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_ipv4_udp_vxlan_any, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_ipv6_udp_vxlan_any, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv4_udp_vxlan_eth_ipv4, ICE_INSET_IPV4_DST, ICE_SW_INSET_DIST_VXLAN_IPV4, ICE_INSET_NONE}, {pattern_eth_ipv4_udp_vxlan_eth_ipv4_udp, ICE_INSET_IPV4_DST, ICE_SW_INSET_DIST_VXLAN_IPV4_UDP, ICE_INSET_NONE}, {pattern_eth_ipv4_udp_vxlan_eth_ipv4_tcp, ICE_INSET_IPV4_DST, ICE_SW_INSET_DIST_VXLAN_IPV4_TCP, ICE_INSET_NONE}, + {pattern_eth_ipv4_udp_vxlan_eth_ipv6, ICE_SW_INSET_DIST_IPV4_VXLAN_IPV6, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_ipv6_udp_vxlan_eth_ipv4, ICE_SW_INSET_DIST_IPV6_VXLAN_IPV4, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_ipv6_udp_vxlan_eth_ipv6, ICE_SW_INSET_DIST_IPV6_VXLAN_IPV6, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv4_nvgre_eth_ipv4, ICE_INSET_IPV4_DST, ICE_SW_INSET_DIST_NVGRE_IPV4, ICE_INSET_NONE}, {pattern_eth_ipv4_nvgre_eth_ipv4_udp, ICE_INSET_IPV4_DST, ICE_SW_INSET_DIST_NVGRE_IPV4_UDP, ICE_INSET_NONE}, {pattern_eth_ipv4_nvgre_eth_ipv4_tcp, ICE_INSET_IPV4_DST, ICE_SW_INSET_DIST_NVGRE_IPV4_TCP, ICE_INSET_NONE}, @@ -301,9 +322,14 @@ ice_pattern_match_item ice_switch_pattern_perm_list[] = { {pattern_eth_ipv6, ICE_SW_INSET_MAC_IPV6, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv6_udp, ICE_SW_INSET_MAC_IPV6_UDP, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv6_tcp, ICE_SW_INSET_MAC_IPV6_TCP, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_ipv4_udp_vxlan_any, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_ipv6_udp_vxlan_any, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv4_udp_vxlan_eth_ipv4, ICE_INSET_NONE, ICE_SW_INSET_PERM_TUNNEL_IPV4, ICE_INSET_NONE}, {pattern_eth_ipv4_udp_vxlan_eth_ipv4_udp, ICE_INSET_NONE, ICE_SW_INSET_PERM_TUNNEL_IPV4_UDP, ICE_INSET_NONE}, {pattern_eth_ipv4_udp_vxlan_eth_ipv4_tcp, ICE_INSET_NONE, ICE_SW_INSET_PERM_TUNNEL_IPV4_TCP, ICE_INSET_NONE}, + {pattern_eth_ipv4_udp_vxlan_eth_ipv6, ICE_SW_INSET_DIST_IPV4_VXLAN_IPV6, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_ipv6_udp_vxlan_eth_ipv4, ICE_SW_INSET_DIST_IPV6_VXLAN_IPV4, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_ipv6_udp_vxlan_eth_ipv6, ICE_SW_INSET_DIST_IPV6_VXLAN_IPV6, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv4_nvgre_eth_ipv4, ICE_INSET_NONE, ICE_SW_INSET_PERM_TUNNEL_IPV4, ICE_INSET_NONE}, {pattern_eth_ipv4_nvgre_eth_ipv4_udp, ICE_INSET_NONE, ICE_SW_INSET_PERM_TUNNEL_IPV4_UDP, ICE_INSET_NONE}, {pattern_eth_ipv4_nvgre_eth_ipv4_tcp, ICE_INSET_NONE, ICE_SW_INSET_PERM_TUNNEL_IPV4_TCP, ICE_INSET_NONE}, @@ -566,6 +592,11 @@ ice_switch_parse_pattern(const struct rte_flow_item pattern[], bool inner_ipv6_valid = 0; bool inner_tcp_valid = 0; bool inner_udp_valid = 0; + bool ipv4_ipv4_valid = 0; + bool ipv4_ipv6_valid = 0; + bool ipv6_ipv4_valid = 0; + bool ipv6_ipv6_valid = 0; + bool any_valid = 0; uint16_t j, k, t = 0; if (*tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ || @@ -586,6 +617,7 @@ ice_switch_parse_pattern(const struct rte_flow_item pattern[], switch (item_type) { case RTE_FLOW_ITEM_TYPE_ANY: *tun_type = ICE_SW_TUN_AND_NON_TUN; + any_valid = 1; break; case RTE_FLOW_ITEM_TYPE_ETH: @@ -654,6 +686,10 @@ ice_switch_parse_pattern(const struct rte_flow_item pattern[], case RTE_FLOW_ITEM_TYPE_IPV4: ipv4_spec = item->spec; ipv4_mask = item->mask; + if (ipv4_valid) + ipv4_ipv4_valid = 1; + if (ipv6_valid) + ipv6_ipv4_valid = 1; if (tunnel_valid) { inner_ipv4_valid = 1; input = &inner_input_set; @@ -734,6 +770,10 @@ ice_switch_parse_pattern(const struct rte_flow_item pattern[], case RTE_FLOW_ITEM_TYPE_IPV6: ipv6_spec = item->spec; ipv6_mask = item->mask; + if (ipv4_valid) + ipv4_ipv6_valid = 1; + if (ipv6_valid) + ipv6_ipv6_valid = 1; if (tunnel_valid) { inner_ipv6_valid = 1; input = &inner_input_set; @@ -1577,9 +1617,7 @@ ice_switch_parse_pattern(const struct rte_flow_item pattern[], } if (*tun_type == ICE_NON_TUN) { - if (vxlan_valid) - *tun_type = ICE_SW_TUN_VXLAN; - else if (nvgre_valid) + if (nvgre_valid) *tun_type = ICE_SW_TUN_NVGRE; else if (ipv4_valid && tcp_valid) *tun_type = ICE_SW_IPV4_TCP; @@ -1591,6 +1629,21 @@ ice_switch_parse_pattern(const struct rte_flow_item pattern[], *tun_type = ICE_SW_IPV6_UDP; } + if (vxlan_valid) { + if (ipv4_ipv4_valid) + *tun_type = ICE_SW_TUN_PROFID_IPV4_VXLAN_IPV4; + else if (ipv4_ipv6_valid) + *tun_type = ICE_SW_TUN_PROFID_IPV4_VXLAN_IPV6; + else if (ipv6_ipv4_valid) + *tun_type = ICE_SW_TUN_PROFID_IPV6_VXLAN_IPV4; + else if (ipv6_ipv6_valid) + *tun_type = ICE_SW_TUN_PROFID_IPV6_VXLAN_IPV6; + else if (ipv6_valid && any_valid) + *tun_type = ICE_SW_TUN_PROFID_IPV6_VXLAN; + else if (ipv4_valid && any_valid) + *tun_type = ICE_SW_TUN_PROFID_IPV4_VXLAN; + } + if (input_set_byte > MAX_INPUT_SET_BYTE) { rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, From patchwork Thu Apr 7 10:56:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109365 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1A435A0508; Thu, 7 Apr 2022 04:59:26 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CBEBC4288E; Thu, 7 Apr 2022 04:58:53 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 476DC42889 for ; Thu, 7 Apr 2022 04:58:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300332; x=1680836332; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Eg+W1/VI+8uwinFV5UxZmP882/27WuMKR2L8a+fQOsw=; b=Qi324CTWSggJ+qQgU0Mku4HiJmHgR3nXVgV377phNsjap0sKMUxFw5kL gLlRb4duELBaejrqq7g+fbwMqgHwCGXzVgajOy0M6VidlMUgkhikRNXig MXxVfyE9uD9zKha4kD1t2QIkEfqnBcktr697zCyXcJDK7FqlL4JZ/Mhc7 jBWv2uda4GgVOwwGwDFwdwddp5IKjnvAcquSUOREYYOjsKxmWVN9CxkXU GhKt5ctGr+eN7zzkjCJPxHn4O/BZt9EUPwszsgR7OwPFFOirjPnCYYlA4 h+qn+nO+HTMFYC3rWEEbf+ZJ0rSdRr1C9YjMh4VY1n5/kGrs8IQ4gtTGI w==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738364" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738364" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:51 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850578" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:49 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Alvin Zhang , Steven Zou , Kevin Liu Subject: [PATCH 13/39] common/iavf: support flushing rules and reporting DCF id Date: Thu, 7 Apr 2022 10:56:40 +0000 Message-Id: <20220407105706.18889-14-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alvin Zhang Add virtual channel opcode for DCF flushing rules. Add virtual channel event for PF reporting DCF id. Signed-off-by: Steven Zou Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/common/iavf/virtchnl.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/common/iavf/virtchnl.h b/drivers/common/iavf/virtchnl.h index 3e44eca7d8..6e2a24b281 100644 --- a/drivers/common/iavf/virtchnl.h +++ b/drivers/common/iavf/virtchnl.h @@ -164,6 +164,12 @@ enum virtchnl_ops { VIRTCHNL_OP_ENABLE_QUEUES_V2 = 107, VIRTCHNL_OP_DISABLE_QUEUES_V2 = 108, VIRTCHNL_OP_MAP_QUEUE_VECTOR = 111, + + /** + * To reduce the risk for future combability issue, + * set VIRTCHNL_OP_DCF_RULE_FLUSH carefully by using a special value. + */ + VIRTCHNL_OP_DCF_RULE_FLUSH = 6000, VIRTCHNL_OP_MAX, }; @@ -1424,6 +1430,12 @@ enum virtchnl_event_codes { VIRTCHNL_EVENT_RESET_IMPENDING, VIRTCHNL_EVENT_PF_DRIVER_CLOSE, VIRTCHNL_EVENT_DCF_VSI_MAP_UPDATE, + + /** + * To reduce the risk for future combability issue, + * set VIRTCHNL_EVENT_DCF_VSI_INFO carefully by using a special value. + */ + VIRTCHNL_EVENT_DCF_VSI_INFO = 1000, }; #define PF_EVENT_SEVERITY_INFO 0 @@ -2200,6 +2212,7 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode, */ valid_len = msglen; break; + case VIRTCHNL_OP_DCF_RULE_FLUSH: case VIRTCHNL_OP_DCF_DISABLE: case VIRTCHNL_OP_DCF_GET_VSI_MAP: case VIRTCHNL_OP_DCF_GET_PKG_INFO: From patchwork Thu Apr 7 10:56:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109366 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6A0D8A0508; Thu, 7 Apr 2022 04:59:31 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DF9A741143; Thu, 7 Apr 2022 04:58:56 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id CDC7342877 for ; Thu, 7 Apr 2022 04:58:54 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300335; x=1680836335; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LV+q9yR0xTP+mFXIzBaBeeG/9OhtLKY9m3tE6qltvrM=; b=lnWdpgYXkwfxFjy6ILV9PcEfrt1H6d2tF1MrDTn9EFfEzDHfoJR57Gpf 6Lamla7Tp5RNJ3tZSTvH2uYEZOoy/iY/1fN4vu83wHsduuqxyQ4zkNS6Q FB2evV7sF1iF3I3O7HyaNFqNF4k7QRw8AJ7CowLvFkKy7ntUf/0y+MYj5 ZyhSmm5k2CIoC+dEWrqwaYV61G8N3+8RI2eOcwm7wJnE+Em7pUWC4StEG CnyNgACbL6nXYCBzD+TPWXA7C1nHaFtrW1kPeUsq7sEiuJhVFPLl7Pjx0 q8p4eHqjWZ3YNiigW90cMDgs8O6vqUbzdff7V8w/I4A6aRLXLe/jTaXGN g==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738368" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738368" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:54 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850586" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:52 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Alvin Zhang , Kevin Liu Subject: [PATCH 14/39] net/ice/base: fix ethertype filter input set Date: Thu, 7 Apr 2022 10:56:41 +0000 Message-Id: <20220407105706.18889-15-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alvin Zhang Add destination and source MAC as the input sets to ethertype filter. For example: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 type is 0x802 / end actions queue index 2 / end This flow will result in all the matched ingress packets be forwarded to queue 2. Fixes: 1f70fb3e958a ("net/ice/base: support flow director for non-IP packets") Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/base/ice_fdir.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index ae76361102..0a1d45a9d7 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -3935,6 +3935,9 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, input->ip.v6.dst_port); break; case ICE_FLTR_PTYPE_NON_IP_L2: + ice_pkt_insert_mac_addr(loc, input->ext_data.dst_mac); + ice_pkt_insert_mac_addr(loc + ETH_ALEN, + input->ext_data.src_mac); ice_pkt_insert_u16(loc, ICE_MAC_ETHTYPE_OFFSET, input->ext_data.ether_type); break; From patchwork Thu Apr 7 10:56:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109367 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4FF69A0509; Thu, 7 Apr 2022 04:59:36 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D577F42877; Thu, 7 Apr 2022 04:58:58 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id A59F242877 for ; Thu, 7 Apr 2022 04:58:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300337; x=1680836337; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Q8zu++if4OJIy2DXqid6J16Ii5Eb2G8jviGgZ00yUCA=; b=eis0SrQUyh9NOCEjDxhdihR5msbaPtIg20SaSuvRNe/3u++ZdUUfQjWl 9cDe9e+l5dNJVmiO1NjiuIOPBs7vZEXIhOeS9i4K2jh5ZIiyLM1pEYhwT dopQfJLpnr0i0rs8aqTl/e/7BJlbp6Yr/QpGjuk9wtmh8JnPT7lzPCT9o PTyBEbZ1lkujU0qaqSLhzaevv4THxamHhtHSoE5SFiknbPIyoMPbLyvML DWuL7hDs2U8vSrQNzMcn2MCyXWadZ2Mew5DRrlZAJjDOuaJlESB1r7ZbE 34KkBTEqmS956o3blAkKRz2zwZvk0xPUwi7Xhe4uBkhD6OXtL1pXxFDOE w==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738373" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738373" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:57 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850594" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:54 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Alvin Zhang , Steven Zou , Kevin Liu Subject: [PATCH 15/39] net/iavf: support checking if device is an MDCF instance Date: Thu, 7 Apr 2022 10:56:42 +0000 Message-Id: <20220407105706.18889-16-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alvin Zhang For an MDCF instance (with 'mdcf' in the parameter list), it should not be bound to iavf PMD. Signed-off-by: Steven Zou Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/iavf/iavf_ethdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c index d6190ac24a..afc1ee53e7 100644 --- a/drivers/net/iavf/iavf_ethdev.c +++ b/drivers/net/iavf/iavf_ethdev.c @@ -2678,7 +2678,7 @@ static int iavf_dcf_cap_check_handler(__rte_unused const char *key, const char *value, __rte_unused void *opaque) { - if (strcmp(value, "dcf")) + if (strcmp(value, "dcf") && strcmp(value, "mdcf")) return -1; return 0; From patchwork Thu Apr 7 10:56:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109368 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C0DF0A0508; Thu, 7 Apr 2022 04:59:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D8D11410DC; Thu, 7 Apr 2022 04:59:02 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 7D22B40689 for ; Thu, 7 Apr 2022 04:59:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300340; x=1680836340; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pWlrl1pDLJsmPPTKlt6Us8AQKvxvo9DooapIJpyowDM=; b=kzjiXzFF86bUBEEF/r/nzWC1T+7wCXQAbYUq11ffx9sItUAnIbad2fsC 4GzOPTkttjFrYLow9WJrPIe11LTMGl0voIyzi3bskqPZtZ8qcBpYYfz4e QpnQQ8rStwh48nWNwXgbKCczT+jlGw+TR4ExpmRm4Y/rceIsqYZa1Dd5g Yifv5I1Xzu8s5BJjbpAE0T5hE4LdHodSup+Oq775xK+voVZOlXa8yRzoj 8yhOCh21D3nsIvk06vr4AB74NO+DRHeTWRxd/+wg7AfyrZ73SGJ6s8Qhw O+7odfYTY5fViJKfrW3RrMxtTdDOz0c1/oHRGKXG48mZ8Hnm9GWwvkORE A==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738381" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738381" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:00 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850611" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:58:57 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Kevin Liu , Steven Zou , Alvin Zhang Subject: [PATCH 16/39] net/ice: support MDCF(multi-DCF) instance Date: Thu, 7 Apr 2022 10:56:43 +0000 Message-Id: <20220407105706.18889-17-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add MDCF flushing flow rule ops. Support parsing commandline device capability 'mdcf'. Support PF reporting current DCF id and disabling the DCF capability of an MDCF instance. Signed-off-by: Steven Zou Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_dcf.c | 23 ++++++- drivers/net/ice/ice_dcf.h | 3 + drivers/net/ice/ice_dcf_ethdev.c | 99 ++++++++++++++++------------- drivers/net/ice/ice_dcf_parent.c | 8 +++ drivers/net/ice/ice_generic_flow.c | 10 +++ drivers/net/ice/ice_switch_filter.c | 5 +- 6 files changed, 100 insertions(+), 48 deletions(-) diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c index 9c2f13cf72..7987b6261d 100644 --- a/drivers/net/ice/ice_dcf.c +++ b/drivers/net/ice/ice_dcf.c @@ -681,7 +681,8 @@ ice_dcf_init_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw) if (ice_dcf_get_vf_vsi_map(hw) < 0) { PMD_INIT_LOG(ERR, "Failed to get VF VSI map"); - ice_dcf_mode_disable(hw); + if (!hw->multi_inst) + ice_dcf_mode_disable(hw); goto err_alloc; } @@ -759,8 +760,8 @@ ice_dcf_uninit_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw) rte_intr_disable(intr_handle); rte_intr_callback_unregister(intr_handle, ice_dcf_dev_interrupt_handler, hw); - - ice_dcf_mode_disable(hw); + if (!hw->multi_inst) + ice_dcf_mode_disable(hw); iavf_shutdown_adminq(&hw->avf); rte_free(hw->arq_buf); @@ -1187,3 +1188,19 @@ ice_dcf_cap_reset(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw) ice_dcf_enable_irq0(hw); return ret; } + +int +ice_dcf_flush_rules(struct ice_dcf_hw *hw) +{ + struct dcf_virtchnl_cmd args; + int err = 0; + + memset(&args, 0, sizeof(args)); + args.v_op = VIRTCHNL_OP_DCF_RULE_FLUSH; + + err = ice_dcf_execute_virtchnl_cmd(hw, &args); + if (err) + PMD_DRV_LOG(WARNING, "fail to execute command OF_DCF_RULE_FLUSH, DCF role must be preempted."); + + return 0; +} diff --git a/drivers/net/ice/ice_dcf.h b/drivers/net/ice/ice_dcf.h index 8cf17e7700..42f4404a37 100644 --- a/drivers/net/ice/ice_dcf.h +++ b/drivers/net/ice/ice_dcf.h @@ -98,6 +98,8 @@ struct ice_dcf_hw { uint16_t vsi_id; struct rte_eth_dev *eth_dev; + bool multi_inst; + bool dcf_replaced; uint8_t *rss_lut; uint8_t *rss_key; uint64_t supported_rxdid; @@ -142,5 +144,6 @@ void ice_dcf_tm_conf_init(struct rte_eth_dev *dev); void ice_dcf_tm_conf_uninit(struct rte_eth_dev *dev); int ice_dcf_replay_vf_bw(struct ice_dcf_hw *hw, uint16_t vf_id); int ice_dcf_clear_bw(struct ice_dcf_hw *hw); +int ice_dcf_flush_rules(struct ice_dcf_hw *hw); #endif /* _ICE_DCF_H_ */ diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index d4bfa182a4..90787d8c49 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -19,6 +19,7 @@ #include #include #include +#include #include @@ -1788,12 +1789,66 @@ static const struct eth_dev_ops ice_dcf_eth_dev_ops = { .mtu_set = ice_dcf_dev_mtu_set, }; +static int +ice_dcf_cap_check_handler(__rte_unused const char *key, + const char *value, void *opaque) +{ + bool *mi = opaque; + + if (!strcmp(value, "dcf")) { + *mi = 0; + return 0; + } + if (!strcmp(value, "mdcf")) { + *mi = 1; + return 0; + } + + return -1; +} + +static int +ice_dcf_cap_selected(struct ice_dcf_adapter *adapter, + struct rte_devargs *devargs) +{ + struct ice_adapter *ad = &adapter->parent; + struct rte_kvargs *kvlist; + const char *key_cap = "cap"; + int ret = 0; + + if (devargs == NULL) + return 0; + + kvlist = rte_kvargs_parse(devargs->args, NULL); + if (kvlist == NULL) + return 0; + + if (!rte_kvargs_count(kvlist, key_cap)) + goto exit; + + /* dcf capability selected when there's a key-value pair: cap=dcf */ + if (rte_kvargs_process(kvlist, key_cap, + ice_dcf_cap_check_handler, + &adapter->real_hw.multi_inst) < 0) + goto exit; + + ret = 1; + +exit: + rte_kvargs_free(kvlist); + return ret; +} + static int ice_dcf_dev_init(struct rte_eth_dev *eth_dev) { + struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device); struct ice_dcf_adapter *adapter = eth_dev->data->dev_private; struct ice_adapter *parent_adapter = &adapter->parent; + if (!ice_dcf_cap_selected(adapter, pci_dev->device.devargs)) + return 1; + eth_dev->dev_ops = &ice_dcf_eth_dev_ops; eth_dev->rx_pkt_burst = ice_dcf_recv_pkts; eth_dev->tx_pkt_burst = ice_dcf_xmit_pkts; @@ -1829,45 +1884,6 @@ ice_dcf_dev_uninit(struct rte_eth_dev *eth_dev) return 0; } -static int -ice_dcf_cap_check_handler(__rte_unused const char *key, - const char *value, __rte_unused void *opaque) -{ - if (strcmp(value, "dcf")) - return -1; - - return 0; -} - -static int -ice_dcf_cap_selected(struct rte_devargs *devargs) -{ - struct rte_kvargs *kvlist; - const char *key = "cap"; - int ret = 0; - - if (devargs == NULL) - return 0; - - kvlist = rte_kvargs_parse(devargs->args, NULL); - if (kvlist == NULL) - return 0; - - if (!rte_kvargs_count(kvlist, key)) - goto exit; - - /* dcf capability selected when there's a key-value pair: cap=dcf */ - if (rte_kvargs_process(kvlist, key, - ice_dcf_cap_check_handler, NULL) < 0) - goto exit; - - ret = 1; - -exit: - rte_kvargs_free(kvlist); - return ret; -} - static int eth_ice_dcf_pci_probe(__rte_unused struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) @@ -1880,9 +1896,6 @@ eth_ice_dcf_pci_probe(__rte_unused struct rte_pci_driver *pci_drv, uint16_t dcf_vsi_id; int i, ret; - if (!ice_dcf_cap_selected(pci_dev->device.devargs)) - return 1; - ret = rte_eth_devargs_parse(pci_dev->device.devargs->args, ð_da); if (ret) return ret; @@ -1995,4 +2008,4 @@ static struct rte_pci_driver rte_ice_dcf_pmd = { RTE_PMD_REGISTER_PCI(net_ice_dcf, rte_ice_dcf_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_ice_dcf, pci_id_ice_dcf_map); RTE_PMD_REGISTER_KMOD_DEP(net_ice_dcf, "* igb_uio | vfio-pci"); -RTE_PMD_REGISTER_PARAM_STRING(net_ice_dcf, "cap=dcf"); +RTE_PMD_REGISTER_PARAM_STRING(net_ice_dcf, "cap=dcf|mdcf"); diff --git a/drivers/net/ice/ice_dcf_parent.c b/drivers/net/ice/ice_dcf_parent.c index 2f96dedcce..2aa69c7368 100644 --- a/drivers/net/ice/ice_dcf_parent.c +++ b/drivers/net/ice/ice_dcf_parent.c @@ -125,6 +125,9 @@ ice_dcf_vsi_update_service_handler(void *param) pthread_detach(pthread_self()); + if (hw->multi_inst) + return NULL; + rte_delay_us(ICE_DCF_VSI_UPDATE_SERVICE_INTERVAL); rte_spinlock_lock(&vsi_update_lock); @@ -269,6 +272,10 @@ ice_dcf_handle_pf_event_msg(struct ice_dcf_hw *dcf_hw, start_vsi_reset_thread(dcf_hw, true, pf_msg->event_data.vf_vsi_map.vf_id); break; + case VIRTCHNL_EVENT_DCF_VSI_INFO: + if (dcf_hw->vsi_id != pf_msg->event_data.vf_vsi_map.vsi_id) + dcf_hw->dcf_replaced = true; + break; default: PMD_DRV_LOG(ERR, "Unknown event received %u", pf_msg->event); break; @@ -436,6 +443,7 @@ ice_dcf_init_parent_adapter(struct rte_eth_dev *eth_dev) parent_hw->aq_send_cmd_fn = ice_dcf_send_aq_cmd; parent_hw->aq_send_cmd_param = &adapter->real_hw; parent_hw->dcf_enabled = true; + hw->dcf_replaced = false; err = ice_dcf_init_parent_hw(parent_hw); if (err) { diff --git a/drivers/net/ice/ice_generic_flow.c b/drivers/net/ice/ice_generic_flow.c index 1433094ed4..2ebe9a1cce 100644 --- a/drivers/net/ice/ice_generic_flow.c +++ b/drivers/net/ice/ice_generic_flow.c @@ -17,6 +17,7 @@ #include "ice_ethdev.h" #include "ice_generic_flow.h" +#include "ice_dcf.h" /** * Non-pipeline mode, fdir and switch both used as distributor, @@ -2533,10 +2534,16 @@ ice_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error) { struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + struct ice_adapter *ad = + ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + struct ice_dcf_hw *hw = ad->hw.aq_send_cmd_param; struct rte_flow *p_flow; void *temp; int ret = 0; + if (ad->hw.dcf_enabled && hw->dcf_replaced) + return ret; + RTE_TAILQ_FOREACH_SAFE(p_flow, &pf->flow_list, node, temp) { ret = ice_flow_destroy(dev, p_flow, error); if (ret) { @@ -2547,6 +2554,9 @@ ice_flow_flush(struct rte_eth_dev *dev, } } + if (ad->hw.dcf_enabled && hw->multi_inst) + return ice_dcf_flush_rules(ad->hw.aq_send_cmd_param); + return ret; } diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c index e90e109eca..1e8625e71e 100644 --- a/drivers/net/ice/ice_switch_filter.c +++ b/drivers/net/ice/ice_switch_filter.c @@ -497,6 +497,7 @@ ice_switch_destroy(struct ice_adapter *ad, struct rte_flow *flow, struct rte_flow_error *error) { + struct ice_dcf_hw *dcf_hw = ad->hw.aq_send_cmd_param; struct ice_hw *hw = &ad->hw; int ret; struct ice_switch_filter_conf *filter_conf_ptr; @@ -524,7 +525,7 @@ ice_switch_destroy(struct ice_adapter *ad, } ret = ice_rem_adv_rule_by_id(hw, &filter_conf_ptr->sw_query_data); - if (ret) { + if (ret && !(hw->dcf_enabled && dcf_hw->multi_inst)) { if (ice_dcf_adminq_need_retry(ad)) ret = -EAGAIN; else @@ -537,7 +538,7 @@ ice_switch_destroy(struct ice_adapter *ad, } ice_switch_filter_rule_free(flow); - return ret; + return 0; } static bool From patchwork Thu Apr 7 10:56:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109369 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 14D5EA0508; Thu, 7 Apr 2022 04:59:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 229C94289A; Thu, 7 Apr 2022 04:59:06 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id AB1F44288C for ; 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d="scan'208";a="570850623" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:00 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Alvin Zhang , Steven Zou , Kevin Liu Subject: [PATCH 17/39] net/ice/base: support custom DDP buildin recipe Date: Thu, 7 Apr 2022 10:56:44 +0000 Message-Id: <20220407105706.18889-18-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alvin Zhang Add control flag and data pointer for custom DDP package buildin recipe. Init the data pointer of buildin recipe. Support dumping buildin recipe lookup info. Signed-off-by: Steven Zou Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/base/ice_common.c | 25 +++++++++++++++ drivers/net/ice/base/ice_switch.c | 52 ++++++++++++++++++++++++++++++- drivers/net/ice/base/ice_type.h | 2 ++ 3 files changed, 78 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index db87bacd97..5d5ce894ff 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -732,6 +732,28 @@ ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); } +static int ice_buildin_recipe_init(struct ice_hw *hw) +{ + struct ice_switch_info *sw = hw->switch_info; + struct ice_sw_recipe *recipe; + + sw->buildin_recipes = ice_malloc(hw, + sizeof(sw->buildin_recipes[0]) * ICE_MAX_NUM_RECIPES); + + if (!sw->buildin_recipes) + return ICE_ERR_NO_MEMORY; + + recipe = &sw->buildin_recipes[10]; + recipe->is_root = 1; + + recipe->lkup_exts.n_val_words = 1; + recipe->lkup_exts.field_mask[0] = 0x00ff; + recipe->lkup_exts.fv_words[0].off = 8; + recipe->lkup_exts.fv_words[0].prot_id = 32; + + return ICE_SUCCESS; +} + /** * ice_init_fltr_mgmt_struct - initializes filter management list and locks * @hw: pointer to the HW struct @@ -752,6 +774,8 @@ enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) INIT_LIST_HEAD(&sw->vsi_list_map_head); sw->prof_res_bm_init = 0; + ice_buildin_recipe_init(hw); + status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list); if (status) { ice_free(hw, hw->switch_info); @@ -822,6 +846,7 @@ ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw) ice_free(hw, recps[i].root_buf); } ice_rm_sw_replay_rule_info(hw, sw); + ice_free(hw, sw->buildin_recipes); ice_free(hw, sw->recp_list); ice_free(hw, sw); } diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index b0c50c8f40..d9bb1e7c31 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -6910,6 +6910,47 @@ static struct ice_protocol_entry ice_prot_id_tbl[ICE_PROTOCOL_LAST] = { { ICE_VLAN_IN, ICE_VLAN_OL_HW }, }; +static u16 buildin_recipe_get(struct ice_switch_info *sw, + struct ice_prot_lkup_ext *lkup_exts) +{ + int i; + + if (!sw->buildin_recipes) + return ICE_MAX_NUM_RECIPES; + + for (i = 10; i < ICE_MAX_NUM_RECIPES; i++) { + struct ice_sw_recipe *recp = &sw->buildin_recipes[i]; + struct ice_fv_word *a = lkup_exts->fv_words; + struct ice_fv_word *b = recp->lkup_exts.fv_words; + u16 *c = recp->lkup_exts.field_mask; + u16 *d = lkup_exts->field_mask; + bool found = true; + u8 p, q; + + if (!recp->is_root) + continue; + + if (recp->lkup_exts.n_val_words != lkup_exts->n_val_words) + continue; + + for (p = 0; p < lkup_exts->n_val_words; p++) { + for (q = 0; q < recp->lkup_exts.n_val_words; q++) { + if (a[p].off == b[q].off && + a[p].prot_id == b[q].prot_id && + d[p] == c[q]) + break; + } + if (q >= recp->lkup_exts.n_val_words) { + found = false; + break; + } + } + if (found) + return i; + } + return ICE_MAX_NUM_RECIPES; +} + /** * ice_find_recp - find a recipe * @hw: pointer to the hardware structure @@ -6922,8 +6963,15 @@ static u16 ice_find_recp(struct ice_hw *hw, struct ice_prot_lkup_ext *lkup_exts, { bool refresh_required = true; struct ice_sw_recipe *recp; + u16 buildin_rid; u8 i; + if (hw->use_buildin_recipe) { + buildin_rid = buildin_recipe_get(hw->switch_info, lkup_exts); + if (buildin_rid < ICE_MAX_NUM_RECIPES) + return buildin_rid; + } + /* Walk through existing recipes to find a match */ recp = hw->switch_info->recp_list; for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { @@ -9457,8 +9505,10 @@ ice_rem_adv_rule_by_id(struct ice_hw *hw, struct ice_switch_info *sw; sw = hw->switch_info; - if (!sw->recp_list[remove_entry->rid].recp_created) + if (!sw->buildin_recipes[remove_entry->rid].is_root && + !sw->recp_list[remove_entry->rid].recp_created) return ICE_ERR_PARAM; + list_head = &sw->recp_list[remove_entry->rid].filt_rules; LIST_FOR_EACH_ENTRY(list_itr, list_head, ice_adv_fltr_mgmt_list_entry, list_entry) { diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index d81984633a..48144ea065 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -1107,6 +1107,7 @@ struct ice_switch_info { u16 max_used_prof_index; ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS); + struct ice_sw_recipe *buildin_recipes; }; /* Port hardware description */ @@ -1263,6 +1264,7 @@ struct ice_hw { ice_declare_bitmap(hw_ptype, ICE_FLOW_PTYPE_MAX); u8 dvm_ena; __le16 io_expander_handle; + u8 use_buildin_recipe; }; /* Statistics collected by each port, VSI, VEB, and S-channel */ From patchwork Thu Apr 7 10:56:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109370 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 777E5A0508; Thu, 7 Apr 2022 04:59:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 13CD64287C; Thu, 7 Apr 2022 04:59:09 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id EEFFE4289D for ; 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d="scan'208";a="570850636" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:03 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Alvin Zhang , Steven Zou , Kevin Liu Subject: [PATCH 18/39] net/ice: support buildin recipe configuration Date: Thu, 7 Apr 2022 10:56:45 +0000 Message-Id: <20220407105706.18889-19-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alvin Zhang Support parsing 'br'(buildin recipe) parameter in device parameter list. Signed-off-by: Steven Zou Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_dcf_ethdev.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index 90787d8c49..a165f74e26 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -1807,6 +1807,23 @@ ice_dcf_cap_check_handler(__rte_unused const char *key, return -1; } +static int +parse_bool(const char *key, const char *value, void *args) +{ + bool *i = (bool *)args; + int num = atoi(value); + + if (num != 0 && num != 1) { + PMD_DRV_LOG(WARNING, + "invalid value:\"%s\" for key:\"%s\", must be 0 or 1", + value, key); + return -1; + } + + *i = (bool)num; + return 0; +} + static int ice_dcf_cap_selected(struct ice_dcf_adapter *adapter, struct rte_devargs *devargs) @@ -1814,7 +1831,9 @@ ice_dcf_cap_selected(struct ice_dcf_adapter *adapter, struct ice_adapter *ad = &adapter->parent; struct rte_kvargs *kvlist; const char *key_cap = "cap"; + const char *key_br = "br"; int ret = 0; + bool br = 0; if (devargs == NULL) return 0; @@ -1832,6 +1851,11 @@ ice_dcf_cap_selected(struct ice_dcf_adapter *adapter, &adapter->real_hw.multi_inst) < 0) goto exit; + /* dcf capability selected when there's a key-value pair: cap=dcf */ + if (rte_kvargs_process(kvlist, key_br, parse_bool, &br) < 0) + goto exit; + + ad->hw.use_buildin_recipe = br; ret = 1; exit: @@ -2008,4 +2032,4 @@ static struct rte_pci_driver rte_ice_dcf_pmd = { RTE_PMD_REGISTER_PCI(net_ice_dcf, rte_ice_dcf_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_ice_dcf, pci_id_ice_dcf_map); RTE_PMD_REGISTER_KMOD_DEP(net_ice_dcf, "* igb_uio | vfio-pci"); -RTE_PMD_REGISTER_PARAM_STRING(net_ice_dcf, "cap=dcf|mdcf"); +RTE_PMD_REGISTER_PARAM_STRING(net_ice_dcf, "cap=dcf|mdcf br=<1|0>"); From patchwork Thu Apr 7 10:56:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109371 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 93F2CA0508; Thu, 7 Apr 2022 04:59:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0663D4289F; Thu, 7 Apr 2022 04:59:12 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 19EA54289F for ; Thu, 7 Apr 2022 04:59:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300350; x=1680836350; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DHWQFnnUiYAdYjxquHNla1sbWJGZHOrbQrtmZBWJcr4=; b=VaepG7y2qpPKmKWl1sBhRoaEagIZj4FW3nrgQlSO8GZ5JNQkPpQvLxCd 5lLXP2IsJLWRLeFD1GJBqhio0SHNdzZDnF13Rj9MAQnACBvfgjkGp1O2H civZYsUjIhpIwycYKrF+nwo9vK3mm15ItuDdd3eS8UcmHtNM5gYp0V6me otHHLx9EsTN5JDwDwTZsrQtEx/dsqfD45jxadHaEwFVxbS+jwOK/M6jLI KADzNe51aa2h9uciPqwxuuVh3UA0LwulwYKXz6n3d+Wgkmv+aUFtovkE3 F/BfPkKegTZPJz2j1LD7fcEWPdEvhuNkDkmMqr+i5PD9wHNxsKTLYQpcG Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738398" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738398" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:09 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850650" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:06 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Alvin Zhang , Junfeng Guo , Kevin Liu Subject: [PATCH 19/39] net/ice/base: support IPv6 GRE UDP pattern Date: Thu, 7 Apr 2022 10:56:46 +0000 Message-Id: <20220407105706.18889-20-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alvin Zhang Add supports(trainer packet and it's offsets, definitions, pattern matching) for IPv6 GRE UDP pattern. Signed-off-by: Junfeng Guo Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/base/ice_protocol_type.h | 1 + drivers/net/ice/base/ice_switch.c | 43 +++++++++++++++++++++++- 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index d6332c5690..eec9f27823 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -44,6 +44,7 @@ enum ice_protocol_type { ICE_GENEVE, ICE_VXLAN_GPE, ICE_NVGRE, + ICE_GRE, ICE_GTP, ICE_PPPOE, ICE_PFCP, diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index d9bb1e7c31..e3658117fc 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -12,6 +12,7 @@ #define ICE_MAX_VLAN_ID 0xFFF #define ICE_IPV6_ETHER_ID 0x86DD #define ICE_IPV4_NVGRE_PROTO_ID 0x002F +#define ICE_IPV6_GRE_PROTO_ID 0x002F #define ICE_PPP_IPV6_PROTO_ID 0x0057 #define ICE_TCP_PROTO_ID 0x06 #define ICE_GTPU_PROFILE 24 @@ -129,6 +130,34 @@ static const u8 dummy_gre_udp_packet[] = { 0x00, 0x08, 0x00, 0x00, }; +static const struct ice_dummy_pkt_offsets +dummy_ipv6_gre_udp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, + { ICE_IPV6_OFOS, 14 }, + { ICE_GRE, 54 }, + { ICE_IPV6_IL, 58 }, + { ICE_UDP_ILOS, 98 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_ipv6_gre_udp_packet[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00, + 0x00, 0x00, 0x00, 0x36, 0x2f, 0x40, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, + 0x86, 0xdd, 0x60, 0x00, 0x00, 0x00, 0x00, 0x0a, + 0x11, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, + 0xff, 0xd8, 0x00, 0x00, +}; + static const struct ice_dummy_pkt_offsets dummy_udp_tun_tcp_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, { ICE_ETYPE_OL, 12 }, @@ -8255,8 +8284,13 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, udp = true; else if (lkups[i].type == ICE_TCP_IL) tcp = true; - else if (lkups[i].type == ICE_IPV6_OFOS) + else if (lkups[i].type == ICE_IPV6_OFOS) { ipv6 = true; + if (lkups[i].h_u.ipv6_hdr.next_hdr == + ICE_IPV6_GRE_PROTO_ID && + lkups[i].m_u.ipv6_hdr.next_hdr == 0xFF) + gre = true; + } else if (lkups[i].type == ICE_VLAN_OFOS) vlan = true; else if (lkups[i].type == ICE_ETYPE_OL && @@ -8616,6 +8650,13 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, return; } + if (ipv6 && gre) { + *pkt = dummy_ipv6_gre_udp_packet; + *pkt_len = sizeof(dummy_ipv6_gre_udp_packet); + *offsets = dummy_ipv6_gre_udp_packet_offsets; + return; + } + if (tun_type == ICE_SW_TUN_NVGRE || gre) { if (tcp) { *pkt = dummy_gre_tcp_packet; From patchwork Thu Apr 7 10:56:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109372 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 78CE6A0508; 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a="248738402" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738402" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:12 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850658" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:09 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Alvin Zhang , Junfeng Guo , Kevin Liu Subject: [PATCH 20/39] net/ice: support IPv6 NVGRE tunnel Date: Thu, 7 Apr 2022 10:56:47 +0000 Message-Id: <20220407105706.18889-21-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alvin Zhang Add protocol definition and pattern matching for IPv6 NVGRE tunnel. Signed-off-by: Junfeng Guo Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_switch_filter.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c index 1e8625e71e..e87baa6234 100644 --- a/drivers/net/ice/ice_switch_filter.c +++ b/drivers/net/ice/ice_switch_filter.c @@ -31,6 +31,7 @@ #define ICE_PPP_IPV4_PROTO 0x0021 #define ICE_PPP_IPV6_PROTO 0x0057 #define ICE_IPV4_PROTO_NVGRE 0x002F +#define ICE_IPV6_PROTO_NVGRE 0x002F #define ICE_SW_PRI_BASE 6 #define ICE_SW_INSET_ETHER ( \ @@ -804,6 +805,10 @@ ice_switch_parse_pattern(const struct rte_flow_item pattern[], break; } } + if ((ipv6_spec->hdr.proto & + ipv6_mask->hdr.proto) == + ICE_IPV6_PROTO_NVGRE) + *tun_type = ICE_SW_TUN_AND_NON_TUN; if (ipv6_mask->hdr.proto) *input |= ICE_INSET_IPV6_NEXT_HDR; if (ipv6_mask->hdr.hop_limits) From patchwork Thu Apr 7 10:56:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109373 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 84A2BA0508; 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a="248738409" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738409" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:16 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850674" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:12 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Alvin Zhang , Junfeng Guo , Kevin Liu Subject: [PATCH 21/39] net/ice: support new pattern of IPv4 Date: Thu, 7 Apr 2022 10:56:48 +0000 Message-Id: <20220407105706.18889-22-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alvin Zhang Add definition and pattern entry for IPv4 pattern: MAC/VLAN/IPv4 Signed-off-by: Junfeng Guo Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_switch_filter.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c index e87baa6234..41086d7929 100644 --- a/drivers/net/ice/ice_switch_filter.c +++ b/drivers/net/ice/ice_switch_filter.c @@ -38,6 +38,8 @@ ICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_ETHERTYPE) #define ICE_SW_INSET_MAC_VLAN ( \ ICE_SW_INSET_ETHER | ICE_INSET_VLAN_INNER) +#define ICE_SW_INSET_MAC_VLAN_IPV4 ( \ + ICE_SW_INSET_MAC_VLAN | ICE_SW_INSET_MAC_IPV4) #define ICE_SW_INSET_MAC_QINQ ( \ ICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_VLAN_INNER | \ ICE_INSET_VLAN_OUTER) @@ -231,6 +233,7 @@ ice_pattern_match_item ice_switch_pattern_dist_list[] = { {pattern_eth_ipv4, ICE_SW_INSET_MAC_IPV4, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv4_udp, ICE_SW_INSET_MAC_IPV4_UDP, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv4_tcp, ICE_SW_INSET_MAC_IPV4_TCP, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_vlan_ipv4, ICE_SW_INSET_MAC_VLAN_IPV4, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv6, ICE_SW_INSET_MAC_IPV6, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv6_udp, ICE_SW_INSET_MAC_IPV6_UDP, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv6_tcp, ICE_SW_INSET_MAC_IPV6_TCP, ICE_INSET_NONE, ICE_INSET_NONE}, From patchwork Thu Apr 7 10:56:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109374 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B9947A0508; Thu, 7 Apr 2022 05:00:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DEB00428A2; Thu, 7 Apr 2022 04:59:19 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 15787428A5 for ; Thu, 7 Apr 2022 04:59:18 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300359; x=1680836359; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tAqQmeTbcGdnvbt9sinf9be0uX4+y/29qD1w3zzNFT4=; b=lA1Fhz8VZMAeNWdDwhTLoSodJO4cVwF6OO3QnQ0AqoEEiDxiVFVLEYK8 N6LGbXOcDpKfnWuXjdkr1vK8okRBTdMVTyBSy0LDGblFEqTFolR2aMRM3 1cL5vOICBKGu8EaaKU4OP9RhFrPghNiyTldKS8k5evhOwjNDizVe+mPun QoMo8dz3Fdudc1EZHb5+bXHd6dVYYcesfrHPzpCEDZZAR2LgSDv03Iw4I oXlSMy1jy16LpWSEqhzxfcAGa32Sr+CJypjYxVh0z403hmiUfPhDRwJdn YkqjMxs/4+3XaEGuoOqxoYHlKszseoraHqIMCv2keGR0mmezNgnyTwyU0 Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738414" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738414" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:18 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850685" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:16 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Alvin Zhang , Junfeng Guo , Kevin Liu Subject: [PATCH 22/39] net/ice/base: support new patterns of TCP and UDP Date: Thu, 7 Apr 2022 10:56:49 +0000 Message-Id: <20220407105706.18889-23-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alvin Zhang Find training packets for below TCP and UDP patterns: MAC/VLAN/IPv4/TCP MAC/VLAN/IPv4/UDP Signed-off-by: Junfeng Guo Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/base/ice_switch.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index e3658117fc..75cc861e93 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -8616,6 +8616,12 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, } if (tun_type == ICE_SW_IPV4_TCP) { + if (vlan && tcp) { + *pkt = dummy_vlan_tcp_packet; + *pkt_len = sizeof(dummy_vlan_tcp_packet); + *offsets = dummy_vlan_tcp_packet_offsets; + return; + } *pkt = dummy_tcp_packet; *pkt_len = sizeof(dummy_tcp_packet); *offsets = dummy_tcp_packet_offsets; @@ -8623,6 +8629,12 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, } if (tun_type == ICE_SW_IPV4_UDP) { + if (vlan && udp) { + *pkt = dummy_vlan_udp_packet; + *pkt_len = sizeof(dummy_vlan_udp_packet); + *offsets = dummy_vlan_udp_packet_offsets; + return; + } *pkt = dummy_udp_packet; *pkt_len = sizeof(dummy_udp_packet); *offsets = dummy_udp_packet_offsets; From patchwork Thu Apr 7 10:56:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109375 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D3290A0508; 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a="248738421" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738421" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:21 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850692" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:18 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Alvin Zhang , Junfeng Guo , Kevin Liu Subject: [PATCH 23/39] net/ice: support new patterns of TCP and UDP Date: Thu, 7 Apr 2022 10:56:50 +0000 Message-Id: <20220407105706.18889-24-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alvin Zhang Add definitions and pattern entries for below TCP and UDP patterns: MAC/VLAN/IPv4/TCP MAC/VLAN/IPv4/UDP Signed-off-by: Junfeng Guo Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_switch_filter.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c index 41086d7929..7c2038d089 100644 --- a/drivers/net/ice/ice_switch_filter.c +++ b/drivers/net/ice/ice_switch_filter.c @@ -62,6 +62,10 @@ ICE_INSET_DMAC | ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \ ICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS | \ ICE_INSET_UDP_DST_PORT | ICE_INSET_UDP_SRC_PORT) +#define ICE_SW_INSET_MAC_VLAN_IPV4_TCP ( \ + ICE_SW_INSET_MAC_VLAN | ICE_SW_INSET_MAC_IPV4_TCP) +#define ICE_SW_INSET_MAC_VLAN_IPV4_UDP ( \ + ICE_SW_INSET_MAC_VLAN | ICE_SW_INSET_MAC_IPV4_UDP) #define ICE_SW_INSET_MAC_IPV6 ( \ ICE_INSET_DMAC | ICE_INSET_IPV6_DST | ICE_INSET_IPV6_SRC | \ ICE_INSET_IPV6_TC | ICE_INSET_IPV6_HOP_LIMIT | \ @@ -234,6 +238,8 @@ ice_pattern_match_item ice_switch_pattern_dist_list[] = { {pattern_eth_ipv4_udp, ICE_SW_INSET_MAC_IPV4_UDP, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv4_tcp, ICE_SW_INSET_MAC_IPV4_TCP, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_vlan_ipv4, ICE_SW_INSET_MAC_VLAN_IPV4, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_vlan_ipv4_tcp, ICE_SW_INSET_MAC_VLAN_IPV4_TCP, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_vlan_ipv4_udp, ICE_SW_INSET_MAC_VLAN_IPV4_UDP, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv6, ICE_SW_INSET_MAC_IPV6, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv6_udp, ICE_SW_INSET_MAC_IPV6_UDP, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv6_tcp, ICE_SW_INSET_MAC_IPV6_TCP, ICE_INSET_NONE, ICE_INSET_NONE}, From patchwork Thu Apr 7 10:56:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109376 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4BDB3A0508; Thu, 7 Apr 2022 05:00:31 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6A616428A6; Thu, 7 Apr 2022 04:59:27 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 08F69428AE for ; Thu, 7 Apr 2022 04:59:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300365; x=1680836365; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PuW1A2FUPOjO0lG5ezS2JEI5Ekw4aShuPIDSEJh7nDM=; b=Xw9p6Vs1Kdy1ujcrdl8nku0ZZw4H0uh10/5iOpWfhzStQbs3T84AiV1B inmtwLM2WSp09CuRS78aCbE3AZq8hu9aJwzim131LeteSOopq4rP1yAR5 EWuL3oHEw7PCmMRqCM9VG2U6HTc5Wmmmt2DLlQMbLlA8M8w5OB94wFuOS aGVyokdp2JLhlpGHWnhmGUjG1kVb0KULN8iJvJqwRA1zFdql/6rQKPlqU WfaSCxxDjtxKTilabbtR7Yze7N0DKNnodiNp/RjNyJc/CNyZypxTbZMDA O+sfo6jiNum/7VTRNsTstMGCoNmqUju9TqD0h6gBfBwzS32BOrQo3D8cO Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738427" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738427" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:24 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850712" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:22 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Alvin Zhang , Junfeng Guo , Kevin Liu Subject: [PATCH 24/39] net/ice/base: support IPv4 GRE tunnel Date: Thu, 7 Apr 2022 10:56:51 +0000 Message-Id: <20220407105706.18889-25-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alvin Zhang Add definitions, trainer packets and routine path for IPv4 GRE tunnel. Ref: https://www.ietf.org/rfc/rfc1701.html Signed-off-by: Junfeng Guo Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/base/ice_flex_pipe.c | 37 ++- drivers/net/ice/base/ice_flex_pipe.h | 3 +- drivers/net/ice/base/ice_protocol_type.h | 15 ++ drivers/net/ice/base/ice_switch.c | 304 ++++++++++++++++++++++- 4 files changed, 332 insertions(+), 27 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index f6a29f87c5..8672c41c69 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -1851,6 +1851,7 @@ ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type req_profs, * @ids_cnt: lookup/protocol count * @bm: bitmap of field vectors to consider * @fv_list: Head of a list + * @lkup_exts: lookup elements * * Finds all the field vector entries from switch block that contain * a given protocol ID and returns a list of structures of type @@ -1861,7 +1862,8 @@ ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type req_profs, */ enum ice_status ice_get_sw_fv_list(struct ice_hw *hw, u8 *prot_ids, u16 ids_cnt, - ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list) + ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list, + struct ice_prot_lkup_ext *lkup_exts) { struct ice_sw_fv_list_entry *fvl; struct ice_sw_fv_list_entry *tmp; @@ -1892,29 +1894,26 @@ ice_get_sw_fv_list(struct ice_hw *hw, u8 *prot_ids, u16 ids_cnt, if (!ice_is_bit_set(bm, (u16)offset)) continue; - for (i = 0; i < ids_cnt; i++) { + int found = 1; + for (i = 0; i < lkup_exts->n_val_words; i++) { int j; - /* This code assumes that if a switch field vector line - * has a matching protocol, then this line will contain - * the entries necessary to represent every field in - * that protocol header. - */ for (j = 0; j < hw->blk[ICE_BLK_SW].es.fvw; j++) - if (fv->ew[j].prot_id == prot_ids[i]) + if (fv->ew[j].prot_id == + lkup_exts->fv_words[i].prot_id && + fv->ew[j].off == lkup_exts->fv_words[i].off) break; if (j >= hw->blk[ICE_BLK_SW].es.fvw) - break; - if (i + 1 == ids_cnt) { - fvl = (struct ice_sw_fv_list_entry *) - ice_malloc(hw, sizeof(*fvl)); - if (!fvl) - goto err; - fvl->fv_ptr = fv; - fvl->profile_id = offset; - LIST_ADD(&fvl->list_entry, fv_list); - break; - } + found = 0; + } + if (found) { + fvl = (struct ice_sw_fv_list_entry *) + ice_malloc(hw, sizeof(*fvl)); + if (!fvl) + goto err; + fvl->fv_ptr = fv; + fvl->profile_id = offset; + LIST_ADD(&fvl->list_entry, fv_list); } } while (fv); if (LIST_EMPTY(fv_list)) diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h index 23ba45564a..a22d66f3cf 100644 --- a/drivers/net/ice/base/ice_flex_pipe.h +++ b/drivers/net/ice/base/ice_flex_pipe.h @@ -37,7 +37,8 @@ void ice_init_prof_result_bm(struct ice_hw *hw); enum ice_status ice_get_sw_fv_list(struct ice_hw *hw, u8 *prot_ids, u16 ids_cnt, - ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list); + ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list, + struct ice_prot_lkup_ext *lkup_exts); enum ice_status ice_pkg_buf_unreserve_section(struct ice_buf_build *bld, u16 count); u16 ice_pkg_buf_get_free_space(struct ice_buf_build *bld); diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index eec9f27823..ffd34606e0 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -67,6 +67,7 @@ enum ice_sw_tunnel_type { ICE_SW_TUN_VXLAN, /* VXLAN matches only non-VLAN pkts */ ICE_SW_TUN_VXLAN_VLAN, /* VXLAN matches both VLAN and non-VLAN pkts */ ICE_SW_TUN_NVGRE, + ICE_SW_TUN_GRE, ICE_SW_TUN_UDP, /* This means all "UDP" tunnel types: VXLAN-GPE, VXLAN * and GENEVE */ @@ -231,6 +232,10 @@ enum ice_prot_id { #define ICE_TUN_FLAG_VLAN_MASK 0x01 #define ICE_TUN_FLAG_FV_IND 2 +#define ICE_GRE_FLAG_MDID 22 +#define ICE_GRE_FLAG_MDID_OFF (ICE_MDID_SIZE * ICE_GRE_FLAG_MDID) +#define ICE_GRE_FLAG_MASK 0x01C0 + #define ICE_PROTOCOL_MAX_ENTRIES 16 /* Mapping of software defined protocol ID to hardware defined protocol ID */ @@ -371,6 +376,15 @@ struct ice_nvgre { __be32 tni_flow; }; +struct ice_gre { + __be16 flags; + __be16 protocol; + __be16 chksum; + __be16 offset; + __be32 key; + __be32 seqnum; +}; + union ice_prot_hdr { struct ice_ether_hdr eth_hdr; struct ice_ethtype_hdr ethertype; @@ -381,6 +395,7 @@ union ice_prot_hdr { struct ice_sctp_hdr sctp_hdr; struct ice_udp_tnl_hdr tnl_hdr; struct ice_nvgre nvgre_hdr; + struct ice_gre gre_hdr; struct ice_udp_gtp_hdr gtp_hdr; struct ice_pppoe_hdr pppoe_hdr; struct ice_pfcp_hdr pfcp_hdr; diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 75cc861e93..b367efaf02 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -12,6 +12,7 @@ #define ICE_MAX_VLAN_ID 0xFFF #define ICE_IPV6_ETHER_ID 0x86DD #define ICE_IPV4_NVGRE_PROTO_ID 0x002F +#define ICE_IPV4_GRE_PROTO_ID 0x002F #define ICE_IPV6_GRE_PROTO_ID 0x002F #define ICE_PPP_IPV6_PROTO_ID 0x0057 #define ICE_TCP_PROTO_ID 0x06 @@ -158,6 +159,188 @@ static const u8 dummy_ipv6_gre_udp_packet[] = { 0xff, 0xd8, 0x00, 0x00, }; +static const struct ice_dummy_pkt_offsets +dummy_gre_rfc1701_c1k1_tcp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_GRE, 34 }, + { ICE_IPV4_IL, 50 }, + { ICE_TCP_IL, 70 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_gre_rfc1701_c1k1_tcp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_OL 12 */ + + 0x45, 0x00, 0x00, 0x4e, /* ICE_IPV4_OFOS 14 */ + 0x00, 0x01, 0x00, 0x00, + 0x40, 0x2f, 0x7c, 0x7e, + 0x7f, 0x00, 0x00, 0x01, + 0x7f, 0x00, 0x00, 0x01, + + 0xb0, 0x00, 0x08, 0x00, /* ICE_GRE 34 */ + 0x46, 0x1e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x45, 0x00, 0x00, 0x2a, /* ICE_IPV4_IL 50 */ + 0x00, 0x01, 0x00, 0x00, + 0x40, 0x06, 0x7c, 0xcb, + 0x7f, 0x00, 0x00, 0x01, + 0x7f, 0x00, 0x00, 0x01, + + 0x00, 0x14, 0x00, 0x50, /* ICE_TCP_IL 70 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x50, 0x02, 0x20, 0x00, + 0x91, 0x7a, 0x00, 0x00, + + 0x00, 0x00, +}; + +static const struct ice_dummy_pkt_offsets +dummy_gre_rfc1701_c1k1_udp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_GRE, 34 }, + { ICE_IPV4_IL, 50 }, + { ICE_UDP_ILOS, 70 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_gre_rfc1701_c1k1_udp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_OL 12 */ + + 0x45, 0x00, 0x00, 0x42, /* ICE_IPV4_OFOS 14 */ + 0x00, 0x01, 0x00, 0x00, + 0x40, 0x2f, 0x7c, 0x8a, + 0x7f, 0x00, 0x00, 0x01, + 0x7f, 0x00, 0x00, 0x01, + + 0xb0, 0x00, 0x08, 0x00, /* ICE_GRE 34 */ + 0x46, 0x1d, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x45, 0x00, 0x00, 0x1e, /* ICE_IPV4_IL 50 */ + 0x00, 0x01, 0x00, 0x00, + 0x40, 0x11, 0x7c, 0xcc, + 0x7f, 0x00, 0x00, 0x01, + 0x7f, 0x00, 0x00, 0x01, + + 0x00, 0x35, 0x00, 0x35, /* ICE_UDP_ILOS 70 */ + 0x00, 0x0a, 0x01, 0x6e, + + 0x00, 0x00, +}; + +static const struct ice_dummy_pkt_offsets +dummy_gre_rfc1701_c0k1_tcp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_GRE, 34 }, + { ICE_IPV4_IL, 46 }, + { ICE_TCP_IL, 66 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_gre_rfc1701_c0k1_tcp_packet[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x4a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f, + 0x7c, 0x82, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00, + 0x00, 0x01, 0x30, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, + 0x00, 0x2a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06, + 0x7c, 0xcb, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00, + 0x00, 0x01, 0x00, 0x14, 0x00, 0x50, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02, + 0x20, 0x00, 0x91, 0x7a, 0x00, 0x00, 0x00, 0x00, +}; + +static const struct ice_dummy_pkt_offsets +dummy_gre_rfc1701_c0k1_udp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_GRE, 34 }, + { ICE_IPV4_IL, 46 }, + { ICE_UDP_ILOS, 66 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_gre_rfc1701_c0k1_udp_packet[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x3e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f, + 0x7c, 0x8e, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00, + 0x00, 0x01, 0x30, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, + 0x00, 0x1e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11, + 0x7c, 0xcc, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00, + 0x00, 0x01, 0x00, 0x35, 0x00, 0x35, 0x00, 0x0a, + 0x01, 0x6e, 0x00, 0x00, +}; + +static const struct ice_dummy_pkt_offsets +dummy_gre_rfc1701_c0k0_tcp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_GRE, 34 }, + { ICE_IPV4_IL, 42 }, + { ICE_TCP_IL, 62 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_gre_rfc1701_c0k0_tcp_packet[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x46, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f, + 0x7c, 0x86, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00, + 0x00, 0x01, 0x10, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x45, 0x00, 0x00, 0x2a, 0x00, 0x01, + 0x00, 0x00, 0x40, 0x06, 0x7c, 0xcb, 0x7f, 0x00, + 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x14, + 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x50, 0x02, 0x20, 0x00, 0x91, 0x7a, + 0x00, 0x00, 0x00, 0x00, +}; + +static const struct ice_dummy_pkt_offsets +dummy_gre_rfc1701_c0k0_udp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_GRE, 34 }, + { ICE_IPV4_IL, 42 }, + { ICE_UDP_ILOS, 62 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_gre_rfc1701_c0k0_udp_packet[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x3a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x2f, + 0x7c, 0x92, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00, + 0x00, 0x01, 0x10, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x45, 0x00, 0x00, 0x1e, 0x00, 0x01, + 0x00, 0x00, 0x40, 0x11, 0x7c, 0xcc, 0x7f, 0x00, + 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x35, + 0x00, 0x35, 0x00, 0x0a, 0x01, 0x6e, 0x00, 0x00, +}; + static const struct ice_dummy_pkt_offsets dummy_udp_tun_tcp_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, { ICE_ETYPE_OL, 12 }, @@ -173,7 +356,7 @@ static const struct ice_dummy_pkt_offsets dummy_udp_tun_tcp_packet_offsets[] = { }; static const u8 dummy_udp_tun_tcp_packet[] = { - 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -224,7 +407,7 @@ static const struct ice_dummy_pkt_offsets dummy_udp_tun_udp_packet_offsets[] = { }; static const u8 dummy_udp_tun_udp_packet[] = { - 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -6892,6 +7075,7 @@ static const struct ice_prot_ext_tbl_entry ice_prot_ext[ICE_PROTOCOL_LAST] = { { ICE_GENEVE, { 8, 10, 12, 14 } }, { ICE_VXLAN_GPE, { 8, 10, 12, 14 } }, { ICE_NVGRE, { 0, 2, 4, 6 } }, + { ICE_GRE, { 0, 2, 4, 6, 8, 10, 12, 14 } }, { ICE_GTP, { 8, 10, 12, 14, 16, 18, 20, 22 } }, { ICE_PPPOE, { 0, 2, 4, 6 } }, { ICE_PFCP, { 8, 10, 12, 14, 16, 18, 20, 22 } }, @@ -6927,6 +7111,7 @@ static struct ice_protocol_entry ice_prot_id_tbl[ICE_PROTOCOL_LAST] = { { ICE_GENEVE, ICE_UDP_OF_HW }, { ICE_VXLAN_GPE, ICE_UDP_OF_HW }, { ICE_NVGRE, ICE_GRE_OF_HW }, + { ICE_GRE, ICE_GRE_OF_HW }, { ICE_GTP, ICE_UDP_OF_HW }, { ICE_PPPOE, ICE_PPPOE_HW }, { ICE_PFCP, ICE_UDP_ILOS_HW }, @@ -7113,6 +7298,7 @@ ice_fill_valid_words(struct ice_adv_lkup_elem *rule, struct ice_prot_lkup_ext *lkup_exts) { u8 j, word, prot_id, ret_val; + u8 extra_byte = 0; if (!ice_prot_type_to_id(rule->type, &prot_id)) return 0; @@ -7125,8 +7311,15 @@ ice_fill_valid_words(struct ice_adv_lkup_elem *rule, /* No more space to accommodate */ if (word >= ICE_MAX_CHAIN_WORDS) return 0; + if (rule->type == ICE_GRE) { + if (ice_prot_ext[rule->type].offs[j] == 0) { + if (((u16 *)&rule->h_u)[j] == 0x20) + extra_byte = 4; + continue; + } + } lkup_exts->fv_words[word].off = - ice_prot_ext[rule->type].offs[j]; + ice_prot_ext[rule->type].offs[j] - extra_byte; lkup_exts->fv_words[word].prot_id = ice_prot_id_tbl[rule->type].protocol_id; lkup_exts->field_mask[word] = @@ -7670,10 +7863,12 @@ ice_create_recipe_group(struct ice_hw *hw, struct ice_sw_recipe *rm, * @lkups_cnt: number of protocols * @bm: bitmap of field vectors to consider * @fv_list: pointer to a list that holds the returned field vectors + * @lkup_exts: lookup elements */ static enum ice_status ice_get_fv(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, - ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list) + ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list, + struct ice_prot_lkup_ext *lkup_exts) { enum ice_status status; u8 *prot_ids; @@ -7693,7 +7888,8 @@ ice_get_fv(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, } /* Find field vectors that include all specified protocol types */ - status = ice_get_sw_fv_list(hw, prot_ids, lkups_cnt, bm, fv_list); + status = ice_get_sw_fv_list(hw, prot_ids, lkups_cnt, bm, fv_list, + lkup_exts); free_mem: ice_free(hw, prot_ids); @@ -7729,6 +7925,10 @@ static bool ice_tun_type_match_word(enum ice_sw_tunnel_type tun_type, u16 *mask) *mask = ICE_TUN_FLAG_MASK; return true; + case ICE_SW_TUN_GRE: + *mask = ICE_GRE_FLAG_MASK; + return true; + case ICE_SW_TUN_GENEVE_VLAN: case ICE_SW_TUN_VXLAN_VLAN: *mask = ICE_TUN_FLAG_MASK & ~ICE_TUN_FLAG_VLAN_MASK; @@ -7750,6 +7950,12 @@ ice_add_special_words(struct ice_adv_rule_info *rinfo, struct ice_prot_lkup_ext *lkup_exts) { u16 mask; + u8 has_gre_key = 0; + u8 i; + + for (i = 0; i < lkup_exts->n_val_words; i++) + if (lkup_exts->fv_words[i].prot_id == 0x40) + has_gre_key = 1; /* If this is a tunneled packet, then add recipe index to match the * tunnel bit in the packet metadata flags. @@ -7761,6 +7967,13 @@ ice_add_special_words(struct ice_adv_rule_info *rinfo, lkup_exts->fv_words[word].prot_id = ICE_META_DATA_ID_HW; lkup_exts->fv_words[word].off = ICE_TUN_FLAG_MDID_OFF; lkup_exts->field_mask[word] = mask; + + if (rinfo->tun_type == ICE_SW_TUN_GRE) + lkup_exts->fv_words[word].off = + ICE_GRE_FLAG_MDID_OFF; + + if (!has_gre_key) + lkup_exts->field_mask[word] = 0x0140; } else { return ICE_ERR_MAX_LIMIT; } @@ -7802,6 +8015,9 @@ ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo, case ICE_SW_TUN_NVGRE: prof_type = ICE_PROF_TUN_GRE; break; + case ICE_SW_TUN_GRE: + prof_type = ICE_PROF_TUN_GRE; + break; case ICE_SW_TUN_PPPOE: case ICE_SW_TUN_PPPOE_QINQ: prof_type = ICE_PROF_TUN_PPPOE; @@ -8127,7 +8343,8 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, */ ice_get_compat_fv_bitmap(hw, rinfo, fv_bitmap); - status = ice_get_fv(hw, lkups, lkups_cnt, fv_bitmap, &rm->fv_list); + status = ice_get_fv(hw, lkups, lkups_cnt, fv_bitmap, &rm->fv_list, + lkup_exts); if (status) goto err_unroll; @@ -8276,6 +8493,8 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, const struct ice_dummy_pkt_offsets **offsets) { bool tcp = false, udp = false, ipv6 = false, vlan = false; + bool gre_c_bit = false; + bool gre_k_bit = false; bool gre = false, mpls = false; u16 i; @@ -8293,6 +8512,17 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, } else if (lkups[i].type == ICE_VLAN_OFOS) vlan = true; + else if (lkups[i].type == ICE_GRE) { + if (lkups[i].h_u.gre_hdr.flags & 0x20) + gre_k_bit = true; + if (lkups[i].h_u.gre_hdr.flags & 0x80) + gre_c_bit = true; + } else if (lkups[i].type == ICE_IPV4_OFOS && + lkups[i].h_u.ipv4_hdr.protocol == + ICE_IPV4_GRE_PROTO_ID && + lkups[i].m_u.ipv4_hdr.protocol == + 0xFF) + gre = true; else if (lkups[i].type == ICE_ETYPE_OL && lkups[i].h_u.ethertype.ethtype_id == CPU_TO_BE16(ICE_IPV6_ETHER_ID) && @@ -8698,6 +8928,46 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, return; } + if (tun_type == ICE_SW_TUN_GRE && tcp) { + if (gre_c_bit && gre_k_bit) { + *pkt = dummy_gre_rfc1701_c1k1_tcp_packet; + *pkt_len = sizeof(dummy_gre_rfc1701_c1k1_tcp_packet); + *offsets = dummy_gre_rfc1701_c1k1_tcp_packet_offsets; + return; + } + if (!gre_c_bit && gre_k_bit) { + *pkt = dummy_gre_rfc1701_c0k1_tcp_packet; + *pkt_len = sizeof(dummy_gre_rfc1701_c0k1_tcp_packet); + *offsets = dummy_gre_rfc1701_c0k1_tcp_packet_offsets; + return; + } + + *pkt = dummy_gre_rfc1701_c0k0_tcp_packet; + *pkt_len = sizeof(dummy_gre_rfc1701_c0k0_tcp_packet); + *offsets = dummy_gre_rfc1701_c0k0_tcp_packet_offsets; + return; + } + + if (tun_type == ICE_SW_TUN_GRE) { + if (gre_c_bit && gre_k_bit) { + *pkt = dummy_gre_rfc1701_c1k1_udp_packet; + *pkt_len = sizeof(dummy_gre_rfc1701_c1k1_udp_packet); + *offsets = dummy_gre_rfc1701_c1k1_udp_packet_offsets; + return; + } + if (!gre_c_bit && gre_k_bit) { + *pkt = dummy_gre_rfc1701_c0k1_udp_packet; + *pkt_len = sizeof(dummy_gre_rfc1701_c0k1_udp_packet); + *offsets = dummy_gre_rfc1701_c0k1_udp_packet_offsets; + return; + } + + *pkt = dummy_gre_rfc1701_c0k0_udp_packet; + *pkt_len = sizeof(dummy_gre_rfc1701_c0k0_udp_packet); + *offsets = dummy_gre_rfc1701_c0k0_udp_packet_offsets; + return; + } + if (tun_type == ICE_SW_TUN_VXLAN || tun_type == ICE_SW_TUN_GENEVE || tun_type == ICE_SW_TUN_VXLAN_GPE || tun_type == ICE_SW_TUN_UDP || tun_type == ICE_SW_TUN_PROFID_IPV4_VXLAN || @@ -8848,6 +9118,9 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, case ICE_NVGRE: len = sizeof(struct ice_nvgre); break; + case ICE_GRE: + len = sizeof(struct ice_gre); + break; case ICE_VXLAN: case ICE_GENEVE: case ICE_VXLAN_GPE: @@ -8881,6 +9154,20 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, if (len % ICE_BYTES_PER_WORD) return ICE_ERR_CFG; + if (lkups[i].type == ICE_GRE) { + if (lkups[i].h_u.gre_hdr.flags == 0x20) + offset -= 4; + + for (j = 1; j < len / sizeof(u16); j++) + if (((u16 *)&lkups[i].m_u)[j]) + ((u16 *)(pkt + offset))[j] = + (((u16 *)(pkt + offset))[j] & + ~((u16 *)&lkups[i].m_u)[j]) | + (((u16 *)&lkups[i].h_u)[j] & + ((u16 *)&lkups[i].m_u)[j]); + continue; + } + /* We have the offset to the header start, the length, the * caller's header values and mask. Use this information to * copy the data into the dummy packet appropriately based on @@ -9468,8 +9755,11 @@ ice_rem_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, return ICE_ERR_CFG; count = ice_fill_valid_words(&lkups[i], &lkup_exts); - if (!count) + if (!count) { + if (lkups[i].type == ICE_GRE) + continue; return ICE_ERR_CFG; + } } /* Create any special protocol/offset pairs, such as looking at tunnel From patchwork Thu Apr 7 10:56:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109377 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7CC47A0508; Thu, 7 Apr 2022 05:00:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 77B86428B3; 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06 Apr 2022 19:59:27 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850721" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:24 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Alvin Zhang , Steven Zou , Kevin Liu Subject: [PATCH 25/39] net/ice: support IPv4 GRE raw pattern type Date: Thu, 7 Apr 2022 10:56:52 +0000 Message-Id: <20220407105706.18889-26-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alvin Zhang Add definitions, matching entries, parsers for below patterns: ETH/IPV4/GRE/RAW/IPV4 ETH/IPV4/GRE/RAW/IPV4/UDP ETH/IPV4/GRE/RAW/IPV4/TCP Signed-off-by: Steven Zou Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_generic_flow.c | 27 +++++++++ drivers/net/ice/ice_generic_flow.h | 9 +++ drivers/net/ice/ice_switch_filter.c | 90 +++++++++++++++++++++++++++++ 3 files changed, 126 insertions(+) diff --git a/drivers/net/ice/ice_generic_flow.c b/drivers/net/ice/ice_generic_flow.c index 2ebe9a1cce..2d7e4c19f8 100644 --- a/drivers/net/ice/ice_generic_flow.c +++ b/drivers/net/ice/ice_generic_flow.c @@ -1085,6 +1085,33 @@ enum rte_flow_item_type pattern_eth_ipv6_nvgre_eth_ipv6_icmp6[] = { RTE_FLOW_ITEM_TYPE_ICMP6, RTE_FLOW_ITEM_TYPE_END, }; +/* IPv4 GRE RAW IPv4 */ +enum rte_flow_item_type pattern_eth_ipv4_gre_raw_ipv4[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_GRE, + RTE_FLOW_ITEM_TYPE_RAW, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_END, +}; +enum rte_flow_item_type pattern_eth_ipv4_gre_raw_ipv4_udp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_GRE, + RTE_FLOW_ITEM_TYPE_RAW, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_END, +}; +enum rte_flow_item_type pattern_eth_ipv4_gre_raw_ipv4_tcp[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_GRE, + RTE_FLOW_ITEM_TYPE_RAW, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_TCP, + RTE_FLOW_ITEM_TYPE_END, +}; /*IPv4 GTPU (EH) */ enum rte_flow_item_type pattern_eth_ipv4_gtpu[] = { diff --git a/drivers/net/ice/ice_generic_flow.h b/drivers/net/ice/ice_generic_flow.h index def7e2d6d6..12193cbd9d 100644 --- a/drivers/net/ice/ice_generic_flow.h +++ b/drivers/net/ice/ice_generic_flow.h @@ -27,6 +27,7 @@ #define ICE_PROT_L2TPV3OIP BIT_ULL(16) #define ICE_PROT_PFCP BIT_ULL(17) #define ICE_PROT_NAT_T_ESP BIT_ULL(18) +#define ICE_PROT_GRE BIT_ULL(19) /* field */ @@ -54,6 +55,7 @@ #define ICE_PFCP_SEID BIT_ULL(42) #define ICE_PFCP_S_FIELD BIT_ULL(41) #define ICE_IP_PK_ID BIT_ULL(40) +#define ICE_RAW_PATTERN BIT_ULL(39) /* input set */ @@ -104,6 +106,8 @@ (ICE_PROT_GTPU | ICE_GTPU_TEID) #define ICE_INSET_GTPU_QFI \ (ICE_PROT_GTPU | ICE_GTPU_QFI) +#define ICE_INSET_RAW \ + (ICE_PROT_GRE | ICE_RAW_PATTERN) #define ICE_INSET_PPPOE_SESSION \ (ICE_PROT_PPPOE_S | ICE_PPPOE_SESSION) #define ICE_INSET_PPPOE_PROTO \ @@ -291,6 +295,11 @@ extern enum rte_flow_item_type pattern_eth_ipv6_nvgre_eth_ipv6_udp[]; extern enum rte_flow_item_type pattern_eth_ipv6_nvgre_eth_ipv6_sctp[]; extern enum rte_flow_item_type pattern_eth_ipv6_nvgre_eth_ipv6_icmp6[]; +/* IPv4 GRE RAW IPv4 */ +extern enum rte_flow_item_type pattern_eth_ipv4_gre_raw_ipv4[]; +extern enum rte_flow_item_type pattern_eth_ipv4_gre_raw_ipv4_udp[]; +extern enum rte_flow_item_type pattern_eth_ipv4_gre_raw_ipv4_tcp[]; + /* IPv4 GTPU (EH) */ extern enum rte_flow_item_type pattern_eth_ipv4_gtpu[]; extern enum rte_flow_item_type pattern_eth_ipv4_gtpu_eh[]; diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c index 7c2038d089..a61d3d0aaa 100644 --- a/drivers/net/ice/ice_switch_filter.c +++ b/drivers/net/ice/ice_switch_filter.c @@ -196,6 +196,22 @@ #define ICE_SW_INSET_GTPU_IPV6_TCP ( \ ICE_SW_INSET_GTPU_IPV6 | ICE_INSET_TCP_SRC_PORT | \ ICE_INSET_TCP_DST_PORT) +#define ICE_SW_INSET_DIST_GRE_RAW_IPV4 ( \ + ICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \ + ICE_INSET_RAW) +#define ICE_SW_INSET_DIST_GRE_RAW_IPV4_TCP ( \ + ICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \ + ICE_INSET_TCP_SRC_PORT | ICE_INSET_TCP_DST_PORT | \ + ICE_INSET_RAW) +#define ICE_SW_INSET_DIST_GRE_RAW_IPV4_UDP ( \ + ICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \ + ICE_INSET_UDP_SRC_PORT | ICE_INSET_UDP_DST_PORT | \ + ICE_INSET_RAW) + +#define CUSTOM_GRE_KEY_OFFSET 4 +#define GRE_CFLAG 0x80 +#define GRE_KFLAG 0x20 +#define GRE_SFLAG 0x10 struct sw_meta { struct ice_adv_lkup_elem *list; @@ -317,6 +333,9 @@ ice_pattern_match_item ice_switch_pattern_dist_list[] = { {pattern_eth_ipv6_gtpu_eh_ipv6_udp, ICE_SW_INSET_MAC_GTPU_EH_OUTER, ICE_SW_INSET_GTPU_IPV6_UDP, ICE_INSET_NONE}, {pattern_eth_ipv6_gtpu_ipv6_tcp, ICE_SW_INSET_MAC_GTPU_OUTER, ICE_SW_INSET_GTPU_IPV6_TCP, ICE_INSET_NONE}, {pattern_eth_ipv6_gtpu_eh_ipv6_tcp, ICE_SW_INSET_MAC_GTPU_EH_OUTER, ICE_SW_INSET_GTPU_IPV6_TCP, ICE_INSET_NONE}, + {pattern_eth_ipv4_gre_raw_ipv4, ICE_SW_INSET_DIST_GRE_RAW_IPV4, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_ipv4_gre_raw_ipv4_tcp, ICE_SW_INSET_DIST_GRE_RAW_IPV4_TCP, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_ipv4_gre_raw_ipv4_udp, ICE_SW_INSET_DIST_GRE_RAW_IPV4_UDP, ICE_INSET_NONE, ICE_INSET_NONE}, }; static struct @@ -609,6 +628,11 @@ ice_switch_parse_pattern(const struct rte_flow_item pattern[], bool ipv6_ipv6_valid = 0; bool any_valid = 0; uint16_t j, k, t = 0; + uint16_t c_rsvd0_ver = 0; + bool gre_valid = 0; + +#define set_cur_item_einval(msg) \ + rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, item, (msg)) if (*tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ || *tun_type == ICE_NON_TUN_QINQ) @@ -1101,6 +1125,70 @@ ice_switch_parse_pattern(const struct rte_flow_item pattern[], } break; + case RTE_FLOW_ITEM_TYPE_GRE: { + const struct rte_flow_item_gre *gre_spec = item->spec; + const struct rte_flow_item_gre *gre_mask = item->mask; + + gre_valid = 1; + tunnel_valid = 1; + if (gre_spec && gre_mask) { + list[t].type = ICE_GRE; + if (gre_mask->c_rsvd0_ver) { + /* GRE RFC1701 */ + list[t].h_u.gre_hdr.flags = + gre_spec->c_rsvd0_ver; + list[t].m_u.gre_hdr.flags = + gre_mask->c_rsvd0_ver; + c_rsvd0_ver = gre_spec->c_rsvd0_ver & + gre_mask->c_rsvd0_ver; + } + } + break; + } + + case RTE_FLOW_ITEM_TYPE_RAW: { + const struct rte_flow_item_raw *raw_spec; + char *endp = NULL; + unsigned long key; + char s[sizeof("0x12345678")]; + + raw_spec = item->spec; + + if (list[t].type != ICE_GRE) + return set_cur_item_einval("RAW must follow GRE."); + + if (!(c_rsvd0_ver & GRE_KFLAG)) { + if (!raw_spec) + break; + + return set_cur_item_einval("Invalid pattern! k_bit is 0 while raw pattern exists."); + } + + if (!raw_spec) + return set_cur_item_einval("Invalid pattern! k_bit is 1 while raw pattern doesn't exist."); + + if ((c_rsvd0_ver & GRE_CFLAG) == GRE_CFLAG && + raw_spec->offset != CUSTOM_GRE_KEY_OFFSET) + return set_cur_item_einval("Invalid pattern! c_bit is 1 while offset is not 4."); + + if (raw_spec->length >= sizeof(s)) + return set_cur_item_einval("Invalid key"); + + memcpy(s, raw_spec->pattern, raw_spec->length); + s[raw_spec->length] = '\0'; + key = strtol(s, &endp, 16); + if (*endp != '\0' || key > UINT32_MAX) + return set_cur_item_einval("Invalid key"); + + list[t].h_u.gre_hdr.key = (uint32_t)key; + list[t].m_u.gre_hdr.key = UINT32_MAX; + *input |= ICE_INSET_RAW; + input_set_byte += 2; + t++; + + break; + } + case RTE_FLOW_ITEM_TYPE_VLAN: vlan_spec = item->spec; vlan_mask = item->mask; @@ -1634,6 +1722,8 @@ ice_switch_parse_pattern(const struct rte_flow_item pattern[], if (*tun_type == ICE_NON_TUN) { if (nvgre_valid) *tun_type = ICE_SW_TUN_NVGRE; + else if (gre_valid) + *tun_type = ICE_SW_TUN_GRE; else if (ipv4_valid && tcp_valid) *tun_type = ICE_SW_IPV4_TCP; else if (ipv4_valid && udp_valid) From patchwork Thu Apr 7 10:56:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109378 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 606D3A0508; Thu, 7 Apr 2022 05:00:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C260F428A7; Thu, 7 Apr 2022 04:59:31 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 7EA85428B4 for ; Thu, 7 Apr 2022 04:59:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300370; x=1680836370; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nfRD6Zu1g0yJzK3dWOMEHm6IwTux3SufOXnJOOlqa3I=; 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Signed-off-by: Steven Zou Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/base/ice_flex_pipe.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index 8672c41c69..1827993f44 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -1467,6 +1467,10 @@ static void ice_init_pkg_regs(struct ice_hw *hw) */ static enum ice_status ice_chk_pkg_version(struct ice_pkg_ver *pkg_ver) { + /* 0xFF indicate a custom pkg */ + if (pkg_ver->major == 0xFF) + return ICE_SUCCESS; + if (pkg_ver->major != ICE_PKG_SUPP_VER_MAJ || pkg_ver->minor != ICE_PKG_SUPP_VER_MNR) return ICE_ERR_NOT_SUPPORTED; From patchwork Thu Apr 7 10:56:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109379 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2A717A0508; Thu, 7 Apr 2022 05:00:50 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D3B5C428C0; Thu, 7 Apr 2022 04:59:33 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 1D22E4288A for ; Thu, 7 Apr 2022 04:59:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300373; x=1680836373; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BJzPDb+/JZ76wsmqp3JOt77KnsMx6yCP+dtPXHhf/s0=; b=FXRrABIm6NZ30IG86TV2IuQ4CC+qytA2xuh0SLEsU8nltEMo9Q54m0Sd pyW3SSzprpHfpazpufRWA0gNnloIL+sZu3mFCmbDRsDvpTZjQ7P9JuM0R wZaXv6+13KsfUIKGI3EzleeAumInppxlSiyfduK74eqp0CDEvoLkYGPsH c+vNwwhHQap7EneThuJJT0XI0KE29XvOziL70enJGQd8nCTNJ/Cz1N18L GaeLiMTNTmYjdKkwptjpMrlIycgNNXbIT32xH6rWbjux8HaVVvYK6ZmHB uc6tjBa2sHjWcmFpg7Eo56FW9CC9eCvTSBs97p2CUfofw/Vk6WQJR2skB A==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738448" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738448" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:32 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850750" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:30 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Kevin Liu , Steven Zou , Alvin Zhang Subject: [PATCH 27/39] net/ice: disable ACL function for MDCF instance Date: Thu, 7 Apr 2022 10:56:54 +0000 Message-Id: <20220407105706.18889-28-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MDCF instance does not support ACL, so disable it. Signed-off-by: Steven Zou Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_acl_filter.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/ice_acl_filter.c b/drivers/net/ice/ice_acl_filter.c index 8fe6f5aeb0..61bb016395 100644 --- a/drivers/net/ice/ice_acl_filter.c +++ b/drivers/net/ice/ice_acl_filter.c @@ -25,6 +25,7 @@ #include "ice_ethdev.h" #include "ice_generic_flow.h" #include "base/ice_flow.h" +#include "ice_dcf_ethdev.h" #define MAX_ACL_SLOTS_ID 2048 @@ -994,8 +995,11 @@ ice_acl_init(struct ice_adapter *ad) struct ice_pf *pf = &ad->pf; struct ice_hw *hw = ICE_PF_TO_HW(pf); struct ice_flow_parser *parser = &ice_acl_parser; + struct rte_eth_dev *eth_dev = &rte_eth_devices[ad->pf.dev_data->port_id]; + struct ice_dcf_adapter *dcf_adapter = eth_dev->data->dev_private; + struct ice_dcf_hw *dcf_hw = &dcf_adapter->real_hw; - if (!ad->hw.dcf_enabled) + if (!ad->hw.dcf_enabled || dcf_hw->multi_inst) return 0; ret = ice_acl_prof_alloc(hw); @@ -1041,8 +1045,11 @@ ice_acl_uninit(struct ice_adapter *ad) struct ice_pf *pf = &ad->pf; struct ice_hw *hw = ICE_PF_TO_HW(pf); struct ice_flow_parser *parser = &ice_acl_parser; + struct rte_eth_dev *eth_dev = &rte_eth_devices[ad->pf.dev_data->port_id]; + struct ice_dcf_adapter *dcf_adapter = eth_dev->data->dev_private; + struct ice_dcf_hw *dcf_hw = &dcf_adapter->real_hw; - if (ad->hw.dcf_enabled) { + if (ad->hw.dcf_enabled && !dcf_hw->multi_inst) { ice_unregister_parser(parser, ad); ice_deinit_acl(pf); ice_acl_prof_free(hw); From patchwork Thu Apr 7 10:56:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109380 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A788CA0508; Thu, 7 Apr 2022 05:00:55 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CCA88428AB; Thu, 7 Apr 2022 04:59:36 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id B041C428AB for ; Thu, 7 Apr 2022 04:59:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300375; x=1680836375; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EX5z1L9Py0aRxNU4gUXbHDsejPvnhgFet+y7t9iFhk4=; b=IPRawy7gTkR8idgqmUu87h7EiOuSirc6pf7DB9vmndSCOFE0In9K3/G9 v+5pOIAym3DTMKJUMSTOGcW7NvVRHmaXTcA0bjPg/MUnKhWWu3I87oJL0 3KSI2T6lGnm0AvujRyk01XF+Uc6YaJAIGD44CbSk+b0cANMnVM+/etZo5 Y54aBCx/5ycsK5o9f6CO+3xwrxHjtU+B9w2Gbjl91GLgIc82ljmTJjYoi 7tWl/+RaljwbiQu6CLxLf0wqFhyM2YSK3JlRjyCypxuHpdSf82ZIIVtF9 pfChHanne3FWSoYr6fIe59hNncVZ0AxHncrTkYr3s0TYuS9WekQbUkuww g==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738460" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738460" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:35 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850766" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:33 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Alvin Zhang , Kevin Liu Subject: [PATCH 28/39] net/ice: treat unknown package as OS default package Date: Thu, 7 Apr 2022 10:56:55 +0000 Message-Id: <20220407105706.18889-29-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alvin Zhang In order to use custom package, unknown package should be treated as OS default package. Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_ethdev.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 73e550f5fb..ad9b09d081 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -1710,13 +1710,16 @@ ice_load_pkg_type(struct ice_hw *hw) /* store the activated package type (OS default or Comms) */ if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME, - ICE_PKG_NAME_SIZE)) + ICE_PKG_NAME_SIZE)) { package_type = ICE_PKG_TYPE_OS_DEFAULT; - else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME, - ICE_PKG_NAME_SIZE)) + } else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME, + ICE_PKG_NAME_SIZE)) { package_type = ICE_PKG_TYPE_COMMS; - else - package_type = ICE_PKG_TYPE_UNKNOWN; + } else { + PMD_INIT_LOG(WARNING, + "The package type is not identified, treaded as OS default type"); + package_type = ICE_PKG_TYPE_OS_DEFAULT; + } PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s (%s VLAN mode)", hw->active_pkg_ver.major, hw->active_pkg_ver.minor, From patchwork Thu Apr 7 10:56:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109381 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 31B9FA0508; Thu, 7 Apr 2022 05:01:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C4D97428C6; Thu, 7 Apr 2022 04:59:39 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 1CC3C428AC for ; Thu, 7 Apr 2022 04:59:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300378; x=1680836378; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YfyqBPReywlBNta2D9Qoy3i5xa2INQkEib+o31XfKd4=; b=eP5fp0n5T02v6Kv9bqdLAruyxLT8p8CWpRGW5G3t31gxNQHU4MankSid rhSAnrA4dEaKij5yj9k1oWpbRTEsnOmcm5Xaw/eaLm9F5fMsRLj5IS/wa QXRABwX7nO0+QyWcCTGOuY7ILOOO7YKn+ktp+mTDL15NlmrZn/tHXCcqq DcD3UW2Jy96DHqz+GqWbZDzDtX2t2XoG1k1n89NBWtt9EEkPOdrizFRZA cTfOd7RTN+QSMgSE7+uIxsKlp0fX9BkM5R/UnhqM7K28xtv12AWCx0ucb ByjaiX/z6NBqcFynu0fNJe4NCVh6WOZS20sBU78/N4unIOej/p0pKxvRb Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738469" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738469" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:37 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850776" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:35 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Junfeng Guo , Kevin Liu Subject: [PATCH 29/39] net/ice/base: update Profile ID table for VXLAN Date: Thu, 7 Apr 2022 10:56:56 +0000 Message-Id: <20220407105706.18889-30-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Junfeng Guo Update Profile ID table for VXLAN to align with Tencent customed DDP. Signed-off-by: Junfeng Guo Signed-off-by: Kevin Liu --- drivers/net/ice/base/ice_switch.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index efb9399b77..c8071aa50d 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -23,15 +23,15 @@ #define ICE_PROFID_IPV4_TUN_M_IPV4_TCP 10 #define ICE_PROFID_IPV4_TUN_M_IPV4_UDP 11 #define ICE_PROFID_IPV4_TUN_M_IPV4_OTHER 12 -#define ICE_PROFID_IPV6_TUN_M_IPV4_TCP 16 -#define ICE_PROFID_IPV6_TUN_M_IPV4_UDP 17 -#define ICE_PROFID_IPV6_TUN_M_IPV4_OTHER 18 -#define ICE_PROFID_IPV4_TUN_M_IPV6_TCP 22 -#define ICE_PROFID_IPV4_TUN_M_IPV6_UDP 23 -#define ICE_PROFID_IPV4_TUN_M_IPV6_OTHER 24 -#define ICE_PROFID_IPV6_TUN_M_IPV6_TCP 25 -#define ICE_PROFID_IPV6_TUN_M_IPV6_UDP 26 -#define ICE_PROFID_IPV6_TUN_M_IPV6_OTHER 27 +#define ICE_PROFID_IPV6_TUN_M_IPV4_TCP 34 +#define ICE_PROFID_IPV6_TUN_M_IPV4_UDP 35 +#define ICE_PROFID_IPV6_TUN_M_IPV4_OTHER 36 +#define ICE_PROFID_IPV4_TUN_M_IPV6_TCP 40 +#define ICE_PROFID_IPV4_TUN_M_IPV6_UDP 41 +#define ICE_PROFID_IPV4_TUN_M_IPV6_OTHER 42 +#define ICE_PROFID_IPV6_TUN_M_IPV6_TCP 43 +#define ICE_PROFID_IPV6_TUN_M_IPV6_UDP 44 +#define ICE_PROFID_IPV6_TUN_M_IPV6_OTHER 45 #define ICE_PROFID_PPPOE_PAY 34 #define ICE_PROFID_PPPOE_IPV4_TCP 35 #define ICE_PROFID_PPPOE_IPV4_UDP 36 From patchwork Thu Apr 7 10:56:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109382 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D938BA0508; Thu, 7 Apr 2022 05:01:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B07DB42891; Thu, 7 Apr 2022 04:59:42 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 87D49428C9 for ; Thu, 7 Apr 2022 04:59:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300380; x=1680836380; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tn+5wexFFPbrMJ4/eThdhmZjOpgBI/fvH7LCZZ2PTfg=; b=a1E3BwIcSq2dUrka6P6S+seb0qka9WEmr9xHeU4nXQEEtL05t3rj/CQV LBvkmfpixW4XUk4dnTgebH3VbxovNDnSI4jknDC3jyklgR2/cTH8rfuEj aspPjuVSgZqvXTOi2LlAuxzfTO6jSovB/okKoSn+8G7rUnYiWl2Z+RQDN hKL4CHLZIBixECnuBkcgEz9ZoBZUyhKi9m6KnScIvkPpPPfi/sjpCOYnn k+OQ5SEcyIVbWys42+yWpUgQbjnXmC8prl+ue3Ea3cl4PnPprIbKYdmMo zErqs4rBUwjAGYYG3w+HUX7N1HF01CQiNOqRFpDRDujtII8OR+n7Hi40U g==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738475" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738475" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:40 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850783" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:37 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Junfeng Guo , Kevin Liu Subject: [PATCH 30/39] net/ice/base: update Protocol ID table to match DVM DDP Date: Thu, 7 Apr 2022 10:56:57 +0000 Message-Id: <20220407105706.18889-31-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Junfeng Guo The ice kernel driver and DDP is working in Double VLAN Mode (DVM), but the DVM is not supported on this PMD. Thus update the SW to HW Protocol ID table for VLAN to support common switch filtering with single VLAN layer. Signed-off-by: Junfeng Guo Signed-off-by: Kevin Liu --- drivers/net/ice/base/ice_switch.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index b367efaf02..3bb9e28898 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -7098,7 +7098,7 @@ static struct ice_protocol_entry ice_prot_id_tbl[ICE_PROTOCOL_LAST] = { { ICE_MAC_OFOS, ICE_MAC_OFOS_HW }, { ICE_MAC_IL, ICE_MAC_IL_HW }, { ICE_ETYPE_OL, ICE_ETYPE_OL_HW }, - { ICE_VLAN_OFOS, ICE_VLAN_OL_HW }, + { ICE_VLAN_OFOS, ICE_VLAN_OF_HW }, { ICE_IPV4_OFOS, ICE_IPV4_OFOS_HW }, { ICE_IPV4_IL, ICE_IPV4_IL_HW }, { ICE_IPV6_OFOS, ICE_IPV6_OFOS_HW }, From patchwork Thu Apr 7 10:56:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109383 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0F40CA0508; Thu, 7 Apr 2022 05:01:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9901B428CB; Thu, 7 Apr 2022 04:59:44 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 38C40428CB for ; Thu, 7 Apr 2022 04:59:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300383; x=1680836383; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=H1+9dem2wMtK2yoYf4nY2nwEmD+x/6W8C5ck/hGYqNU=; b=npE3WzLLlkyuH8KWBpmla0gQyPdvMU6ODpvMa3TOoFlBCjiTKeQYeKk1 U1/qp/Cuy6ehb3FQlEYZYuJ145C2OKYNztG6WvAYtW2ECtVRPaTpEkQI4 R3kL9KCVr1VdbZ8EGlI9pN/1PFCvhyxXX37pQQY2tAFPlHV3H0mRQ3bGq 6yFvherZrME4a9Ch0vFBZypfvNDHQQWYPOJkPPdq1CvVeQsU95jnOGLwZ xjpsCl99UZjEt7W+sgGRcrg4OhSDKgLAggerMVMdTm4kxn8XRSQYf1Y6i uSYRC+QBw2bbJISu6IJ9il2GBkH+QhQC32rnD1WqPesz0zEppgN3Nl1rJ A==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738484" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738484" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:42 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850791" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:40 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Kevin Liu Subject: [PATCH 31/39] net/ice: handle virtchnl event message without interrupt Date: Thu, 7 Apr 2022 10:56:58 +0000 Message-Id: <20220407105706.18889-32-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Steve Yang Currently, VF can only handle virtchnl event message by calling interrupt. It is not available in two cases: 1. If the event message comes during VF initialization before interrupt is enabled, this message will not be handled correctly. 2. Some virtchnl commands need to receive the event message and handle it with interrupt disabled. To solve this issue, we add the virtchnl event message handling in the process of reading vitchnl messages in adminq from PF. Signed-off-by: Steve Yang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_dcf.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c index 7987b6261d..8c47f96341 100644 --- a/drivers/net/ice/ice_dcf.c +++ b/drivers/net/ice/ice_dcf.c @@ -63,11 +63,32 @@ ice_dcf_recv_cmd_rsp_no_irq(struct ice_dcf_hw *hw, enum virtchnl_ops op, goto again; v_op = rte_le_to_cpu_32(event.desc.cookie_high); - if (v_op != op) - goto again; + + if (v_op == VIRTCHNL_OP_EVENT) { + struct virtchnl_pf_event *vpe = + (struct virtchnl_pf_event *)event.msg_buf; + switch (vpe->event) { + case VIRTCHNL_EVENT_RESET_IMPENDING: + hw->resetting = true; + if (rsp_msglen) + *rsp_msglen = 0; + return IAVF_SUCCESS; + default: + goto again; + } + } else { + /* async reply msg on command issued by vf previously */ + if (v_op != op) { + PMD_DRV_LOG(WARNING, + "command mismatch, expect %u, get %u", + op, v_op); + goto again; + } + } if (rsp_msglen != NULL) *rsp_msglen = event.msg_len; + return rte_le_to_cpu_32(event.desc.cookie_low); again: From patchwork Thu Apr 7 10:56:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109384 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4D289A0508; Thu, 7 Apr 2022 05:01:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8A8FC42897; Thu, 7 Apr 2022 04:59:47 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 72E79428CF for ; Thu, 7 Apr 2022 04:59:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300385; x=1680836385; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6KzqEBVsvyg0i/PP2YE/43Tc7/hjP8rCs0NaDhIsKAA=; b=DW5GVwe6pEw3aq9nbRQdNAa/N1rol8y2oaT/RU3A8KAiJ0B80EUOT+Sv ympx3B9cjnshJAGPPwAlUS6ULX/06IocmNiHQSf/ZF5BUIL4EJ/tAKdIO 99h2uPNEfcb7mAEV8o4Gic3L8PLMWPjjUbVdH8N76W/ZEQfwspaTmFWKX Hcqtz5ePol+yCBm0sjwUV9yEMq8d8b9bHw4AA5GqbSOCaKG6T2ceBVpp6 aLhAUQq3nUM3rQPTGCO9XwNwFb4bRT0keEigbNjZ+W0Bun/0tPXirNK4j lHmz8bJZAv3IZOsszvNrnpyACt9FXUwdzJyvNh37kq8pTBEQo7NUmn2eD g==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738492" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738492" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:45 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850798" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:43 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Kevin Liu Subject: [PATCH 32/39] net/ice: add DCF request queues function Date: Thu, 7 Apr 2022 10:56:59 +0000 Message-Id: <20220407105706.18889-33-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Steve Yang Add a new virtchnl function to request additional queues from PF. Current default queue pairs number is 16. In order to support up to 256 queue pairs DCF port, enable this request queues function. Signed-off-by: Steve Yang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_dcf.c | 98 +++++++++++++++++++++++++++++++++------ drivers/net/ice/ice_dcf.h | 1 + 2 files changed, 86 insertions(+), 13 deletions(-) diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c index 8c47f96341..2e651adda7 100644 --- a/drivers/net/ice/ice_dcf.c +++ b/drivers/net/ice/ice_dcf.c @@ -257,7 +257,7 @@ ice_dcf_get_vf_resource(struct ice_dcf_hw *hw) VIRTCHNL_VF_CAP_ADV_LINK_SPEED | VIRTCHNL_VF_CAP_DCF | VIRTCHNL_VF_OFFLOAD_VLAN_V2 | VF_BASE_MODE_OFFLOADS | VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC | - VIRTCHNL_VF_OFFLOAD_QOS; + VIRTCHNL_VF_OFFLOAD_QOS | VIRTCHNL_VF_OFFLOAD_REQ_QUEUES; err = ice_dcf_send_cmd_req_no_irq(hw, VIRTCHNL_OP_GET_VF_RESOURCES, (uint8_t *)&caps, sizeof(caps)); @@ -468,18 +468,38 @@ ice_dcf_execute_virtchnl_cmd(struct ice_dcf_hw *hw, goto ret; } - do { - if (!cmd->pending) - break; - - rte_delay_ms(ICE_DCF_ARQ_CHECK_TIME); - } while (i++ < ICE_DCF_ARQ_MAX_RETRIES); - - if (cmd->v_ret != IAVF_SUCCESS) { - err = -1; - PMD_DRV_LOG(ERR, - "No response (%d times) or return failure (%d) for cmd %d", - i, cmd->v_ret, cmd->v_op); + switch (cmd->v_op) { + case VIRTCHNL_OP_REQUEST_QUEUES: + err = ice_dcf_recv_cmd_rsp_no_irq(hw, + VIRTCHNL_OP_REQUEST_QUEUES, + cmd->rsp_msgbuf, + cmd->rsp_buflen, + NULL); + if (err != IAVF_SUCCESS || !hw->resetting) { + err = -1; + PMD_DRV_LOG(ERR, + "Failed to get response of " + "VIRTCHNL_OP_REQUEST_QUEUES %d", + err); + } + break; + default: + /* For other virtchnl ops in running time, + * wait for the cmd done flag. + */ + do { + if (!cmd->pending) + break; + rte_delay_ms(ICE_DCF_ARQ_CHECK_TIME); + } while (i++ < ICE_DCF_ARQ_MAX_RETRIES); + + if (cmd->v_ret != IAVF_SUCCESS) { + err = -1; + PMD_DRV_LOG(ERR, + "No response (%d times) or " + "return failure (%d) for cmd %d", + i, cmd->v_ret, cmd->v_op); + } } ret: @@ -1012,6 +1032,58 @@ ice_dcf_configure_queues(struct ice_dcf_hw *hw) return err; } +int +ice_dcf_request_queues(struct ice_dcf_hw *hw, uint16_t num) +{ + struct virtchnl_vf_res_request vfres; + struct dcf_virtchnl_cmd args; + uint16_t num_queue_pairs; + int err; + + if (!(hw->vf_res->vf_cap_flags & + VIRTCHNL_VF_OFFLOAD_REQ_QUEUES)) { + PMD_DRV_LOG(ERR, "request queues not supported"); + return -1; + } + + if (num == 0) { + PMD_DRV_LOG(ERR, "queue number cannot be zero"); + return -1; + } + vfres.num_queue_pairs = num; + + memset(&args, 0, sizeof(args)); + args.v_op = VIRTCHNL_OP_REQUEST_QUEUES; + + args.req_msg = (u8 *)&vfres; + args.req_msglen = sizeof(vfres); + + args.rsp_msgbuf = hw->arq_buf; + args.rsp_msglen = ICE_DCF_AQ_BUF_SZ; + args.rsp_buflen = ICE_DCF_AQ_BUF_SZ; + + /* + * disable interrupt to avoid the admin queue message to be read + * before iavf_read_msg_from_pf. + */ + rte_intr_disable(hw->eth_dev->intr_handle); + err = ice_dcf_execute_virtchnl_cmd(hw, &args); + rte_intr_enable(hw->eth_dev->intr_handle); + if (err) { + PMD_DRV_LOG(ERR, "fail to execute command OP_REQUEST_QUEUES"); + return err; + } + + /* request additional queues failed, return available number */ + num_queue_pairs = ((struct virtchnl_vf_res_request *) + args.rsp_msgbuf)->num_queue_pairs; + PMD_DRV_LOG(ERR, + "request queues failed, only %u queues available", + num_queue_pairs); + + return -1; +} + int ice_dcf_config_irq_map(struct ice_dcf_hw *hw) { diff --git a/drivers/net/ice/ice_dcf.h b/drivers/net/ice/ice_dcf.h index 42f4404a37..46e0010848 100644 --- a/drivers/net/ice/ice_dcf.h +++ b/drivers/net/ice/ice_dcf.h @@ -129,6 +129,7 @@ int ice_dcf_configure_rss_key(struct ice_dcf_hw *hw); int ice_dcf_configure_rss_lut(struct ice_dcf_hw *hw); int ice_dcf_init_rss(struct ice_dcf_hw *hw); int ice_dcf_configure_queues(struct ice_dcf_hw *hw); +int ice_dcf_request_queues(struct ice_dcf_hw *hw, uint16_t num); int ice_dcf_config_irq_map(struct ice_dcf_hw *hw); int ice_dcf_switch_queue(struct ice_dcf_hw *hw, uint16_t qid, bool rx, bool on); int ice_dcf_disable_queues(struct ice_dcf_hw *hw); From patchwork Thu Apr 7 10:57:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109385 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A3448A0508; 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a="248738496" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738496" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:47 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850808" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:45 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Kevin Liu Subject: [PATCH 33/39] net/ice: negotiate large VF and request more queues Date: Thu, 7 Apr 2022 10:57:00 +0000 Message-Id: <20220407105706.18889-34-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Steve Yang Negotiate large VF capability with PF during VF initialization. If large VF is supported and the number of queues larger than 16 is required, VF requests additional queues from PF. Mark the state that large VF is supported. If the allocated queues number is larger than 16, the max RSS queue region cannot be 16 anymore. Add the function to query max RSS queue region from PF, use it in the RSS initialization and future filters configuration. Signed-off-by: Steve Yang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_dcf.c | 34 +++++++++++++++- drivers/net/ice/ice_dcf.h | 4 ++ drivers/net/ice/ice_dcf_ethdev.c | 69 +++++++++++++++++++++++++++++++- drivers/net/ice/ice_dcf_ethdev.h | 2 + 4 files changed, 106 insertions(+), 3 deletions(-) diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c index 2e651adda7..8807308bb2 100644 --- a/drivers/net/ice/ice_dcf.c +++ b/drivers/net/ice/ice_dcf.c @@ -257,7 +257,8 @@ ice_dcf_get_vf_resource(struct ice_dcf_hw *hw) VIRTCHNL_VF_CAP_ADV_LINK_SPEED | VIRTCHNL_VF_CAP_DCF | VIRTCHNL_VF_OFFLOAD_VLAN_V2 | VF_BASE_MODE_OFFLOADS | VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC | - VIRTCHNL_VF_OFFLOAD_QOS | VIRTCHNL_VF_OFFLOAD_REQ_QUEUES; + VIRTCHNL_VF_OFFLOAD_QOS | VIRTCHNL_VF_OFFLOAD_REQ_QUEUES | + VIRTCHNL_VF_LARGE_NUM_QPAIRS; err = ice_dcf_send_cmd_req_no_irq(hw, VIRTCHNL_OP_GET_VF_RESOURCES, (uint8_t *)&caps, sizeof(caps)); @@ -1084,6 +1085,37 @@ ice_dcf_request_queues(struct ice_dcf_hw *hw, uint16_t num) return -1; } +int +ice_dcf_get_max_rss_queue_region(struct ice_dcf_hw *hw) +{ + struct dcf_virtchnl_cmd args; + uint16_t qregion_width; + int err; + + memset(&args, 0, sizeof(args)); + args.v_op = VIRTCHNL_OP_GET_MAX_RSS_QREGION; + args.req_msg = NULL; + args.req_msglen = 0; + args.rsp_msgbuf = hw->arq_buf; + args.rsp_msglen = ICE_DCF_AQ_BUF_SZ; + args.rsp_buflen = ICE_DCF_AQ_BUF_SZ; + + err = ice_dcf_execute_virtchnl_cmd(hw, &args); + if (err) { + PMD_DRV_LOG(ERR, + "Failed to execute command of " + "VIRTCHNL_OP_GET_MAX_RSS_QREGION"); + return err; + } + + qregion_width = ((struct virtchnl_max_rss_qregion *) + args.rsp_msgbuf)->qregion_width; + hw->max_rss_qregion = (uint16_t)(1 << qregion_width); + + return 0; +} + + int ice_dcf_config_irq_map(struct ice_dcf_hw *hw) { diff --git a/drivers/net/ice/ice_dcf.h b/drivers/net/ice/ice_dcf.h index 46e0010848..8efa3e5b23 100644 --- a/drivers/net/ice/ice_dcf.h +++ b/drivers/net/ice/ice_dcf.h @@ -107,6 +107,7 @@ struct ice_dcf_hw { uint16_t msix_base; uint16_t nb_msix; + uint16_t max_rss_qregion; /* max RSS queue region supported by PF */ uint16_t rxq_map[16]; struct virtchnl_eth_stats eth_stats_offset; struct virtchnl_vlan_caps vlan_v2_caps; @@ -116,6 +117,8 @@ struct ice_dcf_hw { uint32_t link_speed; bool resetting; + /* Indicate large VF support enabled or not */ + bool lv_enabled; }; int ice_dcf_execute_virtchnl_cmd(struct ice_dcf_hw *hw, @@ -130,6 +133,7 @@ int ice_dcf_configure_rss_lut(struct ice_dcf_hw *hw); int ice_dcf_init_rss(struct ice_dcf_hw *hw); int ice_dcf_configure_queues(struct ice_dcf_hw *hw); int ice_dcf_request_queues(struct ice_dcf_hw *hw, uint16_t num); +int ice_dcf_get_max_rss_queue_region(struct ice_dcf_hw *hw); int ice_dcf_config_irq_map(struct ice_dcf_hw *hw); int ice_dcf_switch_queue(struct ice_dcf_hw *hw, uint16_t qid, bool rx, bool on); int ice_dcf_disable_queues(struct ice_dcf_hw *hw); diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index a165f74e26..4ffc10b0de 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -40,6 +40,8 @@ static int ice_dcf_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, struct rte_eth_udp_tunnel *udp_tunnel); +static int ice_dcf_queues_req_reset(struct rte_eth_dev *dev, uint16_t num); + static int ice_dcf_dev_init(struct rte_eth_dev *eth_dev); @@ -664,6 +666,11 @@ ice_dcf_dev_configure(struct rte_eth_dev *dev) { struct ice_dcf_adapter *dcf_ad = dev->data->dev_private; struct ice_adapter *ad = &dcf_ad->parent; + struct ice_dcf_hw *hw = &dcf_ad->real_hw; + int ret; + + uint16_t num_queue_pairs = + RTE_MAX(dev->data->nb_rx_queues, dev->data->nb_tx_queues); ad->rx_bulk_alloc_allowed = true; ad->tx_simple_allowed = true; @@ -671,6 +678,47 @@ ice_dcf_dev_configure(struct rte_eth_dev *dev) if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; + /* Large VF setting */ + if (num_queue_pairs > ICE_DCF_MAX_NUM_QUEUES_DFLT) { + if (!(hw->vf_res->vf_cap_flags & + VIRTCHNL_VF_LARGE_NUM_QPAIRS)) { + PMD_DRV_LOG(ERR, "large VF is not supported"); + return -1; + } + + if (num_queue_pairs > ICE_DCF_MAX_NUM_QUEUES_LV) { + PMD_DRV_LOG(ERR, + "queue pairs number cannot be larger than %u", + ICE_DCF_MAX_NUM_QUEUES_LV); + return -1; + } + + ret = ice_dcf_queues_req_reset(dev, num_queue_pairs); + if (ret) + return ret; + + ret = ice_dcf_get_max_rss_queue_region(hw); + if (ret) { + PMD_INIT_LOG(ERR, "get max rss queue region failed"); + return ret; + } + + hw->lv_enabled = true; + } else { + /* Check if large VF is already enabled. If so, disable and + * release redundant queue resource. + */ + if (hw->lv_enabled) { + ret = ice_dcf_queues_req_reset(dev, num_queue_pairs); + if (ret) + return ret; + + hw->lv_enabled = false; + } + /* if large VF is not required, use default rss queue region */ + hw->max_rss_qregion = ICE_DCF_MAX_NUM_QUEUES_DFLT; + } + return 0; } @@ -682,8 +730,8 @@ ice_dcf_dev_info_get(struct rte_eth_dev *dev, struct ice_dcf_hw *hw = &adapter->real_hw; dev_info->max_mac_addrs = DCF_NUM_MACADDR_MAX; - dev_info->max_rx_queues = hw->vsi_res->num_queue_pairs; - dev_info->max_tx_queues = hw->vsi_res->num_queue_pairs; + dev_info->max_rx_queues = ICE_DCF_MAX_NUM_QUEUES_LV; + dev_info->max_tx_queues = ICE_DCF_MAX_NUM_QUEUES_LV; dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN; dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX; dev_info->hash_key_size = hw->vf_res->rss_key_size; @@ -1908,6 +1956,23 @@ ice_dcf_dev_uninit(struct rte_eth_dev *eth_dev) return 0; } +static int ice_dcf_queues_req_reset(struct rte_eth_dev *dev, uint16_t num) +{ + struct ice_dcf_adapter *adapter = dev->data->dev_private; + struct ice_dcf_hw *hw = &adapter->real_hw; + int ret; + + ret = ice_dcf_request_queues(hw, num); + if (ret) { + PMD_DRV_LOG(ERR, "request queues from PF failed"); + return ret; + } + PMD_DRV_LOG(INFO, "change queue pairs from %u to %u", + hw->vsi_res->num_queue_pairs, num); + + return ice_dcf_dev_reset(dev); +} + static int eth_ice_dcf_pci_probe(__rte_unused struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) diff --git a/drivers/net/ice/ice_dcf_ethdev.h b/drivers/net/ice/ice_dcf_ethdev.h index 27f6402786..4a08d32e0c 100644 --- a/drivers/net/ice/ice_dcf_ethdev.h +++ b/drivers/net/ice/ice_dcf_ethdev.h @@ -20,6 +20,8 @@ #define ICE_DCF_ETH_OVERHEAD \ (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_DCF_VLAN_TAG_SIZE * 2) #define ICE_DCF_ETH_MAX_LEN (RTE_ETHER_MTU + ICE_DCF_ETH_OVERHEAD) +#define ICE_DCF_MAX_NUM_QUEUES_DFLT 16 +#define ICE_DCF_MAX_NUM_QUEUES_LV 256 struct ice_dcf_queue { uint64_t dummy; From patchwork Thu Apr 7 10:57:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109386 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 615E5A0508; Thu, 7 Apr 2022 05:01:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C3822428D4; Thu, 7 Apr 2022 04:59:51 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id D674A428D1 for ; Thu, 7 Apr 2022 04:59:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300390; x=1680836390; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BXykvfiigE4sMKMZH2fNyM24dHMztkFA7gCGMyrg/jQ=; b=NX1TvtOfj2j5f8RfT2zvq9QMuVoGEYCrCA8U5dl8X1rxW8Y3EucezCzc DipeLSfsSE0kkl9ULXji8fKnGcG1RJAbop/u95BjGiCjFiwjQoQQ6gblJ knCiUoYPSn9iN1OR86W+zSGjIOjD+MK8m2cDF00PcOrc55RTUtegJ8ioB NtNuDC7IBeIBNokGcHC0CDR5ZAWf/xuCKGghfX5zFfZz3dt0ByX+jxlg3 0m/vkctK2+l1CK3/F2ZN1O/kJx1rGC0tddt+FuCH8vocFhivWuCHJEzau 1C1KJzCGwvxGPHxpec8dLY/1zTwe3J6VekqN3nB5xefcokYT4d84nD5Hm w==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738500" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738500" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:49 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850822" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:47 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Kevin Liu Subject: [PATCH 34/39] net/ice: enable multiple queues configurations for large VF Date: Thu, 7 Apr 2022 10:57:01 +0000 Message-Id: <20220407105706.18889-35-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Steve Yang Since the adminq buffer size has a 4K limitation, the current virtchnl command VIRTCHNL_OP_CONFIG_VSI_QUEUES cannot send the message only once to configure up to 256 queues. In this patch, we send the messages multiple times to make sure that the buffer size is less than 4K each time. Signed-off-by: Steve Yang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_dcf.c | 11 ++++++----- drivers/net/ice/ice_dcf.h | 3 ++- drivers/net/ice/ice_dcf_ethdev.c | 20 ++++++++++++++++++-- drivers/net/ice/ice_dcf_ethdev.h | 1 + 4 files changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c index 8807308bb2..7a0a9a3534 100644 --- a/drivers/net/ice/ice_dcf.c +++ b/drivers/net/ice/ice_dcf.c @@ -950,7 +950,8 @@ ice_dcf_init_rss(struct ice_dcf_hw *hw) #define IAVF_RXDID_COMMS_OVS_1 22 int -ice_dcf_configure_queues(struct ice_dcf_hw *hw) +ice_dcf_configure_queues(struct ice_dcf_hw *hw, + uint16_t num_queue_pairs, uint16_t index) { struct ice_rx_queue **rxq = (struct ice_rx_queue **)hw->eth_dev->data->rx_queues; @@ -963,16 +964,16 @@ ice_dcf_configure_queues(struct ice_dcf_hw *hw) int err; size = sizeof(*vc_config) + - sizeof(vc_config->qpair[0]) * hw->num_queue_pairs; + sizeof(vc_config->qpair[0]) * num_queue_pairs; vc_config = rte_zmalloc("cfg_queue", size, 0); if (!vc_config) return -ENOMEM; vc_config->vsi_id = hw->vsi_res->vsi_id; - vc_config->num_queue_pairs = hw->num_queue_pairs; + vc_config->num_queue_pairs = num_queue_pairs; - for (i = 0, vc_qp = vc_config->qpair; - i < hw->num_queue_pairs; + for (i = index, vc_qp = vc_config->qpair; + i < index + num_queue_pairs; i++, vc_qp++) { vc_qp->txq.vsi_id = hw->vsi_res->vsi_id; vc_qp->txq.queue_id = i; diff --git a/drivers/net/ice/ice_dcf.h b/drivers/net/ice/ice_dcf.h index 8efa3e5b23..1f45881315 100644 --- a/drivers/net/ice/ice_dcf.h +++ b/drivers/net/ice/ice_dcf.h @@ -131,7 +131,8 @@ void ice_dcf_uninit_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw); int ice_dcf_configure_rss_key(struct ice_dcf_hw *hw); int ice_dcf_configure_rss_lut(struct ice_dcf_hw *hw); int ice_dcf_init_rss(struct ice_dcf_hw *hw); -int ice_dcf_configure_queues(struct ice_dcf_hw *hw); +int ice_dcf_configure_queues(struct ice_dcf_hw *hw, + uint16_t num_queue_pairs, uint16_t index); int ice_dcf_request_queues(struct ice_dcf_hw *hw, uint16_t num); int ice_dcf_get_max_rss_queue_region(struct ice_dcf_hw *hw); int ice_dcf_config_irq_map(struct ice_dcf_hw *hw); diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index 4ffc10b0de..211a2510fa 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -514,6 +514,8 @@ ice_dcf_dev_start(struct rte_eth_dev *dev) struct rte_intr_handle *intr_handle = dev->intr_handle; struct ice_adapter *ad = &dcf_ad->parent; struct ice_dcf_hw *hw = &dcf_ad->real_hw; + uint16_t num_queue_pairs; + uint16_t index = 0; int ret; if (hw->resetting) { @@ -532,6 +534,7 @@ ice_dcf_dev_start(struct rte_eth_dev *dev) hw->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues, dev->data->nb_tx_queues); + num_queue_pairs = hw->num_queue_pairs; ret = ice_dcf_init_rx_queues(dev); if (ret) { @@ -547,7 +550,20 @@ ice_dcf_dev_start(struct rte_eth_dev *dev) } } - ret = ice_dcf_configure_queues(hw); + /* If needed, send configure queues msg multiple times to make the + * adminq buffer length smaller than the 4K limitation. + */ + while (num_queue_pairs > ICE_DCF_CFG_Q_NUM_PER_BUF) { + if (ice_dcf_configure_queues(hw, + ICE_DCF_CFG_Q_NUM_PER_BUF, index) != 0) { + PMD_DRV_LOG(ERR, "configure queues failed"); + goto err_queue; + } + num_queue_pairs -= ICE_DCF_CFG_Q_NUM_PER_BUF; + index += ICE_DCF_CFG_Q_NUM_PER_BUF; + } + + ret = ice_dcf_configure_queues(hw, num_queue_pairs, index); if (ret) { PMD_DRV_LOG(ERR, "Fail to config queues"); return ret; @@ -587,7 +603,7 @@ ice_dcf_dev_start(struct rte_eth_dev *dev) dev->data->dev_link.link_status = RTE_ETH_LINK_UP; - +err_queue: return 0; } diff --git a/drivers/net/ice/ice_dcf_ethdev.h b/drivers/net/ice/ice_dcf_ethdev.h index 4a08d32e0c..2fac1e5b21 100644 --- a/drivers/net/ice/ice_dcf_ethdev.h +++ b/drivers/net/ice/ice_dcf_ethdev.h @@ -22,6 +22,7 @@ #define ICE_DCF_ETH_MAX_LEN (RTE_ETHER_MTU + ICE_DCF_ETH_OVERHEAD) #define ICE_DCF_MAX_NUM_QUEUES_DFLT 16 #define ICE_DCF_MAX_NUM_QUEUES_LV 256 +#define ICE_DCF_CFG_Q_NUM_PER_BUF 32 struct ice_dcf_queue { uint64_t dummy; From patchwork Thu Apr 7 10:57:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109387 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DB400A0508; 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a="248738509" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738509" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:52 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850832" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:49 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Kevin Liu Subject: [PATCH 35/39] net/ice: enable IRQ mapping configuration for large VF Date: Thu, 7 Apr 2022 10:57:02 +0000 Message-Id: <20220407105706.18889-36-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Steve Yang The current IRQ mapping configuration only supports max 16 queues and 16 MSIX vectors. Change the queue vector mapping structure to indicate up to 256 queues. A new opcode is used to handle the case with large number of queues. To avoid adminq buffer size limitation, we support to send the virtchnl message multiple times if needed. Signed-off-by: Steve Yang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_dcf.c | 50 +++++++++++++++++++++++++++---- drivers/net/ice/ice_dcf.h | 10 ++++++- drivers/net/ice/ice_dcf_ethdev.c | 51 +++++++++++++++++++++++++++----- drivers/net/ice/ice_dcf_ethdev.h | 1 + 4 files changed, 99 insertions(+), 13 deletions(-) diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c index 7a0a9a3534..90af99f8d0 100644 --- a/drivers/net/ice/ice_dcf.c +++ b/drivers/net/ice/ice_dcf.c @@ -1116,7 +1116,6 @@ ice_dcf_get_max_rss_queue_region(struct ice_dcf_hw *hw) return 0; } - int ice_dcf_config_irq_map(struct ice_dcf_hw *hw) { @@ -1133,13 +1132,14 @@ ice_dcf_config_irq_map(struct ice_dcf_hw *hw) return -ENOMEM; map_info->num_vectors = hw->nb_msix; - for (i = 0; i < hw->nb_msix; i++) { - vecmap = &map_info->vecmap[i]; + for (i = 0; i < hw->eth_dev->data->nb_rx_queues; i++) { + vecmap = + &map_info->vecmap[hw->qv_map[i].vector_id - hw->msix_base]; vecmap->vsi_id = hw->vsi_res->vsi_id; vecmap->rxitr_idx = 0; - vecmap->vector_id = hw->msix_base + i; + vecmap->vector_id = hw->qv_map[i].vector_id; vecmap->txq_map = 0; - vecmap->rxq_map = hw->rxq_map[hw->msix_base + i]; + vecmap->rxq_map |= 1 << hw->qv_map[i].queue_id; } memset(&args, 0, sizeof(args)); @@ -1155,6 +1155,46 @@ ice_dcf_config_irq_map(struct ice_dcf_hw *hw) return err; } +int +ice_dcf_config_irq_map_lv(struct ice_dcf_hw *hw, + uint16_t num, uint16_t index) +{ + struct virtchnl_queue_vector_maps *map_info; + struct virtchnl_queue_vector *qv_maps; + struct dcf_virtchnl_cmd args; + int len, i, err; + int count = 0; + + len = sizeof(struct virtchnl_queue_vector_maps) + + sizeof(struct virtchnl_queue_vector) * (num - 1); + + map_info = rte_zmalloc("map_info", len, 0); + if (!map_info) + return -ENOMEM; + + map_info->vport_id = hw->vsi_res->vsi_id; + map_info->num_qv_maps = num; + for (i = index; i < index + map_info->num_qv_maps; i++) { + qv_maps = &map_info->qv_maps[count++]; + qv_maps->itr_idx = VIRTCHNL_ITR_IDX_0; + qv_maps->queue_type = VIRTCHNL_QUEUE_TYPE_RX; + qv_maps->queue_id = hw->qv_map[i].queue_id; + qv_maps->vector_id = hw->qv_map[i].vector_id; + } + + args.v_op = VIRTCHNL_OP_MAP_QUEUE_VECTOR; + args.req_msg = (u8 *)map_info; + args.req_msglen = len; + args.rsp_msgbuf = hw->arq_buf; + args.req_msglen = ICE_DCF_AQ_BUF_SZ; + err = ice_dcf_execute_virtchnl_cmd(hw, &args); + if (err) + PMD_DRV_LOG(ERR, "fail to execute command OP_MAP_QUEUE_VECTOR"); + + rte_free(map_info); + return err; +} + int ice_dcf_switch_queue(struct ice_dcf_hw *hw, uint16_t qid, bool rx, bool on) { diff --git a/drivers/net/ice/ice_dcf.h b/drivers/net/ice/ice_dcf.h index 1f45881315..bd88424034 100644 --- a/drivers/net/ice/ice_dcf.h +++ b/drivers/net/ice/ice_dcf.h @@ -74,6 +74,11 @@ struct ice_dcf_tm_conf { bool committed; }; +struct ice_dcf_qv_map { + uint16_t queue_id; + uint16_t vector_id; +}; + struct ice_dcf_hw { struct iavf_hw avf; @@ -108,7 +113,8 @@ struct ice_dcf_hw { uint16_t msix_base; uint16_t nb_msix; uint16_t max_rss_qregion; /* max RSS queue region supported by PF */ - uint16_t rxq_map[16]; + + struct ice_dcf_qv_map *qv_map; /* queue vector mapping */ struct virtchnl_eth_stats eth_stats_offset; struct virtchnl_vlan_caps vlan_v2_caps; @@ -136,6 +142,8 @@ int ice_dcf_configure_queues(struct ice_dcf_hw *hw, int ice_dcf_request_queues(struct ice_dcf_hw *hw, uint16_t num); int ice_dcf_get_max_rss_queue_region(struct ice_dcf_hw *hw); int ice_dcf_config_irq_map(struct ice_dcf_hw *hw); +int ice_dcf_config_irq_map_lv(struct ice_dcf_hw *hw, + uint16_t num, uint16_t index); int ice_dcf_switch_queue(struct ice_dcf_hw *hw, uint16_t qid, bool rx, bool on); int ice_dcf_disable_queues(struct ice_dcf_hw *hw); int ice_dcf_query_stats(struct ice_dcf_hw *hw, diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index 211a2510fa..82d97fd049 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -144,6 +144,7 @@ ice_dcf_config_rx_queues_irqs(struct rte_eth_dev *dev, { struct ice_dcf_adapter *adapter = dev->data->dev_private; struct ice_dcf_hw *hw = &adapter->real_hw; + struct ice_dcf_qv_map *qv_map; uint16_t interval, i; int vec; @@ -162,6 +163,14 @@ ice_dcf_config_rx_queues_irqs(struct rte_eth_dev *dev, } } + qv_map = rte_zmalloc("qv_map", + dev->data->nb_rx_queues * sizeof(struct ice_dcf_qv_map), 0); + if (!qv_map) { + PMD_DRV_LOG(ERR, "Failed to allocate %d queue-vector map", + dev->data->nb_rx_queues); + return -1; + } + if (!dev->data->dev_conf.intr_conf.rxq || !rte_intr_dp_is_en(intr_handle)) { /* Rx interrupt disabled, Map interrupt only for writeback */ @@ -197,17 +206,22 @@ ice_dcf_config_rx_queues_irqs(struct rte_eth_dev *dev, } IAVF_WRITE_FLUSH(&hw->avf); /* map all queues to the same interrupt */ - for (i = 0; i < dev->data->nb_rx_queues; i++) - hw->rxq_map[hw->msix_base] |= 1 << i; + for (i = 0; i < dev->data->nb_rx_queues; i++) { + qv_map[i].queue_id = i; + qv_map[i].vector_id = hw->msix_base; + } + hw->qv_map = qv_map; } else { if (!rte_intr_allow_others(intr_handle)) { hw->nb_msix = 1; hw->msix_base = IAVF_MISC_VEC_ID; for (i = 0; i < dev->data->nb_rx_queues; i++) { - hw->rxq_map[hw->msix_base] |= 1 << i; + qv_map[i].queue_id = i; + qv_map[i].vector_id = hw->msix_base; rte_intr_vec_list_index_set(intr_handle, i, IAVF_MISC_VEC_ID); } + hw->qv_map = qv_map; PMD_DRV_LOG(DEBUG, "vector %u are mapping to all Rx queues", hw->msix_base); @@ -220,21 +234,44 @@ ice_dcf_config_rx_queues_irqs(struct rte_eth_dev *dev, hw->msix_base = IAVF_MISC_VEC_ID; vec = IAVF_MISC_VEC_ID; for (i = 0; i < dev->data->nb_rx_queues; i++) { - hw->rxq_map[vec] |= 1 << i; + qv_map[i].queue_id = i; + qv_map[i].vector_id = vec; rte_intr_vec_list_index_set(intr_handle, i, vec++); if (vec >= hw->nb_msix) vec = IAVF_RX_VEC_START; } + hw->qv_map = qv_map; PMD_DRV_LOG(DEBUG, "%u vectors are mapping to %u Rx queues", hw->nb_msix, dev->data->nb_rx_queues); } } - if (ice_dcf_config_irq_map(hw)) { - PMD_DRV_LOG(ERR, "config interrupt mapping failed"); - return -1; + if (!hw->lv_enabled) { + if (ice_dcf_config_irq_map(hw)) { + PMD_DRV_LOG(ERR, "config interrupt mapping failed"); + return -1; + } + } else { + uint16_t num_qv_maps = dev->data->nb_rx_queues; + uint16_t index = 0; + + while (num_qv_maps > ICE_DCF_IRQ_MAP_NUM_PER_BUF) { + if (ice_dcf_config_irq_map_lv(hw, + ICE_DCF_IRQ_MAP_NUM_PER_BUF, index)) { + PMD_DRV_LOG(ERR, "config interrupt mapping for large VF failed"); + return -1; + } + num_qv_maps -= ICE_DCF_IRQ_MAP_NUM_PER_BUF; + index += ICE_DCF_IRQ_MAP_NUM_PER_BUF; + } + + if (ice_dcf_config_irq_map_lv(hw, num_qv_maps, index)) { + PMD_DRV_LOG(ERR, "config interrupt mapping for large VF failed"); + return -1; + } + } return 0; } diff --git a/drivers/net/ice/ice_dcf_ethdev.h b/drivers/net/ice/ice_dcf_ethdev.h index 2fac1e5b21..9ef524c97c 100644 --- a/drivers/net/ice/ice_dcf_ethdev.h +++ b/drivers/net/ice/ice_dcf_ethdev.h @@ -23,6 +23,7 @@ #define ICE_DCF_MAX_NUM_QUEUES_DFLT 16 #define ICE_DCF_MAX_NUM_QUEUES_LV 256 #define ICE_DCF_CFG_Q_NUM_PER_BUF 32 +#define ICE_DCF_IRQ_MAP_NUM_PER_BUF 128 struct ice_dcf_queue { uint64_t dummy; From patchwork Thu Apr 7 10:57:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109388 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A098FA0508; Thu, 7 Apr 2022 05:01:45 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 980C0428B9; Thu, 7 Apr 2022 04:59:58 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 139B2428B9 for ; Thu, 7 Apr 2022 04:59:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300397; x=1680836397; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Lcbuk4agSOvOoB7Vtd9VTq5mX2ilgnY7OzCeyQ0zHfw=; b=nBxvyU/Zr8SMvN44ZTXjItdmI+ReG7NuqsZ7kSEMfR5YzT9ISFz4M7/A GITp/+QG212DVhN1hVcTQPbD1F1/jz8batimuyf5BvMCemggRuFeUbyOq eleSJQuohtea8MjFGbzH+Wp3cBUgd5HmJbGazBAUNRf4sPpCNjmYyKt6d tzJEVD9F28P9MAjYuLTrtVQd5lnddUq0RTncEh+rxU4QFjAaM8pkHhR4O yIphj+HJTSt+BM2zqqSQRTSJB97BhFpINjEWPSn0WY2Y+t3rMrq4d/Vxd b5+QbaCcjuCHMBaQTCdyJbYNXdEpvi7Pjrq+wmSYGfJNJLf5i81UEoKPd g==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738514" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738514" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:54 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850850" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:52 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Kevin Liu Subject: [PATCH 36/39] net/ice: add enable/disable queues for DCF large VF Date: Thu, 7 Apr 2022 10:57:03 +0000 Message-Id: <20220407105706.18889-37-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The current virtchnl structure for enable/disable queues only supports max 32 queue pairs. Use a new opcode and structure to indicate up to 256 queue pairs, in order to enable/disable queues in large VF case. Signed-off-by: Steve Yang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_dcf.c | 99 +++++++++++++++++++++++++++++++- drivers/net/ice/ice_dcf.h | 5 ++ drivers/net/ice/ice_dcf_ethdev.c | 26 +++++++-- drivers/net/ice/ice_dcf_ethdev.h | 8 +-- 4 files changed, 125 insertions(+), 13 deletions(-) diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c index 90af99f8d0..6b210176a0 100644 --- a/drivers/net/ice/ice_dcf.c +++ b/drivers/net/ice/ice_dcf.c @@ -90,7 +90,6 @@ ice_dcf_recv_cmd_rsp_no_irq(struct ice_dcf_hw *hw, enum virtchnl_ops op, *rsp_msglen = event.msg_len; return rte_le_to_cpu_32(event.desc.cookie_low); - again: rte_delay_ms(ICE_DCF_ARQ_CHECK_TIME); } while (i++ < ICE_DCF_ARQ_MAX_RETRIES); @@ -897,7 +896,7 @@ ice_dcf_init_rss(struct ice_dcf_hw *hw) { struct rte_eth_dev *dev = hw->eth_dev; struct rte_eth_rss_conf *rss_conf; - uint8_t i, j, nb_q; + uint16_t i, j, nb_q; int ret; rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf; @@ -1076,6 +1075,12 @@ ice_dcf_request_queues(struct ice_dcf_hw *hw, uint16_t num) return err; } + /* request queues succeeded, vf is resetting */ + if (hw->resetting) { + PMD_DRV_LOG(INFO, "vf is resetting"); + return 0; + } + /* request additional queues failed, return available number */ num_queue_pairs = ((struct virtchnl_vf_res_request *) args.rsp_msgbuf)->num_queue_pairs; @@ -1186,7 +1191,8 @@ ice_dcf_config_irq_map_lv(struct ice_dcf_hw *hw, args.req_msg = (u8 *)map_info; args.req_msglen = len; args.rsp_msgbuf = hw->arq_buf; - args.req_msglen = ICE_DCF_AQ_BUF_SZ; + args.rsp_msglen = ICE_DCF_AQ_BUF_SZ; + args.rsp_buflen = ICE_DCF_AQ_BUF_SZ; err = ice_dcf_execute_virtchnl_cmd(hw, &args); if (err) PMD_DRV_LOG(ERR, "fail to execute command OP_MAP_QUEUE_VECTOR"); @@ -1226,6 +1232,50 @@ ice_dcf_switch_queue(struct ice_dcf_hw *hw, uint16_t qid, bool rx, bool on) return err; } +int +ice_dcf_switch_queue_lv(struct ice_dcf_hw *hw, uint16_t qid, bool rx, bool on) +{ + struct virtchnl_del_ena_dis_queues *queue_select; + struct virtchnl_queue_chunk *queue_chunk; + struct dcf_virtchnl_cmd args; + int err, len; + + len = sizeof(struct virtchnl_del_ena_dis_queues); + queue_select = rte_zmalloc("queue_select", len, 0); + if (!queue_select) + return -ENOMEM; + + queue_chunk = queue_select->chunks.chunks; + queue_select->chunks.num_chunks = 1; + queue_select->vport_id = hw->vsi_res->vsi_id; + + if (rx) { + queue_chunk->type = VIRTCHNL_QUEUE_TYPE_RX; + queue_chunk->start_queue_id = qid; + queue_chunk->num_queues = 1; + } else { + queue_chunk->type = VIRTCHNL_QUEUE_TYPE_TX; + queue_chunk->start_queue_id = qid; + queue_chunk->num_queues = 1; + } + + if (on) + args.v_op = VIRTCHNL_OP_ENABLE_QUEUES_V2; + else + args.v_op = VIRTCHNL_OP_DISABLE_QUEUES_V2; + args.req_msg = (u8 *)queue_select; + args.req_msglen = len; + args.rsp_msgbuf = hw->arq_buf; + args.rsp_msglen = ICE_DCF_AQ_BUF_SZ; + args.rsp_buflen = ICE_DCF_AQ_BUF_SZ; + err = ice_dcf_execute_virtchnl_cmd(hw, &args); + if (err) + PMD_DRV_LOG(ERR, "Failed to execute command of %s", + on ? "OP_ENABLE_QUEUES_V2" : "OP_DISABLE_QUEUES_V2"); + rte_free(queue_select); + return err; +} + int ice_dcf_disable_queues(struct ice_dcf_hw *hw) { @@ -1255,6 +1305,49 @@ ice_dcf_disable_queues(struct ice_dcf_hw *hw) return err; } +int +ice_dcf_disable_queues_lv(struct ice_dcf_hw *hw) +{ + struct virtchnl_del_ena_dis_queues *queue_select; + struct virtchnl_queue_chunk *queue_chunk; + struct dcf_virtchnl_cmd args; + int err, len; + + len = sizeof(struct virtchnl_del_ena_dis_queues) + + sizeof(struct virtchnl_queue_chunk) * + (ICE_DCF_RXTX_QUEUE_CHUNKS_NUM - 1); + queue_select = rte_zmalloc("queue_select", len, 0); + if (!queue_select) + return -ENOMEM; + + queue_chunk = queue_select->chunks.chunks; + queue_select->chunks.num_chunks = ICE_DCF_RXTX_QUEUE_CHUNKS_NUM; + queue_select->vport_id = hw->vsi_res->vsi_id; + + queue_chunk[VIRTCHNL_QUEUE_TYPE_TX].type = VIRTCHNL_QUEUE_TYPE_TX; + queue_chunk[VIRTCHNL_QUEUE_TYPE_TX].start_queue_id = 0; + queue_chunk[VIRTCHNL_QUEUE_TYPE_TX].num_queues = + hw->eth_dev->data->nb_tx_queues; + + queue_chunk[VIRTCHNL_QUEUE_TYPE_RX].type = VIRTCHNL_QUEUE_TYPE_RX; + queue_chunk[VIRTCHNL_QUEUE_TYPE_RX].start_queue_id = 0; + queue_chunk[VIRTCHNL_QUEUE_TYPE_RX].num_queues = + hw->eth_dev->data->nb_rx_queues; + + args.v_op = VIRTCHNL_OP_DISABLE_QUEUES_V2; + args.req_msg = (u8 *)queue_select; + args.req_msglen = len; + args.rsp_msgbuf = hw->arq_buf; + args.rsp_msglen = ICE_DCF_AQ_BUF_SZ; + args.rsp_buflen = ICE_DCF_AQ_BUF_SZ; + err = ice_dcf_execute_virtchnl_cmd(hw, &args); + if (err) + PMD_DRV_LOG(ERR, + "Failed to execute command of OP_DISABLE_QUEUES_V2"); + rte_free(queue_select); + return err; +} + int ice_dcf_query_stats(struct ice_dcf_hw *hw, struct virtchnl_eth_stats *pstats) diff --git a/drivers/net/ice/ice_dcf.h b/drivers/net/ice/ice_dcf.h index bd88424034..a6dec86b9b 100644 --- a/drivers/net/ice/ice_dcf.h +++ b/drivers/net/ice/ice_dcf.h @@ -15,6 +15,8 @@ #include "base/ice_type.h" #include "ice_logs.h" +#define ICE_DCF_RXTX_QUEUE_CHUNKS_NUM 2 + struct dcf_virtchnl_cmd { TAILQ_ENTRY(dcf_virtchnl_cmd) next; @@ -145,7 +147,10 @@ int ice_dcf_config_irq_map(struct ice_dcf_hw *hw); int ice_dcf_config_irq_map_lv(struct ice_dcf_hw *hw, uint16_t num, uint16_t index); int ice_dcf_switch_queue(struct ice_dcf_hw *hw, uint16_t qid, bool rx, bool on); +int ice_dcf_switch_queue_lv(struct ice_dcf_hw *hw, + uint16_t qid, bool rx, bool on); int ice_dcf_disable_queues(struct ice_dcf_hw *hw); +int ice_dcf_disable_queues_lv(struct ice_dcf_hw *hw); int ice_dcf_query_stats(struct ice_dcf_hw *hw, struct virtchnl_eth_stats *pstats); int ice_dcf_add_del_all_mac_addr(struct ice_dcf_hw *hw, diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index 82d97fd049..b5381cdfc4 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -318,6 +318,7 @@ static int ice_dcf_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) { struct ice_dcf_adapter *ad = dev->data->dev_private; + struct ice_dcf_hw *dcf_hw = &ad->real_hw; struct iavf_hw *hw = &ad->real_hw.avf; struct ice_rx_queue *rxq; int err = 0; @@ -340,7 +341,11 @@ ice_dcf_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) IAVF_WRITE_FLUSH(hw); /* Ready to switch the queue on */ - err = ice_dcf_switch_queue(&ad->real_hw, rx_queue_id, true, true); + if (!dcf_hw->lv_enabled) + err = ice_dcf_switch_queue(dcf_hw, rx_queue_id, true, true); + else + err = ice_dcf_switch_queue_lv(dcf_hw, rx_queue_id, true, true); + if (err) { PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on", rx_queue_id); @@ -449,6 +454,7 @@ static int ice_dcf_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) { struct ice_dcf_adapter *ad = dev->data->dev_private; + struct ice_dcf_hw *dcf_hw = &ad->real_hw; struct iavf_hw *hw = &ad->real_hw.avf; struct ice_tx_queue *txq; int err = 0; @@ -464,7 +470,10 @@ ice_dcf_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) IAVF_WRITE_FLUSH(hw); /* Ready to switch the queue on */ - err = ice_dcf_switch_queue(&ad->real_hw, tx_queue_id, false, true); + if (!dcf_hw->lv_enabled) + err = ice_dcf_switch_queue(dcf_hw, tx_queue_id, false, true); + else + err = ice_dcf_switch_queue_lv(dcf_hw, tx_queue_id, false, true); if (err) { PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on", @@ -651,12 +660,17 @@ ice_dcf_stop_queues(struct rte_eth_dev *dev) struct ice_dcf_hw *hw = &ad->real_hw; struct ice_rx_queue *rxq; struct ice_tx_queue *txq; - int ret, i; + int i; /* Stop All queues */ - ret = ice_dcf_disable_queues(hw); - if (ret) - PMD_DRV_LOG(WARNING, "Fail to stop queues"); + if (!hw->lv_enabled) { + if (ice_dcf_disable_queues(hw)) + PMD_DRV_LOG(WARNING, "Fail to stop queues"); + } else { + if (ice_dcf_disable_queues_lv(hw)) + PMD_DRV_LOG(WARNING, + "Fail to stop queues for large VF"); + } for (i = 0; i < dev->data->nb_tx_queues; i++) { txq = dev->data->tx_queues[i]; diff --git a/drivers/net/ice/ice_dcf_ethdev.h b/drivers/net/ice/ice_dcf_ethdev.h index 9ef524c97c..3f740e2c7b 100644 --- a/drivers/net/ice/ice_dcf_ethdev.h +++ b/drivers/net/ice/ice_dcf_ethdev.h @@ -20,10 +20,10 @@ #define ICE_DCF_ETH_OVERHEAD \ (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_DCF_VLAN_TAG_SIZE * 2) #define ICE_DCF_ETH_MAX_LEN (RTE_ETHER_MTU + ICE_DCF_ETH_OVERHEAD) -#define ICE_DCF_MAX_NUM_QUEUES_DFLT 16 -#define ICE_DCF_MAX_NUM_QUEUES_LV 256 -#define ICE_DCF_CFG_Q_NUM_PER_BUF 32 -#define ICE_DCF_IRQ_MAP_NUM_PER_BUF 128 +#define ICE_DCF_MAX_NUM_QUEUES_DFLT 16 +#define ICE_DCF_MAX_NUM_QUEUES_LV 256 +#define ICE_DCF_CFG_Q_NUM_PER_BUF 32 +#define ICE_DCF_IRQ_MAP_NUM_PER_BUF 128 struct ice_dcf_queue { uint64_t dummy; From patchwork Thu Apr 7 10:57:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109389 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F164AA0508; Thu, 7 Apr 2022 05:01:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 929F342886; Thu, 7 Apr 2022 05:00:00 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id A796E42896 for ; Thu, 7 Apr 2022 04:59:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300397; x=1680836397; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; 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Fixes: 40d466fa9f76 ("net/ice: support ACL filter in DCF") Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_acl_filter.c | 20 ++++++++++++++---- drivers/net/ice/ice_generic_flow.c | 34 +++++++++++++++++++++++------- 2 files changed, 42 insertions(+), 12 deletions(-) diff --git a/drivers/net/ice/ice_acl_filter.c b/drivers/net/ice/ice_acl_filter.c index 61bb016395..58ccdb53d7 100644 --- a/drivers/net/ice/ice_acl_filter.c +++ b/drivers/net/ice/ice_acl_filter.c @@ -57,6 +57,8 @@ ice_pattern_match_item ice_acl_pattern[] = { {pattern_eth_ipv4_sctp, ICE_ACL_INSET_ETH_IPV4_SCTP, ICE_INSET_NONE, ICE_INSET_NONE}, }; +static void ice_acl_prof_free(struct ice_hw *hw); + static int ice_acl_prof_alloc(struct ice_hw *hw) { @@ -1011,17 +1013,27 @@ ice_acl_init(struct ice_adapter *ad) ret = ice_acl_setup(pf); if (ret) - return ret; + goto deinit_acl; ret = ice_acl_bitmap_init(pf); if (ret) - return ret; + goto deinit_acl; ret = ice_acl_prof_init(pf); if (ret) - return ret; + goto deinit_acl; - return ice_register_parser(parser, ad); + ret = ice_register_parser(parser, ad); + if (ret) + goto deinit_acl; + + return 0; + +deinit_acl: + ice_deinit_acl(pf); + ice_acl_prof_free(hw); + PMD_DRV_LOG(ERR, "ACL init failed, may not supported!"); + return ret; } static void diff --git a/drivers/net/ice/ice_generic_flow.c b/drivers/net/ice/ice_generic_flow.c index 2d7e4c19f8..18183bb5e6 100644 --- a/drivers/net/ice/ice_generic_flow.c +++ b/drivers/net/ice/ice_generic_flow.c @@ -1865,6 +1865,12 @@ ice_register_flow_engine(struct ice_flow_engine *engine) TAILQ_INSERT_TAIL(&engine_list, engine, node); } +static void +ice_unregister_flow_engine(struct ice_flow_engine *engine) +{ + TAILQ_REMOVE(&engine_list, engine, node); +} + int ice_flow_init(struct ice_adapter *ad) { @@ -1888,9 +1894,18 @@ ice_flow_init(struct ice_adapter *ad) ret = engine->init(ad); if (ret) { - PMD_INIT_LOG(ERR, "Failed to initialize engine %d", - engine->type); - return ret; + /** + * ACL may not supported in kernel driver, + * so just unregister the engine. + */ + if (engine->type == ICE_FLOW_ENGINE_ACL) { + ice_unregister_flow_engine(engine); + } else { + PMD_INIT_LOG(ERR, + "Failed to initialize engine %d", + engine->type); + return ret; + } } } return 0; @@ -1977,7 +1992,7 @@ ice_register_parser(struct ice_flow_parser *parser, list = ice_get_parser_list(parser, ad); if (list == NULL) - return -EINVAL; + goto err; if (ad->devargs.pipe_mode_support) { TAILQ_INSERT_TAIL(list, parser_node, node); @@ -1989,7 +2004,7 @@ ice_register_parser(struct ice_flow_parser *parser, ICE_FLOW_ENGINE_ACL) { TAILQ_INSERT_AFTER(list, existing_node, parser_node, node); - goto DONE; + return 0; } } TAILQ_INSERT_HEAD(list, parser_node, node); @@ -2000,7 +2015,7 @@ ice_register_parser(struct ice_flow_parser *parser, ICE_FLOW_ENGINE_SWITCH) { TAILQ_INSERT_AFTER(list, existing_node, parser_node, node); - goto DONE; + return 0; } } TAILQ_INSERT_HEAD(list, parser_node, node); @@ -2009,11 +2024,14 @@ ice_register_parser(struct ice_flow_parser *parser, } else if (parser->engine->type == ICE_FLOW_ENGINE_ACL) { TAILQ_INSERT_HEAD(list, parser_node, node); } else { - return -EINVAL; + goto err; } } -DONE: return 0; +err: + rte_free(parser_node); + PMD_DRV_LOG(ERR, "%s failed.", __func__); + return -EINVAL; } void From patchwork Thu Apr 7 10:57:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109390 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8EB89A0508; Thu, 7 Apr 2022 05:02:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B9A66428C4; Thu, 7 Apr 2022 05:00:01 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id EDD45428DD for ; Thu, 7 Apr 2022 04:59:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; 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06 Apr 2022 19:59:57 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Kevin Liu Subject: [PATCH 38/39] testpmd: force flow flush Date: Thu, 7 Apr 2022 10:57:05 +0000 Message-Id: <20220407105706.18889-39-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Qi Zhang For mdcf, rte_flow_flush is still need to be invoked even there are no flows be created in current instance. Signed-off-by: Qi Zhang Signed-off-by: Kevin Liu --- app/test-pmd/config.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/app/test-pmd/config.c b/app/test-pmd/config.c index cc8e7aa138..3d40e3e43d 100644 --- a/app/test-pmd/config.c +++ b/app/test-pmd/config.c @@ -2923,15 +2923,15 @@ port_flow_flush(portid_t port_id) port = &ports[port_id]; - if (port->flow_list == NULL) - return ret; - /* Poisoning to make sure PMDs update it in case of error. */ memset(&error, 0x44, sizeof(error)); if (rte_flow_flush(port_id, &error)) { port_flow_complain(&error); } + if (port->flow_list == NULL) + return ret; + while (port->flow_list) { struct port_flow *pf = port->flow_list->next; From patchwork Thu Apr 7 10:57:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109391 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 49097A0508; Thu, 7 Apr 2022 05:02:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8D42C428E2; Thu, 7 Apr 2022 05:00:03 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id EBA6D428E9 for ; Thu, 7 Apr 2022 05:00:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649300402; x=1680836402; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vZ1wK6tEwVCGfFyeyKkg16W2Djo88uHh23EhCqeAsCc=; b=HPyUNLBoUOyDKt5z8n65N0LisZhxHNagxw0nS60+oIrfKUkizLhbQeOW rQ7lCJUyfz1JTAfuciFP8O2AN+gVzHVDzVgETsHKKueQ/PSUDq6pocIqb omr2wKitkqrg2uGv3vqSK6EHcjNeRmPhxF+wxPcEejxtLUBufYpDTVfvF TpA901P77oXGUeLAHdJS5AouSD44q2d2kJD68Ivyel3hLmsCWBvMJOJES i09Obdwn3mB5znuiXhhFBPSkeFqxrPQAlSN/Wj0akqju44FR/iGN9S5ln fiTbjCiglUiLV4+YZ8SvGclj2mSPf40rKgoEtkncWyI7fJjPT/n77O1ST g==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="248738523" X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="248738523" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 20:00:01 -0700 X-IronPort-AV: E=Sophos;i="5.90,241,1643702400"; d="scan'208";a="570850893" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 19:59:59 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Kevin Liu , Alvin Zhang Subject: [PATCH 39/39] net/ice: fix DCF reset Date: Thu, 7 Apr 2022 10:57:06 +0000 Message-Id: <20220407105706.18889-40-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220407105706.18889-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org After the PF triggers the VF reset, before the VF PMD can perform any operations on the hardware, it must reinitialize the all resources. This patch adds a flag to indicate whether the VF has been reset by PF, and update the DCF resetting operations according to this flag. Fixes: 1a86f4dbdf42 ("net/ice: support DCF device reset") Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/base/ice_common.c | 4 +++- drivers/net/ice/ice_dcf.c | 2 +- drivers/net/ice/ice_dcf_ethdev.c | 17 ++++++++++++++++- drivers/net/ice/ice_dcf_parent.c | 3 +++ 4 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 5d5ce894ff..530e766abf 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -779,6 +779,7 @@ enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list); if (status) { ice_free(hw, hw->switch_info); + hw->switch_info = NULL; return status; } return ICE_SUCCESS; @@ -848,7 +849,6 @@ ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw) ice_rm_sw_replay_rule_info(hw, sw); ice_free(hw, sw->buildin_recipes); ice_free(hw, sw->recp_list); - ice_free(hw, sw); } /** @@ -858,6 +858,8 @@ ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw) void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) { ice_cleanup_fltr_mgmt_single(hw, hw->switch_info); + ice_free(hw, hw->switch_info); + hw->switch_info = NULL; } /** diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c index 6b210176a0..dfd6d5ff64 100644 --- a/drivers/net/ice/ice_dcf.c +++ b/drivers/net/ice/ice_dcf.c @@ -1430,7 +1430,7 @@ ice_dcf_cap_reset(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw) int ret; struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); - struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + struct rte_intr_handle *intr_handle = pci_dev->intr_handle; ice_dcf_disable_irq0(hw); rte_intr_disable(intr_handle); diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index b5381cdfc4..e09570cd40 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -1005,6 +1005,15 @@ dcf_add_del_mc_addr_list(struct ice_dcf_hw *hw, uint32_t i; int len, err = 0; + if (hw->resetting) { + if (!add) + return 0; + + PMD_DRV_LOG(ERR, + "fail to add multicast MACs for VF resetting"); + return -EIO; + } + len = sizeof(struct virtchnl_ether_addr_list); len += sizeof(struct virtchnl_ether_addr) * mc_addrs_num; @@ -1643,7 +1652,13 @@ ice_dcf_dev_close(struct rte_eth_dev *dev) if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; - (void)ice_dcf_dev_stop(dev); + if (adapter->parent.pf.adapter_stopped) + (void)ice_dcf_dev_stop(dev); + + if (adapter->real_hw.resetting) { + ice_dcf_uninit_hw(dev, &adapter->real_hw); + ice_dcf_init_hw(dev, &adapter->real_hw); + } ice_free_queues(dev); diff --git a/drivers/net/ice/ice_dcf_parent.c b/drivers/net/ice/ice_dcf_parent.c index 2aa69c7368..2a936bd2c1 100644 --- a/drivers/net/ice/ice_dcf_parent.c +++ b/drivers/net/ice/ice_dcf_parent.c @@ -243,6 +243,9 @@ ice_dcf_handle_pf_event_msg(struct ice_dcf_hw *dcf_hw, case VIRTCHNL_EVENT_RESET_IMPENDING: PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event"); dcf_hw->resetting = true; + rte_eth_dev_callback_process(dcf_hw->eth_dev, + RTE_ETH_EVENT_INTR_RESET, + NULL); break; case VIRTCHNL_EVENT_LINK_CHANGE: PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");