From patchwork Fri Apr 8 08:45:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 109496 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EC3F2A0501; Fri, 8 Apr 2022 11:06:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 89A874067E; Fri, 8 Apr 2022 11:06:44 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id 234B54003F for ; Fri, 8 Apr 2022 11:06:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649408802; x=1680944802; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=WWEC+LTpz5OvtVMcn0nZTKR9Vm/r6ftaQKR6rjBuFlo=; b=D4MAYZuxgrw0/lVXvY9IiEXPgoSDUIRjyi6aQvMpZ8+tzLfusFTaYon0 30StUeJfQyYML3KEfqQKWo/cAQ3wT4MWn2bx/5u2KLGlyoLsbQDYXQQr/ l+W5idViJbV/1VhvYvRWASqPfVGWMrVMWOLsiTy01gzOd+XKtK0Z3WW79 bgsLTPTvIlfg5IAZ+k5B/BO3gXx/nWoolK6vJrNPyp6yRFnLH8fXmym7y OWjMCH6z7b2/I1EkpMDg7ieIWAiLgFNsjHpvSE1+lcPHMUSOG2CFAsRsa S3tNHd/KzjY56ywhjxxrZFP3atfiI1tmwJ0E8yJRxE7AR5fXfRr1wcFOm w==; X-IronPort-AV: E=McAfee;i="6400,9594,10310"; a="261726098" X-IronPort-AV: E=Sophos;i="5.90,244,1643702400"; d="scan'208";a="261726098" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Apr 2022 02:06:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,244,1643702400"; d="scan'208";a="659417829" Received: from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181]) by orsmga004.jf.intel.com with ESMTP; 08 Apr 2022 02:06:35 -0700 From: Wenjun Wu To: dev@dpdk.org, qi.z.zhang@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com Subject: [PATCH v4 1/4] common/iavf: support queue rate limit and quanta size configuration Date: Fri, 8 Apr 2022 16:45:34 +0800 Message-Id: <20220408084537.920685-2-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408084537.920685-1-wenjun1.wu@intel.com> References: <20220329020717.1101263-1-wenjun1.wu@intel.com> <20220408084537.920685-1-wenjun1.wu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds new virtchnl opcodes and structures for rate limit and quanta size configuration, which include: 1. VIRTCHNL_OP_CONFIG_QUEUE_BW, to configure max bandwidth for each VF per queue. 2. VIRTCHNL_OP_CONFIG_QUANTA, to configure quanta size per queue. Signed-off-by: Ting Xu Signed-off-by: Wenjun Wu --- drivers/common/iavf/virtchnl.h | 50 ++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/common/iavf/virtchnl.h b/drivers/common/iavf/virtchnl.h index 3e44eca7d8..249ae6ed23 100644 --- a/drivers/common/iavf/virtchnl.h +++ b/drivers/common/iavf/virtchnl.h @@ -164,6 +164,8 @@ enum virtchnl_ops { VIRTCHNL_OP_ENABLE_QUEUES_V2 = 107, VIRTCHNL_OP_DISABLE_QUEUES_V2 = 108, VIRTCHNL_OP_MAP_QUEUE_VECTOR = 111, + VIRTCHNL_OP_CONFIG_QUEUE_BW = 112, + VIRTCHNL_OP_CONFIG_QUANTA = 113, VIRTCHNL_OP_MAX, }; @@ -1872,6 +1874,23 @@ struct virtchnl_queue_tc_mapping { VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_queue_tc_mapping); +/* VIRTCHNL_OP_CONFIG_QUEUE_BW */ +struct virtchnl_queue_bw { + u16 queue_id; + u8 tc; + u8 pad; + struct virtchnl_shaper_bw shaper; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_queue_bw); + +struct virtchnl_queues_bw_cfg { + u16 vsi_id; + u16 num_queues; + struct virtchnl_queue_bw cfg[1]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_queues_bw_cfg); /* TX and RX queue types are valid in legacy as well as split queue models. * With Split Queue model, 2 additional types are introduced - TX_COMPLETION @@ -1978,6 +1997,12 @@ struct virtchnl_queue_vector_maps { VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_queue_vector_maps); +struct virtchnl_quanta_cfg { + u16 quanta_size; + struct virtchnl_queue_chunk queue_select; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_quanta_cfg); /* Since VF messages are limited by u16 size, precalculate the maximum possible * values of nested elements in virtchnl structures that virtual channel can @@ -2244,6 +2269,31 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode, sizeof(q_tc->tc[0]); } break; + case VIRTCHNL_OP_CONFIG_QUEUE_BW: + valid_len = sizeof(struct virtchnl_queues_bw_cfg); + if (msglen >= valid_len) { + struct virtchnl_queues_bw_cfg *q_bw = + (struct virtchnl_queues_bw_cfg *)msg; + if (q_bw->num_queues == 0) { + err_msg_format = true; + break; + } + valid_len += (q_bw->num_queues - 1) * + sizeof(q_bw->cfg[0]); + } + break; + case VIRTCHNL_OP_CONFIG_QUANTA: + valid_len = sizeof(struct virtchnl_quanta_cfg); + if (msglen >= valid_len) { + struct virtchnl_quanta_cfg *q_quanta = + (struct virtchnl_quanta_cfg *)msg; + if (q_quanta->quanta_size == 0 || + q_quanta->queue_select.num_queues == 0) { + err_msg_format = true; + break; + } + } + break; case VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS: break; case VIRTCHNL_OP_ADD_VLAN_V2: From patchwork Fri Apr 8 08:45:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 109498 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BF634A0501; Fri, 8 Apr 2022 11:06:55 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 468B5427EA; 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08 Apr 2022 02:06:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,244,1643702400"; d="scan'208";a="659417853" Received: from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181]) by orsmga004.jf.intel.com with ESMTP; 08 Apr 2022 02:06:37 -0700 From: Wenjun Wu To: dev@dpdk.org, qi.z.zhang@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com Subject: [PATCH v4 2/4] net/iavf: support queue rate limit configuration Date: Fri, 8 Apr 2022 16:45:35 +0800 Message-Id: <20220408084537.920685-3-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408084537.920685-1-wenjun1.wu@intel.com> References: <20220329020717.1101263-1-wenjun1.wu@intel.com> <20220408084537.920685-1-wenjun1.wu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds queue rate limit configuration support. Only max bandwidth is supported. Signed-off-by: Ting Xu Signed-off-by: Wenjun Wu --- drivers/net/iavf/iavf.h | 13 +++ drivers/net/iavf/iavf_tm.c | 190 ++++++++++++++++++++++++++++++++-- drivers/net/iavf/iavf_vchnl.c | 23 ++++ 3 files changed, 218 insertions(+), 8 deletions(-) diff --git a/drivers/net/iavf/iavf.h b/drivers/net/iavf/iavf.h index a01d18e61b..96515a3ee9 100644 --- a/drivers/net/iavf/iavf.h +++ b/drivers/net/iavf/iavf.h @@ -170,11 +170,21 @@ struct iavf_tm_node { uint32_t weight; uint32_t reference_count; struct iavf_tm_node *parent; + struct iavf_tm_shaper_profile *shaper_profile; struct rte_tm_node_params params; }; TAILQ_HEAD(iavf_tm_node_list, iavf_tm_node); +struct iavf_tm_shaper_profile { + TAILQ_ENTRY(iavf_tm_shaper_profile) node; + uint32_t shaper_profile_id; + uint32_t reference_count; + struct rte_tm_shaper_params profile; +}; + +TAILQ_HEAD(iavf_shaper_profile_list, iavf_tm_shaper_profile); + /* node type of Traffic Manager */ enum iavf_tm_node_type { IAVF_TM_NODE_TYPE_PORT, @@ -188,6 +198,7 @@ struct iavf_tm_conf { struct iavf_tm_node *root; /* root node - vf vsi */ struct iavf_tm_node_list tc_list; /* node list for all the TCs */ struct iavf_tm_node_list queue_list; /* node list for all the queues */ + struct iavf_shaper_profile_list shaper_profile_list; uint32_t nb_tc_node; uint32_t nb_queue_node; bool committed; @@ -451,6 +462,8 @@ int iavf_add_del_mc_addr_list(struct iavf_adapter *adapter, int iavf_request_queues(struct rte_eth_dev *dev, uint16_t num); int iavf_get_max_rss_queue_region(struct iavf_adapter *adapter); int iavf_get_qos_cap(struct iavf_adapter *adapter); +int iavf_set_q_bw(struct rte_eth_dev *dev, + struct virtchnl_queues_bw_cfg *q_bw, uint16_t size); int iavf_set_q_tc_map(struct rte_eth_dev *dev, struct virtchnl_queue_tc_mapping *q_tc_mapping, uint16_t size); diff --git a/drivers/net/iavf/iavf_tm.c b/drivers/net/iavf/iavf_tm.c index 8d92062c7f..32bb3be45e 100644 --- a/drivers/net/iavf/iavf_tm.c +++ b/drivers/net/iavf/iavf_tm.c @@ -8,6 +8,13 @@ static int iavf_hierarchy_commit(struct rte_eth_dev *dev, __rte_unused int clear_on_fail, __rte_unused struct rte_tm_error *error); +static int iavf_shaper_profile_add(struct rte_eth_dev *dev, + uint32_t shaper_profile_id, + struct rte_tm_shaper_params *profile, + struct rte_tm_error *error); +static int iavf_shaper_profile_del(struct rte_eth_dev *dev, + uint32_t shaper_profile_id, + struct rte_tm_error *error); static int iavf_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id, uint32_t parent_node_id, uint32_t priority, uint32_t weight, uint32_t level_id, @@ -30,6 +37,8 @@ static int iavf_node_type_get(struct rte_eth_dev *dev, uint32_t node_id, int *is_leaf, struct rte_tm_error *error); const struct rte_tm_ops iavf_tm_ops = { + .shaper_profile_add = iavf_shaper_profile_add, + .shaper_profile_delete = iavf_shaper_profile_del, .node_add = iavf_tm_node_add, .node_delete = iavf_tm_node_delete, .capabilities_get = iavf_tm_capabilities_get, @@ -44,6 +53,9 @@ iavf_tm_conf_init(struct rte_eth_dev *dev) { struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); + /* initialize shaper profile list */ + TAILQ_INIT(&vf->tm_conf.shaper_profile_list); + /* initialize node configuration */ vf->tm_conf.root = NULL; TAILQ_INIT(&vf->tm_conf.tc_list); @@ -57,6 +69,7 @@ void iavf_tm_conf_uninit(struct rte_eth_dev *dev) { struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); + struct iavf_tm_shaper_profile *shaper_profile; struct iavf_tm_node *tm_node; /* clear node configuration */ @@ -74,6 +87,14 @@ iavf_tm_conf_uninit(struct rte_eth_dev *dev) rte_free(vf->tm_conf.root); vf->tm_conf.root = NULL; } + + /* Remove all shaper profiles */ + while ((shaper_profile = + TAILQ_FIRST(&vf->tm_conf.shaper_profile_list))) { + TAILQ_REMOVE(&vf->tm_conf.shaper_profile_list, + shaper_profile, node); + rte_free(shaper_profile); + } } static inline struct iavf_tm_node * @@ -132,13 +153,6 @@ iavf_node_param_check(struct iavf_info *vf, uint32_t node_id, return -EINVAL; } - /* not support shaper profile */ - if (params->shaper_profile_id) { - error->type = RTE_TM_ERROR_TYPE_NODE_PARAMS_SHAPER_PROFILE_ID; - error->message = "shaper profile not supported"; - return -EINVAL; - } - /* not support shared shaper */ if (params->shared_shaper_id) { error->type = RTE_TM_ERROR_TYPE_NODE_PARAMS_SHARED_SHAPER_ID; @@ -236,6 +250,23 @@ iavf_node_type_get(struct rte_eth_dev *dev, uint32_t node_id, return 0; } +static inline struct iavf_tm_shaper_profile * +iavf_shaper_profile_search(struct rte_eth_dev *dev, + uint32_t shaper_profile_id) +{ + struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); + struct iavf_shaper_profile_list *shaper_profile_list = + &vf->tm_conf.shaper_profile_list; + struct iavf_tm_shaper_profile *shaper_profile; + + TAILQ_FOREACH(shaper_profile, shaper_profile_list, node) { + if (shaper_profile_id == shaper_profile->shaper_profile_id) + return shaper_profile; + } + + return NULL; +} + static int iavf_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id, uint32_t parent_node_id, uint32_t priority, @@ -246,6 +277,7 @@ iavf_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id, struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); enum iavf_tm_node_type node_type = IAVF_TM_NODE_TYPE_MAX; enum iavf_tm_node_type parent_node_type = IAVF_TM_NODE_TYPE_MAX; + struct iavf_tm_shaper_profile *shaper_profile = NULL; struct iavf_tm_node *tm_node; struct iavf_tm_node *parent_node; uint16_t tc_nb = vf->qos_cap->num_elem; @@ -273,6 +305,18 @@ iavf_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id, return -EINVAL; } + /* check the shaper profile id */ + if (params->shaper_profile_id != RTE_TM_SHAPER_PROFILE_ID_NONE) { + shaper_profile = iavf_shaper_profile_search(dev, + params->shaper_profile_id); + if (!shaper_profile) { + error->type = + RTE_TM_ERROR_TYPE_NODE_PARAMS_SHAPER_PROFILE_ID; + error->message = "shaper profile not exist"; + return -EINVAL; + } + } + /* root node if not have a parent */ if (parent_node_id == RTE_TM_NODE_ID_NULL) { /* check level */ @@ -358,6 +402,7 @@ iavf_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id, tm_node->id = node_id; tm_node->reference_count = 0; tm_node->parent = parent_node; + tm_node->shaper_profile = shaper_profile; rte_memcpy(&tm_node->params, params, sizeof(struct rte_tm_node_params)); if (parent_node_type == IAVF_TM_NODE_TYPE_PORT) { @@ -373,6 +418,10 @@ iavf_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id, } tm_node->parent->reference_count++; + /* increase the reference counter of the shaper profile */ + if (shaper_profile) + shaper_profile->reference_count++; + return 0; } @@ -437,6 +486,103 @@ iavf_tm_node_delete(struct rte_eth_dev *dev, uint32_t node_id, return 0; } +static int +iavf_shaper_profile_param_check(struct rte_tm_shaper_params *profile, + struct rte_tm_error *error) +{ + /* min bucket size not supported */ + if (profile->committed.size) { + error->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_COMMITTED_SIZE; + error->message = "committed bucket size not supported"; + return -EINVAL; + } + /* max bucket size not supported */ + if (profile->peak.size) { + error->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PEAK_SIZE; + error->message = "peak bucket size not supported"; + return -EINVAL; + } + /* length adjustment not supported */ + if (profile->pkt_length_adjust) { + error->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PKT_ADJUST_LEN; + error->message = "packet length adjustment not supported"; + return -EINVAL; + } + + return 0; +} + +static int +iavf_shaper_profile_add(struct rte_eth_dev *dev, + uint32_t shaper_profile_id, + struct rte_tm_shaper_params *profile, + struct rte_tm_error *error) +{ + struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); + struct iavf_tm_shaper_profile *shaper_profile; + int ret; + + if (!profile || !error) + return -EINVAL; + + ret = iavf_shaper_profile_param_check(profile, error); + if (ret) + return ret; + + shaper_profile = iavf_shaper_profile_search(dev, shaper_profile_id); + + if (shaper_profile) { + error->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID; + error->message = "profile ID exist"; + return -EINVAL; + } + + shaper_profile = rte_zmalloc("iavf_tm_shaper_profile", + sizeof(struct iavf_tm_shaper_profile), + 0); + if (!shaper_profile) + return -ENOMEM; + shaper_profile->shaper_profile_id = shaper_profile_id; + rte_memcpy(&shaper_profile->profile, profile, + sizeof(struct rte_tm_shaper_params)); + TAILQ_INSERT_TAIL(&vf->tm_conf.shaper_profile_list, + shaper_profile, node); + + return 0; +} + +static int +iavf_shaper_profile_del(struct rte_eth_dev *dev, + uint32_t shaper_profile_id, + struct rte_tm_error *error) +{ + struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); + struct iavf_tm_shaper_profile *shaper_profile; + + if (!error) + return -EINVAL; + + shaper_profile = iavf_shaper_profile_search(dev, shaper_profile_id); + + if (!shaper_profile) { + error->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID; + error->message = "profile ID not exist"; + return -EINVAL; + } + + /* don't delete a profile if it's used by one or several nodes */ + if (shaper_profile->reference_count) { + error->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE; + error->message = "profile in use"; + return -EINVAL; + } + + TAILQ_REMOVE(&vf->tm_conf.shaper_profile_list, shaper_profile, node); + rte_free(shaper_profile); + + return 0; +} + static int iavf_tm_capabilities_get(struct rte_eth_dev *dev, struct rte_tm_capabilities *cap, @@ -656,10 +802,11 @@ static int iavf_hierarchy_commit(struct rte_eth_dev *dev, struct iavf_adapter *adapter = IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); struct virtchnl_queue_tc_mapping *q_tc_mapping; + struct virtchnl_queues_bw_cfg *q_bw; struct iavf_tm_node_list *queue_list = &vf->tm_conf.queue_list; struct iavf_tm_node *tm_node; struct iavf_qtc_map *qtc_map; - uint16_t size; + uint16_t size, size_q; int index = 0, node_committed = 0; int i, ret_val = IAVF_SUCCESS; @@ -691,10 +838,21 @@ static int iavf_hierarchy_commit(struct rte_eth_dev *dev, goto fail_clear; } + size_q = sizeof(*q_bw) + sizeof(q_bw->cfg[0]) * + (vf->num_queue_pairs - 1); + q_bw = rte_zmalloc("q_bw", size_q, 0); + if (!q_bw) { + ret_val = IAVF_ERR_NO_MEMORY; + goto fail_clear; + } + q_tc_mapping->vsi_id = vf->vsi.vsi_id; q_tc_mapping->num_tc = vf->qos_cap->num_elem; q_tc_mapping->num_queue_pairs = vf->num_queue_pairs; + q_bw->vsi_id = vf->vsi.vsi_id; + q_bw->num_queues = vf->num_queue_pairs; + TAILQ_FOREACH(tm_node, queue_list, node) { if (tm_node->tc >= q_tc_mapping->num_tc) { PMD_DRV_LOG(ERR, "TC%d is not enabled", tm_node->tc); @@ -702,6 +860,18 @@ static int iavf_hierarchy_commit(struct rte_eth_dev *dev, goto fail_clear; } q_tc_mapping->tc[tm_node->tc].req.queue_count++; + + if (tm_node->shaper_profile) { + q_bw->cfg[node_committed].queue_id = node_committed; + q_bw->cfg[node_committed].shaper.peak = + tm_node->shaper_profile->profile.peak.rate / + 1000 * IAVF_BITS_PER_BYTE; + q_bw->cfg[node_committed].shaper.committed = + tm_node->shaper_profile->profile.committed.rate / + 1000 * IAVF_BITS_PER_BYTE; + q_bw->cfg[node_committed].tc = tm_node->tc; + } + node_committed++; } @@ -712,6 +882,10 @@ static int iavf_hierarchy_commit(struct rte_eth_dev *dev, goto fail_clear; } + ret_val = iavf_set_q_bw(dev, q_bw, size_q); + if (ret_val) + goto fail_clear; + /* store the queue TC mapping info */ qtc_map = rte_zmalloc("qtc_map", sizeof(struct iavf_qtc_map) * q_tc_mapping->num_tc, 0); diff --git a/drivers/net/iavf/iavf_vchnl.c b/drivers/net/iavf/iavf_vchnl.c index 169e1f2012..537369f736 100644 --- a/drivers/net/iavf/iavf_vchnl.c +++ b/drivers/net/iavf/iavf_vchnl.c @@ -1636,6 +1636,29 @@ int iavf_set_q_tc_map(struct rte_eth_dev *dev, return err; } +int iavf_set_q_bw(struct rte_eth_dev *dev, + struct virtchnl_queues_bw_cfg *q_bw, uint16_t size) +{ + struct iavf_adapter *adapter = + IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); + struct iavf_cmd_info args; + int err; + + memset(&args, 0, sizeof(args)); + args.ops = VIRTCHNL_OP_CONFIG_QUEUE_BW; + args.in_args = (uint8_t *)q_bw; + args.in_args_size = size; + args.out_buffer = vf->aq_resp; + args.out_size = IAVF_AQ_BUF_SZ; + + err = iavf_execute_vf_cmd(adapter, &args, 0); + if (err) + PMD_DRV_LOG(ERR, "Failed to execute command of" + " VIRTCHNL_OP_CONFIG_QUEUE_BW"); + return err; +} + int iavf_add_del_mc_addr_list(struct iavf_adapter *adapter, struct rte_ether_addr *mc_addrs, From patchwork Fri Apr 8 08:45:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 109499 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B77DEA0501; Fri, 8 Apr 2022 11:07:03 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 870A142803; Fri, 8 Apr 2022 11:06:47 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id BE66F4067E for ; Fri, 8 Apr 2022 11:06:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; 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08 Apr 2022 02:06:39 -0700 From: Wenjun Wu To: dev@dpdk.org, qi.z.zhang@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com Subject: [PATCH v4 3/4] net/iavf: support quanta size configuration Date: Fri, 8 Apr 2022 16:45:36 +0800 Message-Id: <20220408084537.920685-4-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408084537.920685-1-wenjun1.wu@intel.com> References: <20220329020717.1101263-1-wenjun1.wu@intel.com> <20220408084537.920685-1-wenjun1.wu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds quanta size configuration support. Quanta size should between 256 and 4096, and be a product of 64. Signed-off-by: Wenjun Wu --- drivers/net/iavf/iavf.h | 3 +++ drivers/net/iavf/iavf_ethdev.c | 38 ++++++++++++++++++++++++++++++++++ drivers/net/iavf/iavf_vchnl.c | 31 +++++++++++++++++++++++++++ 3 files changed, 72 insertions(+) diff --git a/drivers/net/iavf/iavf.h b/drivers/net/iavf/iavf.h index 96515a3ee9..c0a4a47b04 100644 --- a/drivers/net/iavf/iavf.h +++ b/drivers/net/iavf/iavf.h @@ -292,6 +292,7 @@ enum iavf_proto_xtr_type { struct iavf_devargs { uint8_t proto_xtr_dflt; uint8_t proto_xtr[IAVF_MAX_QUEUE_NUM]; + uint16_t quanta_size; }; struct iavf_security_ctx; @@ -467,6 +468,8 @@ int iavf_set_q_bw(struct rte_eth_dev *dev, int iavf_set_q_tc_map(struct rte_eth_dev *dev, struct virtchnl_queue_tc_mapping *q_tc_mapping, uint16_t size); +int iavf_set_vf_quanta_size(struct iavf_adapter *adapter, u16 start_queue_id, + u16 num_queues); void iavf_tm_conf_init(struct rte_eth_dev *dev); void iavf_tm_conf_uninit(struct rte_eth_dev *dev); int iavf_ipsec_crypto_request(struct iavf_adapter *adapter, diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c index d6190ac24a..7d093bdc24 100644 --- a/drivers/net/iavf/iavf_ethdev.c +++ b/drivers/net/iavf/iavf_ethdev.c @@ -34,9 +34,11 @@ /* devargs */ #define IAVF_PROTO_XTR_ARG "proto_xtr" +#define IAVF_QUANTA_SIZE_ARG "quanta_size" static const char * const iavf_valid_args[] = { IAVF_PROTO_XTR_ARG, + IAVF_QUANTA_SIZE_ARG, NULL }; @@ -950,6 +952,9 @@ iavf_dev_start(struct rte_eth_dev *dev) return -1; } + if (iavf_set_vf_quanta_size(adapter, index, num_queue_pairs) != 0) + PMD_DRV_LOG(WARNING, "configure quanta size failed"); + /* If needed, send configure queues msg multiple times to make the * adminq buffer length smaller than the 4K limitation. */ @@ -2092,6 +2097,25 @@ iavf_handle_proto_xtr_arg(__rte_unused const char *key, const char *value, return 0; } +static int +parse_u16(__rte_unused const char *key, const char *value, void *args) +{ + u16 *num = (u16 *)args; + u16 tmp; + + errno = 0; + tmp = strtoull(value, NULL, 10); + if (errno || !tmp) { + PMD_DRV_LOG(WARNING, "%s: \"%s\" is not a valid u16", + key, value); + return -1; + } + + *num = tmp; + + return 0; +} + static int iavf_parse_devargs(struct rte_eth_dev *dev) { struct iavf_adapter *ad = @@ -2118,6 +2142,20 @@ static int iavf_parse_devargs(struct rte_eth_dev *dev) if (ret) goto bail; + ret = rte_kvargs_process(kvlist, IAVF_QUANTA_SIZE_ARG, + &parse_u16, &ad->devargs.quanta_size); + if (ret) + goto bail; + + if (ad->devargs.quanta_size == 0) + ad->devargs.quanta_size = 1024; + + if (ad->devargs.quanta_size < 256 || ad->devargs.quanta_size > 4096 || + ad->devargs.quanta_size & 0x40) { + PMD_INIT_LOG(ERR, "invalid quanta size\n"); + return -EINVAL; + } + bail: rte_kvargs_free(kvlist); return ret; diff --git a/drivers/net/iavf/iavf_vchnl.c b/drivers/net/iavf/iavf_vchnl.c index 537369f736..f9452d14ae 100644 --- a/drivers/net/iavf/iavf_vchnl.c +++ b/drivers/net/iavf/iavf_vchnl.c @@ -1828,3 +1828,34 @@ iavf_ipsec_crypto_request(struct iavf_adapter *adapter, return 0; } + +int +iavf_set_vf_quanta_size(struct iavf_adapter *adapter, u16 start_queue_id, u16 num_queues) +{ + struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(adapter); + struct iavf_cmd_info args; + struct virtchnl_quanta_cfg q_quanta; + int err; + + if (adapter->devargs.quanta_size == 0) + return 0; + + q_quanta.quanta_size = adapter->devargs.quanta_size; + q_quanta.queue_select.type = VIRTCHNL_QUEUE_TYPE_TX; + q_quanta.queue_select.start_queue_id = start_queue_id; + q_quanta.queue_select.num_queues = num_queues; + + args.ops = VIRTCHNL_OP_CONFIG_QUANTA; + args.in_args = (uint8_t *)&q_quanta; + args.in_args_size = sizeof(q_quanta); + args.out_buffer = vf->aq_resp; + args.out_size = IAVF_AQ_BUF_SZ; + + err = iavf_execute_vf_cmd(adapter, &args, 0); + if (err) { + PMD_DRV_LOG(ERR, "Failed to execute command VIRTCHNL_OP_CONFIG_QUANTA"); + return err; + } + + return 0; +} From patchwork Fri Apr 8 08:45:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 109500 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BC4EDA0501; Fri, 8 Apr 2022 11:07:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 63E2F42846; Fri, 8 Apr 2022 11:06:48 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id 43AD540E5A for ; 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d="scan'208";a="659417887" Received: from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181]) by orsmga004.jf.intel.com with ESMTP; 08 Apr 2022 02:06:40 -0700 From: Wenjun Wu To: dev@dpdk.org, qi.z.zhang@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com Subject: [PATCH v4 4/4] doc: add release notes for 22.07 Date: Fri, 8 Apr 2022 16:45:37 +0800 Message-Id: <20220408084537.920685-5-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408084537.920685-1-wenjun1.wu@intel.com> References: <20220329020717.1101263-1-wenjun1.wu@intel.com> <20220408084537.920685-1-wenjun1.wu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for queue rate limit and quanta size configuration Signed-off-by: Wenjun Wu --- doc/guides/rel_notes/release_22_07.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index 42a5f2d990..f1b4057d70 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -55,6 +55,10 @@ New Features Also, make sure to start the actual text at the margin. ======================================================= +* **Updated Intel iavf driver.** + + * Added Tx QoS queue rate limitation support. + * Added quanta size configuration support. Removed Items -------------