From patchwork Thu May 5 17:29:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislaw Kardach X-Patchwork-Id: 110740 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BFA36A00C2; Thu, 5 May 2022 19:30:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1749642825; Thu, 5 May 2022 19:30:28 +0200 (CEST) Received: from mail-lj1-f176.google.com (mail-lj1-f176.google.com [209.85.208.176]) by mails.dpdk.org (Postfix) with ESMTP id 3984140042 for ; Thu, 5 May 2022 19:30:27 +0200 (CEST) Received: by mail-lj1-f176.google.com with SMTP id q130so6486581ljb.5 for ; Thu, 05 May 2022 10:30:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cZBY9ii8Wxi+L9gJ8D5E7imG5MV5WiZ5E/pagL9SWz8=; b=kWr0oC7dE3BprYA4YoZ13lFRczo94oIIuJVyFwtmRZD6Kbt7RxmgfJAP4/poXI8yK3 Z0PygrT/ZCM9q6yfNgCI7TP3qAv3lroXJU89FJn81hOcr0WuQwKzuxe1+Xg8hDma2GAc boBIiBcQqjs4gOk55VCOfTmk/uiY7anJeOSEFhrrWGw3/dOk4kx13qy5POFYgmc1zPM0 GjaP8Uvz7TIMjLrQigPVWaqmIzxjyR99CJGvYdxl9v0bUCMC2rp89neV7bYKSWN3k9zK 4QizM9/gnhEnMQYG/s+Th2Ep7bIEvkODsVcIh1cs8tafCzPIwnAuVyuQ94mgHpsm3jut O4uA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cZBY9ii8Wxi+L9gJ8D5E7imG5MV5WiZ5E/pagL9SWz8=; b=Igcv7FYyep1k0rixvKyyvd06fHvQgzZyznWAIj3eqniBEi529aiyP4SjSl7othlb7Q JY9LyTk9abBOpx2HmJmsc7jv7RyqrKsUjw8Cu+s4uHRknL4YLxKbPO0Av1doo2kdLraV 0a1bgolva4Yf2J1OqA4Xj/Wg8Xx85PUpB99+t9I5GAjfKd4NRPuDJQisesoDlUS5oXtt rx3Aad2rOMN+15HDgUBNAhy5D+8iUlQSXjnP1LfAd+cygGPwzxQBrVIoXXHyY9y3hBhl vST83E0xHf3nHqgdBxaYDJk8lpp8uYAJeoUGMNDCkaFlzrLh7N8Vq/bnvAwcEuwv5L84 Xauw== X-Gm-Message-State: AOAM533623WntHNSE8MY1RkNjLuszGMM8sPUUzi0ZAFajCfIModKygnJ dtncyf1L49elobboX0xjBSnMug== X-Google-Smtp-Source: ABdhPJwd+qWD0ExyP8qDUc9MQk86Ydf6Ft6FiR9TlX2n5S8lLX5OPbAlPUrxQcwbGIeoZmncB4kkfA== X-Received: by 2002:a2e:8e31:0:b0:24f:632:fa9 with SMTP id r17-20020a2e8e31000000b0024f06320fa9mr17295189ljk.185.1651771826714; Thu, 05 May 2022 10:30:26 -0700 (PDT) Received: from localhost.localdomain (89-73-146-138.dynamic.chello.pl. [89.73.146.138]) by smtp.gmail.com with ESMTPSA id z26-20020ac25dfa000000b0047255d21203sm289640lfq.306.2022.05.05.10.30.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 10:30:26 -0700 (PDT) From: Stanislaw Kardach To: Bruce Richardson Cc: Michal Mazurek , dev@dpdk.org, Frank Zhao , Sam Grove , mw@semihalf.com, upstream@semihalf.com, Stanislaw Kardach Subject: [PATCH 01/11] lpm: add a scalar version of lookupx4 function Date: Thu, 5 May 2022 19:29:53 +0200 Message-Id: <20220505173003.3242618-2-kda@semihalf.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220505173003.3242618-1-kda@semihalf.com> References: <20220505173003.3242618-1-kda@semihalf.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Michal Mazurek Add an implementation of the rte_lpm_lookupx4() function for platforms without support for vector operations. Signed-off-by: Michal Mazurek Signed-off-by: Stanislaw Kardach Sponsored-by: Frank Zhao Sponsored-by: Sam Grove --- doc/guides/rel_notes/release_22_07.rst | 5 + lib/lpm/meson.build | 1 + lib/lpm/rte_lpm.h | 4 +- lib/lpm/rte_lpm_scalar.h | 122 +++++++++++++++++++++++++ 4 files changed, 131 insertions(+), 1 deletion(-) create mode 100644 lib/lpm/rte_lpm_scalar.h diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index 88d6e96cc1..067118174b 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -65,6 +65,11 @@ New Features * Added support for promiscuous mode on Windows. * Added support for MTU on Windows. +* **Added scalar version of the LPM library.** + + * Added scalar implementation of ``rte_lpm_lookupx4``. This is a fall-back + implementation for platforms that don't support vector operations. + Removed Items ------------- diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build index 78d91d3421..6b47361fce 100644 --- a/lib/lpm/meson.build +++ b/lib/lpm/meson.build @@ -14,6 +14,7 @@ headers = files('rte_lpm.h', 'rte_lpm6.h') indirect_headers += files( 'rte_lpm_altivec.h', 'rte_lpm_neon.h', + 'rte_lpm_scalar.h', 'rte_lpm_sse.h', 'rte_lpm_sve.h', ) diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h index eb91960e81..b5db6a353a 100644 --- a/lib/lpm/rte_lpm.h +++ b/lib/lpm/rte_lpm.h @@ -405,8 +405,10 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], #endif #elif defined(RTE_ARCH_PPC_64) #include "rte_lpm_altivec.h" -#else +#elif defined(RTE_ARCH_X86) #include "rte_lpm_sse.h" +#else +#include "rte_lpm_scalar.h" #endif #ifdef __cplusplus diff --git a/lib/lpm/rte_lpm_scalar.h b/lib/lpm/rte_lpm_scalar.h new file mode 100644 index 0000000000..991b94e687 --- /dev/null +++ b/lib/lpm/rte_lpm_scalar.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 StarFive + * Copyright(c) 2022 SiFive + * Copyright(c) 2022 Semihalf + */ + +#ifndef _RTE_LPM_SCALAR_H_ +#define _RTE_LPM_SCALAR_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void +rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], + uint32_t defv) +{ + rte_xmm_t i24; + rte_xmm_t i8; + uint32_t tbl[4]; + uint64_t pt, pt2; + const uint32_t *ptbl; + + const rte_xmm_t mask8 = { + .u32 = {UINT8_MAX, UINT8_MAX, UINT8_MAX, UINT8_MAX}}; + + /* + * RTE_LPM_VALID_EXT_ENTRY_BITMASK for 2 LPM entries + * as one 64-bit value (0x0300000003000000). + */ + const uint64_t mask_xv = + ((uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK | + (uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK << 32); + + /* + * RTE_LPM_LOOKUP_SUCCESS for 2 LPM entries + * as one 64-bit value (0x0100000001000000). + */ + const uint64_t mask_v = + ((uint64_t)RTE_LPM_LOOKUP_SUCCESS | + (uint64_t)RTE_LPM_LOOKUP_SUCCESS << 32); + + /* get 4 indexes for tbl24[]. */ + i24.x = ip; + i24.u32[0] >>= CHAR_BIT; + i24.u32[1] >>= CHAR_BIT; + i24.u32[2] >>= CHAR_BIT; + i24.u32[3] >>= CHAR_BIT; + + /* extract values from tbl24[] */ + ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[0]]; + tbl[0] = *ptbl; + ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[1]]; + tbl[1] = *ptbl; + ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[2]]; + tbl[2] = *ptbl; + ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[3]]; + tbl[3] = *ptbl; + + /* get 4 indexes for tbl8[]. */ + i8.x = ip; + i8.u64[0] &= mask8.u64[0]; + i8.u64[1] &= mask8.u64[1]; + + pt = (uint64_t)tbl[0] | + (uint64_t)tbl[1] << 32; + pt2 = (uint64_t)tbl[2] | + (uint64_t)tbl[3] << 32; + + /* search successfully finished for all 4 IP addresses. */ + if (likely((pt & mask_xv) == mask_v) && + likely((pt2 & mask_xv) == mask_v)) { + *(uint64_t *)hop = pt & RTE_LPM_MASKX4_RES; + *(uint64_t *)(hop + 2) = pt2 & RTE_LPM_MASKX4_RES; + return; + } + + if (unlikely((pt & RTE_LPM_VALID_EXT_ENTRY_BITMASK) == + RTE_LPM_VALID_EXT_ENTRY_BITMASK)) { + i8.u32[0] = i8.u32[0] + + (tbl[0] & 0x00FFFFFF) * RTE_LPM_TBL8_GROUP_NUM_ENTRIES; + ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[0]]; + tbl[0] = *ptbl; + } + if (unlikely((pt >> 32 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) == + RTE_LPM_VALID_EXT_ENTRY_BITMASK)) { + i8.u32[1] = i8.u32[1] + + (tbl[1] & 0x00FFFFFF) * RTE_LPM_TBL8_GROUP_NUM_ENTRIES; + ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[1]]; + tbl[1] = *ptbl; + } + if (unlikely((pt2 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) == + RTE_LPM_VALID_EXT_ENTRY_BITMASK)) { + i8.u32[2] = i8.u32[2] + + (tbl[2] & 0x00FFFFFF) * RTE_LPM_TBL8_GROUP_NUM_ENTRIES; + ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[2]]; + tbl[2] = *ptbl; + } + if (unlikely((pt2 >> 32 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) == + RTE_LPM_VALID_EXT_ENTRY_BITMASK)) { + i8.u32[3] = i8.u32[3] + + (tbl[3] & 0x00FFFFFF) * RTE_LPM_TBL8_GROUP_NUM_ENTRIES; + ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[3]]; + tbl[3] = *ptbl; + } + + hop[0] = (tbl[0] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[0] & 0x00FFFFFF : defv; + hop[1] = (tbl[1] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[1] & 0x00FFFFFF : defv; + hop[2] = (tbl[2] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[2] & 0x00FFFFFF : defv; + hop[3] = (tbl[3] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[3] & 0x00FFFFFF : defv; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_LPM_SCALAR_H_ */ From patchwork Thu May 5 17:29:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislaw Kardach X-Patchwork-Id: 110741 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4BB88A00C2; Thu, 5 May 2022 19:30:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2BA4942836; Thu, 5 May 2022 19:30:30 +0200 (CEST) Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) by mails.dpdk.org (Postfix) with ESMTP id 15D0542824 for ; Thu, 5 May 2022 19:30:28 +0200 (CEST) Received: by mail-lf1-f44.google.com with SMTP id h29so8639066lfj.2 for ; Thu, 05 May 2022 10:30:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nYL6pNCthM4VSQpF6G0XvpFSHAYdyD8kms9UXfuP2kw=; b=lCH/UOx16E2eTQlC3CkGrqtu3vOJthIG5C8G8qPqAo+KwR31SaxBBsqKCATSkomLax BMNXL79zrpDAEBygy5gYWadF6RLqpsQA2GBXHMRmc1xJ+qH4q1wEXXhlTS6BBMwdknS0 Xz1FeQZ0Y5NfC8a7+UEgwb0Z9KjTeHT9qP035l9FdzjLC/dPGMeaK1SkVzfRamZ1xFBx xjqL4t7EGQDz8OtbD+Z9k8pMOsNYKXFMIuTw3GBSu2nHPLhiVBrcujJIELQfZ31wTmHI bR1z2okO7jG/zgnFLtACNEyBX//+MCJifnHWmjtYAlo6EGLQqDvcgYi3SE5TJJtVY/Jp sA6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nYL6pNCthM4VSQpF6G0XvpFSHAYdyD8kms9UXfuP2kw=; b=6rHWQIrWmcTxBa7jAx5XMmZllnfAdBzuQFOyCV985TuYRru7TjLDYOJM6Rkeefeokv UOVOSUKXS+BwWWMjar65iJLD6WxUn/UCQJ5fPRKCi67pUfXiy/07yQosdboqcReeQXJN 812sFc+V6O241QumFUV5td2xXeGKYgELWh8CJ69eihB3M4G+1cLLH/mxbOBVXI+rjguT 5Zfly0GAbe2POwxOrOxHQPWqODZ3S2kvOiXbPx2iaQs7Wo3IEXmg0epFnLJXkS/272Ym gh5VvlLErxbvbs4DjNQrs+MLX/CaJ8pQ8p0Ft+sT4HlEQu5UYPF3R4LYofMpLICYq8Tr SKeg== X-Gm-Message-State: AOAM530UpqYbTh8ANzO0l6LcyuD73bBpBOT/y4HTX+FkB/klQg5CBNAx 9mU9yhw1EZhOhxs7CNsmSHt2I6r0JxQYSw== X-Google-Smtp-Source: ABdhPJyza+Anz0ZfIOdnQpzp53CU1aihVFGYzQs26Wv2GIdVsNW5VJ+joU+xoiVNsdmlg+6oXvoPzA== X-Received: by 2002:a05:6512:448:b0:472:3c0e:cf7f with SMTP id y8-20020a056512044800b004723c0ecf7fmr19043976lfk.279.1651771827716; Thu, 05 May 2022 10:30:27 -0700 (PDT) Received: from localhost.localdomain (89-73-146-138.dynamic.chello.pl. [89.73.146.138]) by smtp.gmail.com with ESMTPSA id z26-20020ac25dfa000000b0047255d21203sm289640lfq.306.2022.05.05.10.30.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 10:30:27 -0700 (PDT) From: Stanislaw Kardach To: dev@dpdk.org Cc: Stanislaw Kardach , Frank Zhao , Sam Grove , mw@semihalf.com, upstream@semihalf.com, pbhagavatula@marvell.com Subject: [PATCH 02/11] examples/l3fwd: fix scalar LPM compilation Date: Thu, 5 May 2022 19:29:54 +0200 Message-Id: <20220505173003.3242618-3-kda@semihalf.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220505173003.3242618-1-kda@semihalf.com> References: <20220505173003.3242618-1-kda@semihalf.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The lpm_process_event_pkt() can either process a packet using an architecture specific (defined for X86/SSE, ARM/Neon and PPC64/Altivec) path or a scalar one. The choice is however done using an ifdef pre-processor macro. Because of that the scalar version was apparently not widely excersized/compiled. Due to some copy/paste errors, the scalar logic in lpm_process_event_pkt() retained a "continue" statement where a BAD_PORT should be returned after refactoring of the LPM logic in the l3fwd example. Fixes: 99fc91d18082 ("examples/l3fwd: add event lpm main loop") Cc: pbhagavatula@marvell.com Signed-off-by: Stanislaw Kardach Sponsored-by: Frank Zhao Sponsored-by: Sam Grove --- examples/l3fwd/l3fwd_lpm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/l3fwd/l3fwd_lpm.c b/examples/l3fwd/l3fwd_lpm.c index bec22c44cd..6e1defbf7f 100644 --- a/examples/l3fwd/l3fwd_lpm.c +++ b/examples/l3fwd/l3fwd_lpm.c @@ -248,7 +248,7 @@ lpm_process_event_pkt(const struct lcore_conf *lconf, struct rte_mbuf *mbuf) if (is_valid_ipv4_pkt(ipv4_hdr, mbuf->pkt_len) < 0) { mbuf->port = BAD_PORT; - continue; + return mbuf->port; } /* Update time to live and header checksum */ --(ipv4_hdr->time_to_live); From patchwork Thu May 5 17:29:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislaw Kardach X-Patchwork-Id: 110743 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 32434A00C2; Thu, 5 May 2022 19:30:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EA6AE42838; Thu, 5 May 2022 19:30:32 +0200 (CEST) Received: from mail-lj1-f182.google.com (mail-lj1-f182.google.com [209.85.208.182]) by mails.dpdk.org (Postfix) with ESMTP id 1759942833 for ; Thu, 5 May 2022 19:30:30 +0200 (CEST) Received: by mail-lj1-f182.google.com with SMTP id g16so6493529lja.3 for ; Thu, 05 May 2022 10:30:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/L84mA7V9g6tqXWgHeafxP0DfAq0Q8F7lHA6wwPy1+U=; b=8W+GAkVzQMAXDUWVYjLbcRByZ9D6tLAjZuxctGVogCJ7fm024o7AgHvHQJIyLF++my jutAPXYbgrSxhCeD4znQCXSi9f0UjI9YGadFN1/jociTUZkYJlcefXj3TueunH8Or8vl JhNhxAkJ2xi6OqbFhBeNU7t5G9oVb5GsTVdMVOI/Zd27FlkwuQZwweWaYBxxhK12maOq aAWj9fe0fIkaG8IUc84AiHDXKJiqJNEcFrWioJQJ3BUJz0V//ZFZlSAo6YT0ZDCndqVn Wzzv2CcMCtKj8NWU+qH/AUQynXlOwcIX5Au+NJc47vOqH0h5Jb7DPARso9R/ueZn5m6f mNaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/L84mA7V9g6tqXWgHeafxP0DfAq0Q8F7lHA6wwPy1+U=; b=jL3bLyPXYsRNbNF1Ee5d49ESmTcQK0IcnMlHDLnzoE0lfQZGMe/MCrGA6cMnIY284D 5UmMhLV1IVVNJHrOkiPuL4rhMl5GszO9EM3CFEDZcG9K7yPUz7DCeMKLqzKhn8Ktz/qd 0ic0V/LCVJCrf85dGzVtlHbM/XWecs/TqJLF5uAIRaRoXdeA2Lw+arK74lhNbUEk4sEj JAUCTemS2iFGdw6GuD0ofRmP9/yBPOLTWockOWQh1aQWDNhfgtbwtTo8aQg9EYgQb+cw ceQOZ4qbfiXuwDs2X3SMG7Egr5puelzKGUT5bFS+EJWGAXT+LBk67IOp0LiZIbZlSsbd 5oZw== X-Gm-Message-State: AOAM532TuUjiiXF3w+wkJN6N/9eH5Cg/Xg2OhELes5taNBHJKCqz5+Iu YYADYxBe+0sYf15uLhESyRVXRQ== X-Google-Smtp-Source: ABdhPJyFQzBSXMtLVF6ZpSP4kw3JpiGi3mYzMFGUEWfbBGvol93xYm9zwUWkALz9UK3EJOLULeLf/w== X-Received: by 2002:a05:651c:483:b0:24f:2ae0:61f3 with SMTP id s3-20020a05651c048300b0024f2ae061f3mr17444896ljc.229.1651771828851; Thu, 05 May 2022 10:30:28 -0700 (PDT) Received: from localhost.localdomain (89-73-146-138.dynamic.chello.pl. [89.73.146.138]) by smtp.gmail.com with ESMTPSA id z26-20020ac25dfa000000b0047255d21203sm289640lfq.306.2022.05.05.10.30.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 10:30:28 -0700 (PDT) From: Stanislaw Kardach To: Thomas Monjalon Cc: Michal Mazurek , dev@dpdk.org, Frank Zhao , Sam Grove , mw@semihalf.com, upstream@semihalf.com, Stanislaw Kardach Subject: [PATCH 03/11] eal: add initial support for RISC-V architecture Date: Thu, 5 May 2022 19:29:55 +0200 Message-Id: <20220505173003.3242618-4-kda@semihalf.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220505173003.3242618-1-kda@semihalf.com> References: <20220505173003.3242618-1-kda@semihalf.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Michal Mazurek Add all necessary elements for DPDK to compile and run EAL on SiFive Freedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc) core complex. This includes: - EAL library implementation for rv64imafdc ISA. - meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define is added for architecture identification. - xmm_t structure operation stubs as there is no vector support in the U74 core. Compilation was tested on Ubuntu and Arch Linux using riscv64 toolchain. Two rte_rdtsc() schemes are provided: stable low-resolution using rdtime (default) and unstable high-resolution using rdcycle. User can override the scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of both DPDK and the application. The reasoning for this is as follows. The RISC-V ISA mandates that clock read by rdtime has to be of constant period and synchronized between all hardware threads within 1 tick (chapter 10.1 in version 20191213 of RISC-V spec). However this clock may not be of high-enough frequency for dataplane uses. I.e. on HiFive Unmatched (FU740) it is 1MHz. There is a high-resolution alternative in form of rdcycle which is clocked at the core clock frequency. The drawbacks are that it may be disabled during sleep (WFI) and its frequency might change due to DVFS. The platform is currently marked as linux-only because rte_cycles implementation uses the timebase-frequency device-tree node read through the proc file system. Such approach was chosen because Linux kernel depends on the presence of this device-tree node. The compilation of following modules has been disabled by this commit and will be re-enabled in later commits as fixes are introduced: net/ixgbe, net/memif, net/tap, example/l3fwd. Known checkpatch errors/warnings: - ERROR:COMPLEX_MACRO in rte_atomic.h and rte_cycles.h due to inline assembly declarations. - vector_size compiler attribute used in rte_vect.h directly. - rte_*mb() used directly in rte_atomic.h to reduce code duplication. - __atomic_thread_fence() used to implement rte_atomic_thread_fence(). Signed-off-by: Michal Mazurek Signed-off-by: Stanislaw Kardach Sponsored-by: Frank Zhao Sponsored-by: Sam Grove --- MAINTAINERS | 6 + app/test/test_xmmt_ops.h | 16 ++ config/meson.build | 2 + config/riscv/meson.build | 143 ++++++++++++++++++ config/riscv/riscv64_linux_gcc | 17 +++ config/riscv/riscv64_sifive_u740_linux_gcc | 19 +++ doc/guides/contributing/design.rst | 2 +- .../linux_gsg/cross_build_dpdk_for_riscv.rst | 125 +++++++++++++++ doc/guides/linux_gsg/index.rst | 1 + doc/guides/nics/features.rst | 5 + doc/guides/nics/features/default.ini | 1 + doc/guides/rel_notes/release_22_07.rst | 23 +++ drivers/net/i40e/meson.build | 6 + drivers/net/ixgbe/meson.build | 6 + drivers/net/memif/meson.build | 5 + drivers/net/tap/meson.build | 5 + examples/l3fwd/meson.build | 6 + lib/eal/riscv/include/meson.build | 23 +++ lib/eal/riscv/include/rte_atomic.h | 52 +++++++ lib/eal/riscv/include/rte_byteorder.h | 44 ++++++ lib/eal/riscv/include/rte_cpuflags.h | 55 +++++++ lib/eal/riscv/include/rte_cycles.h | 103 +++++++++++++ lib/eal/riscv/include/rte_io.h | 21 +++ lib/eal/riscv/include/rte_mcslock.h | 18 +++ lib/eal/riscv/include/rte_memcpy.h | 63 ++++++++ lib/eal/riscv/include/rte_pause.h | 31 ++++ lib/eal/riscv/include/rte_pflock.h | 17 +++ lib/eal/riscv/include/rte_power_intrinsics.h | 22 +++ lib/eal/riscv/include/rte_prefetch.h | 50 ++++++ lib/eal/riscv/include/rte_rwlock.h | 44 ++++++ lib/eal/riscv/include/rte_spinlock.h | 67 ++++++++ lib/eal/riscv/include/rte_ticketlock.h | 21 +++ lib/eal/riscv/include/rte_vect.h | 55 +++++++ lib/eal/riscv/meson.build | 11 ++ lib/eal/riscv/rte_cpuflags.c | 122 +++++++++++++++ lib/eal/riscv/rte_cycles.c | 77 ++++++++++ lib/eal/riscv/rte_hypervisor.c | 13 ++ lib/eal/riscv/rte_power_intrinsics.c | 56 +++++++ meson.build | 2 + 39 files changed, 1354 insertions(+), 1 deletion(-) create mode 100644 config/riscv/meson.build create mode 100644 config/riscv/riscv64_linux_gcc create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst create mode 100644 lib/eal/riscv/include/meson.build create mode 100644 lib/eal/riscv/include/rte_atomic.h create mode 100644 lib/eal/riscv/include/rte_byteorder.h create mode 100644 lib/eal/riscv/include/rte_cpuflags.h create mode 100644 lib/eal/riscv/include/rte_cycles.h create mode 100644 lib/eal/riscv/include/rte_io.h create mode 100644 lib/eal/riscv/include/rte_mcslock.h create mode 100644 lib/eal/riscv/include/rte_memcpy.h create mode 100644 lib/eal/riscv/include/rte_pause.h create mode 100644 lib/eal/riscv/include/rte_pflock.h create mode 100644 lib/eal/riscv/include/rte_power_intrinsics.h create mode 100644 lib/eal/riscv/include/rte_prefetch.h create mode 100644 lib/eal/riscv/include/rte_rwlock.h create mode 100644 lib/eal/riscv/include/rte_spinlock.h create mode 100644 lib/eal/riscv/include/rte_ticketlock.h create mode 100644 lib/eal/riscv/include/rte_vect.h create mode 100644 lib/eal/riscv/meson.build create mode 100644 lib/eal/riscv/rte_cpuflags.c create mode 100644 lib/eal/riscv/rte_cycles.c create mode 100644 lib/eal/riscv/rte_hypervisor.c create mode 100644 lib/eal/riscv/rte_power_intrinsics.c diff --git a/MAINTAINERS b/MAINTAINERS index 7c4f541dba..2c732a1912 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -296,6 +296,12 @@ F: drivers/*/*/*_altivec.* F: app/*/*_altivec.* F: examples/*/*_altivec.* +RISC-V +M: Stanislaw Kardach +F: config/riscv/ +F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst +F: lib/eal/riscv/ + Intel x86 M: Bruce Richardson M: Konstantin Ananyev diff --git a/app/test/test_xmmt_ops.h b/app/test/test_xmmt_ops.h index 3a82d5ecac..55f256599e 100644 --- a/app/test/test_xmmt_ops.h +++ b/app/test/test_xmmt_ops.h @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright(c) 2015 Cavium, Inc + * Copyright(c) 2022 StarFive + * Copyright(c) 2022 SiFive + * Copyright(c) 2022 Semihalf */ #ifndef _TEST_XMMT_OPS_H_ @@ -49,6 +52,19 @@ vect_set_epi32(int i3, int i2, int i1, int i0) return data; } +#elif defined(RTE_ARCH_RISCV) + +#define vect_loadu_sil128(p) vect_load_128(p) + +/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */ +static __rte_always_inline xmm_t +vect_set_epi32(int i3, int i2, int i1, int i0) +{ + xmm_t data = (xmm_t){i0, i1, i2, i3}; + + return data; +} + #endif #endif /* _TEST_XMMT_OPS_H_ */ diff --git a/config/meson.build b/config/meson.build index 7134e80e8d..7f7b6c92fd 100644 --- a/config/meson.build +++ b/config/meson.build @@ -121,6 +121,8 @@ if cpu_instruction_set == 'generic' cpu_instruction_set = 'generic' elif host_machine.cpu_family().startswith('ppc') cpu_instruction_set = 'power8' + elif host_machine.cpu_family().startswith('riscv') + cpu_instruction_set = 'riscv' endif endif diff --git a/config/riscv/meson.build b/config/riscv/meson.build new file mode 100644 index 0000000000..0c16c31fc2 --- /dev/null +++ b/config/riscv/meson.build @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Intel Corporation. +# Copyright(c) 2017 Cavium, Inc +# Copyright(c) 2021 PANTHEON.tech s.r.o. +# Copyright(c) 2022 StarFive +# Copyright(c) 2022 SiFive +# Copyright(c) 2022 Semihalf + +if not is_linux + error('Only Linux is supported at this point in time.') +endif + +if not dpdk_conf.get('RTE_ARCH_64') + error('Only 64-bit compiles are supported for this platform type') +endif + +dpdk_conf.set('RTE_ARCH', 'riscv') +dpdk_conf.set('RTE_ARCH_RISCV', 1) +dpdk_conf.set('RTE_FORCE_INTRINSICS', 1) + +# common flags to all riscv builds, with lowest priority +flags_common = [ + ['RTE_ARCH_RISCV', true], + ['RTE_CACHE_LINE_SIZE', 64], + # Set this to true if target emulates U-mode TIME CSR via M or S mode trap. + # This allows to remove a FENCE on rte_rdtsc_precise() as trap effectively + # acts as one. + ['RTE_RISCV_EMU_UTIME', false], + # Set this to true if target emulates U-mode CYCLE CSR via M or S mode trap. + # This allows to remove a FENCE on rte_rdtsc_precise() as trap effectively + # acts as one. + ['RTE_RISCV_EMU_UCYCLE', false], + # Manually set wall time clock frequency for the target. If 0, then it is + # read from /proc/device-tree/cpus/timebase-frequency. This property is + # guaranteed on Linux, as riscv time_init() requires it. + ['RTE_RISCV_TIME_FREQ', 0], +] + +## SoC-specific options. +# The priority is like this: arch > vendor > common. +# +# Note that currently there's no way of getting vendor/microarchitecture id +# values in userspace which is why the logic of choosing the right flag +# combination is strictly based on the values passed from a cross-file. +vendor_generic = { + 'description': 'Generic RISC-V', + 'flags': [ + ['RTE_MACHINE', '"riscv"'], + ['RTE_USE_C11_MEM_MODEL', true], + ['RTE_MAX_LCORE', 128], + ['RTE_MAX_NUMA_NODES', 2] + ], + 'arch_config': { + 'generic': {'machine_args': ['-march=rv64gc']} + } +} + +arch_config_riscv = { + '0x8000000000000007': { + 'machine_args': ['-march=rv64gc', '-mtune=sifive-7-series'], + 'flags': [ + ['RTE_RISCV_EMU_UTIME', true], + ['RTE_RISCV_EMU_UCYCLE', true] + ] + }, +} + +vendor_sifive = { + 'description': 'SiFive', + 'flags': [ + ['RTE_MACHINE', '"riscv"'], + ['RTE_USE_C11_MEM_MODEL', true], + ['RTE_MAX_LCORE', 4], + ['RTE_MAX_NUMA_NODES', 1], + ], + 'arch_config': arch_config_riscv +} + +vendors = { + 'generic': vendor_generic, + '0x489': vendor_sifive +} + +# Native/cross vendor/arch detection +if not meson.is_cross_build() + if machine == 'default' + # default build + vendor_id = 'generic' + arch_id = 'generic' + message('generic RISC-V') + else + vendor_id = 'generic' + arch_id = 'generic' + warning('RISC-V arch discovery not available, using generic!') + endif +else + # cross build + vendor_id = meson.get_cross_property('vendor_id') + arch_id = meson.get_cross_property('arch_id') +endif + +if vendors.has_key(vendor_id) + vendor_config = vendors[vendor_id] +else + error('Unsupported RISC-V vendor: @0@. '.format(vendor_id) + + 'Please add support for it or use the generic ' + + '(-Dmachine=generic) build.') +endif + +message('RISC-V vendor: ' + vendor_config['description']) +message('RISC-V architecture id: ' + arch_id) + +arch_config = vendor_config['arch_config'] +if arch_config.has_key(arch_id) + # use the specified arch_id machine args if found + arch_config = arch_config[arch_id] +else + # unknown micro-architecture id + error('Unsupported architecture @0@ of vendor @1@. ' + .format(arch_id, vendor_id) + + 'Please add support for it or use the generic ' + + '(-Dmachine=generic) build.') +endif + +# Concatenate flags respecting priorities. +dpdk_flags = flags_common + vendor_config['flags'] + arch_config.get('flags', []) + +# apply supported machine args +machine_args = [] # Clear previous machine args +foreach flag: arch_config['machine_args'] + if cc.has_argument(flag) + machine_args += flag + endif +endforeach + +# apply flags +foreach flag: dpdk_flags + if flag.length() > 0 + dpdk_conf.set(flag[0], flag[1]) + endif +endforeach +message('Using machine args: @0@'.format(machine_args)) + diff --git a/config/riscv/riscv64_linux_gcc b/config/riscv/riscv64_linux_gcc new file mode 100644 index 0000000000..04248d7ecb --- /dev/null +++ b/config/riscv/riscv64_linux_gcc @@ -0,0 +1,17 @@ +[binaries] +c = 'riscv64-linux-gnu-gcc' +cpp = 'riscv64-linux-gnu-g++' +ar = 'riscv64-linux-gnu-ar' +strip = 'riscv64-linux-gnu-strip' +pcap-config = '' +pkgconfig = 'riscv64-linux-gnu-pkg-config' + +[host_machine] +system = 'linux' +cpu_family = 'riscv64' +cpu = 'rv64gc' +endian = 'little' + +[properties] +vendor_id = 'generic' +arch_id = 'generic' diff --git a/config/riscv/riscv64_sifive_u740_linux_gcc b/config/riscv/riscv64_sifive_u740_linux_gcc new file mode 100644 index 0000000000..7b5ad2562d --- /dev/null +++ b/config/riscv/riscv64_sifive_u740_linux_gcc @@ -0,0 +1,19 @@ +[binaries] +c = 'riscv64-unknown-linux-gnu-gcc' +cpp = 'riscv64-unknown-linux-gnu-g++' +ar = 'riscv64-unknown-linux-gnu-ar' +strip = 'riscv64-unknown-linux-gnu-strip' +pcap-config = '' +pkgconfig = 'riscv64-unknown-linux-gnu-pkg-config' + +[host_machine] +system = 'linux' +cpu_family = 'riscv64' +cpu = 'rv64gc' +endian = 'little' + +[properties] +vendor_id = '0x489' +arch_id = '0x8000000000000007' +max_lcores = 4 +max_numa_nodes = 1 diff --git a/doc/guides/contributing/design.rst b/doc/guides/contributing/design.rst index d5ca8b4d9c..0383afe5c8 100644 --- a/doc/guides/contributing/design.rst +++ b/doc/guides/contributing/design.rst @@ -42,7 +42,7 @@ Per Architecture Sources The following macro options can be used: * ``RTE_ARCH`` is a string that contains the name of the architecture. -* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures. +* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_RISCV``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures. Per Execution Environment Sources ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst new file mode 100644 index 0000000000..9907b35a1d --- /dev/null +++ b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst @@ -0,0 +1,125 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2020 ARM Corporation. + Copyright(c) 2022 StarFive + Copyright(c) 2022 SiFive + Copyright(c) 2022 Semihalf + +Cross compiling DPDK for RISC-V +=============================== + +This chapter describes how to cross compile DPDK for RISC-V from x86 build +hosts. + +.. note:: + + While it's possible to compile DPDK natively on a RISC-V host, it is + currently recommended to cross-compile as Linux kernel does not offer any + way for userspace to discover the vendor and architecture identifiers of the + CPU and therefore any per-chip optimization options have to be chosen via + a cross-file or ``c_args``. + + +Prerequisites +------------- + + +Linux kernel +~~~~~~~~~~~~ + +It is recommended to use Linux kernel built from +`SiFive Freedom Unleashed SDK `_. + + +Meson prerequisites +~~~~~~~~~~~~~~~~~~~ + +Meson depends on pkgconfig to find the dependencies. +The package ``pkg-config-riscv64-linux-gnu`` is required for RISC-V. +To install it in Ubuntu:: + + sudo apt install pkg-config-riscv64-linux-gnu + + +GNU toolchain +------------- + + +Obtain the cross toolchain +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The build process was tested using: + +* Ubuntu toolchain (the ``crossbuild-essential-riscv64`` package). + +* Latest `RISC-V GNU toolchain + `_ on Ubuntu or Arch + Linux. + +Alternatively the toolchain may be built straight from the source, to do that +follow the instructions on the riscv-gnu-toolchain github page. + + +Unzip and add into the PATH +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This step is only required for the riscv-gnu-toolchain. The Ubuntu toolchain is +in the PATH already. + +.. code-block:: console + + tar -xvf riscv64-glibc-ubuntu-20.04-.tar.gz + export PATH=$PATH:/riscv/bin + + +Cross Compiling DPDK with GNU toolchain using Meson +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To cross-compile DPDK for a desired target machine use the following command:: + + meson cross-build --cross-file + ninja -C cross-build + +For example if the target machine is a generic rv64gc RISC-V, use the following +command:: + + meson riscv64-build-gcc --cross-file config/riscv/riscv64_linux_gcc + ninja -C riscv64-build-gcc + +If riscv-gnu-toolchain is used, binary names should be updated to match. Update the following lines in the cross-file: + +.. code-block:: console + + [binaries] + c = 'riscv64-unknown-linux-gnu-gcc' + cpp = 'riscv64-unknown-linux-gnu-g++' + ar = 'riscv64-unknown-linux-gnu-ar' + strip = 'riscv64-unknown-linux-gnu-strip' + ... + +Some toolchains (such as freedom-u-sdk one) require also setting ``--sysroot``, +otherwise include paths might not be resolved. To do so, add the appropriate +paths to the cross-file: + +.. code-block:: console + + [properties] + ... + c_args = ['--sysroot', ''] + cpp_args = c_args + c_link_args = ['--sysroot', ''] + cpp_link_args = c_link_args + ... + + +Supported cross-compilation targets +----------------------------------- + +Currently the following targets are supported: + +* Generic rv64gc ISA: ``config/riscv/riscv64_linux_gcc`` + +* SiFive U740 SoC: ``config/riscv/riscv64_sifive_u740_linux_gcc`` + +To add a new target support, ``config/riscv/meson.build`` has to be modified by +adding a new vendor/architecture id and a corresponding cross-file has to be +added to ``config/riscv`` directory. diff --git a/doc/guides/linux_gsg/index.rst b/doc/guides/linux_gsg/index.rst index 16a9a67260..747552c385 100644 --- a/doc/guides/linux_gsg/index.rst +++ b/doc/guides/linux_gsg/index.rst @@ -14,6 +14,7 @@ Getting Started Guide for Linux sys_reqs build_dpdk cross_build_dpdk_for_arm64 + cross_build_dpdk_for_riscv linux_drivers build_sample_apps linux_eal_parameters diff --git a/doc/guides/nics/features.rst b/doc/guides/nics/features.rst index 21bedb743f..6c4fa74bc7 100644 --- a/doc/guides/nics/features.rst +++ b/doc/guides/nics/features.rst @@ -855,6 +855,11 @@ x86-64 Support 64bits x86 architecture. +rv64 +---- + +Support 64-bit RISC-V architecture. + .. _nic_features_usage_doc: diff --git a/doc/guides/nics/features/default.ini b/doc/guides/nics/features/default.ini index b1d18ac62c..02198682c6 100644 --- a/doc/guides/nics/features/default.ini +++ b/doc/guides/nics/features/default.ini @@ -74,6 +74,7 @@ ARMv8 = Power8 = x86-32 = x86-64 = +rv64 = Usage doc = Design doc = Perf doc = diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index 067118174b..453591e568 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -55,6 +55,29 @@ New Features Also, make sure to start the actual text at the margin. ======================================================= +* **Added initial RISC-V architecture support.*** + + Added EAL implementation for RISC-V architecture. The initial device the + porting was tested on is a HiFive Unmatched development board based on the + SiFive Freedom U740 SoC. In theory this implementation should work with any + ``rv64gc`` ISA compatible implementation with MMU supporting a reasonable + address space size (U740 uses sv39 MMU). + + * Verified with meson tests. ``fast-tests`` suite passing with default config. + * Verified PMD operation with Intel x520-DA2 NIC (``ixgbe``) and ``test-pmd`` + application. Packet transfer checked using all UIO drivers available for + non-IOMMU platforms: ``uio_pci_generic``, ``vfio-pci noiommu`` and + ``igb_uio``. + * The ``i40e`` PMD driver is disabled on RISC-V as ``rv64gc`` ISA has no + vector operations. + * RISCV support is currently limited to Linux. + * Clang compilation currently not supported due to issues with relocation + relaxation. + * Debug build of ``app/test/dpdk-test`` fails currently on RISC-V due to + seemingly invalid loop and goto jump code generation by GCC in + ``test_ring.c`` where extensive inlining increases the code size beyond the + capability of the generated instruction (JAL: +/-1MB PC-relative). + * **Updated Intel iavf driver.** * Added Tx QoS queue rate limitation support. diff --git a/drivers/net/i40e/meson.build b/drivers/net/i40e/meson.build index efc5f93e35..a4c1c9079a 100644 --- a/drivers/net/i40e/meson.build +++ b/drivers/net/i40e/meson.build @@ -1,6 +1,12 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation +if arch_subdir == 'riscv' + build = false + reason = 'riscv arch not supported' + subdir_done() +endif + cflags += ['-DPF_DRIVER', '-DVF_DRIVER', '-DINTEGRATED_VF', diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build index 162f8d5f46..88539e97d5 100644 --- a/drivers/net/ixgbe/meson.build +++ b/drivers/net/ixgbe/meson.build @@ -1,6 +1,12 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation +if arch_subdir == 'riscv' + build = false + reason = 'riscv arch not supported' + subdir_done() +endif + cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS'] subdir('base') diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build index 680bc8631c..9afb495953 100644 --- a/drivers/net/memif/meson.build +++ b/drivers/net/memif/meson.build @@ -5,6 +5,11 @@ if not is_linux build = false reason = 'only supported on Linux' endif +if arch_subdir == 'riscv' + build = false + reason = 'riscv arch not supported' + subdir_done() +endif sources = files( 'memif_socket.c', diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build index c09713a67b..3efac9ac07 100644 --- a/drivers/net/tap/meson.build +++ b/drivers/net/tap/meson.build @@ -5,6 +5,11 @@ if not is_linux build = false reason = 'only supported on Linux' endif +if arch_subdir == 'riscv' + build = false + reason = 'riscv arch not supported' + subdir_done() +endif sources = files( 'rte_eth_tap.c', 'tap_bpf_api.c', diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build index 0830b3eb31..75fa19b7fe 100644 --- a/examples/l3fwd/meson.build +++ b/examples/l3fwd/meson.build @@ -6,6 +6,12 @@ # To build this example as a standalone application with an already-installed # DPDK instance, use 'make' +if dpdk_conf.has('RTE_ARCH_RISCV') + build = false + reason = 'riscv arch not supported' + subdir_done() +endif + allow_experimental_apis = true deps += ['hash', 'lpm', 'fib', 'eventdev'] sources = files( diff --git a/lib/eal/riscv/include/meson.build b/lib/eal/riscv/include/meson.build new file mode 100644 index 0000000000..d290ed82ed --- /dev/null +++ b/lib/eal/riscv/include/meson.build @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2022 StarFive +# Copyright(c) 2022 SiFive +# Copyright(c) 2022 Semihalf + +arch_headers = files( + 'rte_atomic.h', + 'rte_byteorder.h', + 'rte_cpuflags.h', + 'rte_cycles.h', + 'rte_io.h', + 'rte_mcslock.h', + 'rte_memcpy.h', + 'rte_pause.h', + 'rte_pflock.h', + 'rte_power_intrinsics.h', + 'rte_prefetch.h', + 'rte_rwlock.h', + 'rte_spinlock.h', + 'rte_ticketlock.h', + 'rte_vect.h' +) +install_headers(arch_headers, subdir: get_option('include_subdir_arch')) diff --git a/lib/eal/riscv/include/rte_atomic.h b/lib/eal/riscv/include/rte_atomic.h new file mode 100644 index 0000000000..4b4633c914 --- /dev/null +++ b/lib/eal/riscv/include/rte_atomic.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 StarFive + * Copyright(c) 2022 SiFive + * Copyright(c) 2022 Semihalf + * All rights reserved. + */ + +#ifndef RTE_ATOMIC_RISCV_H +#define RTE_ATOMIC_RISCV_H + +#ifndef RTE_FORCE_INTRINSICS +# error Platform must be built with RTE_FORCE_INTRINSICS +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include "generic/rte_atomic.h" + +#define rte_mb() asm volatile("fence rw, rw" : : : "memory") + +#define rte_wmb() asm volatile("fence w, w" : : : "memory") + +#define rte_rmb() asm volatile("fence r, r" : : : "memory") + +#define rte_smp_mb() rte_mb() + +#define rte_smp_wmb() rte_wmb() + +#define rte_smp_rmb() rte_rmb() + +#define rte_io_mb() asm volatile("fence iorw, iorw" : : : "memory") + +#define rte_io_wmb() asm volatile("fence orw, ow" : : : "memory") + +#define rte_io_rmb() asm volatile("fence ir, ir" : : : "memory") + +static __rte_always_inline void +rte_atomic_thread_fence(int memorder) +{ + __atomic_thread_fence(memorder); +} + +#ifdef __cplusplus +} +#endif + +#endif /* RTE_ATOMIC_RISCV_H */ diff --git a/lib/eal/riscv/include/rte_byteorder.h b/lib/eal/riscv/include/rte_byteorder.h new file mode 100644 index 0000000000..21893505d6 --- /dev/null +++ b/lib/eal/riscv/include/rte_byteorder.h @@ -0,0 +1,44 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Inspired from FreeBSD src/sys/powerpc/include/endian.h + * Copyright(c) 1987, 1991, 1993 + * The Regents of the University of California. All rights reserved. + */ + +#ifndef RTE_BYTEORDER_RISCV_H +#define RTE_BYTEORDER_RISCV_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "generic/rte_byteorder.h" + +#ifndef RTE_BYTE_ORDER +#define RTE_BYTE_ORDER RTE_LITTLE_ENDIAN +#endif + +#define rte_cpu_to_le_16(x) (x) +#define rte_cpu_to_le_32(x) (x) +#define rte_cpu_to_le_64(x) (x) + +#define rte_cpu_to_be_16(x) rte_bswap16(x) +#define rte_cpu_to_be_32(x) rte_bswap32(x) +#define rte_cpu_to_be_64(x) rte_bswap64(x) + +#define rte_le_to_cpu_16(x) (x) +#define rte_le_to_cpu_32(x) (x) +#define rte_le_to_cpu_64(x) (x) + +#define rte_be_to_cpu_16(x) rte_bswap16(x) +#define rte_be_to_cpu_32(x) rte_bswap32(x) +#define rte_be_to_cpu_64(x) rte_bswap64(x) + + +#ifdef __cplusplus +} +#endif + +#endif /* RTE_BYTEORDER_RISCV_H */ diff --git a/lib/eal/riscv/include/rte_cpuflags.h b/lib/eal/riscv/include/rte_cpuflags.h new file mode 100644 index 0000000000..66e787f898 --- /dev/null +++ b/lib/eal/riscv/include/rte_cpuflags.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014 IBM Corporation + * Copyright(c) 2022 StarFive + * Copyright(c) 2022 SiFive + * Copyright(c) 2022 Semihalf + */ + +#ifndef RTE_CPUFLAGS_RISCV_H +#define RTE_CPUFLAGS_RISCV_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Enumeration of all CPU features supported + */ +enum rte_cpu_flag_t { + RTE_CPUFLAG_RISCV_ISA_A, /* Atomic */ + RTE_CPUFLAG_RISCV_ISA_B, /* Bit-Manipulation */ + RTE_CPUFLAG_RISCV_ISA_C, /* Compressed instruction */ + RTE_CPUFLAG_RISCV_ISA_D, /* Double precision floating-point */ + RTE_CPUFLAG_RISCV_ISA_E, /* RV32E ISA */ + RTE_CPUFLAG_RISCV_ISA_F, /* Single precision floating-point */ + RTE_CPUFLAG_RISCV_ISA_G, /* Extension pack (IMAFD, Zicsr, Zifencei) */ + RTE_CPUFLAG_RISCV_ISA_H, /* Hypervisor */ + RTE_CPUFLAG_RISCV_ISA_I, /* RV32I/RV64I/IRV128I base ISA */ + RTE_CPUFLAG_RISCV_ISA_J, /* Dynamic Translation Language */ + RTE_CPUFLAG_RISCV_ISA_K, /* Reserved */ + RTE_CPUFLAG_RISCV_ISA_L, /* Decimal Floating-Point */ + RTE_CPUFLAG_RISCV_ISA_M, /* Integer Multiply/Divide */ + RTE_CPUFLAG_RISCV_ISA_N, /* User-level interrupts */ + RTE_CPUFLAG_RISCV_ISA_O, /* Reserved */ + RTE_CPUFLAG_RISCV_ISA_P, /* Packed-SIMD */ + RTE_CPUFLAG_RISCV_ISA_Q, /* Quad-precision floating-points */ + RTE_CPUFLAG_RISCV_ISA_R, /* Reserved */ + RTE_CPUFLAG_RISCV_ISA_S, /* Supervisor mode */ + RTE_CPUFLAG_RISCV_ISA_T, /* Transactional memory */ + RTE_CPUFLAG_RISCV_ISA_U, /* User mode */ + RTE_CPUFLAG_RISCV_ISA_V, /* Vector */ + RTE_CPUFLAG_RISCV_ISA_W, /* Reserved */ + RTE_CPUFLAG_RISCV_ISA_X, /* Non-standard extension present */ + RTE_CPUFLAG_RISCV_ISA_Y, /* Reserved */ + RTE_CPUFLAG_RISCV_ISA_Z, /* Reserved */ + /* The last item */ + RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */ +}; + +#include "generic/rte_cpuflags.h" + +#ifdef __cplusplus +} +#endif + +#endif /* RTE_CPUFLAGS_RISCV_H */ diff --git a/lib/eal/riscv/include/rte_cycles.h b/lib/eal/riscv/include/rte_cycles.h new file mode 100644 index 0000000000..1eb6e2bad2 --- /dev/null +++ b/lib/eal/riscv/include/rte_cycles.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2015 Cavium, Inc + * Copyright(c) 2022 StarFive + * Copyright(c) 2022 SiFive + * Copyright(c) 2022 Semihalf + */ + +#ifndef RTE_CYCLES_RISCV_H +#define RTE_CYCLES_RISCV_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_cycles.h" + +#ifndef RTE_RISCV_RDTSC_USE_HPM +#define RTE_RISCV_RDTSC_USE_HPM 0 +#endif + +#define RV64_CSRR(reg, value) \ + asm volatile("csrr %0, " #reg : "=r" (value) : : "memory") + +/** Read wall time counter */ +static __rte_always_inline uint64_t +__rte_riscv_rdtime(void) +{ + uint64_t tsc; + RV64_CSRR(time, tsc); + return tsc; +} + +/** Read wall time counter ensuring no re-ordering */ +static __rte_always_inline uint64_t +__rte_riscv_rdtime_precise(void) +{ +#if !defined(RTE_RISCV_EMU_UTIME) + asm volatile("fence" : : : "memory"); +#endif + return __rte_riscv_rdtime(); +} + +/** Read hart cycle counter */ +static __rte_always_inline uint64_t +__rte_riscv_rdcycle(void) +{ + uint64_t tsc; + RV64_CSRR(cycle, tsc); + return tsc; +} + +/** Read hart cycle counter ensuring no re-ordering */ +static __rte_always_inline uint64_t +__rte_riscv_rdcycle_precise(void) +{ +#if !defined(RTE_RISCV_EMU_UCYCLE) + asm volatile("fence" : : : "memory"); +#endif + return __rte_riscv_rdcycle(); +} + +/** + * Read the time base register. + * + * @return + * The time base for this lcore. + */ +static __rte_always_inline uint64_t +rte_rdtsc(void) +{ + /** + * By default TIME userspace counter is used. Although it's frequency + * may not be enough for all applications. + */ + if (!RTE_RISCV_RDTSC_USE_HPM) + return __rte_riscv_rdtime(); + /** + * Alternatively HPM's CYCLE counter may be used. However this counter + * is not guaranteed by ISA to either be stable frequency or always + * enabled for userspace access (it may trap to kernel or firmware). + */ + return __rte_riscv_rdcycle(); +} + +static inline uint64_t +rte_rdtsc_precise(void) +{ + if (!RTE_RISCV_RDTSC_USE_HPM) + return __rte_riscv_rdtime_precise(); + return __rte_riscv_rdcycle_precise(); +} + +static __rte_always_inline uint64_t +rte_get_tsc_cycles(void) +{ + return rte_rdtsc(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* RTE_CYCLES_RISCV_H */ diff --git a/lib/eal/riscv/include/rte_io.h b/lib/eal/riscv/include/rte_io.h new file mode 100644 index 0000000000..29659c9590 --- /dev/null +++ b/lib/eal/riscv/include/rte_io.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2016 Cavium, Inc + * Copyright(c) 2022 StarFive + * Copyright(c) 2022 SiFive + * Copyright(c) 2022 Semihalf + */ + +#ifndef RTE_IO_RISCV_H +#define RTE_IO_RISCV_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_io.h" + +#ifdef __cplusplus +} +#endif + +#endif /* RTE_IO_RISCV_H */ diff --git a/lib/eal/riscv/include/rte_mcslock.h b/lib/eal/riscv/include/rte_mcslock.h new file mode 100644 index 0000000000..b517cd5fc5 --- /dev/null +++ b/lib/eal/riscv/include/rte_mcslock.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019 Arm Limited + */ + +#ifndef RTE_MCSLOCK_RISCV_H +#define RTE_MCSLOCK_RISCV_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_mcslock.h" + +#ifdef __cplusplus +} +#endif + +#endif /* RTE_MCSLOCK_RISCV_H */ diff --git a/lib/eal/riscv/include/rte_memcpy.h b/lib/eal/riscv/include/rte_memcpy.h new file mode 100644 index 0000000000..e34f19396e --- /dev/null +++ b/lib/eal/riscv/include/rte_memcpy.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 StarFive + * Copyright(c) 2022 SiFive + * Copyright(c) 2022 Semihalf + */ + +#ifndef RTE_MEMCPY_RISCV_H +#define RTE_MEMCPY_RISCV_H + +#include +#include + +#include "rte_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_memcpy.h" + +static inline void +rte_mov16(uint8_t *dst, const uint8_t *src) +{ + memcpy(dst, src, 16); +} + +static inline void +rte_mov32(uint8_t *dst, const uint8_t *src) +{ + memcpy(dst, src, 32); +} + +static inline void +rte_mov48(uint8_t *dst, const uint8_t *src) +{ + memcpy(dst, src, 48); +} + +static inline void +rte_mov64(uint8_t *dst, const uint8_t *src) +{ + memcpy(dst, src, 64); +} + +static inline void +rte_mov128(uint8_t *dst, const uint8_t *src) +{ + memcpy(dst, src, 128); +} + +static inline void +rte_mov256(uint8_t *dst, const uint8_t *src) +{ + memcpy(dst, src, 256); +} + +#define rte_memcpy(d, s, n) memcpy((d), (s), (n)) + +#ifdef __cplusplus +} +#endif + +#endif /* RTE_MEMCPY_RISCV_H */ diff --git a/lib/eal/riscv/include/rte_pause.h b/lib/eal/riscv/include/rte_pause.h new file mode 100644 index 0000000000..c24c1f32e8 --- /dev/null +++ b/lib/eal/riscv/include/rte_pause.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 StarFive + * Copyright(c) 2022 SiFive + * Copyright(c) 2022 Semihalf + */ + +#ifndef RTE_PAUSE_RISCV_H +#define RTE_PAUSE_RISCV_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "rte_atomic.h" + +#include "generic/rte_pause.h" + +static inline void rte_pause(void) +{ + /* Insert pause hint directly to be compatible with old compilers. + * This will work even on platforms without Zihintpause extension + * because this is a FENCE hint instruction which evaluates to NOP then. + */ + asm volatile(".int 0x0100000F"::: "memory"); +} + +#ifdef __cplusplus +} +#endif + +#endif /* RTE_PAUSE_RISCV_H */ diff --git a/lib/eal/riscv/include/rte_pflock.h b/lib/eal/riscv/include/rte_pflock.h new file mode 100644 index 0000000000..ce6ca02aca --- /dev/null +++ b/lib/eal/riscv/include/rte_pflock.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021 Microsoft Corporation + */ +#ifndef RTE_PFLOCK_RISCV_H +#define RTE_PFLOCK_RISCV_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_pflock.h" + +#ifdef __cplusplus +} +#endif + +#endif /* RTE_PFLOCK_RISCV_H */ diff --git a/lib/eal/riscv/include/rte_power_intrinsics.h b/lib/eal/riscv/include/rte_power_intrinsics.h new file mode 100644 index 0000000000..636e58e71f --- /dev/null +++ b/lib/eal/riscv/include/rte_power_intrinsics.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 StarFive + * Copyright(c) 2022 SiFive + * Copyright(c) 2022 Semihalf + */ + +#ifndef RTE_POWER_INTRINSIC_RISCV_H +#define RTE_POWER_INTRINSIC_RISCV_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#include "generic/rte_power_intrinsics.h" + +#ifdef __cplusplus +} +#endif + +#endif /* RTE_POWER_INTRINSIC_RISCV_H */ diff --git a/lib/eal/riscv/include/rte_prefetch.h b/lib/eal/riscv/include/rte_prefetch.h new file mode 100644 index 0000000000..966d9e2687 --- /dev/null +++ b/lib/eal/riscv/include/rte_prefetch.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014 IBM Corporation + * Copyright(c) 2022 StarFive + * Copyright(c) 2022 SiFive + * Copyright(c) 2022 Semihalf + */ + +#ifndef RTE_PREFETCH_RISCV_H +#define RTE_PREFETCH_RISCV_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "generic/rte_prefetch.h" + +static inline void rte_prefetch0(const volatile void *p) +{ + RTE_SET_USED(p); +} + +static inline void rte_prefetch1(const volatile void *p) +{ + RTE_SET_USED(p); +} + +static inline void rte_prefetch2(const volatile void *p) +{ + RTE_SET_USED(p); +} + +static inline void rte_prefetch_non_temporal(const volatile void *p) +{ + /* non-temporal version not available, fallback to rte_prefetch0 */ + rte_prefetch0(p); +} + +__rte_experimental +static inline void +rte_cldemote(const volatile void *p) +{ + RTE_SET_USED(p); +} + +#ifdef __cplusplus +} +#endif + +#endif /* RTE_PREFETCH_RISCV_H */ diff --git a/lib/eal/riscv/include/rte_rwlock.h b/lib/eal/riscv/include/rte_rwlock.h new file mode 100644 index 0000000000..9cdaf1b0ef --- /dev/null +++ b/lib/eal/riscv/include/rte_rwlock.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 StarFive + * Copyright(c) 2022 SiFive + * Copyright(c) 2022 Semihalf + */ + +#ifndef RTE_RWLOCK_RISCV_H +#define RTE_RWLOCK_RISCV_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_rwlock.h" + +static inline void +rte_rwlock_read_lock_tm(rte_rwlock_t *rwl) +{ + rte_rwlock_read_lock(rwl); +} + +static inline void +rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl) +{ + rte_rwlock_read_unlock(rwl); +} + +static inline void +rte_rwlock_write_lock_tm(rte_rwlock_t *rwl) +{ + rte_rwlock_write_lock(rwl); +} + +static inline void +rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl) +{ + rte_rwlock_write_unlock(rwl); +} + +#ifdef __cplusplus +} +#endif + +#endif /* RTE_RWLOCK_RISCV_H */ diff --git a/lib/eal/riscv/include/rte_spinlock.h b/lib/eal/riscv/include/rte_spinlock.h new file mode 100644 index 0000000000..6af430735c --- /dev/null +++ b/lib/eal/riscv/include/rte_spinlock.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2015 RehiveTech. All rights reserved. + * Copyright(c) 2022 StarFive + * Copyright(c) 2022 SiFive + * Copyright(c) 2022 Semihalf + */ + +#ifndef RTE_SPINLOCK_RISCV_H +#define RTE_SPINLOCK_RISCV_H + +#ifndef RTE_FORCE_INTRINSICS +# error Platform must be built with RTE_FORCE_INTRINSICS +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "generic/rte_spinlock.h" + +static inline int rte_tm_supported(void) +{ + return 0; +} + +static inline void +rte_spinlock_lock_tm(rte_spinlock_t *sl) +{ + rte_spinlock_lock(sl); /* fall-back */ +} + +static inline int +rte_spinlock_trylock_tm(rte_spinlock_t *sl) +{ + return rte_spinlock_trylock(sl); +} + +static inline void +rte_spinlock_unlock_tm(rte_spinlock_t *sl) +{ + rte_spinlock_unlock(sl); +} + +static inline void +rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr) +{ + rte_spinlock_recursive_lock(slr); /* fall-back */ +} + +static inline void +rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr) +{ + rte_spinlock_recursive_unlock(slr); +} + +static inline int +rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr) +{ + return rte_spinlock_recursive_trylock(slr); +} + +#ifdef __cplusplus +} +#endif + +#endif /* RTE_SPINLOCK_RISCV_H */ diff --git a/lib/eal/riscv/include/rte_ticketlock.h b/lib/eal/riscv/include/rte_ticketlock.h new file mode 100644 index 0000000000..b8d2a4f937 --- /dev/null +++ b/lib/eal/riscv/include/rte_ticketlock.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019 Arm Limited + * Copyright(c) 2022 StarFive + * Copyright(c) 2022 SiFive + * Copyright(c) 2022 Semihalf + */ + +#ifndef RTE_TICKETLOCK_RISCV_H +#define RTE_TICKETLOCK_RISCV_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_ticketlock.h" + +#ifdef __cplusplus +} +#endif + +#endif /* RTE_TICKETLOCK_RISCV_H */ diff --git a/lib/eal/riscv/include/rte_vect.h b/lib/eal/riscv/include/rte_vect.h new file mode 100644 index 0000000000..4600521c20 --- /dev/null +++ b/lib/eal/riscv/include/rte_vect.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 StarFive + * Copyright(c) 2022 SiFive + * Copyright(c) 2022 Semihalf + */ + +#ifndef RTE_VECT_RISCV_H +#define RTE_VECT_RISCV_H + +#include +#include "generic/rte_vect.h" +#include "rte_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define RTE_VECT_DEFAULT_SIMD_BITWIDTH RTE_VECT_SIMD_DISABLED + +typedef int32_t xmm_t __attribute__((vector_size(16))); + +#define XMM_SIZE (sizeof(xmm_t)) +#define XMM_MASK (XMM_SIZE - 1) + +typedef union rte_xmm { + xmm_t x; + uint8_t u8[XMM_SIZE / sizeof(uint8_t)]; + uint16_t u16[XMM_SIZE / sizeof(uint16_t)]; + uint32_t u32[XMM_SIZE / sizeof(uint32_t)]; + uint64_t u64[XMM_SIZE / sizeof(uint64_t)]; + double pd[XMM_SIZE / sizeof(double)]; +} __rte_aligned(8) rte_xmm_t; + +static inline xmm_t +vect_load_128(void *p) +{ + xmm_t ret = *((xmm_t *)p); + return ret; +} + +static inline xmm_t +vect_and(xmm_t data, xmm_t mask) +{ + rte_xmm_t ret = (rte_xmm_t)data; + rte_xmm_t m = (rte_xmm_t)mask; + ret.u64[0] &= m.u64[0]; + ret.u64[1] &= m.u64[1]; + return ret.x; +} + +#ifdef __cplusplus +} +#endif + +#endif /* RTE_VECT_RISCV_H */ diff --git a/lib/eal/riscv/meson.build b/lib/eal/riscv/meson.build new file mode 100644 index 0000000000..6ec53ea03a --- /dev/null +++ b/lib/eal/riscv/meson.build @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2017 Intel Corporation. + +subdir('include') + +sources += files( + 'rte_cpuflags.c', + 'rte_cycles.c', + 'rte_hypervisor.c', + 'rte_power_intrinsics.c', +) diff --git a/lib/eal/riscv/rte_cpuflags.c b/lib/eal/riscv/rte_cpuflags.c new file mode 100644 index 0000000000..4f6d29b947 --- /dev/null +++ b/lib/eal/riscv/rte_cpuflags.c @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 StarFive + * Copyright(c) 2022 SiFive + * Copyright(c) 2022 Semihalf + */ + +#include "rte_cpuflags.h" + +#include +#include +#include +#include +#include + +#ifndef AT_HWCAP +#define AT_HWCAP 16 +#endif + +#ifndef AT_HWCAP2 +#define AT_HWCAP2 26 +#endif + +#ifndef AT_PLATFORM +#define AT_PLATFORM 15 +#endif + +enum cpu_register_t { + REG_NONE = 0, + REG_HWCAP, + REG_HWCAP2, + REG_PLATFORM, + REG_MAX +}; + +typedef uint32_t hwcap_registers_t[REG_MAX]; + +/** + * Struct to hold a processor feature entry + */ +struct feature_entry { + uint32_t reg; + uint32_t bit; +#define CPU_FLAG_NAME_MAX_LEN 64 + char name[CPU_FLAG_NAME_MAX_LEN]; +}; + +#define FEAT_DEF(name, reg, bit) \ + [RTE_CPUFLAG_##name] = {reg, bit, #name}, + +typedef Elf64_auxv_t _Elfx_auxv_t; + +const struct feature_entry rte_cpu_feature_table[] = { + FEAT_DEF(RISCV_ISA_A, REG_HWCAP, 0) + FEAT_DEF(RISCV_ISA_B, REG_HWCAP, 1) + FEAT_DEF(RISCV_ISA_C, REG_HWCAP, 2) + FEAT_DEF(RISCV_ISA_D, REG_HWCAP, 3) + FEAT_DEF(RISCV_ISA_E, REG_HWCAP, 4) + FEAT_DEF(RISCV_ISA_F, REG_HWCAP, 5) + FEAT_DEF(RISCV_ISA_G, REG_HWCAP, 6) + FEAT_DEF(RISCV_ISA_H, REG_HWCAP, 7) + FEAT_DEF(RISCV_ISA_I, REG_HWCAP, 8) + FEAT_DEF(RISCV_ISA_J, REG_HWCAP, 9) + FEAT_DEF(RISCV_ISA_K, REG_HWCAP, 10) + FEAT_DEF(RISCV_ISA_L, REG_HWCAP, 11) + FEAT_DEF(RISCV_ISA_M, REG_HWCAP, 12) + FEAT_DEF(RISCV_ISA_N, REG_HWCAP, 13) + FEAT_DEF(RISCV_ISA_O, REG_HWCAP, 14) + FEAT_DEF(RISCV_ISA_P, REG_HWCAP, 15) + FEAT_DEF(RISCV_ISA_Q, REG_HWCAP, 16) + FEAT_DEF(RISCV_ISA_R, REG_HWCAP, 17) + FEAT_DEF(RISCV_ISA_S, REG_HWCAP, 18) + FEAT_DEF(RISCV_ISA_T, REG_HWCAP, 19) + FEAT_DEF(RISCV_ISA_U, REG_HWCAP, 20) + FEAT_DEF(RISCV_ISA_V, REG_HWCAP, 21) + FEAT_DEF(RISCV_ISA_W, REG_HWCAP, 22) + FEAT_DEF(RISCV_ISA_X, REG_HWCAP, 23) + FEAT_DEF(RISCV_ISA_Y, REG_HWCAP, 24) + FEAT_DEF(RISCV_ISA_Z, REG_HWCAP, 25) +}; +/* + * Read AUXV software register and get cpu features for ARM + */ +static void +rte_cpu_get_features(hwcap_registers_t out) +{ + out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP); + out[REG_HWCAP2] = rte_cpu_getauxval(AT_HWCAP2); +} + +/* + * Checks if a particular flag is available on current machine. + */ +int +rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) +{ + const struct feature_entry *feat; + hwcap_registers_t regs = {0}; + + if (feature >= RTE_CPUFLAG_NUMFLAGS) + return -ENOENT; + + feat = &rte_cpu_feature_table[feature]; + if (feat->reg == REG_NONE) + return -EFAULT; + + rte_cpu_get_features(regs); + return (regs[feat->reg] >> feat->bit) & 1; +} + +const char * +rte_cpu_get_flag_name(enum rte_cpu_flag_t feature) +{ + if (feature >= RTE_CPUFLAG_NUMFLAGS) + return NULL; + return rte_cpu_feature_table[feature].name; +} + +void +rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics) +{ + memset(intrinsics, 0, sizeof(*intrinsics)); +} diff --git a/lib/eal/riscv/rte_cycles.c b/lib/eal/riscv/rte_cycles.c new file mode 100644 index 0000000000..358f271311 --- /dev/null +++ b/lib/eal/riscv/rte_cycles.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2015 Cavium, Inc + * Copyright(c) 2022 StarFive + * Copyright(c) 2022 SiFive + * Copyright(c) 2022 Semihalf + */ + +#include + +#include "eal_private.h" +#include "rte_byteorder.h" +#include "rte_cycles.h" +#include "rte_log.h" + +/** Read generic counter frequency */ +static uint64_t +__rte_riscv_timefrq(void) +{ +#define TIMEBASE_FREQ_SIZE 8 + if (RTE_RISCV_TIME_FREQ > 0) + return RTE_RISCV_TIME_FREQ; + uint8_t buf[TIMEBASE_FREQ_SIZE]; + ssize_t cnt; + FILE *file; + + file = fopen("/proc/device-tree/cpus/timebase-frequency", "rb"); + if (!file) + goto fail; + + cnt = fread(buf, 1, TIMEBASE_FREQ_SIZE, file); + fclose(file); + switch (cnt) { + case 8: + return rte_be_to_cpu_64(*(uint64_t *)buf); + case 4: + return rte_be_to_cpu_32(*(uint32_t *)buf); + default: + break; + } +fail: + RTE_LOG(WARNING, EAL, "Unable to read timebase-frequency from FDT.\n"); + return 0; +} + +uint64_t +get_tsc_freq_arch(void) +{ + RTE_LOG(NOTICE, EAL, "TSC using RISC-V %s.\n", + RTE_RISCV_RDTSC_USE_HPM ? "rdcycle" : "rdtime"); + if (!RTE_RISCV_RDTSC_USE_HPM) + return __rte_riscv_timefrq(); +#define CYC_PER_1MHZ 1E6 + /* + * Use real time clock to estimate current cycle frequency + */ + uint64_t ticks, frq; + uint64_t start_ticks, cur_ticks; + uint64_t start_cycle, end_cycle; + + /* Do not proceed unless clock frequency can be obtained. */ + frq = __rte_riscv_timefrq(); + if (!frq) + return 0; + + /* Number of ticks for 1/10 second */ + ticks = frq / 10; + + start_ticks = __rte_riscv_rdtime_precise(); + start_cycle = rte_rdtsc_precise(); + do { + cur_ticks = __rte_riscv_rdtime(); + } while ((cur_ticks - start_ticks) < ticks); + end_cycle = rte_rdtsc_precise(); + + /* Adjust the cycles to next 1Mhz */ + return RTE_ALIGN_MUL_CEIL((end_cycle - start_cycle) * 10, CYC_PER_1MHZ); +} diff --git a/lib/eal/riscv/rte_hypervisor.c b/lib/eal/riscv/rte_hypervisor.c new file mode 100644 index 0000000000..92b5435993 --- /dev/null +++ b/lib/eal/riscv/rte_hypervisor.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 StarFive + * Copyright(c) 2022 SiFive + * Copyright(c) 2022 Semihalf + */ + +#include "rte_hypervisor.h" + +enum rte_hypervisor +rte_hypervisor_get(void) +{ + return RTE_HYPERVISOR_UNKNOWN; +} diff --git a/lib/eal/riscv/rte_power_intrinsics.c b/lib/eal/riscv/rte_power_intrinsics.c new file mode 100644 index 0000000000..240e7b6b87 --- /dev/null +++ b/lib/eal/riscv/rte_power_intrinsics.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 StarFive + * Copyright(c) 2022 SiFive + * Copyright(c) 2022 Semihalf + */ + +#include "rte_power_intrinsics.h" + +/** + * This function is not supported on RISC-V 64 + */ +int +rte_power_monitor(const struct rte_power_monitor_cond *pmc, + const uint64_t tsc_timestamp) +{ + RTE_SET_USED(pmc); + RTE_SET_USED(tsc_timestamp); + + return -ENOTSUP; +} + +/** + * This function is not supported on RISC-V 64 + */ +int +rte_power_pause(const uint64_t tsc_timestamp) +{ + RTE_SET_USED(tsc_timestamp); + + return -ENOTSUP; +} + +/** + * This function is not supported on RISC-V 64 + */ +int +rte_power_monitor_wakeup(const unsigned int lcore_id) +{ + RTE_SET_USED(lcore_id); + + return -ENOTSUP; +} + +/** + * This function is not supported on RISC-V 64 + */ +int +rte_power_monitor_multi(const struct rte_power_monitor_cond pmc[], + const uint32_t num, const uint64_t tsc_timestamp) +{ + RTE_SET_USED(pmc); + RTE_SET_USED(num); + RTE_SET_USED(tsc_timestamp); + + return -ENOTSUP; +} diff --git a/meson.build b/meson.build index 937f6110c0..a8db04a1ee 100644 --- a/meson.build +++ b/meson.build @@ -50,6 +50,8 @@ elif host_machine.cpu_family().startswith('arm') or host_machine.cpu_family().st arch_subdir = 'arm' elif host_machine.cpu_family().startswith('ppc') arch_subdir = 'ppc' +elif host_machine.cpu_family().startswith('riscv') + arch_subdir = 'riscv' endif # configure the build, and make sure configs here and in config folder are From patchwork Thu May 5 17:29:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislaw Kardach X-Patchwork-Id: 110742 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9EDD8A00C2; Thu, 5 May 2022 19:30:47 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0FE7D4281F; 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[89.73.146.138]) by smtp.gmail.com with ESMTPSA id z26-20020ac25dfa000000b0047255d21203sm289640lfq.306.2022.05.05.10.30.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 10:30:29 -0700 (PDT) From: Stanislaw Kardach To: Haiyue Wang Cc: Stanislaw Kardach , dev@dpdk.org, Frank Zhao , Sam Grove , mw@semihalf.com, upstream@semihalf.com Subject: [PATCH 04/11] net/ixgbe: enable vector stubs for RISC-V Date: Thu, 5 May 2022 19:29:56 +0200 Message-Id: <20220505173003.3242618-5-kda@semihalf.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220505173003.3242618-1-kda@semihalf.com> References: <20220505173003.3242618-1-kda@semihalf.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Re-use vector processing stubs in ixgbe PMD defined for PPC for RISC-V. This enables ixgbe PMD usage in scalar mode on this architecture. The ixgbe PMD driver was validated with Intel X520-DA2 NIC and the test-pmd application. Packet transfer checked using all UIO drivers available for non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and igb_uio. Signed-off-by: Stanislaw Kardach Sponsored-by: Frank Zhao Sponsored-by: Sam Grove --- doc/guides/nics/features/ixgbe.ini | 1 + drivers/net/ixgbe/ixgbe_rxtx.c | 4 ++-- drivers/net/ixgbe/meson.build | 6 ------ 3 files changed, 3 insertions(+), 8 deletions(-) diff --git a/doc/guides/nics/features/ixgbe.ini b/doc/guides/nics/features/ixgbe.ini index c5333d1142..b776ca1cf1 100644 --- a/doc/guides/nics/features/ixgbe.ini +++ b/doc/guides/nics/features/ixgbe.ini @@ -54,6 +54,7 @@ Windows = Y ARMv8 = Y x86-32 = Y x86-64 = Y +rv64 = Y [rte_flow items] eth = Y diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index 9e8ea366a5..009d9b624a 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -5957,8 +5957,8 @@ ixgbe_config_rss_filter(struct rte_eth_dev *dev, return 0; } -/* Stubs needed for linkage when RTE_ARCH_PPC_64 is set */ -#if defined(RTE_ARCH_PPC_64) +/* Stubs needed for linkage when RTE_ARCH_PPC_64 or RTE_ARCH_RISCV is set */ +#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_RISCV) int ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev) { diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build index 88539e97d5..162f8d5f46 100644 --- a/drivers/net/ixgbe/meson.build +++ b/drivers/net/ixgbe/meson.build @@ -1,12 +1,6 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation -if arch_subdir == 'riscv' - build = false - reason = 'riscv arch not supported' - subdir_done() -endif - cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS'] subdir('base') From patchwork Thu May 5 17:29:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislaw Kardach X-Patchwork-Id: 110744 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 25388A00C2; Thu, 5 May 2022 19:31:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2A68242842; Thu, 5 May 2022 19:30:34 +0200 (CEST) Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) by mails.dpdk.org (Postfix) with ESMTP id 295724282B for ; Thu, 5 May 2022 19:30:31 +0200 (CEST) Received: by mail-lf1-f52.google.com with SMTP id bu29so8677287lfb.0 for ; Thu, 05 May 2022 10:30:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EBdI1LWmwlmztdZHTFS3GlDR4JFoY38ZJCnGBf0izmE=; b=l77uJ6vFFwbpu9ga/8ItiNohP08uxqqxHsUeZMYQI03S4xQ3pjCIIEUAm/z+axnJ4B nSO5tvas/WSegcLgEYTHMrgDfo4Rf9Wtk1YGA08jDkPyVpOEI+NAm2zi+CIk+YWRfUfe cpWXU2coNfuBWpAn5ELV7MkOD1nyhKbu1v8GNHUFoCC5fZ0RLK/vi+1jLliEvlnDlTdi bUS/XwB+7SpkhsEI2WHMHbPpRxN7V61HMT2czGs6Ki7t5zKNlvBkWHxt1KLaFl0gKWEW XlfmoJCdrwXnlsJpq26suAdVMzzbEGOk+Q70ZeNEiJTYgeSvJNVb9+tkvHFcC0eSeWrj 24pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EBdI1LWmwlmztdZHTFS3GlDR4JFoY38ZJCnGBf0izmE=; b=meMxdU8RG7S+kgxJb27qY6xH1pKZDhseJPpeHOXWxkogvFL7pXqTHNzuechYZd17KJ AlWrxbzxIu6shARYIgol0NvsnyNeDAr8SQJoVRVLy/rvmEiKVpuOfKMM4M4eI018CxM0 cdpWVbX4eFU3+4lu2dmCmOwqsnTKEbO8/IKoKW73+XKxbkLQm2wf9LdmkX3RvEV1dUOS mHRmT6ZjCw5dkgWeBsndrmmoAC4yv1bg1yc+A9Qvx9FNNegLSo99z/SoQL02gUWTehB9 YUQ35pL0gLGXXv4VuAJhq1j87ZJq+Nv/CVr+xXmrzcAoqvfNe/ABUtHbLd9sNI+hTTSw FaGA== X-Gm-Message-State: AOAM531urpmXj1rwkCdCRUFKrCrhnwjgoCo3rHawKfde1pMXHuoHZ1L8 MWAKP0Oh9H0B4ddVOa0DKBfjHA== X-Google-Smtp-Source: ABdhPJyGPIxZEEezu6KT7XKQicncKjeOSdJwHL36dRbdwOom7w2bd6V3rSmhIQbB+0S1zjm452YqIw== X-Received: by 2002:a05:6512:2203:b0:473:b472:98d4 with SMTP id h3-20020a056512220300b00473b47298d4mr8464713lfu.533.1651771830774; Thu, 05 May 2022 10:30:30 -0700 (PDT) Received: from localhost.localdomain (89-73-146-138.dynamic.chello.pl. [89.73.146.138]) by smtp.gmail.com with ESMTPSA id z26-20020ac25dfa000000b0047255d21203sm289640lfq.306.2022.05.05.10.30.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 10:30:30 -0700 (PDT) From: Stanislaw Kardach To: Jakub Grajciar Cc: Stanislaw Kardach , dev@dpdk.org, Frank Zhao , Sam Grove , mw@semihalf.com, upstream@semihalf.com Subject: [PATCH 05/11] net/memif: set memfd syscall ID on RISC-V Date: Thu, 5 May 2022 19:29:57 +0200 Message-Id: <20220505173003.3242618-6-kda@semihalf.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220505173003.3242618-1-kda@semihalf.com> References: <20220505173003.3242618-1-kda@semihalf.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Define the missing __NR_memfd_create syscall id to enable the memif PMD. Signed-off-by: Stanislaw Kardach --- drivers/net/memif/meson.build | 5 ----- drivers/net/memif/rte_eth_memif.h | 2 ++ 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build index 9afb495953..680bc8631c 100644 --- a/drivers/net/memif/meson.build +++ b/drivers/net/memif/meson.build @@ -5,11 +5,6 @@ if not is_linux build = false reason = 'only supported on Linux' endif -if arch_subdir == 'riscv' - build = false - reason = 'riscv arch not supported' - subdir_done() -endif sources = files( 'memif_socket.c', diff --git a/drivers/net/memif/rte_eth_memif.h b/drivers/net/memif/rte_eth_memif.h index a5ee23d42e..81e7dceae0 100644 --- a/drivers/net/memif/rte_eth_memif.h +++ b/drivers/net/memif/rte_eth_memif.h @@ -180,6 +180,8 @@ const char *memif_version(void); #define __NR_memfd_create 360 #elif defined __i386__ #define __NR_memfd_create 356 +#elif defined __riscv +#define __NR_memfd_create 279 #else #error "__NR_memfd_create unknown for this architecture" #endif From patchwork Thu May 5 17:29:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislaw Kardach X-Patchwork-Id: 110745 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 41937A00C2; Thu, 5 May 2022 19:31:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1976342848; Thu, 5 May 2022 19:30:35 +0200 (CEST) Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) by mails.dpdk.org (Postfix) with ESMTP id 1378542828 for ; Thu, 5 May 2022 19:30:32 +0200 (CEST) Received: by mail-lf1-f44.google.com with SMTP id h29so8639066lfj.2 for ; Thu, 05 May 2022 10:30:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b03o/0bd6DDrP2rPbOVsvu56wRO7aTzNJUFwnYqOJ9k=; b=7rgTKzVM796OmbpQEa18SgqgIuXIyqsFeqXMUmgWueE0BbV8bGz0UZUIa93KsK6pUm yvVF0rJytl92QiCBNLDScnEHr8IVrbErNGPDmVEk7O64plBILMO4B7tUMEh/WiOT/kIt GhrRHnSkfYQBDJt/Uwzrf2pIxUgp88oSuL3FnACwxI03wnQOhyBc3CyALC+rfyJ5DSvP Wt78RwYDb5jFHwX6kNzOdMoROnKbZXw237w4Doav2RDOhbochaITHFI6R6ma41cFu3eb YPijOTJPH99OQF5Vc9QvkUwrkpUNDyo4ODdahPuVFzmljzzf4FOb6bqeG3A3DBuqDMiZ 1iGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b03o/0bd6DDrP2rPbOVsvu56wRO7aTzNJUFwnYqOJ9k=; b=sXANuhCFoTCgNBQYUpsActWVcKpjQ6MxtdZrrwhkF1Mr50ztHsorugV3iey2N1yr8m g7uzVE219LM86Wgc5TXcdSuZKcFCSJo/p5mRwC0+yK9ILIa/0xvq1ZlQ3C5AGfN2ZgbP yrlmRvaIIDvNv31ojaGZsT7JLSJEMrxkYbFUQYQKGrtEh0G2RedIYNBTC/RWZUWFyD9c dKH9/BIA5w8lJPTMhmxWQuCYVL7zgy98ixOKJ/1hovo8RMH4HpRpLc7+fJvOscYcJQR9 HsOli07Ub01/oWug36MyjN92jQoS1TvLv93CpsNiO8IDZtpJnRHHrss2/6DdQ9t28lCi djOg== X-Gm-Message-State: AOAM531b+rICktKQAaKHEQYnaDCro1Fb7ak9Um6SBTSY4Q6aqBdR2IJo jdGF0I3T9jLLaGZQulDinf807hUsdpYeaw== X-Google-Smtp-Source: ABdhPJxIeRNYrSWKOKBR6bIBQKADGtcoRLF4IPrEdLMOLgc+3PVcL9pa1sC0Dd0WOf1g0C9mJxZopg== X-Received: by 2002:a19:3852:0:b0:473:dc7b:cd1 with SMTP id d18-20020a193852000000b00473dc7b0cd1mr1828647lfj.549.1651771831829; Thu, 05 May 2022 10:30:31 -0700 (PDT) Received: from localhost.localdomain (89-73-146-138.dynamic.chello.pl. [89.73.146.138]) by smtp.gmail.com with ESMTPSA id z26-20020ac25dfa000000b0047255d21203sm289640lfq.306.2022.05.05.10.30.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 10:30:31 -0700 (PDT) From: Stanislaw Kardach To: dev@dpdk.org Cc: Stanislaw Kardach , Frank Zhao , Sam Grove , mw@semihalf.com, upstream@semihalf.com Subject: [PATCH 06/11] net/tap: set BPF syscall ID for RISC-V Date: Thu, 5 May 2022 19:29:58 +0200 Message-Id: <20220505173003.3242618-7-kda@semihalf.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220505173003.3242618-1-kda@semihalf.com> References: <20220505173003.3242618-1-kda@semihalf.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Define the missing __NR_bpf syscall id to enable the tap PMD. Signed-off-by: Stanislaw Kardach --- drivers/net/tap/meson.build | 5 ----- drivers/net/tap/tap_bpf.h | 2 ++ 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build index 3efac9ac07..c09713a67b 100644 --- a/drivers/net/tap/meson.build +++ b/drivers/net/tap/meson.build @@ -5,11 +5,6 @@ if not is_linux build = false reason = 'only supported on Linux' endif -if arch_subdir == 'riscv' - build = false - reason = 'riscv arch not supported' - subdir_done() -endif sources = files( 'rte_eth_tap.c', 'tap_bpf_api.c', diff --git a/drivers/net/tap/tap_bpf.h b/drivers/net/tap/tap_bpf.h index f0b9fc7a2c..639bdf3a79 100644 --- a/drivers/net/tap/tap_bpf.h +++ b/drivers/net/tap/tap_bpf.h @@ -101,6 +101,8 @@ union bpf_attr { # define __NR_bpf 351 # elif defined(__powerpc__) # define __NR_bpf 361 +# elif defined(__riscv) +# define __NR_bpf 280 # else # error __NR_bpf not defined # endif From patchwork Thu May 5 17:29:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislaw Kardach X-Patchwork-Id: 110746 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4E005A00C2; Thu, 5 May 2022 19:31:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 00C214283D; Thu, 5 May 2022 19:30:36 +0200 (CEST) Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) by mails.dpdk.org (Postfix) with ESMTP id 137B14283A for ; Thu, 5 May 2022 19:30:33 +0200 (CEST) Received: by mail-lf1-f54.google.com with SMTP id x17so8612974lfa.10 for ; Thu, 05 May 2022 10:30:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wWE0V/zfRUDZbtl2fjPItvPJtNofBjGwNJMACdcwbJU=; b=BDHHTUFzHTo0ekuqQZImTvyFZCakTwViRNHJ0I/HNhecDF2CCEHN0kU+rTP2AcXJpa 7DvWtcN/rGVD/f+8DWTW3I2WOluwjNcoBsoBGxVFIZP07yK10AwSw5QsOjZzxqX6iG+v p9i1fPPF97eedPCGGMR0IudCjK/ZjgVPbiheg1Nv0PhrQykK57BtyLz9W1tKu5eXOLrS g2YabP+PUEodgoBLy2zflm+0sAvrVuryX92CuaC5Zyh20MyHrNMGnib5YZ7sAzqYt8xK KVXZk16a38bOKoo6OXRHj46alaiWmLIznKPcZvPMnAaBLnQGhn+4nR0BuUX24cgcGU/i ZYJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wWE0V/zfRUDZbtl2fjPItvPJtNofBjGwNJMACdcwbJU=; b=kRWMamE4O9H7T2G97RO4j5FIYa1DyQB7jejHBjxg9EnH0l+XHudtTZSKbxCwFA6Uj6 nq/0vRT7lB3mMrOooNjA4ZMllKIR+re9orZB5YwxQ9gQ+RpMxd4qL5z5lIlHKcb7S8uW hERsnL4s9BB8L3SvnxwtQgWZjevaENwnBOA3csDDqUobAjlwdZrnYxJi4V/nMMRN+Zy1 DzM3N52lFjd8WScFtClnLW5e36q+RBJC/X8+W+OlAv3Wxt04AX9BS4rkKvkz8qniQpAY NUU6eL12RXReTh84MiQJ5UiFc8nxi1fBKW9VI49HoVXHbug7W5xQOksefGHidpD06tJw uMaQ== X-Gm-Message-State: AOAM530DvuTwHEs0qNFIPVUhqvBSLjx4DDhELsxLP6JDKkCGfcoC66QZ MGruWOeDt5vPOels8H79DQW4SS1dVwcyvw== X-Google-Smtp-Source: ABdhPJwdrNZmCQCFBw6HDFYclTiu0d0z6IXiO4tMwXY37njUCZxwvb29jJtF7gw2k7WaYSCS2N35aA== X-Received: by 2002:a05:6512:2a92:b0:472:5c09:c1a8 with SMTP id dt18-20020a0565122a9200b004725c09c1a8mr16417000lfb.265.1651771832688; Thu, 05 May 2022 10:30:32 -0700 (PDT) Received: from localhost.localdomain (89-73-146-138.dynamic.chello.pl. [89.73.146.138]) by smtp.gmail.com with ESMTPSA id z26-20020ac25dfa000000b0047255d21203sm289640lfq.306.2022.05.05.10.30.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 10:30:32 -0700 (PDT) From: Stanislaw Kardach To: dev@dpdk.org Cc: Stanislaw Kardach , Frank Zhao , Sam Grove , mw@semihalf.com, upstream@semihalf.com Subject: [PATCH 07/11] examples/l3fwd: enable RISC-V operation Date: Thu, 5 May 2022 19:29:59 +0200 Message-Id: <20220505173003.3242618-8-kda@semihalf.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220505173003.3242618-1-kda@semihalf.com> References: <20220505173003.3242618-1-kda@semihalf.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add missing em_mask_key() implementation and fix l3fwd_common.h inclusion in FIB lookup functions to enable the l3fwd to be run on RISC-V. Signed-off-by: Stanislaw Kardach Sponsored-by: Frank Zhao Sponsored-by: Sam Grove --- examples/l3fwd/l3fwd_em.c | 8 ++++++++ examples/l3fwd/l3fwd_fib.c | 2 ++ examples/l3fwd/meson.build | 6 ------ 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c index 24d0910fe0..bbd3452546 100644 --- a/examples/l3fwd/l3fwd_em.c +++ b/examples/l3fwd/l3fwd_em.c @@ -239,6 +239,14 @@ em_mask_key(void *key, xmm_t mask) return vec_and(data, mask); } +#elif defined(RTE_ARCH_RISCV) +static inline xmm_t +em_mask_key(void *key, xmm_t mask) +{ + xmm_t data = vect_load_128(key); + + return vect_and(data, mask); +} #else #error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain #endif diff --git a/examples/l3fwd/l3fwd_fib.c b/examples/l3fwd/l3fwd_fib.c index 6e0054b4cb..bdb7d7535d 100644 --- a/examples/l3fwd/l3fwd_fib.c +++ b/examples/l3fwd/l3fwd_fib.c @@ -18,6 +18,8 @@ #include "l3fwd_neon.h" #elif defined RTE_ARCH_PPC_64 #include "l3fwd_altivec.h" +#else +#include "l3fwd_common.h" #endif #include "l3fwd_event.h" #include "l3fwd_route.h" diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build index 75fa19b7fe..0830b3eb31 100644 --- a/examples/l3fwd/meson.build +++ b/examples/l3fwd/meson.build @@ -6,12 +6,6 @@ # To build this example as a standalone application with an already-installed # DPDK instance, use 'make' -if dpdk_conf.has('RTE_ARCH_RISCV') - build = false - reason = 'riscv arch not supported' - subdir_done() -endif - allow_experimental_apis = true deps += ['hash', 'lpm', 'fib', 'eventdev'] sources = files( From patchwork Thu May 5 17:30:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislaw Kardach X-Patchwork-Id: 110747 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 90168A00C2; Thu, 5 May 2022 19:31:22 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D8A5F4284F; Thu, 5 May 2022 19:30:36 +0200 (CEST) Received: from mail-lj1-f174.google.com (mail-lj1-f174.google.com [209.85.208.174]) by mails.dpdk.org (Postfix) with ESMTP id 26BF442843 for ; Thu, 5 May 2022 19:30:34 +0200 (CEST) Received: by mail-lj1-f174.google.com with SMTP id q14so6481757ljc.12 for ; Thu, 05 May 2022 10:30:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NsvKHV50P8eyjkcSn3XumW8sSl+3syDFWSTC1jk/6ug=; b=gReMkbSl9hOV/fDMBZYh+REAz3kQXOqDw+lJws1GpUm3NUOwpT70ltW9ihUENGvUmw mbZBb6meef0LmSisiriHuMG0toTJK9kjRTOfWhBa+bR8bR8jhmbA/JP6sXhMgyS66SCW /3JMjtIYPACd4wA2HolfP+cRJ5YfHqFeK9cm7l23hfalFyF5eLrNl6DNuzl0yFaD6Gc6 o4VLSCECaEhPFu26pCO4QPmY/T8q+uIP6fy1HTD13QPo1nnCMhFaF2vcZhsk1nk4gZpI tCY+wsoKtfEcJo9eFKwTqQF+PAv5hPhpn+wBhHWbsW9iK3+EQ8Y+hxM3r+yG1Hfdy9dT dJYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NsvKHV50P8eyjkcSn3XumW8sSl+3syDFWSTC1jk/6ug=; b=tkx57FZMIR1Rfswct36DShUws+fhFcq5WVDgYxi/9ELHW5Lx19T5FVwa1w/+fTJAWk ruargNRvLnkuNAfDar4KOyJIRhLLaAaH5vuJiBdlk0S5ujmjG+fw9OehHjGDltUAB/6A h46xuoJmAOHkYIGAPDPuNA748MoHoEo9hcBmeBYvxoXxrhqx2vcW/SgLnt/QJXDr5zBr rjl3bGN9H7PVhhRS8x3rOeGMmFTJ6Ao+bpHsUUXvpMEU2uNnbX/q+47shU65PJFP564h Dq5aUnkPr6FS3CRk3mwBS6eTJ5x2IC4ovqHKJVMhR50v8AjjIvYvu2As1LkdflfOFJtg mNkw== X-Gm-Message-State: AOAM532FFPQyWhJwXc0bL9b7GxblUYrnAktG9CQ7QZYpkUg1jpujng5O 0R7Wjodq9QAnt34O2rxawk0gxDtb1bqtKw== X-Google-Smtp-Source: ABdhPJzrPBe2dmRSiQoE4nHEf+iAZFG/Ps4F0as7yVaIroAEyNvS/uH7WC0dGsEf1nn3xwHtHWP0Hw== X-Received: by 2002:a2e:81c1:0:b0:24b:f44:3970 with SMTP id s1-20020a2e81c1000000b0024b0f443970mr17206911ljg.97.1651771833769; Thu, 05 May 2022 10:30:33 -0700 (PDT) Received: from localhost.localdomain (89-73-146-138.dynamic.chello.pl. [89.73.146.138]) by smtp.gmail.com with ESMTPSA id z26-20020ac25dfa000000b0047255d21203sm289640lfq.306.2022.05.05.10.30.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 10:30:33 -0700 (PDT) From: Stanislaw Kardach To: dev@dpdk.org Cc: Michal Mazurek , Frank Zhao , Sam Grove , mw@semihalf.com, upstream@semihalf.com, Stanislaw Kardach Subject: [PATCH 08/11] test/cpuflags: add test for RISC-V cpu flag Date: Thu, 5 May 2022 19:30:00 +0200 Message-Id: <20220505173003.3242618-9-kda@semihalf.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220505173003.3242618-1-kda@semihalf.com> References: <20220505173003.3242618-1-kda@semihalf.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Michal Mazurek Add checks for all flag values defined in the RISC-V misa CSR register. Signed-off-by: Michal Mazurek Signed-off-by: Stanislaw Kardach Sponsored-by: Frank Zhao Sponsored-by: Sam Grove --- app/test/test_cpuflags.c | 81 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c index 40f6ac7fca..98a99c2c7d 100644 --- a/app/test/test_cpuflags.c +++ b/app/test/test_cpuflags.c @@ -200,6 +200,87 @@ test_cpuflags(void) CHECK_FOR_FLAG(RTE_CPUFLAG_INVTSC); #endif +#if defined(RTE_ARCH_RISCV) + + printf("Check for RISCV_ISA_A:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_A); + + printf("Check for RISCV_ISA_B:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_B); + + printf("Check for RISCV_ISA_C:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_C); + + printf("Check for RISCV_ISA_D:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_D); + + printf("Check for RISCV_ISA_E:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_E); + + printf("Check for RISCV_ISA_F:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_F); + + printf("Check for RISCV_ISA_G:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_G); + + printf("Check for RISCV_ISA_H:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_H); + + printf("Check for RISCV_ISA_I:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_I); + + printf("Check for RISCV_ISA_J:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_J); + + printf("Check for RISCV_ISA_K:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_K); + + printf("Check for RISCV_ISA_L:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_L); + + printf("Check for RISCV_ISA_M:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_M); + + printf("Check for RISCV_ISA_N:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_N); + + printf("Check for RISCV_ISA_O:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_O); + + printf("Check for RISCV_ISA_P:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_P); + + printf("Check for RISCV_ISA_Q:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Q); + + printf("Check for RISCV_ISA_R:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_R); + + printf("Check for RISCV_ISA_S:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_S); + + printf("Check for RISCV_ISA_T:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_T); + + printf("Check for RISCV_ISA_U:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_U); + + printf("Check for RISCV_ISA_V:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_V); + + printf("Check for RISCV_ISA_W:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_W); + + printf("Check for RISCV_ISA_X:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_X); + + printf("Check for RISCV_ISA_Y:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Y); + + printf("Check for RISCV_ISA_Z:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Z); +#endif + /* * Check if invalid data is handled properly */ From patchwork Thu May 5 17:30:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislaw Kardach X-Patchwork-Id: 110748 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4D995A00C2; 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[89.73.146.138]) by smtp.gmail.com with ESMTPSA id z26-20020ac25dfa000000b0047255d21203sm289640lfq.306.2022.05.05.10.30.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 10:30:34 -0700 (PDT) From: Stanislaw Kardach To: Honnappa Nagarahalli Cc: Stanislaw Kardach , dev@dpdk.org, Frank Zhao , Sam Grove , mw@semihalf.com, upstream@semihalf.com Subject: [PATCH 09/11] test/ring: disable problematic tests for RISC-V Date: Thu, 5 May 2022 19:30:01 +0200 Message-Id: <20220505173003.3242618-10-kda@semihalf.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220505173003.3242618-1-kda@semihalf.com> References: <20220505173003.3242618-1-kda@semihalf.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When compiling for RISC-V in debug mode the large amount of inlining in test_ring_basic_ex() and test_ring_with_exact_size() (in test_ring.c) leads to large loop bodies. This causes 'goto' and 'for' loop PC-relative jumps generated by the compiler to go beyond the architecture limitation of +/-1MB offset (the 'j ' instruction). This instruction should not be generated by the compiler since C language does not limit the maximum distance for 'goto' or 'for' loop jumps. This only happens in the unit test for ring which tries to perform long loops with ring enqueue/dequeue and it seems to be caused by excessive __rte_always_inline usage. ring perf test compiles just fine under debug. To work around this, disable the offending tests in debug mode. Signed-off-by: Stanislaw Kardach Sponsored-by: Frank Zhao Sponsored-by: Sam Grove --- app/test/test_ring.c | 8 ++++++++ config/riscv/meson.build | 5 +++++ doc/guides/rel_notes/release_22_07.rst | 3 ++- 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/app/test/test_ring.c b/app/test/test_ring.c index bde33ab4a1..7d809c147b 100644 --- a/app/test/test_ring.c +++ b/app/test/test_ring.c @@ -955,6 +955,7 @@ test_ring_burst_bulk_tests4(unsigned int test_idx) return -1; } +#if !defined(RTE_RISCV_WO_DISABLE_RING_TESTS) /* * Test default, single element, bulk and burst APIs */ @@ -1189,6 +1190,7 @@ test_ring_with_exact_size(void) rte_ring_free(exact_sz_r); return -1; } +#endif static int test_ring(void) @@ -1200,12 +1202,18 @@ test_ring(void) if (test_ring_negative_tests() < 0) goto test_fail; +/* Disable the following tests on RISC-V in debug mode. This is a work-around + * GCC bug for RISC-V which fails to generate proper jumps for loops with large + * bodies. + */ +#if !defined(RTE_RISCV_WO_DISABLE_RING_TESTS) /* Some basic operations */ if (test_ring_basic_ex() < 0) goto test_fail; if (test_ring_with_exact_size() < 0) goto test_fail; +#endif /* Burst and bulk operations with sp/sc, mp/mc and default. * The test cases are split into smaller test cases to diff --git a/config/riscv/meson.build b/config/riscv/meson.build index 0c16c31fc2..50d0b513bf 100644 --- a/config/riscv/meson.build +++ b/config/riscv/meson.build @@ -141,3 +141,8 @@ foreach flag: dpdk_flags endforeach message('Using machine args: @0@'.format(machine_args)) +# Enable work-around for ring unit tests in debug mode which fail to link +# properly due to bad code generation by GCC. +if get_option('optimization') == '0' or get_option('optimization') == 'g' + add_project_arguments('-DRTE_RISCV_WO_DISABLE_RING_TESTS', language: 'c') +endif diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index 453591e568..4d64b68dfd 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -76,7 +76,8 @@ New Features * Debug build of ``app/test/dpdk-test`` fails currently on RISC-V due to seemingly invalid loop and goto jump code generation by GCC in ``test_ring.c`` where extensive inlining increases the code size beyond the - capability of the generated instruction (JAL: +/-1MB PC-relative). + capability of the generated instruction (JAL: +/-1MB PC-relative). The + workaround is to disable ``test_ring_basic_ex()`` and ``test_ring_with_exact_size()`` on RISC-V on ``-O0`` or ``-Og``. * **Updated Intel iavf driver.** From patchwork Thu May 5 17:30:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislaw Kardach X-Patchwork-Id: 110749 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3EF71A00C2; Thu, 5 May 2022 19:31:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B6D4D42857; Thu, 5 May 2022 19:30:38 +0200 (CEST) Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) by mails.dpdk.org (Postfix) with ESMTP id 2FB484284C for ; Thu, 5 May 2022 19:30:36 +0200 (CEST) Received: by mail-lf1-f42.google.com with SMTP id t25so8611291lfg.7 for ; Thu, 05 May 2022 10:30:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GK5wKzslayOdqHyBtWIe6z+OqiYLFSHY6eOWitDRi28=; b=0FYkWzSqc2go0gDMXu+snPU2yocL6JlMeVkYRBtFO1kTRrSM8zoO603l+cWYCUCxdp uHVu3Lpd4sXoKPW0SUlRk0NAUmegqtXmKhIbHwapVCm2UMDbBlhrsi+hB1PIzYcDRbqZ uxEQJ2slhkboQQjusXjRsBt0AHSLnze4DAapCpjD5FLltK19XBTbJGvz9Jb5Nv5omAas 25H38hI/x4jif2GJbEe1xkNEOZsbv60InkR6kKIJGm32zxgubdVNYMbT2rb3N2ZG0K9D nGoCv+H98nO2UiXiAw/2Ufd9kolI3nvj/ZxviIDyGlFwwCEPsrDhHonUmCTTl7HqDpjw KLOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GK5wKzslayOdqHyBtWIe6z+OqiYLFSHY6eOWitDRi28=; b=umC3VbGnfRfQIVOo53ns9DVDlbqNigwMyncqMZ7BNIR+GGiClNSGmaPRxyBxKFOCTR szatQx7WzTGeKwGQnK51pgS04OT2xdYeTh8COHysPJhZbY2KHtQHYbDyhyc4/VzIFiug ua1ag//KHYXsLxiDyggEfwJD8YSs87WGjYe0cmjdEzFQmQlR/0RSE2Z1v0MXU23gk2tA acJHvuEX+uIvaR9wphKkaOFjCx5mfMGqsUUOFq+y2c2Dz78OxxkzhG0YIj1YPauPG+LZ WPEJplguuEfgnlMYILLV0s4IidWxl+qUpLKxfRoBBLbv0sivfSK2d6Ms8LcUZ4rsbCaY 60ZQ== X-Gm-Message-State: AOAM532Tp19EQ6OL8PB8aNDtQgBzt7y8XImqrqGAwI+ffO5ioebgEkgg 3vVQ+k4rc5vLw1ZSglOqc/hPog== X-Google-Smtp-Source: ABdhPJyxoLUtVquCp9SrDu8AXom84TP8L7bo+EFb6jd5zQA3wW3CPs2LW/tE/MUc7crrQdTMSecrug== X-Received: by 2002:a05:6512:16a7:b0:445:862e:a1ba with SMTP id bu39-20020a05651216a700b00445862ea1bamr17771425lfb.85.1651771835767; Thu, 05 May 2022 10:30:35 -0700 (PDT) Received: from localhost.localdomain (89-73-146-138.dynamic.chello.pl. [89.73.146.138]) by smtp.gmail.com with ESMTPSA id z26-20020ac25dfa000000b0047255d21203sm289640lfq.306.2022.05.05.10.30.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 10:30:35 -0700 (PDT) From: Stanislaw Kardach To: Bruce Richardson Cc: Stanislaw Kardach , dev@dpdk.org, Frank Zhao , Sam Grove , mw@semihalf.com, upstream@semihalf.com Subject: [PATCH 10/11] devtools: add RISC-V to test-meson-builds.sh Date: Thu, 5 May 2022 19:30:02 +0200 Message-Id: <20220505173003.3242618-11-kda@semihalf.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220505173003.3242618-1-kda@semihalf.com> References: <20220505173003.3242618-1-kda@semihalf.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Validate RISC-V compilation when test-meson-builds.sh is called. The check will be only performed if appropriate toolchain is present on the system (same as with other architectures). Signed-off-by: Stanislaw Kardach Sponsored-by: Frank Zhao Sponsored-by: Sam Grove --- devtools/test-meson-builds.sh | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/devtools/test-meson-builds.sh b/devtools/test-meson-builds.sh index a653b253cb..12513e9d7f 100755 --- a/devtools/test-meson-builds.sh +++ b/devtools/test-meson-builds.sh @@ -275,6 +275,12 @@ for f in $srcdir/config/ppc/ppc* ; do build $targetdir $f ABI $use_shared done +# RISC-V configurations +for f in $srcdir/config/riscv/riscv* ; do + targetdir=build-$(basename $f | tr '_' '-' | cut -d'-' -f-2) + build $targetdir $f ABI $use_shared +done + # Test installation of the x86-generic target, to be used for checking # the sample apps build using the pkg-config file for cflags and libs load_env cc From patchwork Thu May 5 17:30:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislaw Kardach X-Patchwork-Id: 110750 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E247FA00C2; Thu, 5 May 2022 19:31:42 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D165642862; Thu, 5 May 2022 19:30:39 +0200 (CEST) Received: from mail-lj1-f172.google.com (mail-lj1-f172.google.com [209.85.208.172]) by mails.dpdk.org (Postfix) with ESMTP id 19BD742851 for ; Thu, 5 May 2022 19:30:37 +0200 (CEST) Received: by mail-lj1-f172.google.com with SMTP id c15so6479958ljr.9 for ; Thu, 05 May 2022 10:30:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P6WK2La26r/WLOadGIQACtGagnI+cR8L/1kByHyE95E=; b=rz9UVf+vfxsFCPvpsgikSvdF16u/2iJP0F5uAAo8IEd9k+MaZhSqz8uR4CUHyl7dwb sHL7dpNOKqRYXh9Z/Kv92YV/2UG31DH9yKjGZ/Alc6B3o6zlSepkAL1AEgkHdE2IztBB OOaBJTaR+QFfCdquH/CNG26tqeracgQSxsAYcrurl0f3bwet1H24DzSWGo7FwYpJORqz SG3vn9qSr/GwE3LLFAKr5EnC3EvZNNYrATCstO+Nj2REb0VHA9hkWBWuLm9pL7k0UkiP SPs2uAYCNii7HeU299wktA7Rm1SU8FzeQgVTldjpReeDphYYx9XEpCIgF6tiODUhg7ny 9muQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P6WK2La26r/WLOadGIQACtGagnI+cR8L/1kByHyE95E=; b=zzRv1exbFwxX2F4h1Jofi2fdHM066892y9C7LbN8iKiGGpq8qI02UwnKOGCY4we4nC GwkH2DeQ6mdCzCL1layJrw/MLHwAXJrBEDP7CYB45R83ug9MoC2eg5g+hFdUhyFnyweS NaOuVpX66DwoSAqmEwfrEt8u7vgZq62CEIznpTna5vHwzze8ShdOFRsV84WIh+Mi6R4q SM6hzcgTDFnes8QzrxQB+K4l9ara1xtgPJZ6Ob4RD9wkECwmdjNC0gayagd7mOQG1Tml pgJOPudxOQIP5nWVVfdShI8ec3BDM4UjhaUEWcS9N8q7nkCYAwX6UYwPB32eYPXmT9jc xopw== X-Gm-Message-State: AOAM533uM+u1a9KW8BCjON5AqSpms/QBZqwDdAEvVFz6TT75cAvfzNUZ 044HPGZDl/3dA2yJrxGvfwgVDt7HzF/OAA== X-Google-Smtp-Source: ABdhPJxYAkYbHnB7g2MnCDQnRzIjhHtQ6VJ7vXFa+tww/3ojN9gfij6AfVED5GVRXG0VoXDwUOqiUw== X-Received: by 2002:a05:651c:1781:b0:247:daa7:4358 with SMTP id bn1-20020a05651c178100b00247daa74358mr16887656ljb.477.1651771836710; Thu, 05 May 2022 10:30:36 -0700 (PDT) Received: from localhost.localdomain (89-73-146-138.dynamic.chello.pl. [89.73.146.138]) by smtp.gmail.com with ESMTPSA id z26-20020ac25dfa000000b0047255d21203sm289640lfq.306.2022.05.05.10.30.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 10:30:36 -0700 (PDT) From: Stanislaw Kardach To: Yipeng Wang Cc: Stanislaw Kardach , dev@dpdk.org, Frank Zhao , Sam Grove , mw@semihalf.com, upstream@semihalf.com Subject: [PATCH 11/11] test/hash: report non HTM numbers for single r/w Date: Thu, 5 May 2022 19:30:03 +0200 Message-Id: <20220505173003.3242618-12-kda@semihalf.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220505173003.3242618-1-kda@semihalf.com> References: <20220505173003.3242618-1-kda@semihalf.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In hash_readwrite_perf_autotest a single read and write operation is benchmarked for both HTM and non HTM cases. However the result summary only shows the HTM value. Therefore add the non HTM value for completeness. Fixes: 0eb3726ebcf1 ("test/hash: add test for read/write concurrency") Cc: yipeng1.wang@intel.com Signed-off-by: Stanislaw Kardach Sponsored-by: Frank Zhao Sponsored-by: Sam Grove --- app/test/test_hash_readwrite.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/app/test/test_hash_readwrite.c b/app/test/test_hash_readwrite.c index 9b192f2b5e..6373e62d33 100644 --- a/app/test/test_hash_readwrite.c +++ b/app/test/test_hash_readwrite.c @@ -664,8 +664,12 @@ test_hash_rw_perf_main(void) printf("Results summary:\n"); printf("================\n"); - printf("single read: %u\n", htm_results.single_read); - printf("single write: %u\n", htm_results.single_write); + printf("HTM:\n"); + printf(" single read: %u\n", htm_results.single_read); + printf(" single write: %u\n", htm_results.single_write); + printf("non HTM:\n"); + printf(" single read: %u\n", non_htm_results.single_read); + printf(" single write: %u\n", non_htm_results.single_write); for (i = 0; i < NUM_TEST; i++) { printf("+++ core_cnt: %u +++\n", core_cnt[i]); printf("HTM:\n");