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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.238 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.238; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.238) by CO1NAM11FT066.mail.protection.outlook.com (10.13.175.18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5273.14 via Frontend Transport; Tue, 24 May 2022 15:21:01 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL105.nvidia.com (10.27.9.14) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Tue, 24 May 2022 15:21:00 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 24 May 2022 08:20:58 -0700 From: Spike Du To: , , , CC: , Subject: [PATCH v3 1/7] net/mlx5: add LWM support for Rxq Date: Tue, 24 May 2022 18:20:35 +0300 Message-ID: <20220524152041.737154-2-spiked@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220524152041.737154-1-spiked@nvidia.com> References: <20220522055900.417282-1-spiked@nvidia.com> <20220524152041.737154-1-spiked@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d6a05d8c-6d13-4901-d2fe-08da3d9902ef X-MS-TrafficTypeDiagnostic: BYAPR12MB2661:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2022 15:21:01.3815 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d6a05d8c-6d13-4901-d2fe-08da3d9902ef X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT066.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2661 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add lwm(Limit WaterMark) field to Rxq object which indicates the percentage of RX queue size used by HW to raise LWM event to the user. Allow LWM setting in modify_rq command. Allow the LWM configuration dynamically by adding RDY2RDY state change. Signed-off-by: Spike Du --- drivers/net/mlx5/mlx5.h | 1 + drivers/net/mlx5/mlx5_devx.c | 13 ++++++++++++- drivers/net/mlx5/mlx5_devx.h | 1 + drivers/net/mlx5/mlx5_rx.h | 1 + 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index ef755ee8cf..305edffe71 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1395,6 +1395,7 @@ enum mlx5_rxq_modify_type { MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */ MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */ MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */ + MLX5_RXQ_MOD_RDY2RDY, /* modify state from ready to ready. */ }; enum mlx5_txq_modify_type { diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index 4b48f9433a..c918a50ae9 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -62,7 +62,7 @@ mlx5_rxq_obj_modify_rq_vlan_strip(struct mlx5_rxq_priv *rxq, int on) * @return * 0 on success, a negative errno value otherwise and rte_errno is set. */ -static int +int mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type) { struct mlx5_devx_modify_rq_attr rq_attr; @@ -76,6 +76,11 @@ mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type) case MLX5_RXQ_MOD_RST2RDY: rq_attr.rq_state = MLX5_RQC_STATE_RST; rq_attr.state = MLX5_RQC_STATE_RDY; + if (rxq->lwm) { + rq_attr.modify_bitmask |= + MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM; + rq_attr.lwm = rxq->lwm; + } break; case MLX5_RXQ_MOD_RDY2ERR: rq_attr.rq_state = MLX5_RQC_STATE_RDY; @@ -85,6 +90,12 @@ mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type) rq_attr.rq_state = MLX5_RQC_STATE_RDY; rq_attr.state = MLX5_RQC_STATE_RST; break; + case MLX5_RXQ_MOD_RDY2RDY: + rq_attr.rq_state = MLX5_RQC_STATE_RDY; + rq_attr.state = MLX5_RQC_STATE_RDY; + rq_attr.modify_bitmask |= MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM; + rq_attr.lwm = rxq->lwm; + break; default: break; } diff --git a/drivers/net/mlx5/mlx5_devx.h b/drivers/net/mlx5/mlx5_devx.h index a95207a6b9..ebd1da455a 100644 --- a/drivers/net/mlx5/mlx5_devx.h +++ b/drivers/net/mlx5/mlx5_devx.h @@ -11,6 +11,7 @@ int mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx); int mlx5_txq_devx_modify(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type, uint8_t dev_port); void mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj); +int mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type); extern struct mlx5_obj_ops devx_obj_ops; diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index e715ed6b62..25a5f2c1fa 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -175,6 +175,7 @@ struct mlx5_rxq_priv { struct mlx5_devx_rq devx_rq; struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ uint32_t hairpin_status; /* Hairpin binding status. */ + uint32_t lwm:16; }; /* External RX queue descriptor. */ From patchwork Tue May 24 15:20:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Spike Du X-Patchwork-Id: 111746 X-Patchwork-Delegate: andrew.rybchenko@oktetlabs.ru Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6970AA04FF; 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Tue, 24 May 2022 15:21:03 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 24 May 2022 08:21:00 -0700 From: Spike Du To: , , , CC: , Subject: [PATCH v3 2/7] common/mlx5: share interrupt management Date: Tue, 24 May 2022 18:20:36 +0300 Message-ID: <20220524152041.737154-3-spiked@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220524152041.737154-1-spiked@nvidia.com> References: <20220522055900.417282-1-spiked@nvidia.com> <20220524152041.737154-1-spiked@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d1d8d4dc-4ea1-41a2-d1c4-08da3d991555 X-MS-TrafficTypeDiagnostic: BYAPR12MB2743:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2022 15:21:32.2489 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d1d8d4dc-4ea1-41a2-d1c4-08da3d991555 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2743 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org There are many duplicate code of creating and initializing rte_intr_handle. Add a new mlx5_os API to do this, replace all PMD related code with this API. Signed-off-by: Spike Du --- drivers/common/mlx5/linux/mlx5_common_os.c | 131 ++++++++++++++++++ drivers/common/mlx5/linux/mlx5_common_os.h | 11 ++ drivers/common/mlx5/version.map | 2 + drivers/common/mlx5/windows/mlx5_common_os.h | 24 ++++ drivers/net/mlx5/linux/mlx5_ethdev_os.c | 71 ---------- drivers/net/mlx5/linux/mlx5_os.c | 132 ++++--------------- drivers/net/mlx5/linux/mlx5_socket.c | 53 +------- drivers/net/mlx5/mlx5.h | 2 - drivers/net/mlx5/mlx5_txpp.c | 28 +--- drivers/net/mlx5/windows/mlx5_ethdev_os.c | 22 ---- drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 48 +------ 11 files changed, 217 insertions(+), 307 deletions(-) diff --git a/drivers/common/mlx5/linux/mlx5_common_os.c b/drivers/common/mlx5/linux/mlx5_common_os.c index d40cfd5cd1..f10a981a37 100644 --- a/drivers/common/mlx5/linux/mlx5_common_os.c +++ b/drivers/common/mlx5/linux/mlx5_common_os.c @@ -11,6 +11,7 @@ #endif #include #include +#include #include #include @@ -964,3 +965,133 @@ mlx5_os_wrapped_mkey_destroy(struct mlx5_pmd_wrapped_mr *pmd_mr) claim_zero(mlx5_glue->dereg_mr(pmd_mr->obj)); memset(pmd_mr, 0, sizeof(*pmd_mr)); } + +/** + * Rte_intr_handle create and init helper. + * + * @param[in] mode + * interrupt instance can be shared between primary and secondary + * processes or not. + * @param[in] set_fd_nonblock + * Whether to set fd to O_NONBLOCK. + * @param[in] fd + * Fd to set in created intr_handle. + * @param[in] cb + * Callback to register for intr_handle. + * @param[in] cb_arg + * Callback argument for cb. + * + * @return + * - Interrupt handle on success. + * - NULL on failure, with rte_errno set. + */ +struct rte_intr_handle * +mlx5_os_interrupt_handler_create(int mode, bool set_fd_nonblock, int fd, + rte_intr_callback_fn cb, void *cb_arg) +{ + struct rte_intr_handle *tmp_intr_handle; + int ret, flags; + + tmp_intr_handle = rte_intr_instance_alloc(mode); + if (!tmp_intr_handle) { + rte_errno = ENOMEM; + goto err; + } + if (set_fd_nonblock) { + flags = fcntl(fd, F_GETFL); + ret = fcntl(fd, F_SETFL, flags | O_NONBLOCK); + if (ret) { + rte_errno = errno; + goto err; + } + } + ret = rte_intr_fd_set(tmp_intr_handle, fd); + if (ret) + goto err; + ret = rte_intr_type_set(tmp_intr_handle, RTE_INTR_HANDLE_EXT); + if (ret) + goto err; + ret = rte_intr_callback_register(tmp_intr_handle, cb, cb_arg); + if (ret) { + rte_errno = -ret; + goto err; + } + return tmp_intr_handle; +err: + if (tmp_intr_handle) + rte_intr_instance_free(tmp_intr_handle); + return NULL; +} + +/* Safe unregistration for interrupt callback. */ +static void +mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, + rte_intr_callback_fn cb_fn, void *cb_arg) +{ + uint64_t twait = 0; + uint64_t start = 0; + + do { + int ret; + + ret = rte_intr_callback_unregister(handle, cb_fn, cb_arg); + if (ret >= 0) + return; + if (ret != -EAGAIN) { + DRV_LOG(INFO, "failed to unregister interrupt" + " handler (error: %d)", ret); + MLX5_ASSERT(false); + return; + } + if (twait) { + struct timespec onems; + + /* Wait one millisecond and try again. */ + onems.tv_sec = 0; + onems.tv_nsec = NS_PER_S / MS_PER_S; + nanosleep(&onems, 0); + /* Check whether one second elapsed. */ + if ((rte_get_timer_cycles() - start) <= twait) + continue; + } else { + /* + * We get the amount of timer ticks for one second. + * If this amount elapsed it means we spent one + * second in waiting. This branch is executed once + * on first iteration. + */ + twait = rte_get_timer_hz(); + MLX5_ASSERT(twait); + } + /* + * Timeout elapsed, show message (once a second) and retry. + * We have no other acceptable option here, if we ignore + * the unregistering return code the handler will not + * be unregistered, fd will be closed and we may get the + * crush. Hanging and messaging in the loop seems not to be + * the worst choice. + */ + DRV_LOG(INFO, "Retrying to unregister interrupt handler"); + start = rte_get_timer_cycles(); + } while (true); +} + +/** + * Rte_intr_handle destroy helper. + * + * @param[in] intr_handle + * Rte_intr_handle to destroy. + * @param[in] cb + * Callback which is registered to intr_handle. + * @param[in] cb_arg + * Callback argument for cb. + * + */ +void +mlx5_os_interrupt_handler_destroy(struct rte_intr_handle *intr_handle, + rte_intr_callback_fn cb, void *cb_arg) +{ + if (rte_intr_fd_get(intr_handle) >= 0) + mlx5_intr_callback_unregister(intr_handle, cb, cb_arg); + rte_intr_instance_free(intr_handle); +} diff --git a/drivers/common/mlx5/linux/mlx5_common_os.h b/drivers/common/mlx5/linux/mlx5_common_os.h index 27f1192205..479bb3c7cb 100644 --- a/drivers/common/mlx5/linux/mlx5_common_os.h +++ b/drivers/common/mlx5/linux/mlx5_common_os.h @@ -15,6 +15,7 @@ #include #include #include +#include #include "mlx5_autoconf.h" #include "mlx5_glue.h" @@ -299,4 +300,14 @@ __rte_internal int mlx5_get_device_guid(const struct rte_pci_addr *dev, uint8_t *guid, size_t len); +__rte_internal +struct rte_intr_handle * +mlx5_os_interrupt_handler_create(int mode, bool set_fd_nonblock, int fd, + rte_intr_callback_fn cb, void *cb_arg); + +__rte_internal +void +mlx5_os_interrupt_handler_destroy(struct rte_intr_handle *intr_handle, + rte_intr_callback_fn cb, void *cb_arg); + #endif /* RTE_PMD_MLX5_COMMON_OS_H_ */ diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index a23a30a6c0..413dec14ab 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -153,5 +153,7 @@ INTERNAL { mlx5_mr_mempool2mr_bh; mlx5_mr_mempool_populate_cache; + mlx5_os_interrupt_handler_create; # WINDOWS_NO_EXPORT + mlx5_os_interrupt_handler_destroy; # WINDOWS_NO_EXPORT local: *; }; diff --git a/drivers/common/mlx5/windows/mlx5_common_os.h b/drivers/common/mlx5/windows/mlx5_common_os.h index ee7973f1ec..e9e9108127 100644 --- a/drivers/common/mlx5/windows/mlx5_common_os.h +++ b/drivers/common/mlx5/windows/mlx5_common_os.h @@ -9,6 +9,7 @@ #include #include +#include #include "mlx5_autoconf.h" #include "mlx5_glue.h" @@ -253,4 +254,27 @@ void *mlx5_os_umem_reg(void *ctx, void *addr, size_t size, uint32_t access); __rte_internal int mlx5_os_umem_dereg(void *pumem); +static inline struct rte_intr_handle * +mlx5_os_interrupt_handler_create(int mode, bool set_fd_nonblock, int fd, + rte_intr_callback_fn cb, void *cb_arg) +{ + (void)mode; + (void)set_fd_nonblock; + (void)fd; + (void)cb; + (void)cb_arg; + rte_errno = ENOTSUP; + return NULL; +} + +static inline void +mlx5_os_interrupt_handler_destroy(struct rte_intr_handle *intr_handle, + rte_intr_callback_fn cb, void *cb_arg) +{ + (void)intr_handle; + (void)cb; + (void)cb_arg; +} + + #endif /* RTE_PMD_MLX5_COMMON_OS_H_ */ diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c index 8fe73f1adb..a276b2ba4f 100644 --- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c @@ -881,77 +881,6 @@ mlx5_dev_interrupt_handler(void *cb_arg) } } -/* - * Unregister callback handler safely. The handler may be active - * while we are trying to unregister it, in this case code -EAGAIN - * is returned by rte_intr_callback_unregister(). This routine checks - * the return code and tries to unregister handler again. - * - * @param handle - * interrupt handle - * @param cb_fn - * pointer to callback routine - * @cb_arg - * opaque callback parameter - */ -void -mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, - rte_intr_callback_fn cb_fn, void *cb_arg) -{ - /* - * Try to reduce timeout management overhead by not calling - * the timer related routines on the first iteration. If the - * unregistering succeeds on first call there will be no - * timer calls at all. - */ - uint64_t twait = 0; - uint64_t start = 0; - - do { - int ret; - - ret = rte_intr_callback_unregister(handle, cb_fn, cb_arg); - if (ret >= 0) - return; - if (ret != -EAGAIN) { - DRV_LOG(INFO, "failed to unregister interrupt" - " handler (error: %d)", ret); - MLX5_ASSERT(false); - return; - } - if (twait) { - struct timespec onems; - - /* Wait one millisecond and try again. */ - onems.tv_sec = 0; - onems.tv_nsec = NS_PER_S / MS_PER_S; - nanosleep(&onems, 0); - /* Check whether one second elapsed. */ - if ((rte_get_timer_cycles() - start) <= twait) - continue; - } else { - /* - * We get the amount of timer ticks for one second. - * If this amount elapsed it means we spent one - * second in waiting. This branch is executed once - * on first iteration. - */ - twait = rte_get_timer_hz(); - MLX5_ASSERT(twait); - } - /* - * Timeout elapsed, show message (once a second) and retry. - * We have no other acceptable option here, if we ignore - * the unregistering return code the handler will not - * be unregistered, fd will be closed and we may get the - * crush. Hanging and messaging in the loop seems not to be - * the worst choice. - */ - DRV_LOG(INFO, "Retrying to unregister interrupt handler"); - start = rte_get_timer_cycles(); - } while (true); -} - /** * Handle DEVX interrupts from the NIC. * This function is probably called from the DPDK host thread. diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index a821153b35..0741028dab 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -2494,40 +2494,6 @@ mlx5_os_net_cleanup(void) mlx5_pmd_socket_uninit(); } -static int -mlx5_os_dev_shared_handler_install_lsc(struct mlx5_dev_ctx_shared *sh) -{ - int nlsk_fd, flags, ret; - - nlsk_fd = mlx5_nl_init(NETLINK_ROUTE, RTMGRP_LINK); - if (nlsk_fd < 0) { - DRV_LOG(ERR, "Failed to create a socket for Netlink events: %s", - rte_strerror(rte_errno)); - return -1; - } - flags = fcntl(nlsk_fd, F_GETFL); - ret = fcntl(nlsk_fd, F_SETFL, flags | O_NONBLOCK); - if (ret != 0) { - DRV_LOG(ERR, "Failed to make Netlink event socket non-blocking: %s", - strerror(errno)); - rte_errno = errno; - goto error; - } - rte_intr_type_set(sh->intr_handle_nl, RTE_INTR_HANDLE_EXT); - rte_intr_fd_set(sh->intr_handle_nl, nlsk_fd); - if (rte_intr_callback_register(sh->intr_handle_nl, - mlx5_dev_interrupt_handler_nl, - sh) != 0) { - DRV_LOG(ERR, "Failed to register Netlink events interrupt"); - rte_intr_fd_set(sh->intr_handle_nl, -1); - goto error; - } - return 0; -error: - close(nlsk_fd); - return -1; -} - /** * Install shared asynchronous device events handler. * This function is implemented to support event sharing @@ -2539,76 +2505,47 @@ mlx5_os_dev_shared_handler_install_lsc(struct mlx5_dev_ctx_shared *sh) void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) { - int ret; - int flags; struct ibv_context *ctx = sh->cdev->ctx; + int nlsk_fd; - sh->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); - if (sh->intr_handle == NULL) { - DRV_LOG(ERR, "Fail to allocate intr_handle"); - rte_errno = ENOMEM; + sh->intr_handle = mlx5_os_interrupt_handler_create + (RTE_INTR_INSTANCE_F_SHARED, true, + ctx->async_fd, mlx5_dev_interrupt_handler, sh); + if (!sh->intr_handle) { + DRV_LOG(ERR, "Failed to allocate intr_handle."); return; } - rte_intr_fd_set(sh->intr_handle, -1); - - flags = fcntl(ctx->async_fd, F_GETFL); - ret = fcntl(ctx->async_fd, F_SETFL, flags | O_NONBLOCK); - if (ret) { - DRV_LOG(INFO, "failed to change file descriptor async event" - " queue"); - } else { - rte_intr_fd_set(sh->intr_handle, ctx->async_fd); - rte_intr_type_set(sh->intr_handle, RTE_INTR_HANDLE_EXT); - if (rte_intr_callback_register(sh->intr_handle, - mlx5_dev_interrupt_handler, sh)) { - DRV_LOG(INFO, "Fail to install the shared interrupt."); - rte_intr_fd_set(sh->intr_handle, -1); - } + nlsk_fd = mlx5_nl_init(NETLINK_ROUTE, RTMGRP_LINK); + if (nlsk_fd < 0) { + DRV_LOG(ERR, "Failed to create a socket for Netlink events: %s", + rte_strerror(rte_errno)); + return; } - sh->intr_handle_nl = rte_intr_instance_alloc - (RTE_INTR_INSTANCE_F_SHARED); + sh->intr_handle_nl = mlx5_os_interrupt_handler_create + (RTE_INTR_INSTANCE_F_SHARED, true, + nlsk_fd, mlx5_dev_interrupt_handler_nl, sh); if (sh->intr_handle_nl == NULL) { DRV_LOG(ERR, "Fail to allocate intr_handle"); - rte_errno = ENOMEM; return; } - rte_intr_fd_set(sh->intr_handle_nl, -1); - if (mlx5_os_dev_shared_handler_install_lsc(sh) < 0) { - DRV_LOG(INFO, "Fail to install the shared Netlink event handler."); - rte_intr_fd_set(sh->intr_handle_nl, -1); - } if (sh->cdev->config.devx) { #ifdef HAVE_IBV_DEVX_ASYNC - sh->intr_handle_devx = - rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); - if (!sh->intr_handle_devx) { - DRV_LOG(ERR, "Fail to allocate intr_handle"); - rte_errno = ENOMEM; - return; - } - rte_intr_fd_set(sh->intr_handle_devx, -1); + struct mlx5dv_devx_cmd_comp *devx_comp; + sh->devx_comp = (void *)mlx5_glue->devx_create_cmd_comp(ctx); - struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; + devx_comp = sh->devx_comp; if (!devx_comp) { DRV_LOG(INFO, "failed to allocate devx_comp."); return; } - flags = fcntl(devx_comp->fd, F_GETFL); - ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); - if (ret) { - DRV_LOG(INFO, "failed to change file descriptor" - " devx comp"); + sh->intr_handle_devx = mlx5_os_interrupt_handler_create + (RTE_INTR_INSTANCE_F_SHARED, true, + devx_comp->fd, + mlx5_dev_interrupt_handler_devx, sh); + if (!sh->intr_handle_devx) { + DRV_LOG(ERR, "Failed to allocate intr_handle."); return; } - rte_intr_fd_set(sh->intr_handle_devx, devx_comp->fd); - rte_intr_type_set(sh->intr_handle_devx, - RTE_INTR_HANDLE_EXT); - if (rte_intr_callback_register(sh->intr_handle_devx, - mlx5_dev_interrupt_handler_devx, sh)) { - DRV_LOG(INFO, "Fail to install the devx shared" - " interrupt."); - rte_intr_fd_set(sh->intr_handle_devx, -1); - } #endif /* HAVE_IBV_DEVX_ASYNC */ } } @@ -2624,24 +2561,13 @@ mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) { - int nlsk_fd; - - if (rte_intr_fd_get(sh->intr_handle) >= 0) - mlx5_intr_callback_unregister(sh->intr_handle, - mlx5_dev_interrupt_handler, sh); - rte_intr_instance_free(sh->intr_handle); - nlsk_fd = rte_intr_fd_get(sh->intr_handle_nl); - if (nlsk_fd >= 0) { - mlx5_intr_callback_unregister - (sh->intr_handle_nl, mlx5_dev_interrupt_handler_nl, sh); - close(nlsk_fd); - } - rte_intr_instance_free(sh->intr_handle_nl); + mlx5_os_interrupt_handler_destroy(sh->intr_handle, + mlx5_dev_interrupt_handler, sh); + mlx5_os_interrupt_handler_destroy(sh->intr_handle_nl, + mlx5_dev_interrupt_handler_nl, sh); #ifdef HAVE_IBV_DEVX_ASYNC - if (rte_intr_fd_get(sh->intr_handle_devx) >= 0) - rte_intr_callback_unregister(sh->intr_handle_devx, - mlx5_dev_interrupt_handler_devx, sh); - rte_intr_instance_free(sh->intr_handle_devx); + mlx5_os_interrupt_handler_destroy(sh->intr_handle_devx, + mlx5_dev_interrupt_handler_devx, sh); if (sh->devx_comp) mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); #endif diff --git a/drivers/net/mlx5/linux/mlx5_socket.c b/drivers/net/mlx5/linux/mlx5_socket.c index 4882e5fa2f..0e01aff0e7 100644 --- a/drivers/net/mlx5/linux/mlx5_socket.c +++ b/drivers/net/mlx5/linux/mlx5_socket.c @@ -133,51 +133,6 @@ mlx5_pmd_socket_handle(void *cb __rte_unused) fclose(file); } -/** - * Install interrupt handler. - * - * @param dev - * Pointer to Ethernet device. - * @return - * 0 on success, a negative errno value otherwise. - */ -static int -mlx5_pmd_interrupt_handler_install(void) -{ - MLX5_ASSERT(server_socket != -1); - - server_intr_handle = - rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE); - if (server_intr_handle == NULL) { - DRV_LOG(ERR, "Fail to allocate intr_handle"); - return -ENOMEM; - } - if (rte_intr_fd_set(server_intr_handle, server_socket)) - return -rte_errno; - - if (rte_intr_type_set(server_intr_handle, RTE_INTR_HANDLE_EXT)) - return -rte_errno; - - return rte_intr_callback_register(server_intr_handle, - mlx5_pmd_socket_handle, NULL); -} - -/** - * Uninstall interrupt handler. - */ -static void -mlx5_pmd_interrupt_handler_uninstall(void) -{ - if (server_socket != -1) { - mlx5_intr_callback_unregister(server_intr_handle, - mlx5_pmd_socket_handle, - NULL); - } - rte_intr_fd_set(server_intr_handle, 0); - rte_intr_type_set(server_intr_handle, RTE_INTR_HANDLE_UNKNOWN); - rte_intr_instance_free(server_intr_handle); -} - /** * Initialise the socket to communicate with external tools. * @@ -224,7 +179,10 @@ mlx5_pmd_socket_init(void) strerror(errno)); goto remove; } - if (mlx5_pmd_interrupt_handler_install()) { + server_intr_handle = mlx5_os_interrupt_handler_create + (RTE_INTR_INSTANCE_F_PRIVATE, false, + server_socket, mlx5_pmd_socket_handle, NULL); + if (server_intr_handle == NULL) { DRV_LOG(WARNING, "cannot register interrupt handler for mlx5 socket: %s", strerror(errno)); goto remove; @@ -248,7 +206,8 @@ mlx5_pmd_socket_uninit(void) { if (server_socket == -1) return; - mlx5_pmd_interrupt_handler_uninstall(); + mlx5_os_interrupt_handler_destroy(server_intr_handle, + mlx5_pmd_socket_handle, NULL); claim_zero(close(server_socket)); server_socket = -1; MKSTR(path, MLX5_SOCKET_PATH, getpid()); diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 305edffe71..7ebb2cc961 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1682,8 +1682,6 @@ int mlx5_sysfs_switch_info(unsigned int ifindex, struct mlx5_switch_info *info); void mlx5_translate_port_name(const char *port_name_in, struct mlx5_switch_info *port_info_out); -void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, - rte_intr_callback_fn cb_fn, void *cb_arg); int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex, char *ifname); int mlx5_get_module_info(struct rte_eth_dev *dev, diff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c index fe74317fe8..f853a67f58 100644 --- a/drivers/net/mlx5/mlx5_txpp.c +++ b/drivers/net/mlx5/mlx5_txpp.c @@ -741,11 +741,8 @@ mlx5_txpp_interrupt_handler(void *cb_arg) static void mlx5_txpp_stop_service(struct mlx5_dev_ctx_shared *sh) { - if (!rte_intr_fd_get(sh->txpp.intr_handle)) - return; - mlx5_intr_callback_unregister(sh->txpp.intr_handle, - mlx5_txpp_interrupt_handler, sh); - rte_intr_instance_free(sh->txpp.intr_handle); + mlx5_os_interrupt_handler_destroy(sh->txpp.intr_handle, + mlx5_txpp_interrupt_handler, sh); } /* Attach interrupt handler and fires first request to Rearm Queue. */ @@ -769,23 +766,12 @@ mlx5_txpp_start_service(struct mlx5_dev_ctx_shared *sh) rte_errno = errno; return -rte_errno; } - sh->txpp.intr_handle = - rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); - if (sh->txpp.intr_handle == NULL) { - DRV_LOG(ERR, "Fail to allocate intr_handle"); - return -ENOMEM; - } fd = mlx5_os_get_devx_channel_fd(sh->txpp.echan); - if (rte_intr_fd_set(sh->txpp.intr_handle, fd)) - return -rte_errno; - - if (rte_intr_type_set(sh->txpp.intr_handle, RTE_INTR_HANDLE_EXT)) - return -rte_errno; - - if (rte_intr_callback_register(sh->txpp.intr_handle, - mlx5_txpp_interrupt_handler, sh)) { - rte_intr_fd_set(sh->txpp.intr_handle, 0); - DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno); + sh->txpp.intr_handle = mlx5_os_interrupt_handler_create + (RTE_INTR_INSTANCE_F_SHARED, false, + fd, mlx5_txpp_interrupt_handler, sh); + if (!sh->txpp.intr_handle) { + DRV_LOG(ERR, "Fail to allocate intr_handle"); return -rte_errno; } /* Subscribe CQ event to the event channel controlled by the driver. */ diff --git a/drivers/net/mlx5/windows/mlx5_ethdev_os.c b/drivers/net/mlx5/windows/mlx5_ethdev_os.c index f97526580d..88d8213f55 100644 --- a/drivers/net/mlx5/windows/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/windows/mlx5_ethdev_os.c @@ -140,28 +140,6 @@ mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) return 0; } -/* - * Unregister callback handler safely. The handler may be active - * while we are trying to unregister it, in this case code -EAGAIN - * is returned by rte_intr_callback_unregister(). This routine checks - * the return code and tries to unregister handler again. - * - * @param handle - * interrupt handle - * @param cb_fn - * pointer to callback routine - * @cb_arg - * opaque callback parameter - */ -void -mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, - rte_intr_callback_fn cb_fn, void *cb_arg) -{ - RTE_SET_USED(handle); - RTE_SET_USED(cb_fn); - RTE_SET_USED(cb_arg); -} - /** * DPDK callback to get flow control status. * diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c index e025be47d2..fd447cc650 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c @@ -93,22 +93,10 @@ mlx5_vdpa_virtqs_cleanup(struct mlx5_vdpa_priv *priv) static int mlx5_vdpa_virtq_unset(struct mlx5_vdpa_virtq *virtq) { - int ret = -EAGAIN; - - if (rte_intr_fd_get(virtq->intr_handle) >= 0) { - while (ret == -EAGAIN) { - ret = rte_intr_callback_unregister(virtq->intr_handle, - mlx5_vdpa_virtq_kick_handler, virtq); - if (ret == -EAGAIN) { - DRV_LOG(DEBUG, "Try again to unregister fd %d of virtq %hu interrupt", - rte_intr_fd_get(virtq->intr_handle), - virtq->index); - usleep(MLX5_VDPA_INTR_RETRIES_USEC); - } - } - rte_intr_fd_set(virtq->intr_handle, -1); - } - rte_intr_instance_free(virtq->intr_handle); + int ret; + + mlx5_os_interrupt_handler_destroy(virtq->intr_handle, + mlx5_vdpa_virtq_kick_handler, virtq); if (virtq->virtq) { ret = mlx5_vdpa_virtq_stop(virtq->priv, virtq->index); if (ret) @@ -365,35 +353,13 @@ mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index) virtq->priv = priv; rte_write32(virtq->index, priv->virtq_db_addr); /* Setup doorbell mapping. */ - virtq->intr_handle = - rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); + virtq->intr_handle = mlx5_os_interrupt_handler_create( + RTE_INTR_INSTANCE_F_SHARED, false, + vq.kickfd, mlx5_vdpa_virtq_kick_handler, virtq); if (virtq->intr_handle == NULL) { DRV_LOG(ERR, "Fail to allocate intr_handle"); goto error; } - - if (rte_intr_fd_set(virtq->intr_handle, vq.kickfd)) - goto error; - - if (rte_intr_fd_get(virtq->intr_handle) == -1) { - DRV_LOG(WARNING, "Virtq %d kickfd is invalid.", index); - } else { - if (rte_intr_type_set(virtq->intr_handle, RTE_INTR_HANDLE_EXT)) - goto error; - - if (rte_intr_callback_register(virtq->intr_handle, - mlx5_vdpa_virtq_kick_handler, - virtq)) { - rte_intr_fd_set(virtq->intr_handle, -1); - DRV_LOG(ERR, "Failed to register virtq %d interrupt.", - index); - goto error; - } else { - DRV_LOG(DEBUG, "Register fd %d interrupt for virtq %d.", - rte_intr_fd_get(virtq->intr_handle), - index); - } - } /* Subscribe virtq error event. */ virtq->version++; cookie = ((uint64_t)virtq->version << 32) + index; From patchwork Tue May 24 15:20:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Spike Du X-Patchwork-Id: 111741 X-Patchwork-Delegate: andrew.rybchenko@oktetlabs.ru Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9EDD6A04FF; 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Tue, 24 May 2022 15:21:05 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 24 May 2022 08:21:03 -0700 From: Spike Du To: , , , CC: , Subject: [PATCH v3 3/7] ethdev: introduce Rx queue based limit watermark Date: Tue, 24 May 2022 18:20:37 +0300 Message-ID: <20220524152041.737154-4-spiked@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220524152041.737154-1-spiked@nvidia.com> References: <20220522055900.417282-1-spiked@nvidia.com> <20220524152041.737154-1-spiked@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1663f3c8-e4af-466e-0381-08da3d9905a3 X-MS-TrafficTypeDiagnostic: SA0PR12MB4477:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2022 15:21:05.9269 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1663f3c8-e4af-466e-0381-08da3d9905a3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT011.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4477 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org LWM (limit watermark) describes the fullness of a Rx queue. If the Rx queue fullness is above LWM, the device will trigger the event RTE_ETH_EVENT_RX_LWM. LWM is defined as a percentage of Rx queue size with valid value of [0,99]. Setting LWM to 0 means disable it, which is the default. Add LWM's configuration and query driver callbacks in eth_dev_ops. Signed-off-by: Spike Du --- lib/ethdev/ethdev_driver.h | 22 ++++++++++++ lib/ethdev/rte_ethdev.c | 52 ++++++++++++++++++++++++++++ lib/ethdev/rte_ethdev.h | 71 ++++++++++++++++++++++++++++++++++++++ lib/ethdev/version.map | 2 ++ 4 files changed, 147 insertions(+) diff --git a/lib/ethdev/ethdev_driver.h b/lib/ethdev/ethdev_driver.h index 69d9dc21d8..49e4ef0fbb 100644 --- a/lib/ethdev/ethdev_driver.h +++ b/lib/ethdev/ethdev_driver.h @@ -470,6 +470,23 @@ typedef int (*eth_rx_queue_setup_t)(struct rte_eth_dev *dev, const struct rte_eth_rxconf *rx_conf, struct rte_mempool *mb_pool); +/** + * @internal Set Rx queue limit watermark. + * @see rte_eth_rx_lwm_set() + */ +typedef int (*eth_rx_queue_lwm_set_t)(struct rte_eth_dev *dev, + uint16_t rx_queue_id, + uint8_t lwm); + +/** + * @internal Query queue limit watermark event. + * @see rte_eth_rx_lwm_query() + */ + +typedef int (*eth_rx_queue_lwm_query_t)(struct rte_eth_dev *dev, + uint16_t *rx_queue_id, + uint8_t *lwm); + /** @internal Setup a transmit queue of an Ethernet device. */ typedef int (*eth_tx_queue_setup_t)(struct rte_eth_dev *dev, uint16_t tx_queue_id, @@ -1168,6 +1185,11 @@ struct eth_dev_ops { /** Priority flow control queue configure */ priority_flow_ctrl_queue_config_t priority_flow_ctrl_queue_config; + /** Set Rx queue limit watermark. */ + eth_rx_queue_lwm_set_t rx_queue_lwm_set; + /** Query Rx queue limit watermark event. */ + eth_rx_queue_lwm_query_t rx_queue_lwm_query; + /** Set Unicast Table Array */ eth_uc_hash_table_set_t uc_hash_table_set; /** Set Unicast hash bitmap */ diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c index a175867651..e10e874aae 100644 --- a/lib/ethdev/rte_ethdev.c +++ b/lib/ethdev/rte_ethdev.c @@ -4424,6 +4424,58 @@ int rte_eth_set_queue_rate_limit(uint16_t port_id, uint16_t queue_idx, queue_idx, tx_rate)); } +int rte_eth_rx_lwm_set(uint16_t port_id, uint16_t queue_id, + uint8_t lwm) +{ + struct rte_eth_dev *dev; + struct rte_eth_dev_info dev_info; + int ret; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); + dev = &rte_eth_devices[port_id]; + + ret = rte_eth_dev_info_get(port_id, &dev_info); + if (ret != 0) + return ret; + + if (queue_id > dev_info.max_rx_queues) { + RTE_ETHDEV_LOG(ERR, + "Set queue LWM: port %u: invalid queue ID=%u.\n", + port_id, queue_id); + return -EINVAL; + } + + if (lwm > 99) + return -EINVAL; + RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_lwm_set, -ENOTSUP); + return eth_err(port_id, (*dev->dev_ops->rx_queue_lwm_set)(dev, + queue_id, lwm)); +} + +int rte_eth_rx_lwm_query(uint16_t port_id, uint16_t *queue_id, + uint8_t *lwm) +{ + struct rte_eth_dev_info dev_info; + struct rte_eth_dev *dev; + int ret; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); + dev = &rte_eth_devices[port_id]; + + ret = rte_eth_dev_info_get(port_id, &dev_info); + if (ret != 0) + return ret; + + if (queue_id == NULL) + return -EINVAL; + if (*queue_id >= dev_info.max_rx_queues) + *queue_id = 0; + + RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_lwm_query, -ENOTSUP); + return eth_err(port_id, (*dev->dev_ops->rx_queue_lwm_query)(dev, + queue_id, lwm)); +} + RTE_INIT(eth_dev_init_fp_ops) { uint32_t i; diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h index 04225bba4d..541178fa76 100644 --- a/lib/ethdev/rte_ethdev.h +++ b/lib/ethdev/rte_ethdev.h @@ -1931,6 +1931,14 @@ struct rte_eth_rxq_info { uint8_t queue_state; /**< one of RTE_ETH_QUEUE_STATE_*. */ uint16_t nb_desc; /**< configured number of RXDs. */ uint16_t rx_buf_size; /**< hardware receive buffer size. */ + /** + * Per-queue Rx limit watermark defined as percentage of Rx queue + * size. If Rx queue receives traffic higher than this percentage, + * the event RTE_ETH_EVENT_RX_LWM is triggered. + * Value 0 means watermark monitoring is disabled, no event is + * triggered. + */ + uint8_t lwm; } __rte_cache_min_aligned; /** @@ -3672,6 +3680,64 @@ int rte_eth_dev_get_vlan_offload(uint16_t port_id); */ int rte_eth_dev_set_vlan_pvid(uint16_t port_id, uint16_t pvid, int on); +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Set Rx queue based limit watermark. + * + * @param port_id + * The port identifier of the Ethernet device. + * @param queue_id + * The index of the receive queue. + * @param lwm + * The limit watermark percentage of Rx queue size which describes + * the fullness of Rx queue. If the Rx queue fullness is above LWM, + * the device will trigger the event RTE_ETH_EVENT_RX_LWM. + * [1-99] to set a new LWM. + * 0 to disable watermark monitoring. + * + * @return + * - 0 if successful. + * - negative if failed. + */ +__rte_experimental +int rte_eth_rx_lwm_set(uint16_t port_id, uint16_t queue_id, uint8_t lwm); + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Query Rx queue based limit watermark event. + * The function queries all queues in the port circularly until one + * pending LWM event is found or no pending LWM event is found. + * + * @param port_id + * The port identifier of the Ethernet device. + * @param queue_id + * The API caller sets the starting Rx queue id in the pointer. + * If the queue_id is bigger than maximum queue id of the port, + * it's rewinded to 0 so that application can keep calling + * this function to handle all pending LWM events in the queues + * with a simple increment between calls. + * If a Rx queue has pending LWM event, the pointer is updated + * with this Rx queue id; otherwise this pointer's content is + * unchanged. + * @param lwm + * The pointer to the limit watermark percentage of Rx queue. + * If Rx queue with pending LWM event is found, the queue's LWM + * percentage is stored in this pointer, otherwise the pointer's + * content is unchanged. + * + * @return + * - 1 if a Rx queue with pending LWM event is found. + * - 0 if no Rx queue with pending LWM event is found. + * - -EINVAL if queue_id is NULL. + */ +__rte_experimental +int rte_eth_rx_lwm_query(uint16_t port_id, uint16_t *queue_id, + uint8_t *lwm); + typedef void (*buffer_tx_error_fn)(struct rte_mbuf **unsent, uint16_t count, void *userdata); @@ -3877,6 +3943,11 @@ enum rte_eth_event_type { RTE_ETH_EVENT_DESTROY, /**< port is released */ RTE_ETH_EVENT_IPSEC, /**< IPsec offload related event */ RTE_ETH_EVENT_FLOW_AGED,/**< New aged-out flows is detected */ + /** + * Watermark value is exceeded in a queue. + * @see rte_eth_rx_lwm_set() + */ + RTE_ETH_EVENT_RX_LWM, RTE_ETH_EVENT_MAX /**< max value of this enum */ }; diff --git a/lib/ethdev/version.map b/lib/ethdev/version.map index daca7851f2..2e60765bbd 100644 --- a/lib/ethdev/version.map +++ b/lib/ethdev/version.map @@ -285,6 +285,8 @@ EXPERIMENTAL { rte_mtr_color_in_protocol_priority_get; rte_mtr_color_in_protocol_set; rte_mtr_meter_vlan_table_update; + rte_eth_rx_lwm_set; + rte_eth_rx_lwm_query; }; INTERNAL { From patchwork Tue May 24 15:20:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Spike Du X-Patchwork-Id: 111742 X-Patchwork-Delegate: andrew.rybchenko@oktetlabs.ru Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7D563A04FF; Tue, 24 May 2022 17:21:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2D55F42BA9; Tue, 24 May 2022 17:21:13 +0200 (CEST) Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2048.outbound.protection.outlook.com [40.107.92.48]) by mails.dpdk.org (Postfix) with ESMTP id 7B86342BB0 for ; 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Tue, 24 May 2022 15:21:07 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 24 May 2022 08:21:05 -0700 From: Spike Du To: , , , CC: , Subject: [PATCH v3 4/7] net/mlx5: add LWM event handling support Date: Tue, 24 May 2022 18:20:38 +0300 Message-ID: <20220524152041.737154-5-spiked@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220524152041.737154-1-spiked@nvidia.com> References: <20220522055900.417282-1-spiked@nvidia.com> <20220524152041.737154-1-spiked@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: dffe745e-a94f-41c8-17d7-08da3d99072c X-MS-TrafficTypeDiagnostic: DM5PR1201MB0233:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2022 15:21:08.4873 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dffe745e-a94f-41c8-17d7-08da3d99072c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT042.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0233 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When LWM meets RQ WQE, the kernel driver raises an event to SW. Use devx event_channel to catch this and to notify the user. Allocate this channel per shared device. The channel has a cookie that informs the specific event port and queue. Signed-off-by: Spike Du --- drivers/net/mlx5/mlx5.c | 66 ++++++++++++++++++++++++++++++++++++ drivers/net/mlx5/mlx5.h | 7 ++++ drivers/net/mlx5/mlx5_devx.c | 47 +++++++++++++++++++++++++ drivers/net/mlx5/mlx5_rx.c | 33 ++++++++++++++++++ drivers/net/mlx5/mlx5_rx.h | 7 ++++ 5 files changed, 160 insertions(+) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index f0988712df..e04a66625e 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -22,6 +23,7 @@ #include #include #include +#include #include #include @@ -1524,6 +1526,69 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, return NULL; } +/** + * Create LWM event_channel and interrupt handle for shared device + * context. All rxqs sharing the device context share the event_channel. + * A callback is registered in interrupt thread to receive the LWM event. + * + * @param[in] priv + * Pointer to mlx5_priv instance. + * + * @return + * 0 on success, negative with rte_errno set. + */ +int +mlx5_lwm_setup(struct mlx5_priv *priv) +{ + int fd_lwm; + + pthread_mutex_init(&priv->sh->lwm_config_lock, NULL); + priv->sh->devx_channel_lwm = mlx5_os_devx_create_event_channel + (priv->sh->cdev->ctx, + MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA); + if (!priv->sh->devx_channel_lwm) + goto err; + fd_lwm = mlx5_os_get_devx_channel_fd(priv->sh->devx_channel_lwm); + priv->sh->intr_handle_lwm = mlx5_os_interrupt_handler_create + (RTE_INTR_INSTANCE_F_SHARED, true, + fd_lwm, mlx5_dev_interrupt_handler_lwm, priv); + if (!priv->sh->intr_handle_lwm) + goto err; + return 0; +err: + if (priv->sh->devx_channel_lwm) { + mlx5_os_devx_destroy_event_channel + (priv->sh->devx_channel_lwm); + priv->sh->devx_channel_lwm = NULL; + } + pthread_mutex_destroy(&priv->sh->lwm_config_lock); + return -rte_errno; +} + +/** + * Destroy LWM event_channel and interrupt handle for shared device + * context before free this context. The interrupt handler is also + * unregistered. + * + * @param[in] sh + * Pointer to shared device context. + */ +void +mlx5_lwm_unset(struct mlx5_dev_ctx_shared *sh) +{ + if (sh->intr_handle_lwm) { + mlx5_os_interrupt_handler_destroy(sh->intr_handle_lwm, + mlx5_dev_interrupt_handler_lwm, (void *)-1); + sh->intr_handle_lwm = NULL; + } + if (sh->devx_channel_lwm) { + mlx5_os_devx_destroy_event_channel + (sh->devx_channel_lwm); + sh->devx_channel_lwm = NULL; + } + pthread_mutex_destroy(&sh->lwm_config_lock); +} + /** * Free shared IB device context. Decrement counter and if zero free * all allocated resources and close handles. @@ -1601,6 +1666,7 @@ mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh) claim_zero(mlx5_devx_cmd_destroy(sh->td)); MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL); pthread_mutex_destroy(&sh->txpp.mutex); + mlx5_lwm_unset(sh); mlx5_free(sh); return; exit: diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 7ebb2cc961..a76f2fed3d 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1268,6 +1268,9 @@ struct mlx5_dev_ctx_shared { struct mlx5_lb_ctx self_lb; /* QP to enable self loopback for Devx. */ unsigned int flow_max_priority; enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM]; + void *devx_channel_lwm; + struct rte_intr_handle *intr_handle_lwm; + pthread_mutex_t lwm_config_lock; /* Availability of mreg_c's. */ struct mlx5_dev_shared_port port[]; /* per device port data array. */ }; @@ -1405,6 +1408,7 @@ enum mlx5_txq_modify_type { }; struct mlx5_rxq_priv; +struct mlx5_priv; /* HW objects operations structure. */ struct mlx5_obj_ops { @@ -1413,6 +1417,7 @@ struct mlx5_obj_ops { int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj); int (*rxq_obj_modify)(struct mlx5_rxq_priv *rxq, uint8_t type); void (*rxq_obj_release)(struct mlx5_rxq_priv *rxq); + int (*rxq_event_get_lwm)(struct mlx5_priv *priv, int *rxq_idx, int *port_id); int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n, struct mlx5_ind_table_obj *ind_tbl); int (*ind_table_modify)(struct rte_eth_dev *dev, @@ -1603,6 +1608,8 @@ int mlx5_net_remove(struct mlx5_common_device *cdev); bool mlx5_is_hpf(struct rte_eth_dev *dev); bool mlx5_is_sf_repr(struct rte_eth_dev *dev); void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh); +int mlx5_lwm_setup(struct mlx5_priv *priv); +void mlx5_lwm_unset(struct mlx5_dev_ctx_shared *sh); /* Macro to iterate over all valid ports for mlx5 driver. */ #define MLX5_ETH_FOREACH_DEV(port_id, dev) \ diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index c918a50ae9..6886ae1f22 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -232,6 +232,52 @@ mlx5_rx_devx_get_event(struct mlx5_rxq_obj *rxq_obj) #endif /* HAVE_IBV_DEVX_EVENT */ } +/** + * Get LWM event for shared context, return the correct port/rxq for this event. + * + * @param priv + * Mlx5_priv object. + * @param rxq_idx [out] + * Which rxq gets this event. + * @param port_id [out] + * Which port gets this event. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +mlx5_rx_devx_get_event_lwm(struct mlx5_priv *priv, int *rxq_idx, int *port_id) +{ +#ifdef HAVE_IBV_DEVX_EVENT + union { + struct mlx5dv_devx_async_event_hdr event_resp; + uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128]; + } out; + int ret; + + memset(&out, 0, sizeof(out)); + ret = mlx5_glue->devx_get_event(priv->sh->devx_channel_lwm, + &out.event_resp, + sizeof(out.buf)); + if (ret < 0) { + rte_errno = errno; + DRV_LOG(WARNING, "%s err\n", __func__); + return -rte_errno; + } + *port_id = (((uint32_t)out.event_resp.cookie) >> + LWM_COOKIE_PORTID_OFFSET) & LWM_COOKIE_PORTID_MASK; + *rxq_idx = (((uint32_t)out.event_resp.cookie) >> + LWM_COOKIE_RXQID_OFFSET) & LWM_COOKIE_RXQID_MASK; + return 0; +#else + (void)priv; + (void)rxq_idx; + (void)port_id; + rte_errno = ENOTSUP; + return -rte_errno; +#endif /* HAVE_IBV_DEVX_EVENT */ +} + /** * Create a RQ object using DevX. * @@ -1421,6 +1467,7 @@ struct mlx5_obj_ops devx_obj_ops = { .rxq_event_get = mlx5_rx_devx_get_event, .rxq_obj_modify = mlx5_devx_modify_rq, .rxq_obj_release = mlx5_rxq_devx_obj_release, + .rxq_event_get_lwm = mlx5_rx_devx_get_event_lwm, .ind_table_new = mlx5_devx_ind_table_new, .ind_table_modify = mlx5_devx_ind_table_modify, .ind_table_destroy = mlx5_devx_ind_table_destroy, diff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c index e5eea0ad94..7d556c2b45 100644 --- a/drivers/net/mlx5/mlx5_rx.c +++ b/drivers/net/mlx5/mlx5_rx.c @@ -1187,3 +1187,36 @@ mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused) { return -ENOTSUP; } + +/** + * Rte interrupt handler for LWM event. + * It first checks if the event arrives, if so process the callback for + * RTE_ETH_EVENT_RX_LWM. + * + * @param args + * Generic pointer to mlx5_priv. + */ +void +mlx5_dev_interrupt_handler_lwm(void *args) +{ + struct mlx5_priv *priv = args; + struct mlx5_rxq_priv *rxq; + struct rte_eth_dev *dev; + int ret, rxq_idx = 0, port_id = 0; + + ret = priv->obj_ops.rxq_event_get_lwm(priv, &rxq_idx, &port_id); + if (unlikely(ret < 0)) { + DRV_LOG(WARNING, "Cannot get LWM event context."); + return; + } + DRV_LOG(INFO, "%s get LWM event, port_id:%d rxq_id:%d.", __func__, + port_id, rxq_idx); + dev = &rte_eth_devices[port_id]; + rxq = mlx5_rxq_get(dev, rxq_idx); + if (rxq) { + pthread_mutex_lock(&priv->sh->lwm_config_lock); + rxq->lwm_event_pending = 1; + pthread_mutex_unlock(&priv->sh->lwm_config_lock); + } + rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_RX_LWM, NULL); +} diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index 25a5f2c1fa..068dff5863 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -176,6 +176,7 @@ struct mlx5_rxq_priv { struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ uint32_t hairpin_status; /* Hairpin binding status. */ uint32_t lwm:16; + uint32_t lwm_event_pending:1; }; /* External RX queue descriptor. */ @@ -295,6 +296,7 @@ void mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, struct rte_eth_burst_mode *mode); int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc); +void mlx5_dev_interrupt_handler_lwm(void *args); /* Vectorized version of mlx5_rx.c */ int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data); @@ -675,4 +677,9 @@ mlx5_is_external_rxq(struct rte_eth_dev *dev, uint16_t queue_idx) return !!__atomic_load_n(&rxq->refcnt, __ATOMIC_RELAXED); } +#define LWM_COOKIE_RXQID_OFFSET 0 +#define LWM_COOKIE_RXQID_MASK 0xffff +#define LWM_COOKIE_PORTID_OFFSET 16 +#define LWM_COOKIE_PORTID_MASK 0xffff + #endif /* RTE_PMD_MLX5_RX_H_ */ From patchwork Tue May 24 15:20:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Spike Du X-Patchwork-Id: 111745 X-Patchwork-Delegate: andrew.rybchenko@oktetlabs.ru Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 14504A04FF; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2022 15:21:32.9363 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cbf83dc3-1e93-4d05-198e-08da3d9915c1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6630 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add mlx5 specific LWM(limit watermark) configuration and query handler. While the Rx queue fullness reaches the LWM limit, the driver catches an HW event and invokes the user callback. The query handler finds the next RX queue with pending LWM event if any, starting from the given RX queue index. Signed-off-by: Spike Du --- doc/guides/nics/mlx5.rst | 12 ++ doc/guides/rel_notes/release_22_07.rst | 1 + drivers/common/mlx5/mlx5_prm.h | 1 + drivers/net/mlx5/mlx5.c | 2 + drivers/net/mlx5/mlx5_rx.c | 156 +++++++++++++++++++++++++ drivers/net/mlx5/mlx5_rx.h | 5 + 6 files changed, 177 insertions(+) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index d83c56de11..79f56018ef 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -93,6 +93,7 @@ Features - Connection tracking. - Sub-Function representors. - Sub-Function. +- Rx queue LWM (Limit WaterMark) configuration. Limitations @@ -520,6 +521,9 @@ Limitations - The NIC egress flow rules on representor port are not supported. +- LWM: + + - Doesn't support shared Rx queue and Hairpin Rx queue. Statistics ---------- @@ -1680,3 +1684,11 @@ The procedure below is an example of using a ConnectX-5 adapter card (pf0) with #. For each VF PCIe, using the following command to bind the driver:: $ echo "0000:82:00.2" >> /sys/bus/pci/drivers/mlx5_core/bind + +LWM introduction +---------------- + +LWM (Limit WaterMark) is a per Rx queue attribute, it should be configured as +a percentage of the Rx queue size. +When Rx queue fullness is above LWM, an event is sent to PMD. + diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index 0ed4f92820..34f86eaffa 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -89,6 +89,7 @@ New Features * Added support for promiscuous mode on Windows. * Added support for MTU on Windows. * Added matching and RSS on IPsec ESP. + * Added Rx queue LWM(Limit WaterMark) support. * **Updated Marvell cnxk crypto driver.** diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 630b2c5100..3b5e60532a 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3293,6 +3293,7 @@ struct mlx5_aso_wqe { enum { MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27, + MLX5_EVENT_TYPE_SRQ_LIMIT_REACHED = 0x14, }; enum { diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index e04a66625e..35ae51b3af 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -2071,6 +2071,8 @@ const struct eth_dev_ops mlx5_dev_ops = { .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, .vlan_filter_set = mlx5_vlan_filter_set, .rx_queue_setup = mlx5_rx_queue_setup, + .rx_queue_lwm_set = mlx5_rx_queue_lwm_set, + .rx_queue_lwm_query = mlx5_rx_queue_lwm_query, .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, .tx_queue_setup = mlx5_tx_queue_setup, .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, diff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c index 7d556c2b45..406eae9b39 100644 --- a/drivers/net/mlx5/mlx5_rx.c +++ b/drivers/net/mlx5/mlx5_rx.c @@ -19,12 +19,14 @@ #include #include #include +#include #include "mlx5_autoconf.h" #include "mlx5_defs.h" #include "mlx5.h" #include "mlx5_utils.h" #include "mlx5_rxtx.h" +#include "mlx5_devx.h" #include "mlx5_rx.h" @@ -128,6 +130,17 @@ mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset) return RTE_ETH_RX_DESC_AVAIL; } +/* Get rxq lwm percentage according to lwm number. */ +static uint8_t +mlx5_rxq_lwm_to_percentage(struct mlx5_rxq_priv *rxq) +{ + struct mlx5_rxq_data *rxq_data = &rxq->ctrl->rxq; + uint32_t wqe_cnt = 1 << rxq_data->elts_n; + + /* ethdev LWM describes fullness, mlx5 LWM describes emptiness. */ + return rxq->lwm ? (100 - rxq->lwm * 100 / wqe_cnt) : 0; +} + /** * DPDK callback to get the RX queue information. * @@ -150,6 +163,7 @@ mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, { struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, rx_queue_id); struct mlx5_rxq_data *rxq = mlx5_rxq_data_get(dev, rx_queue_id); + struct mlx5_rxq_priv *rxq_priv = mlx5_rxq_get(dev, rx_queue_id); if (!rxq) return; @@ -169,6 +183,8 @@ mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, qinfo->nb_desc = mlx5_rxq_mprq_enabled(rxq) ? RTE_BIT32(rxq->elts_n) * RTE_BIT32(rxq->log_strd_num) : RTE_BIT32(rxq->elts_n); + qinfo->lwm = rxq_priv ? + mlx5_rxq_lwm_to_percentage(rxq_priv) : 0; } /** @@ -1188,6 +1204,34 @@ mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused) return -ENOTSUP; } +int +mlx5_rx_queue_lwm_query(struct rte_eth_dev *dev, + uint16_t *queue_id, uint8_t *lwm) +{ + struct mlx5_priv *priv = dev->data->dev_private; + unsigned int rxq_id, found = 0, n; + struct mlx5_rxq_priv *rxq; + + if (!queue_id) + return -EINVAL; + /* Query all the Rx queues of the port in a circular way. */ + for (rxq_id = *queue_id, n = 0; n < priv->rxqs_n; n++) { + rxq = mlx5_rxq_get(dev, rxq_id); + if (rxq && rxq->lwm_event_pending) { + pthread_mutex_lock(&priv->sh->lwm_config_lock); + rxq->lwm_event_pending = 0; + pthread_mutex_unlock(&priv->sh->lwm_config_lock); + *queue_id = rxq_id; + found = 1; + if (lwm) + *lwm = mlx5_rxq_lwm_to_percentage(rxq); + break; + } + rxq_id = (rxq_id + 1) % priv->rxqs_n; + } + return found; +} + /** * Rte interrupt handler for LWM event. * It first checks if the event arrives, if so process the callback for @@ -1220,3 +1264,115 @@ mlx5_dev_interrupt_handler_lwm(void *args) } rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_RX_LWM, NULL); } + +/** + * DPDK callback to arm an Rx queue LWM(limit watermark) event. + * While the Rx queue fullness reaches the LWM limit, the driver catches + * an HW event and invokes the user event callback. + * After the last event handling, the user needs to call this API again + * to arm an additional event. + * + * @param dev + * Pointer to the device structure. + * @param[in] rx_queue_id + * Rx queue identificator. + * @param[in] lwm + * The LWM value, is defined by a percentage of the Rx queue size. + * [1-99] to set a new LWM (update the old value). + * 0 to unarm the event. + * + * @return + * 0 : operation success. + * Otherwise: + * - ENOMEM - not enough memory to create LWM event channel. + * - EINVAL - the input Rxq is not created by devx. + * - E2BIG - lwm is bigger than 99. + */ +int +mlx5_rx_queue_lwm_set(struct rte_eth_dev *dev, uint16_t rx_queue_id, + uint8_t lwm) +{ + struct mlx5_priv *priv = dev->data->dev_private; + uint16_t port_id = PORT_ID(priv); + struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, rx_queue_id); + uint16_t event_nums[1] = {MLX5_EVENT_TYPE_SRQ_LIMIT_REACHED}; + struct mlx5_rxq_data *rxq_data; + uint32_t wqe_cnt; + uint64_t cookie; + int ret = 0; + + if (!rxq) { + rte_errno = EINVAL; + return -rte_errno; + } + rxq_data = &rxq->ctrl->rxq; + /* Ensure the Rq is created by devx. */ + if (priv->obj_ops.rxq_obj_new != devx_obj_ops.rxq_obj_new) { + rte_errno = EINVAL; + return -rte_errno; + } + if (lwm > 99) { + DRV_LOG(WARNING, "Too big LWM configuration."); + rte_errno = E2BIG; + return -rte_errno; + } + /* Start config LWM. */ + pthread_mutex_lock(&priv->sh->lwm_config_lock); + if (rxq->lwm == 0 && lwm == 0) { + /* Both old/new values are 0, do nothing. */ + ret = 0; + goto end; + } + wqe_cnt = 1 << rxq_data->elts_n; + if (lwm) { + if (!priv->sh->devx_channel_lwm) { + ret = mlx5_lwm_setup(priv); + if (ret) { + DRV_LOG(WARNING, + "Failed to create shared_lwm."); + rte_errno = ENOMEM; + ret = -rte_errno; + goto end; + } + } + if (!rxq->lwm_devx_subscribed) { + cookie = ((uint32_t) + (port_id << LWM_COOKIE_PORTID_OFFSET)) | + (rx_queue_id << LWM_COOKIE_RXQID_OFFSET); + ret = mlx5_os_devx_subscribe_devx_event + (priv->sh->devx_channel_lwm, + rxq->devx_rq.rq->obj, + sizeof(event_nums), + event_nums, + cookie); + if (ret) { + rte_errno = rte_errno ? rte_errno : EINVAL; + ret = -rte_errno; + goto end; + } + rxq->lwm_devx_subscribed = 1; + } + } + /* The ethdev LWM describes fullness, mlx5 lwm describes emptiness. */ + if (lwm) + lwm = 100 - lwm; + /* Save LWM to rxq and send modify_rq devx command. */ + rxq->lwm = lwm * wqe_cnt / 100; + /* Prevent integer division loss when switch lwm number to percentage. */ + if (lwm && (lwm * wqe_cnt % 100)) { + rxq->lwm = ((uint32_t)(rxq->lwm + 1) >= wqe_cnt) ? + rxq->lwm : (rxq->lwm + 1); + } + if (lwm && !rxq->lwm) { + /* With mprq, wqe_cnt may be < 100. */ + DRV_LOG(WARNING, "Too small LWM configuration."); + rte_errno = EINVAL; + ret = -rte_errno; + goto end; + } + ret = mlx5_devx_modify_rq(rxq, MLX5_RXQ_MOD_RDY2RDY); +end: + pthread_mutex_unlock(&priv->sh->lwm_config_lock); + return ret; +} + diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index 068dff5863..e078aaf3dc 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -177,6 +177,7 @@ struct mlx5_rxq_priv { uint32_t hairpin_status; /* Hairpin binding status. */ uint32_t lwm:16; uint32_t lwm_event_pending:1; + uint32_t lwm_devx_subscribed:1; }; /* External RX queue descriptor. */ @@ -297,6 +298,10 @@ int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, struct rte_eth_burst_mode *mode); int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc); void mlx5_dev_interrupt_handler_lwm(void *args); +int mlx5_rx_queue_lwm_set(struct rte_eth_dev *dev, uint16_t rx_queue_id, + uint8_t lwm); +int mlx5_rx_queue_lwm_query(struct rte_eth_dev *dev, uint16_t *rx_queue_id, + uint8_t *lwm); /* Vectorized version of mlx5_rx.c */ int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data); From patchwork Tue May 24 15:20:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Spike Du X-Patchwork-Id: 111743 X-Patchwork-Delegate: andrew.rybchenko@oktetlabs.ru Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8808AA04FF; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2022 15:21:13.1377 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 57994183-2c7b-4d1b-8763-08da3d990a09 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1262 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Host port shaper can be configured with QSHR(QoS Shaper Host Register). Add check in build files to enable this function or not. The host shaper configuration affects all the ethdev ports belonging to the same host port. Host shaper can configure shaper rate and lwm-triggered for a host port. The shaper limits the rate of traffic from host port to wire port. If lwm-triggered is enabled, a 100Mbps shaper is enabled automatically when one of the host port's Rx queues receives LWM(Limit Watermark) event. Signed-off-by: Spike Du --- doc/guides/nics/mlx5.rst | 26 +++++++ doc/guides/rel_notes/release_22_07.rst | 1 + drivers/common/mlx5/linux/meson.build | 13 ++++ drivers/common/mlx5/mlx5_prm.h | 25 ++++++ drivers/net/mlx5/mlx5.h | 2 + drivers/net/mlx5/mlx5_rx.c | 103 +++++++++++++++++++++++++ drivers/net/mlx5/rte_pmd_mlx5.h | 30 +++++++ drivers/net/mlx5/version.map | 2 + 8 files changed, 202 insertions(+) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 79f56018ef..3da6f5a03c 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -94,6 +94,7 @@ Features - Sub-Function representors. - Sub-Function. - Rx queue LWM (Limit WaterMark) configuration. +- Host shaper support. Limitations @@ -525,6 +526,12 @@ Limitations - Doesn't support shared Rx queue and Hairpin Rx queue. +- Host shaper: + + - Support BlueField series NIC from BlueField 2. + - When configure host shaper with MLX5_HOST_SHAPER_FLAG_LWM_TRIGGERED flag set, + only rate 0 and 100Mbps are supported. + Statistics ---------- @@ -1692,3 +1699,22 @@ LWM (Limit WaterMark) is a per Rx queue attribute, it should be configured as a percentage of the Rx queue size. When Rx queue fullness is above LWM, an event is sent to PMD. +Host shaper introduction +------------------------ + +Host shaper register is per host port register which sets a shaper +on the host port. +All VF/hostPF representors belonging to one host port share one host shaper. +For example, if representor 0 and representor 1 belong to same host port, +and a host shaper rate of 1Gbps is configured, the shaper throttles both +representors' traffic from host. +Host shaper has two modes for setting the shaper, immediate and deferred to +LWM event trigger. In immediate mode, the rate limit is configured immediately +to host shaper. When deferring to LWM trigger, the shaper is not set until an +LWM event is received by any Rx queue in a VF representor belonging to the host +port. The only rate supported for deferred mode is 100Mbps (there is no limit +on the supported rates for immediate mode). In deferred mode, the shaper is set +on the host port by the firmware upon receiving the LMW event, which allows +throttling host traffic on LWM events at minimum latency, preventing excess +drops in the Rx queue. + diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index 34f86eaffa..94720af3af 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -90,6 +90,7 @@ New Features * Added support for MTU on Windows. * Added matching and RSS on IPsec ESP. * Added Rx queue LWM(Limit WaterMark) support. + * Added host shaper support. * **Updated Marvell cnxk crypto driver.** diff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build index 5335f5b027..51c6e5dd2e 100644 --- a/drivers/common/mlx5/linux/meson.build +++ b/drivers/common/mlx5/linux/meson.build @@ -45,6 +45,13 @@ if static_ibverbs ext_deps += declare_dependency(link_args:ibv_ldflags.split()) endif +libmtcr_ul_found = false +lib = cc.find_library('mtcr_ul', required:false) +if lib.found() and run_command('meson', '--version').stdout().version_compare('>= 0.49.2') + libmtcr_ul_found = true + ext_deps += lib +endif + sources += files('mlx5_nl.c') sources += files('mlx5_common_auxiliary.c') sources += files('mlx5_common_os.c') @@ -207,6 +214,12 @@ has_sym_args = [ [ 'HAVE_MLX5_IBV_IMPORT_CTX_PD_AND_MR', 'infiniband/verbs.h', 'ibv_import_device' ], ] +if libmtcr_ul_found + has_sym_args += [ + [ 'HAVE_MLX5_MSTFLINT', 'mstflint/mtcr.h', + 'mopen'], + ] +endif config = configuration_data() foreach arg:has_sym_args config.set(arg[0], cc.has_header_symbol(arg[1], arg[2], dependencies: libs)) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 3b5e60532a..92d05a7368 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3771,6 +3771,7 @@ enum { MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003, MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004, MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005, + MLX5_QSHR_REGISTER_ID = 0x4030, }; struct mlx5_ifc_register_mtutc_bits { @@ -3785,6 +3786,30 @@ struct mlx5_ifc_register_mtutc_bits { u8 time_adjustment[0x20]; }; +struct mlx5_ifc_ets_global_config_register_bits { + u8 reserved_at_0[0x2]; + u8 rate_limit_update[0x1]; + u8 reserved_at_3[0x29]; + u8 max_bw_units[0x4]; + u8 reserved_at_48[0x8]; + u8 max_bw_value[0x8]; +}; + +#define ETS_GLOBAL_CONFIG_BW_UNIT_DISABLED 0x0 +#define ETS_GLOBAL_CONFIG_BW_UNIT_HUNDREDS_MBPS 0x3 +#define ETS_GLOBAL_CONFIG_BW_UNIT_GBPS 0x4 + +struct mlx5_ifc_register_qshr_bits { + u8 reserved_at_0[0x4]; + u8 connected_host[0x1]; + u8 vqos[0x1]; + u8 fast_response[0x1]; + u8 reserved_at_7[0x1]; + u8 local_port[0x8]; + u8 reserved_at_16[0x230]; + struct mlx5_ifc_ets_global_config_register_bits global_config; +}; + #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1 diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index a76f2fed3d..8af84aef50 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1271,6 +1271,8 @@ struct mlx5_dev_ctx_shared { void *devx_channel_lwm; struct rte_intr_handle *intr_handle_lwm; pthread_mutex_t lwm_config_lock; + uint32_t host_shaper_rate:8; + uint32_t lwm_triggered:1; /* Availability of mreg_c's. */ struct mlx5_dev_shared_port port[]; /* per device port data array. */ }; diff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c index 406eae9b39..b503d89289 100644 --- a/drivers/net/mlx5/mlx5_rx.c +++ b/drivers/net/mlx5/mlx5_rx.c @@ -28,6 +28,9 @@ #include "mlx5_rxtx.h" #include "mlx5_devx.h" #include "mlx5_rx.h" +#ifdef HAVE_MLX5_MSTFLINT +#include +#endif static __rte_always_inline uint32_t @@ -1376,3 +1379,103 @@ mlx5_rx_queue_lwm_set(struct rte_eth_dev *dev, uint16_t rx_queue_id, return ret; } +/** + * Mlx5 access register function to configure host shaper. + * It calls API in libmtcr_ul to access QSHR(Qos Shaper Host Register) + * in firmware. + * + * @param dev + * Pointer to rte_eth_dev. + * @param lwm_triggered + * Flag to enable/disable lwm_triggered bit in QSHR. + * @param rate + * Host shaper rate, unit is 100Mbps, set to 0 means disable the shaper. + * @return + * 0 : operation success. + * Otherwise: + * - ENOENT - no ibdev interface. + * - EBUSY - the register access unit is busy. + * - EIO - the register access command meets IO error. + */ +static int +mlxreg_host_shaper_config(struct rte_eth_dev *dev, + bool lwm_triggered, uint8_t rate) +{ +#ifdef HAVE_MLX5_MSTFLINT + struct mlx5_priv *priv = dev->data->dev_private; + uint32_t data[MLX5_ST_SZ_DW(register_qshr)] = {0}; + int rc, retry_count = 3; + mfile *mf = NULL; + int status; + void *ptr; + + mf = mopen(priv->sh->ibdev_name); + if (!mf) { + DRV_LOG(WARNING, "mopen failed\n"); + rte_errno = ENOENT; + return -rte_errno; + } + MLX5_SET(register_qshr, data, connected_host, 1); + MLX5_SET(register_qshr, data, fast_response, lwm_triggered ? 1 : 0); + MLX5_SET(register_qshr, data, local_port, 1); + ptr = MLX5_ADDR_OF(register_qshr, data, global_config); + MLX5_SET(ets_global_config_register, ptr, rate_limit_update, 1); + MLX5_SET(ets_global_config_register, ptr, max_bw_units, + rate ? ETS_GLOBAL_CONFIG_BW_UNIT_HUNDREDS_MBPS : + ETS_GLOBAL_CONFIG_BW_UNIT_DISABLED); + MLX5_SET(ets_global_config_register, ptr, max_bw_value, rate); + do { + rc = maccess_reg(mf, + MLX5_QSHR_REGISTER_ID, + MACCESS_REG_METHOD_SET, + (u_int32_t *)&data[0], + sizeof(data), + sizeof(data), + sizeof(data), + &status); + if ((rc != ME_ICMD_STATUS_IFC_BUSY && + status != ME_REG_ACCESS_BAD_PARAM) || + !(mf->flags & MDEVS_REM)) { + break; + } + DRV_LOG(WARNING, "%s retry.", __func__); + usleep(10000); + } while (retry_count-- > 0); + mclose(mf); + rte_errno = (rc == ME_REG_ACCESS_DEV_BUSY) ? EBUSY : EIO; + return rc ? -rte_errno : 0; +#else + (void)dev; + (void)lwm_triggered; + (void)rate; + return -1; +#endif +} + +int rte_pmd_mlx5_host_shaper_config(int port_id, uint8_t rate, + uint32_t flags) +{ + struct rte_eth_dev *dev = &rte_eth_devices[port_id]; + struct mlx5_priv *priv = dev->data->dev_private; + bool lwm_triggered = + !!(flags & RTE_BIT32(MLX5_HOST_SHAPER_FLAG_LWM_TRIGGERED)); + + if (!lwm_triggered) { + priv->sh->host_shaper_rate = rate; + } else { + switch (rate) { + case 0: + /* Rate 0 means disable lwm_triggered. */ + priv->sh->lwm_triggered = 0; + break; + case 1: + /* Rate 1 means enable lwm_triggered. */ + priv->sh->lwm_triggered = 1; + break; + default: + return -ENOTSUP; + } + } + return mlxreg_host_shaper_config(dev, priv->sh->lwm_triggered, + priv->sh->host_shaper_rate); +} diff --git a/drivers/net/mlx5/rte_pmd_mlx5.h b/drivers/net/mlx5/rte_pmd_mlx5.h index 6e7907ee59..9964126df5 100644 --- a/drivers/net/mlx5/rte_pmd_mlx5.h +++ b/drivers/net/mlx5/rte_pmd_mlx5.h @@ -109,6 +109,36 @@ __rte_experimental int rte_pmd_mlx5_external_rx_queue_id_unmap(uint16_t port_id, uint16_t dpdk_idx); +/** + * The rate of the host port shaper will be updated directly at the next + * LWM event to the rate that comes with this flag set; set rate 0 + * to disable this rate update. + * Unset this flag to update the rate of the host port shaper directly in + * the API call; use rate 0 to disable the current shaper. + */ +#define MLX5_HOST_SHAPER_FLAG_LWM_TRIGGERED 0 + +/** + * Configure a HW shaper to limit Tx rate for a host port. + * The configuration will affect all the ethdev ports belonging to + * the same rte_device. + * + * @param[in] port_id + * The port identifier of the Ethernet device. + * @param[in] rate + * Unit is 100Mbps, setting the rate to 0 disables the shaper. + * @param[in] flags + * Host shaper flags. + * @return + * 0 : operation success. + * Otherwise: + * - ENOENT - no ibdev interface. + * - EBUSY - the register access unit is busy. + * - EIO - the register access command meets IO error. + */ +__rte_experimental +int rte_pmd_mlx5_host_shaper_config(int port_id, uint8_t rate, uint32_t flags); + #ifdef __cplusplus } #endif diff --git a/drivers/net/mlx5/version.map b/drivers/net/mlx5/version.map index 79cb79acc6..c97dfe440a 100644 --- a/drivers/net/mlx5/version.map +++ b/drivers/net/mlx5/version.map @@ -12,4 +12,6 @@ EXPERIMENTAL { # added in 22.03 rte_pmd_mlx5_external_rx_queue_id_map; rte_pmd_mlx5_external_rx_queue_id_unmap; + # added in 22.07 + rte_pmd_mlx5_host_shaper_config; }; From patchwork Tue May 24 15:20:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Spike Du X-Patchwork-Id: 111744 X-Patchwork-Delegate: andrew.rybchenko@oktetlabs.ru Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 251C9A04FF; Tue, 24 May 2022 17:21:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 19A5E42BB7; Tue, 24 May 2022 17:21:19 +0200 (CEST) Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2052.outbound.protection.outlook.com [40.107.93.52]) by mails.dpdk.org (Postfix) with ESMTP id 4ECE14281F for ; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2022 15:21:15.1587 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3322feb7-fb7a-44d1-72ef-08da3d990b28 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT042.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2889 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add command line options to support LWM per-rxq configure. - Command syntax: set port rxq lwm mlx5 set port host_shaper lwm_triggered <0|1> rate - Example commands: To configure LWM as 30% of rxq size on port 1 rxq 0: testpmd> set port 1 rxq 0 lwm 30 To disable LWM on port 1 rxq 0: testpmd> set port 1 rxq 0 lwm 0 To enable lwm_triggered on port 1 and disable current host shaper: testpmd> mlx5 set port 1 host_shaper lwm_triggered 1 rate 0 To disable lwm_triggered and current host shaper on port 1: testpmd> mlx5 set port 1 host_shaper lwm_triggered 0 rate 0 The rate unit is 100Mbps. To disable lwm_triggered and configure a shaper of 5Gbps on port 1: testpmd> mlx5 set port 1 host_shaper lwm_triggered 0 rate 50 Add sample code to handle rxq LWM event, it delays a while so that rxq empties, then disables host shaper and rearms LWM event. Signed-off-by: Spike Du --- app/test-pmd/cmdline.c | 74 +++++++++++++ app/test-pmd/config.c | 21 ++++ app/test-pmd/meson.build | 4 + app/test-pmd/testpmd.c | 24 +++++ app/test-pmd/testpmd.h | 1 + doc/guides/nics/mlx5.rst | 46 ++++++++ drivers/net/mlx5/mlx5_testpmd.c | 184 ++++++++++++++++++++++++++++++++ drivers/net/mlx5/mlx5_testpmd.h | 27 +++++ 8 files changed, 381 insertions(+) create mode 100644 drivers/net/mlx5/mlx5_testpmd.c create mode 100644 drivers/net/mlx5/mlx5_testpmd.h diff --git a/app/test-pmd/cmdline.c b/app/test-pmd/cmdline.c index 1e5b294ab3..86342f2ac6 100644 --- a/app/test-pmd/cmdline.c +++ b/app/test-pmd/cmdline.c @@ -67,6 +67,9 @@ #include "cmdline_mtr.h" #include "cmdline_tm.h" #include "bpf_cmd.h" +#ifdef RTE_NET_MLX5 +#include "mlx5_testpmd.h" +#endif static struct cmdline *testpmd_cl; @@ -17804,6 +17807,73 @@ cmdline_parse_inst_t cmd_show_port_flow_transfer_proxy = { } }; +/* *** SET LIMIT WARTER MARK FOR A RXQ OF A PORT *** */ +struct cmd_rxq_lwm_result { + cmdline_fixed_string_t set; + cmdline_fixed_string_t port; + uint16_t port_num; + cmdline_fixed_string_t rxq; + uint16_t rxq_num; + cmdline_fixed_string_t lwm; + uint16_t lwm_num; +}; + +static void cmd_rxq_lwm_parsed(void *parsed_result, + __rte_unused struct cmdline *cl, + __rte_unused void *data) +{ + struct cmd_rxq_lwm_result *res = parsed_result; + int ret = 0; + + if ((strcmp(res->set, "set") == 0) && (strcmp(res->port, "port") == 0) + && (strcmp(res->rxq, "rxq") == 0) + && (strcmp(res->lwm, "lwm") == 0)) + ret = set_rxq_lwm(res->port_num, res->rxq_num, + res->lwm_num); + if (ret < 0) + printf("rxq_lwm_cmd error: (%s)\n", strerror(-ret)); + +} + +cmdline_parse_token_string_t cmd_rxq_lwm_set = + TOKEN_STRING_INITIALIZER(struct cmd_rxq_lwm_result, + set, "set"); +cmdline_parse_token_string_t cmd_rxq_lwm_port = + TOKEN_STRING_INITIALIZER(struct cmd_rxq_lwm_result, + port, "port"); +cmdline_parse_token_num_t cmd_rxq_lwm_portnum = + TOKEN_NUM_INITIALIZER(struct cmd_rxq_lwm_result, + port_num, RTE_UINT16); +cmdline_parse_token_string_t cmd_rxq_lwm_rxq = + TOKEN_STRING_INITIALIZER(struct cmd_rxq_lwm_result, + rxq, "rxq"); +cmdline_parse_token_num_t cmd_rxq_lwm_rxqnum = + TOKEN_NUM_INITIALIZER(struct cmd_rxq_lwm_result, + rxq_num, RTE_UINT8); +cmdline_parse_token_string_t cmd_rxq_lwm_lwm = + TOKEN_STRING_INITIALIZER(struct cmd_rxq_lwm_result, + lwm, "lwm"); +cmdline_parse_token_num_t cmd_rxq_lwm_lwmnum = + TOKEN_NUM_INITIALIZER(struct cmd_rxq_lwm_result, + lwm_num, RTE_UINT16); + +cmdline_parse_inst_t cmd_rxq_lwm = { + .f = cmd_rxq_lwm_parsed, + .data = (void *)0, + .help_str = "set port rxq lwm " + "Set lwm for rxq on port_id", + .tokens = { + (void *)&cmd_rxq_lwm_set, + (void *)&cmd_rxq_lwm_port, + (void *)&cmd_rxq_lwm_portnum, + (void *)&cmd_rxq_lwm_rxq, + (void *)&cmd_rxq_lwm_rxqnum, + (void *)&cmd_rxq_lwm_lwm, + (void *)&cmd_rxq_lwm_lwmnum, + NULL, + }, +}; + /* ******************************************************************************** */ /* list of instructions */ @@ -18091,6 +18161,10 @@ cmdline_parse_ctx_t main_ctx[] = { (cmdline_parse_inst_t *)&cmd_show_capability, (cmdline_parse_inst_t *)&cmd_set_flex_is_pattern, (cmdline_parse_inst_t *)&cmd_set_flex_spec_pattern, + (cmdline_parse_inst_t *)&cmd_rxq_lwm, +#ifdef RTE_NET_MLX5 + (cmdline_parse_inst_t *)&mlx5_test_cmd_port_host_shaper, +#endif NULL, }; diff --git a/app/test-pmd/config.c b/app/test-pmd/config.c index 1b1e738f83..a752c6367f 100644 --- a/app/test-pmd/config.c +++ b/app/test-pmd/config.c @@ -6342,3 +6342,24 @@ show_mcast_macs(portid_t port_id) printf(" %s\n", buf); } } + +int +set_rxq_lwm(portid_t port_id, uint16_t queue_idx, uint16_t lwm) +{ + struct rte_eth_link link; + int ret; + + if (port_id_is_invalid(port_id, ENABLED_WARN)) + return -EINVAL; + ret = eth_link_get_nowait_print_err(port_id, &link); + if (ret < 0) + return -EINVAL; + if (lwm > 99) + return -EINVAL; + ret = rte_eth_rx_lwm_set(port_id, queue_idx, lwm); + + if (ret) + return ret; + return 0; +} + diff --git a/app/test-pmd/meson.build b/app/test-pmd/meson.build index 43130c8856..c3577a02c1 100644 --- a/app/test-pmd/meson.build +++ b/app/test-pmd/meson.build @@ -73,3 +73,7 @@ endif if dpdk_conf.has('RTE_NET_DPAA') deps += ['bus_dpaa', 'mempool_dpaa', 'net_dpaa'] endif +if dpdk_conf.has('RTE_NET_MLX5') + deps += 'net_mlx5' + sources += files('../../drivers/net/mlx5/mlx5_testpmd.c') +endif diff --git a/app/test-pmd/testpmd.c b/app/test-pmd/testpmd.c index 777763f749..ee6693dddf 100644 --- a/app/test-pmd/testpmd.c +++ b/app/test-pmd/testpmd.c @@ -69,6 +69,9 @@ #ifdef RTE_NET_BOND #include #endif +#ifdef RTE_NET_MLX5 +#include "mlx5_testpmd.h" +#endif #include "testpmd.h" @@ -420,6 +423,7 @@ static const char * const eth_event_desc[] = { [RTE_ETH_EVENT_NEW] = "device probed", [RTE_ETH_EVENT_DESTROY] = "device released", [RTE_ETH_EVENT_FLOW_AGED] = "flow aged", + [RTE_ETH_EVENT_RX_LWM] = "rxq limit reached", [RTE_ETH_EVENT_MAX] = NULL, }; @@ -3616,6 +3620,10 @@ static int eth_event_callback(portid_t port_id, enum rte_eth_event_type type, void *param, void *ret_param) { + struct rte_eth_dev_info dev_info; + uint16_t rxq_id; + uint8_t lwm; + int ret; RTE_SET_USED(param); RTE_SET_USED(ret_param); @@ -3647,6 +3655,22 @@ eth_event_callback(portid_t port_id, enum rte_eth_event_type type, void *param, ports[port_id].port_status = RTE_PORT_CLOSED; printf("Port %u is closed\n", port_id); break; + case RTE_ETH_EVENT_RX_LWM: + ret = rte_eth_dev_info_get(port_id, &dev_info); + if (ret != 0) + break; + /* LWM query API rewinds rxq_id, no need to check max rxq num. */ + for (rxq_id = 0; ; rxq_id++) { + ret = rte_eth_rx_lwm_query(port_id, &rxq_id, &lwm); + if (ret <= 0) + break; + printf("Received LWM event, port:%d rxq_id:%d\n", + port_id, rxq_id); +#ifdef RTE_NET_MLX5 + mlx5_test_lwm_event_handler(port_id, rxq_id); +#endif + } + break; default: break; } diff --git a/app/test-pmd/testpmd.h b/app/test-pmd/testpmd.h index f04a9a11b4..f2ecbe7013 100644 --- a/app/test-pmd/testpmd.h +++ b/app/test-pmd/testpmd.h @@ -1166,6 +1166,7 @@ int update_jumbo_frame_offload(portid_t portid); void flex_item_create(portid_t port_id, uint16_t flex_id, const char *filename); void flex_item_destroy(portid_t port_id, uint16_t flex_id); void port_flex_item_flush(portid_t port_id); +int set_rxq_lwm(portid_t port_id, uint16_t queue_idx, uint16_t lwm); extern int flow_parse(const char *src, void *result, unsigned int size, struct rte_flow_attr **attr, diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 3da6f5a03c..fb1c957544 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -1718,3 +1718,49 @@ on the host port by the firmware upon receiving the LMW event, which allows throttling host traffic on LWM events at minimum latency, preventing excess drops in the Rx queue. +How to use LWM and Host Shaper +------------------------------ + +There are sample command lines to configure LWM in testpmd. +Testpmd also contains sample logic to handle LWM event. +The typical workflow is: testpmd configure LWM for Rx queues, enable +lwm_triggered in host shaper and register a callback, when traffic from host is +too high and Rx queue fullness is above LWM, PMD receives an event and +firmware configures a 100Mbps shaper on host port automatically, then PMD call +the callback registered previously, which will delay a while to let Rx queue +empty, then disable host shaper. + +Let's assume we have a simple Blue Field 2 setup: port 0 is uplink, port 1 +is VF representor. Each port has 2 Rx queues. +In order to control traffic from host to ARM, we can enable LWM in testpmd by: + +.. code-block:: console + + testpmd> mlx5 set port 1 host_shaper lwm_triggered 1 rate 0 + testpmd> set port 1 rxq 0 lwm 70 + testpmd> set port 1 rxq 1 lwm 70 + +The first command disables current host shaper, and enables LWM triggered mode. +The left commands configure LWM to 70% of Rx queue size for both Rx queues, +When traffic from host is too high, you can see testpmd console prints log +about LWM event receiving, then host shaper is disabled. +The traffic rate from host is controlled and less drop happens in Rx queues. + +When disable LWM and lwm_triggered, we can invoke below commands in testpmd: + +.. code-block:: console + + testpmd> mlx5 set port 1 host_shaper lwm_triggered 0 rate 0 + testpmd> set port 1 rxq 0 lwm 0 + testpmd> set port 1 rxq 1 lwm 0 + +It's recommended an application disables LWM and lwm_triggered before exit, +if it enables them before. + +We can also configure the shaper with a value, the rate unit is 100Mbps, below +command sets current shaper to 5Gbps and disables lwm_triggered. + +.. code-block:: console + + testpmd> mlx5 set port 1 host_shaper lwm_triggered 0 rate 50 + diff --git a/drivers/net/mlx5/mlx5_testpmd.c b/drivers/net/mlx5/mlx5_testpmd.c new file mode 100644 index 0000000000..122d6cbc4f --- /dev/null +++ b/drivers/net/mlx5/mlx5_testpmd.c @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2021 6WIND S.A. + * Copyright 2021 Mellanox Technologies, Ltd + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include "mlx5_testpmd.h" + +static uint8_t host_shaper_lwm_triggered[RTE_MAX_ETHPORTS]; +#define SHAPER_DISABLE_DELAY_US 100000 /* 100ms */ + +/** + * Disable the host shaper and re-arm LWM event. + * + * @param[in] args + * uint32_t integer combining port_id and rxq_id. + */ +static void +mlx5_test_host_shaper_disable(void *args) +{ + uint32_t port_rxq_id = (uint32_t)(uintptr_t)args; + uint16_t port_id = port_rxq_id & 0xffff; + uint16_t qid = (port_rxq_id >> 16) & 0xffff; + struct rte_eth_rxq_info qinfo; + + printf("%s disable shaper\n", __func__); + if (rte_eth_rx_queue_info_get(port_id, qid, &qinfo)) { + printf("rx_queue_info_get returns error\n"); + return; + } + /* Rearm the LWM event. */ + if (rte_eth_rx_lwm_set(port_id, qid, qinfo.lwm)) { + printf("config lwm returns error\n"); + return; + } + /* Only disable the shaper when lwm_triggered is set. */ + if (host_shaper_lwm_triggered[port_id] && + rte_pmd_mlx5_host_shaper_config(port_id, 0, 0)) + printf("%s disable shaper returns error\n", __func__); +} + +void +mlx5_test_lwm_event_handler(uint16_t port_id, uint16_t rxq_id) +{ + uint32_t port_rxq_id = port_id | (rxq_id << 16); + + rte_eal_alarm_set(SHAPER_DISABLE_DELAY_US, + mlx5_test_host_shaper_disable, + (void *)(uintptr_t)port_rxq_id); + printf("%s port_id:%u rxq_id:%u\n", __func__, port_id, rxq_id); +} + +/** + * Configure host shaper's lwm_triggered and current rate. + * + * @param[in] lwm_triggered + * Disable/enable lwm_triggered. + * @param[in] rate + * Configure current host shaper rate. + * @return + * On success, returns 0. + * On failure, returns < 0. + */ +static int +mlx5_test_set_port_host_shaper(uint16_t port_id, uint16_t lwm_triggered, uint8_t rate) +{ + struct rte_eth_link link; + bool port_id_valid = false; + uint16_t pid; + int ret; + + RTE_ETH_FOREACH_DEV(pid) + if (port_id == pid) { + port_id_valid = true; + break; + } + if (!port_id_valid) + return -EINVAL; + ret = rte_eth_link_get_nowait(port_id, &link); + if (ret < 0) + return ret; + host_shaper_lwm_triggered[port_id] = lwm_triggered ? 1 : 0; + if (!lwm_triggered) { + ret = rte_pmd_mlx5_host_shaper_config(port_id, 0, + RTE_BIT32(MLX5_HOST_SHAPER_FLAG_LWM_TRIGGERED)); + } else { + ret = rte_pmd_mlx5_host_shaper_config(port_id, 1, + RTE_BIT32(MLX5_HOST_SHAPER_FLAG_LWM_TRIGGERED)); + } + if (ret) + return ret; + ret = rte_pmd_mlx5_host_shaper_config(port_id, rate, 0); + if (ret) + return ret; + return 0; +} + +/* *** SET HOST_SHAPER FOR A PORT *** */ +struct cmd_port_host_shaper_result { + cmdline_fixed_string_t mlx5; + cmdline_fixed_string_t set; + cmdline_fixed_string_t port; + uint16_t port_num; + cmdline_fixed_string_t host_shaper; + cmdline_fixed_string_t lwm_triggered; + uint16_t fr; + cmdline_fixed_string_t rate; + uint8_t rate_num; +}; + +static void cmd_port_host_shaper_parsed(void *parsed_result, + __rte_unused struct cmdline *cl, + __rte_unused void *data) +{ + struct cmd_port_host_shaper_result *res = parsed_result; + int ret = 0; + + if ((strcmp(res->mlx5, "mlx5") == 0) && + (strcmp(res->set, "set") == 0) && + (strcmp(res->port, "port") == 0) && + (strcmp(res->host_shaper, "host_shaper") == 0) && + (strcmp(res->lwm_triggered, "lwm_triggered") == 0) && + (strcmp(res->rate, "rate") == 0)) + ret = mlx5_test_set_port_host_shaper(res->port_num, res->fr, + res->rate_num); + if (ret < 0) + printf("cmd_port_host_shaper error: (%s)\n", strerror(-ret)); +} + +cmdline_parse_token_string_t cmd_port_host_shaper_mlx5 = + TOKEN_STRING_INITIALIZER(struct cmd_port_host_shaper_result, + mlx5, "mlx5"); +cmdline_parse_token_string_t cmd_port_host_shaper_set = + TOKEN_STRING_INITIALIZER(struct cmd_port_host_shaper_result, + set, "set"); +cmdline_parse_token_string_t cmd_port_host_shaper_port = + TOKEN_STRING_INITIALIZER(struct cmd_port_host_shaper_result, + port, "port"); +cmdline_parse_token_num_t cmd_port_host_shaper_portnum = + TOKEN_NUM_INITIALIZER(struct cmd_port_host_shaper_result, + port_num, RTE_UINT16); +cmdline_parse_token_string_t cmd_port_host_shaper_host_shaper = + TOKEN_STRING_INITIALIZER(struct cmd_port_host_shaper_result, + host_shaper, "host_shaper"); +cmdline_parse_token_string_t cmd_port_host_shaper_lwm_triggered = + TOKEN_STRING_INITIALIZER(struct cmd_port_host_shaper_result, + lwm_triggered, "lwm_triggered"); +cmdline_parse_token_num_t cmd_port_host_shaper_fr = + TOKEN_NUM_INITIALIZER(struct cmd_port_host_shaper_result, + fr, RTE_UINT16); +cmdline_parse_token_string_t cmd_port_host_shaper_rate = + TOKEN_STRING_INITIALIZER(struct cmd_port_host_shaper_result, + rate, "rate"); +cmdline_parse_token_num_t cmd_port_host_shaper_rate_num = + TOKEN_NUM_INITIALIZER(struct cmd_port_host_shaper_result, + rate_num, RTE_UINT8); +cmdline_parse_inst_t mlx5_test_cmd_port_host_shaper = { + .f = cmd_port_host_shaper_parsed, + .data = (void *)0, + .help_str = "mlx5 set port host_shaper lwm_triggered <0|1> " + "rate : Set HOST_SHAPER lwm_triggered and rate with port_id", + .tokens = { + (void *)&cmd_port_host_shaper_mlx5, + (void *)&cmd_port_host_shaper_set, + (void *)&cmd_port_host_shaper_port, + (void *)&cmd_port_host_shaper_portnum, + (void *)&cmd_port_host_shaper_host_shaper, + (void *)&cmd_port_host_shaper_lwm_triggered, + (void *)&cmd_port_host_shaper_fr, + (void *)&cmd_port_host_shaper_rate, + (void *)&cmd_port_host_shaper_rate_num, + NULL, + } +}; diff --git a/drivers/net/mlx5/mlx5_testpmd.h b/drivers/net/mlx5/mlx5_testpmd.h new file mode 100644 index 0000000000..50f3cf0bf9 --- /dev/null +++ b/drivers/net/mlx5/mlx5_testpmd.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2021 6WIND S.A. + * Copyright 2021 Mellanox Technologies, Ltd + */ + +#ifndef RTE_PMD_MLX5_TEST_H_ +#define RTE_PMD_MLX5_TEST_H_ + +#include +#include +#include + +/** + * RTE_ETH_EVENT_RX_LWM handler sample code. + * It's called in testpmd, the work flow here is delay a while until + * RX queueu is empty, then disable host shaper. + * + * @param[in] port_id + * Port identifier. + * @param[in] rxq_id + * Rx queue identifier. + */ +void +mlx5_test_lwm_event_handler(uint16_t port_id, uint16_t rxq_id); + +extern cmdline_parse_inst_t mlx5_test_cmd_port_host_shaper; +#endif