From patchwork Wed Jun 29 10:47:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 113533 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 29C75A056B; Wed, 29 Jun 2022 04:48:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DB45E40143; Wed, 29 Jun 2022 04:48:28 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 67C7E40042 for ; Wed, 29 Jun 2022 04:48:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656470907; x=1688006907; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=h0ZAN3lK2uKVJpLSFaVY9XtqitiLJkZbv43x+HNAhrE=; b=ksdhi4isazwKnQF0U7t1ig6orhdw9fBoYkgFqB9Jbz8EEldWbxwTTeKL nx7Jz6SB1f3SwuPEVVmTqOrVfTw7qyh9YIw9jfqO5Ncjw7vKglH9N7SOS PoWSBWZrZoMr96Z0T1CLkI36rHiHYOUbSNLm007fdumkKw9Ni1bD8TJgv jlD0A6XARziX1FmQ6stMTS7nkxXoMTeb99wbQ2DGXPqgecI4dkVRpnP6M nNJb584nUNXrcSeB3lpNyAgiouiC4bEd6IQzXTreK8Z6MYj/cXU8ylJGA VK327mf/RU/HEY8OEpjiO7EG/dHLZMzXvgOpUBV7fLlJZkvwLMeH+DJFN w==; X-IronPort-AV: E=McAfee;i="6400,9594,10392"; a="264943835" X-IronPort-AV: E=Sophos;i="5.92,230,1650956400"; d="scan'208";a="264943835" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2022 19:48:26 -0700 X-IronPort-AV: E=Sophos;i="5.92,230,1650956400"; d="scan'208";a="836934385" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.191]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2022 19:48:23 -0700 From: Kevin Liu To: dev@dpdk.org Cc: beilei.xing@intel.com, Yuying.Zhang@intel.com, stevex.yang@intel.com, Kevin Liu Subject: [PATCH v2] net/i40e: fix error disable double VLAN Date: Wed, 29 Jun 2022 10:47:29 +0000 Message-Id: <20220629104729.324397-1-kevinx.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220629095710.300200-1-kevinx.liu@intel.com> References: <20220629095710.300200-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sync the kernel driver, enable double VLAN by default after firmware v8.3 and disable double VLAN is not allowed in subsequent operations. Fixes: 4f13a78f1b8f ("net/i40e: add outer VLAN processing") Signed-off-by: Kevin Liu v2: update the document --- doc/guides/nics/i40e.rst | 5 ++-- drivers/net/i40e/i40e_ethdev.c | 45 ++++++++++++---------------------- 2 files changed, 17 insertions(+), 33 deletions(-) diff --git a/doc/guides/nics/i40e.rst b/doc/guides/nics/i40e.rst index a7b51618b0..d051c7ec36 100644 --- a/doc/guides/nics/i40e.rst +++ b/doc/guides/nics/i40e.rst @@ -969,11 +969,10 @@ it will fail and return the info "Conflict with the first rule's input set", which means the current rule's input set conflicts with the first rule's. Remove the first rule if want to change the input set of the PCTYPE. -PF reset fail after QinQ set with FW >= 8.4 +Disable Qinq is not supported when FW >= 8.4 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -If upgrade FW to version 8.4 and higher, after set MAC VLAN filter and configure outer VLAN on PF, kill -DPDK process will cause the card crash. +If upgrade FW to version 8.4 and higher, sync kernel driver, enable Qinq by default and disable Qinq is not supported. Example of getting best performance with l3fwd example diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index dd471d487e..b07ef89220 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -2575,7 +2575,6 @@ i40e_dev_close(struct rte_eth_dev *dev) struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); struct rte_intr_handle *intr_handle = pci_dev->intr_handle; - struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; struct i40e_filter_control_settings settings; struct rte_flow *p_flow; uint32_t reg; @@ -2588,18 +2587,6 @@ i40e_dev_close(struct rte_eth_dev *dev) if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; - /* - * It is a workaround, if the double VLAN is disabled when - * the program exits, an abnormal error will occur on the - * NIC. Need to enable double VLAN when dev is closed. - */ - if (pf->fw8_3gt) { - if (!(rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND)) { - rxmode->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_EXTEND; - i40e_vlan_offload_set(dev, RTE_ETH_VLAN_EXTEND_MASK); - } - } - ret = rte_eth_switch_domain_free(pf->switch_domain_id); if (ret) PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret); @@ -3950,20 +3937,8 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev, else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) hw->second_tag = rte_cpu_to_le_16(tpid); } else { - /* - * If tpid is equal to 0x88A8, indicates that the - * disable double VLAN operation is in progress. - * Need set switch configuration back to default. - */ - if (pf->fw8_3gt && tpid == RTE_ETHER_TYPE_QINQ) { - sw_flags = 0; - valid_flags = I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN; - if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) - hw->first_tag = rte_cpu_to_le_16(tpid); - } else { - if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) - hw->second_tag = rte_cpu_to_le_16(tpid); - } + if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) + hw->second_tag = rte_cpu_to_le_16(tpid); } ret = i40e_aq_set_switch_config(hw, sw_flags, valid_flags, 0, NULL); @@ -4043,6 +4018,12 @@ i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask) } if (mask & RTE_ETH_VLAN_EXTEND_MASK) { + /* Sync the kernel driver. Double VLAN not allowed to be disabled.*/ + if (pf->fw8_3gt && !(rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND)) { + PMD_DRV_LOG(WARNING, + "Disable double VLAN is not allowed after firmwarev8.3!"); + return 0; + } i = 0; num = vsi->mac_num; mac_filter = rte_zmalloc("mac_filter_info_data", @@ -4078,9 +4059,6 @@ i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask) i40e_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_INNER, RTE_ETHER_TYPE_VLAN); } else { - if (pf->fw8_3gt) - i40e_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_OUTER, - RTE_ETHER_TYPE_QINQ); i40e_vsi_config_double_vlan(vsi, FALSE); } /* Restore all mac */ @@ -6176,6 +6154,7 @@ i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on) static int i40e_dev_init_vlan(struct rte_eth_dev *dev) { + struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); struct rte_eth_dev_data *data = dev->data; int ret; int mask = 0; @@ -6185,6 +6164,12 @@ i40e_dev_init_vlan(struct rte_eth_dev *dev) RTE_ETH_QINQ_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK | RTE_ETH_VLAN_EXTEND_MASK; + + /* Sync the kernel driver. Double VLAN be enabled by default.*/ + if (pf->fw8_3gt) { + struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; + rxmode->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_EXTEND; + } ret = i40e_vlan_offload_set(dev, mask); if (ret) { PMD_DRV_LOG(INFO, "Failed to update vlan offload");