From patchwork Wed Aug 3 16:25:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Naga Harish K, S V" X-Patchwork-Id: 114588 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B2EB6A00C5; Wed, 3 Aug 2022 18:26:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4BA5942BAB; Wed, 3 Aug 2022 18:26:18 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id CA83C40A7E for ; Wed, 3 Aug 2022 18:26:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659543977; x=1691079977; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=6p4KfRgzX+l9BHj9AnBI1eLFngu5AMzX+714DFN56do=; b=RmzqDV2uqaT5b4LUIUdEH3+jVCoQGVTEQWhBrE/y3et/jnxU1svWuFzZ l/4Ykzvq9sPeqQERWkZZUC+1eqeNyeSDnSOxusR9039b5ec8e0eQsHuoI Kia6FDUoTz/cXaLL9qm1qiB+BFfBnRdGNXPoPOhl2SVRSsLXfTT4/s5YJ VMuP8R+XnqBBa6uUm08msssriXr+1MRUA9maNTomNAj/xCMDOr8aQJOcu +OjkV5D52alTL6S/KAwf7JARMiZEyvCju10fNL9iFXBCUWf0C1li3XEDR 4NC4zXmt2nsLtYebfOUvcCJD32jCxeg/q1uB6GTay4PDYnSok5OAkqI2z g==; X-IronPort-AV: E=McAfee;i="6400,9594,10428"; a="276634541" X-IronPort-AV: E=Sophos;i="5.93,214,1654585200"; d="scan'208";a="276634541" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2022 09:26:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,214,1654585200"; d="scan'208";a="662147895" Received: from txandevlnx322.an.intel.com ([10.123.117.44]) by fmsmga008.fm.intel.com with ESMTP; 03 Aug 2022 09:26:14 -0700 From: Naga Harish K S V To: erik.g.carrillo@intel.com, jerinj@marvell.com Cc: pbhagavatula@marvell.com, sthotton@marvell.com, dev@dpdk.org Subject: [PATCH 1/4] eventdev/timer: add periodic event timer support Date: Wed, 3 Aug 2022 11:25:41 -0500 Message-Id: <20220803162542.3145559-1-s.v.naga.harish.k@intel.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds support to configure and use periodic event timers in software timer adapter. The structure ``rte_event_timer_adapter_stats`` is extended by adding a new field, ``evtim_drop_count``. This stat represents the number of times an event_timer expiry event is dropped by the event timer adapter. Signed-off-by: Naga Harish K S V --- lib/eventdev/rte_event_timer_adapter.c | 86 ++++++++++++++++++-------- lib/eventdev/rte_event_timer_adapter.h | 2 + lib/eventdev/rte_eventdev.c | 6 +- 3 files changed, 67 insertions(+), 27 deletions(-) diff --git a/lib/eventdev/rte_event_timer_adapter.c b/lib/eventdev/rte_event_timer_adapter.c index e0d978d641..f96cb98b5b 100644 --- a/lib/eventdev/rte_event_timer_adapter.c +++ b/lib/eventdev/rte_event_timer_adapter.c @@ -53,6 +53,14 @@ static const struct event_timer_adapter_ops swtim_ops; #define EVTIM_SVC_LOG_DBG(...) (void)0 #endif +static inline enum rte_timer_type +get_event_timer_type(const struct rte_event_timer_adapter *adapter) +{ + return (adapter->data->conf.flags & + RTE_EVENT_TIMER_ADAPTER_F_PERIODIC) ? + PERIODICAL : SINGLE; +} + static int default_port_conf_cb(uint16_t id, uint8_t event_dev_id, uint8_t *event_port_id, void *conf_arg) @@ -195,10 +203,11 @@ rte_event_timer_adapter_create_ext( adapter->data->conf = *conf; /* copy conf structure */ /* Query eventdev PMD for timer adapter capabilities and ops */ - ret = dev->dev_ops->timer_adapter_caps_get(dev, + ret = dev->dev_ops->timer_adapter_caps_get ? + dev->dev_ops->timer_adapter_caps_get(dev, adapter->data->conf.flags, &adapter->data->caps, - &adapter->ops); + &adapter->ops) : 0; if (ret < 0) { rte_errno = -ret; goto free_memzone; @@ -348,10 +357,11 @@ rte_event_timer_adapter_lookup(uint16_t adapter_id) dev = &rte_eventdevs[adapter->data->event_dev_id]; /* Query eventdev PMD for timer adapter capabilities and ops */ - ret = dev->dev_ops->timer_adapter_caps_get(dev, + ret = dev->dev_ops->timer_adapter_caps_get ? + dev->dev_ops->timer_adapter_caps_get(dev, adapter->data->conf.flags, &adapter->data->caps, - &adapter->ops); + &adapter->ops) : 0; if (ret < 0) { rte_errno = EINVAL; return NULL; @@ -612,35 +622,44 @@ swtim_callback(struct rte_timer *tim) uint64_t opaque; int ret; int n_lcores; + enum rte_timer_type type; opaque = evtim->impl_opaque[1]; adapter = (struct rte_event_timer_adapter *)(uintptr_t)opaque; sw = swtim_pmd_priv(adapter); + type = get_event_timer_type(adapter); + + if (unlikely(sw->in_use[lcore].v == 0)) { + sw->in_use[lcore].v = 1; + n_lcores = __atomic_fetch_add(&sw->n_poll_lcores, 1, + __ATOMIC_RELAXED); + __atomic_store_n(&sw->poll_lcores[n_lcores], lcore, + __ATOMIC_RELAXED); + } ret = event_buffer_add(&sw->buffer, &evtim->ev); if (ret < 0) { - /* If event buffer is full, put timer back in list with - * immediate expiry value, so that we process it again on the - * next iteration. - */ - ret = rte_timer_alt_reset(sw->timer_data_id, tim, 0, SINGLE, - lcore, NULL, evtim); - if (ret < 0) { - EVTIM_LOG_DBG("event buffer full, failed to reset " - "timer with immediate expiry value"); + if (type == SINGLE) { + /* If event buffer is full, put timer back in list with + * immediate expiry value, so that we process it again + * on the next iteration. + */ + ret = rte_timer_alt_reset(sw->timer_data_id, tim, 0, + SINGLE, lcore, NULL, evtim); + if (ret < 0) { + EVTIM_LOG_DBG("event buffer full, failed to " + "reset timer with immediate " + "expiry value"); + } else { + sw->stats.evtim_retry_count++; + EVTIM_LOG_DBG("event buffer full, resetting " + "rte_timer with immediate " + "expiry value"); + } } else { - sw->stats.evtim_retry_count++; - EVTIM_LOG_DBG("event buffer full, resetting rte_timer " - "with immediate expiry value"); + sw->stats.evtim_drop_count++; } - if (unlikely(sw->in_use[lcore].v == 0)) { - sw->in_use[lcore].v = 1; - n_lcores = __atomic_fetch_add(&sw->n_poll_lcores, 1, - __ATOMIC_RELAXED); - __atomic_store_n(&sw->poll_lcores[n_lcores], lcore, - __ATOMIC_RELAXED); - } } else { EVTIM_BUF_LOG_DBG("buffered an event timer expiry event"); @@ -654,10 +673,15 @@ swtim_callback(struct rte_timer *tim) sw->n_expired_timers = 0; } - sw->expired_timers[sw->n_expired_timers++] = tim; + /* Don't free rte_timer for a periodic event timer until + * it is cancelled + */ + if (type == SINGLE) + sw->expired_timers[sw->n_expired_timers++] = tim; sw->stats.evtim_exp_count++; - __atomic_store_n(&evtim->state, RTE_EVENT_TIMER_NOT_ARMED, + if (type == SINGLE) + __atomic_store_n(&evtim->state, RTE_EVENT_TIMER_NOT_ARMED, __ATOMIC_RELEASE); } @@ -947,6 +971,12 @@ swtim_uninit(struct rte_event_timer_adapter *adapter) swtim_free_tim, sw); + ret = rte_timer_data_dealloc(sw->timer_data_id); + if (ret < 0) { + EVTIM_LOG_ERR("failed to deallocate timer data instance"); + return ret; + } + ret = rte_service_component_unregister(sw->service_id); if (ret < 0) { EVTIM_LOG_ERR("failed to unregister service component"); @@ -1053,6 +1083,7 @@ __swtim_arm_burst(const struct rte_event_timer_adapter *adapter, /* Timer list for this lcore is not in use. */ uint16_t exp_state = 0; enum rte_event_timer_state n_state; + enum rte_timer_type type = SINGLE; #ifdef RTE_LIBRTE_EVENTDEV_DEBUG /* Check that the service is running. */ @@ -1092,6 +1123,9 @@ __swtim_arm_burst(const struct rte_event_timer_adapter *adapter, return 0; } + /* update timer type for periodic adapter */ + type = get_event_timer_type(adapter); + for (i = 0; i < nb_evtims; i++) { n_state = __atomic_load_n(&evtims[i]->state, __ATOMIC_ACQUIRE); if (n_state == RTE_EVENT_TIMER_ARMED) { @@ -1135,7 +1169,7 @@ __swtim_arm_burst(const struct rte_event_timer_adapter *adapter, cycles = get_timeout_cycles(evtims[i], adapter); ret = rte_timer_alt_reset(sw->timer_data_id, tim, cycles, - SINGLE, lcore_id, NULL, evtims[i]); + type, lcore_id, NULL, evtims[i]); if (ret < 0) { /* tim was in RUNNING or CONFIG state */ __atomic_store_n(&evtims[i]->state, diff --git a/lib/eventdev/rte_event_timer_adapter.h b/lib/eventdev/rte_event_timer_adapter.h index eab8e59a57..cd10db19e4 100644 --- a/lib/eventdev/rte_event_timer_adapter.h +++ b/lib/eventdev/rte_event_timer_adapter.h @@ -193,6 +193,8 @@ struct rte_event_timer_adapter_stats { /**< Event timer retry count */ uint64_t adapter_tick_count; /**< Tick count for the adapter, at its resolution */ + uint64_t evtim_drop_count; + /**< event timer expiries dropped */ }; struct rte_event_timer_adapter; diff --git a/lib/eventdev/rte_eventdev.c b/lib/eventdev/rte_eventdev.c index 1dc4f966be..4a2a1178da 100644 --- a/lib/eventdev/rte_eventdev.c +++ b/lib/eventdev/rte_eventdev.c @@ -139,7 +139,11 @@ rte_event_timer_adapter_caps_get(uint8_t dev_id, uint32_t *caps) if (caps == NULL) return -EINVAL; - *caps = 0; + + if (dev->dev_ops->timer_adapter_caps_get == NULL) + *caps = RTE_EVENT_TIMER_ADAPTER_CAP_PERIODIC; + else + *caps = 0; return dev->dev_ops->timer_adapter_caps_get ? (*dev->dev_ops->timer_adapter_caps_get)(dev, From patchwork Wed Aug 3 16:26:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Naga Harish K, S V" X-Patchwork-Id: 114590 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3363DA00C5; Wed, 3 Aug 2022 18:26:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2686842BB1; Wed, 3 Aug 2022 18:26:43 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id D9DA640A7E for ; Wed, 3 Aug 2022 18:26:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659544001; x=1691080001; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; 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RTE_SET_USED(flags); - *caps = 0; + *caps = RTE_EVENT_TIMER_ADAPTER_CAP_PERIODIC; /* Use default SW ops */ *ops = NULL; From patchwork Wed Aug 3 16:26:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Naga Harish K, S V" X-Patchwork-Id: 114591 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3A173A00C5; Wed, 3 Aug 2022 18:27:14 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 26A4E42BAB; Wed, 3 Aug 2022 18:27:14 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 41D6D40A7E for ; Wed, 3 Aug 2022 18:27:13 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659544033; x=1691080033; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=xvTtyyPK/XBsMwTewbRd6gRN6CxbjYBTKDWEUgyfG/g=; b=JwJ0mnDlEnCMgdRJwHSXFedOjc56BVg7LNlRdeVFiIVbji/8IJ+zSaXH FDL+9nylGbKhZVebcTkexLam2yrZ0v9cZgpbc4QA/E1mANXR9I/fr6Eka YBZqenZEL98bNPcSs6+QhQiuRO3aHmdOZecOGRW5VTt3nWXJ1kKOIQBqF RekCX45Iv/CDTJqaLmyUUSVwjJa+IJlaCcsF79Tsow1Uoctq4VdB+8TBh nQvXpzwVjrY118gM4Ltva/9vihn3GvK/veLxcIN69s4Wf18jnHolIF33L tP05ky3BF5CwpyBIZN+NHBEcV32p706owjW6N6hXmWkoy4kPHQlBsGAR7 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10428"; a="290491342" X-IronPort-AV: E=Sophos;i="5.93,214,1654585200"; d="scan'208";a="290491342" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2022 09:26:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,214,1654585200"; d="scan'208";a="578711150" Received: from txandevlnx322.an.intel.com ([10.123.117.44]) by orsmga006.jf.intel.com with ESMTP; 03 Aug 2022 09:26:55 -0700 From: Naga Harish K S V To: erik.g.carrillo@intel.com Cc: dev@dpdk.org Subject: [PATCH 3/4] timer: fix rte_timer_stop_all Date: Wed, 3 Aug 2022 11:26:51 -0500 Message-Id: <20220803162651.3145945-1-s.v.naga.harish.k@intel.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org there is a possibility of deadlock in this api, as same spinlock is tried to be acquired in nested manner. This patch removes the acquisition of nested locking. Signed-off-by: Naga Harish K S V --- lib/timer/rte_timer.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/lib/timer/rte_timer.c b/lib/timer/rte_timer.c index 9994813d0d..cfbc8cb028 100644 --- a/lib/timer/rte_timer.c +++ b/lib/timer/rte_timer.c @@ -987,21 +987,16 @@ rte_timer_stop_all(uint32_t timer_data_id, unsigned int *walk_lcores, walk_lcore = walk_lcores[i]; priv_timer = &timer_data->priv_timer[walk_lcore]; - rte_spinlock_lock(&priv_timer->list_lock); - for (tim = priv_timer->pending_head.sl_next[0]; tim != NULL; tim = next_tim) { next_tim = tim->sl_next[0]; - /* Call timer_stop with lock held */ - __rte_timer_stop(tim, 1, timer_data); + __rte_timer_stop(tim, 0, timer_data); if (f) f(tim, f_arg); } - - rte_spinlock_unlock(&priv_timer->list_lock); } return 0; From patchwork Wed Aug 3 16:25:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Naga Harish K, S V" X-Patchwork-Id: 114589 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E8F68A00C5; Wed, 3 Aug 2022 18:26:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 97D6042BBC; Wed, 3 Aug 2022 18:26:21 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 9756442BBC for ; Wed, 3 Aug 2022 18:26:19 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659543979; x=1691079979; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=F2DhGW6Wj153VHDWa9kSSjyuHOVsERdtkPWTfWkalMc=; b=A0vZ2R053rg4RNeVgiBKnhHrzcrpMOeJtryfbDVf1Hy+2n5ByKD/UdVz oDGMYMc16HjF05nR76HtaTzEaO1+kUhZv/EMTIR6QAmBNcW8KIzAQDhn2 ETkb92751bHl5r0jgOep72kX6/nzKdhw1d1GtIkwshZPDYSTmXucnPz3N pnCMXAU0Amu6aQzwKwQTFE6CyStm9xke22aekX7VpIHCKjehfkJ/lGcFr AmXsddJQ1ZOxIxzvEo+fJA103y87BN69eWEF2xa3Vlxo8SPYFnhmthEK5 tU3FWThzM5ERy/lGAC+qMPu9jlIT5iVys4uwUL7baM4YlqpAXafuo9v8W A==; X-IronPort-AV: E=McAfee;i="6400,9594,10428"; a="276634551" X-IronPort-AV: E=Sophos;i="5.93,214,1654585200"; d="scan'208";a="276634551" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2022 09:26:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,214,1654585200"; d="scan'208";a="662147908" Received: from txandevlnx322.an.intel.com ([10.123.117.44]) by fmsmga008.fm.intel.com with ESMTP; 03 Aug 2022 09:26:18 -0700 From: Naga Harish K S V To: erik.g.carrillo@intel.com, jerinj@marvell.com Cc: pbhagavatula@marvell.com, sthotton@marvell.com, dev@dpdk.org Subject: [PATCH 4/4] test/event: update periodic event timer tests Date: Wed, 3 Aug 2022 11:25:42 -0500 Message-Id: <20220803162542.3145559-2-s.v.naga.harish.k@intel.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20220803162542.3145559-1-s.v.naga.harish.k@intel.com> References: <20220803162542.3145559-1-s.v.naga.harish.k@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch updates the software timer adapter tests to configure and use periodic event timers Signed-off-by: Naga Harish K S V --- app/test/test_event_timer_adapter.c | 41 ++++++++++++++++++++++++++--- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/app/test/test_event_timer_adapter.c b/app/test/test_event_timer_adapter.c index d6170bb589..654c412836 100644 --- a/app/test/test_event_timer_adapter.c +++ b/app/test/test_event_timer_adapter.c @@ -386,11 +386,22 @@ timdev_setup_msec(void) static int timdev_setup_msec_periodic(void) { + uint32_t caps = 0; + uint64_t max_tmo_ns; + uint64_t flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES | RTE_EVENT_TIMER_ADAPTER_F_PERIODIC; + TEST_ASSERT_SUCCESS(rte_event_timer_adapter_caps_get(evdev, &caps), + "failed to get adapter capabilities"); + + if (caps & RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT) + max_tmo_ns = 0; + else + max_tmo_ns = 180 * NSECPERSEC; + /* Periodic mode with 100 ms resolution */ - return _timdev_setup(0, NSECPERSEC / 10, flags); + return _timdev_setup(max_tmo_ns, NSECPERSEC / 10, flags); } static int @@ -409,7 +420,7 @@ timdev_setup_sec_periodic(void) RTE_EVENT_TIMER_ADAPTER_F_PERIODIC; /* Periodic mode with 1 sec resolution */ - return _timdev_setup(0, NSECPERSEC, flags); + return _timdev_setup(180 * NSECPERSEC, NSECPERSEC, flags); } static int @@ -561,12 +572,23 @@ test_timer_arm(void) static inline int test_timer_arm_periodic(void) { + uint32_t caps = 0; + uint32_t timeout_count = 0; + TEST_ASSERT_SUCCESS(_arm_timers(1, MAX_TIMERS), "Failed to arm timers"); /* With a resolution of 100ms and wait time of 1sec, * there will be 10 * MAX_TIMERS periodic timer triggers. */ - TEST_ASSERT_SUCCESS(_wait_timer_triggers(1, 10 * MAX_TIMERS, 0), + TEST_ASSERT_SUCCESS(rte_event_timer_adapter_caps_get(evdev, &caps), + "failed to get adapter capabilities"); + + if (caps & RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT) + timeout_count = 10; + else + timeout_count = 9; + + TEST_ASSERT_SUCCESS(_wait_timer_triggers(1, timeout_count * MAX_TIMERS, 0), "Timer triggered count doesn't match arm count"); return TEST_SUCCESS; } @@ -649,12 +671,23 @@ test_timer_arm_burst(void) static inline int test_timer_arm_burst_periodic(void) { + uint32_t caps = 0; + uint32_t timeout_count = 0; + TEST_ASSERT_SUCCESS(_arm_timers_burst(1, MAX_TIMERS), "Failed to arm timers"); /* With a resolution of 100ms and wait time of 1sec, * there will be 10 * MAX_TIMERS periodic timer triggers. */ - TEST_ASSERT_SUCCESS(_wait_timer_triggers(1, 10 * MAX_TIMERS, 0), + TEST_ASSERT_SUCCESS(rte_event_timer_adapter_caps_get(evdev, &caps), + "failed to get adapter capabilities"); + + if (caps & RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT) + timeout_count = 10; + else + timeout_count = 9; + + TEST_ASSERT_SUCCESS(_wait_timer_triggers(1, timeout_count * MAX_TIMERS, 0), "Timer triggered count doesn't match arm count"); return TEST_SUCCESS;